java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerCInline_WitnessPrinter.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf -i ../../../trunk/examples/svcomp/array-tiling/nr5_true-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-61f4311 [2018-11-23 10:28:47,422 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 10:28:47,427 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 10:28:47,447 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 10:28:47,448 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 10:28:47,449 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 10:28:47,450 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 10:28:47,453 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 10:28:47,455 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 10:28:47,456 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 10:28:47,457 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 10:28:47,457 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 10:28:47,458 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 10:28:47,459 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 10:28:47,460 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 10:28:47,461 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 10:28:47,462 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 10:28:47,464 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 10:28:47,465 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 10:28:47,467 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 10:28:47,468 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 10:28:47,469 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 10:28:47,472 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 10:28:47,472 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 10:28:47,472 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 10:28:47,473 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 10:28:47,474 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 10:28:47,475 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 10:28:47,476 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 10:28:47,477 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 10:28:47,477 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 10:28:47,478 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 10:28:47,478 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 10:28:47,478 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 10:28:47,479 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 10:28:47,480 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 10:28:47,480 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-23 10:28:47,500 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 10:28:47,501 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 10:28:47,501 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 10:28:47,502 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 10:28:47,503 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 10:28:47,503 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 10:28:47,503 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 10:28:47,504 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 10:28:47,504 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 10:28:47,504 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 10:28:47,504 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 10:28:47,504 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 10:28:47,504 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 10:28:47,505 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 10:28:47,505 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-23 10:28:47,505 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-23 10:28:47,505 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 10:28:47,506 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 10:28:47,506 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 10:28:47,506 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 10:28:47,506 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 10:28:47,506 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 10:28:47,508 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 10:28:47,508 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 10:28:47,509 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:28:47,509 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 10:28:47,509 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 10:28:47,509 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 10:28:47,509 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-23 10:28:47,510 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 10:28:47,510 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-23 10:28:47,510 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-23 10:28:47,510 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 10:28:47,560 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 10:28:47,573 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 10:28:47,577 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 10:28:47,578 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 10:28:47,579 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 10:28:47,580 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-tiling/nr5_true-unreach-call.i [2018-11-23 10:28:47,644 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8089ade08/94699c4838d34f4fa3ad96dd983aba57/FLAGad91aaf42 [2018-11-23 10:28:48,086 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 10:28:48,087 INFO L161 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-tiling/nr5_true-unreach-call.i [2018-11-23 10:28:48,093 INFO L355 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8089ade08/94699c4838d34f4fa3ad96dd983aba57/FLAGad91aaf42 [2018-11-23 10:28:48,452 INFO L363 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8089ade08/94699c4838d34f4fa3ad96dd983aba57 [2018-11-23 10:28:48,463 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 10:28:48,465 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 10:28:48,466 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 10:28:48,466 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 10:28:48,470 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 10:28:48,472 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,475 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1128d40e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48, skipping insertion in model container [2018-11-23 10:28:48,475 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,486 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 10:28:48,509 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 10:28:48,762 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:28:48,768 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 10:28:48,797 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:28:48,822 INFO L195 MainTranslator]: Completed translation [2018-11-23 10:28:48,823 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48 WrapperNode [2018-11-23 10:28:48,823 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 10:28:48,824 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 10:28:48,824 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 10:28:48,825 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 10:28:48,834 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,845 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,854 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 10:28:48,854 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 10:28:48,854 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 10:28:48,854 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 10:28:48,864 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,864 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,867 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,867 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,881 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,889 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,891 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,894 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 10:28:48,894 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 10:28:48,894 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 10:28:48,894 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 10:28:48,895 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:28:49,016 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 10:28:49,016 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 10:28:49,016 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 10:28:49,016 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-23 10:28:49,017 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 10:28:49,017 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 10:28:49,017 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 10:28:49,017 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 10:28:49,017 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-23 10:28:49,017 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-23 10:28:49,018 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-23 10:28:49,018 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 10:28:49,739 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 10:28:49,740 INFO L280 CfgBuilder]: Removed 3 assue(true) statements. [2018-11-23 10:28:49,740 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:28:49 BoogieIcfgContainer [2018-11-23 10:28:49,740 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 10:28:49,741 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 10:28:49,741 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 10:28:49,744 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 10:28:49,744 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 10:28:48" (1/3) ... [2018-11-23 10:28:49,745 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@49828a80 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:28:49, skipping insertion in model container [2018-11-23 10:28:49,745 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (2/3) ... [2018-11-23 10:28:49,746 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@49828a80 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:28:49, skipping insertion in model container [2018-11-23 10:28:49,746 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:28:49" (3/3) ... [2018-11-23 10:28:49,748 INFO L112 eAbstractionObserver]: Analyzing ICFG nr5_true-unreach-call.i [2018-11-23 10:28:49,757 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 10:28:49,765 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 10:28:49,784 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 10:28:49,818 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 10:28:49,819 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 10:28:49,819 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 10:28:49,819 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 10:28:49,820 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 10:28:49,820 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 10:28:49,820 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 10:28:49,820 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 10:28:49,820 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 10:28:49,839 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states. [2018-11-23 10:28:49,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-11-23 10:28:49,847 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:49,848 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:49,850 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:49,857 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:49,857 INFO L82 PathProgramCache]: Analyzing trace with hash 1453831941, now seen corresponding path program 1 times [2018-11-23 10:28:49,862 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:49,862 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:49,881 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:49,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:49,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:49,971 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:50,447 INFO L256 TraceCheckUtils]: 0: Hoare triple {34#true} call ULTIMATE.init(); {34#true} is VALID [2018-11-23 10:28:50,450 INFO L273 TraceCheckUtils]: 1: Hoare triple {34#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {34#true} is VALID [2018-11-23 10:28:50,451 INFO L273 TraceCheckUtils]: 2: Hoare triple {34#true} assume true; {34#true} is VALID [2018-11-23 10:28:50,451 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {34#true} {34#true} #83#return; {34#true} is VALID [2018-11-23 10:28:50,451 INFO L256 TraceCheckUtils]: 4: Hoare triple {34#true} call #t~ret8 := main(); {34#true} is VALID [2018-11-23 10:28:50,452 INFO L273 TraceCheckUtils]: 5: Hoare triple {34#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {34#true} is VALID [2018-11-23 10:28:50,452 INFO L273 TraceCheckUtils]: 6: Hoare triple {34#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {34#true} is VALID [2018-11-23 10:28:50,452 INFO L273 TraceCheckUtils]: 7: Hoare triple {34#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {34#true} is VALID [2018-11-23 10:28:50,453 INFO L273 TraceCheckUtils]: 8: Hoare triple {34#true} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {34#true} is VALID [2018-11-23 10:28:50,453 INFO L273 TraceCheckUtils]: 9: Hoare triple {34#true} ~i~0 := 0bv32; {34#true} is VALID [2018-11-23 10:28:50,453 INFO L273 TraceCheckUtils]: 10: Hoare triple {34#true} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {34#true} is VALID [2018-11-23 10:28:50,454 INFO L273 TraceCheckUtils]: 11: Hoare triple {34#true} assume #t~short7; {72#|main_#t~short7|} is VALID [2018-11-23 10:28:50,456 INFO L256 TraceCheckUtils]: 12: Hoare triple {72#|main_#t~short7|} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {76#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:50,456 INFO L273 TraceCheckUtils]: 13: Hoare triple {76#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {80#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:50,468 INFO L273 TraceCheckUtils]: 14: Hoare triple {80#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {35#false} is VALID [2018-11-23 10:28:50,469 INFO L273 TraceCheckUtils]: 15: Hoare triple {35#false} assume !false; {35#false} is VALID [2018-11-23 10:28:50,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:50,473 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:28:50,482 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:28:50,483 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 10:28:50,488 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2018-11-23 10:28:50,492 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:50,497 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states. [2018-11-23 10:28:50,570 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:50,570 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 10:28:50,578 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 10:28:50,579 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 10:28:50,582 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 5 states. [2018-11-23 10:28:51,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:51,432 INFO L93 Difference]: Finished difference Result 60 states and 81 transitions. [2018-11-23 10:28:51,432 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 10:28:51,432 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2018-11-23 10:28:51,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:51,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-23 10:28:51,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 81 transitions. [2018-11-23 10:28:51,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-23 10:28:51,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 81 transitions. [2018-11-23 10:28:51,453 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 81 transitions. [2018-11-23 10:28:52,046 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 81 edges. 81 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:52,060 INFO L225 Difference]: With dead ends: 60 [2018-11-23 10:28:52,060 INFO L226 Difference]: Without dead ends: 31 [2018-11-23 10:28:52,064 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 10:28:52,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2018-11-23 10:28:52,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2018-11-23 10:28:52,130 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:52,130 INFO L82 GeneralOperation]: Start isEquivalent. First operand 31 states. Second operand 30 states. [2018-11-23 10:28:52,131 INFO L74 IsIncluded]: Start isIncluded. First operand 31 states. Second operand 30 states. [2018-11-23 10:28:52,131 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 30 states. [2018-11-23 10:28:52,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:52,136 INFO L93 Difference]: Finished difference Result 31 states and 35 transitions. [2018-11-23 10:28:52,136 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2018-11-23 10:28:52,137 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:52,137 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:52,137 INFO L74 IsIncluded]: Start isIncluded. First operand 30 states. Second operand 31 states. [2018-11-23 10:28:52,138 INFO L87 Difference]: Start difference. First operand 30 states. Second operand 31 states. [2018-11-23 10:28:52,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:52,142 INFO L93 Difference]: Finished difference Result 31 states and 35 transitions. [2018-11-23 10:28:52,142 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2018-11-23 10:28:52,143 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:52,143 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:52,143 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:52,144 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:52,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-11-23 10:28:52,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 34 transitions. [2018-11-23 10:28:52,149 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 34 transitions. Word has length 16 [2018-11-23 10:28:52,149 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:52,149 INFO L480 AbstractCegarLoop]: Abstraction has 30 states and 34 transitions. [2018-11-23 10:28:52,150 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 10:28:52,150 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 34 transitions. [2018-11-23 10:28:52,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-11-23 10:28:52,151 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:52,151 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:52,151 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:52,152 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:52,152 INFO L82 PathProgramCache]: Analyzing trace with hash 1455678983, now seen corresponding path program 1 times [2018-11-23 10:28:52,153 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:52,153 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:52,183 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:52,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:52,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:52,407 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:52,692 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification that was a NOOP. DAG size: 12 [2018-11-23 10:28:52,752 INFO L256 TraceCheckUtils]: 0: Hoare triple {267#true} call ULTIMATE.init(); {267#true} is VALID [2018-11-23 10:28:52,753 INFO L273 TraceCheckUtils]: 1: Hoare triple {267#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {267#true} is VALID [2018-11-23 10:28:52,753 INFO L273 TraceCheckUtils]: 2: Hoare triple {267#true} assume true; {267#true} is VALID [2018-11-23 10:28:52,754 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {267#true} {267#true} #83#return; {267#true} is VALID [2018-11-23 10:28:52,754 INFO L256 TraceCheckUtils]: 4: Hoare triple {267#true} call #t~ret8 := main(); {267#true} is VALID [2018-11-23 10:28:52,755 INFO L273 TraceCheckUtils]: 5: Hoare triple {267#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {267#true} is VALID [2018-11-23 10:28:52,756 INFO L273 TraceCheckUtils]: 6: Hoare triple {267#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {290#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} is VALID [2018-11-23 10:28:52,757 INFO L273 TraceCheckUtils]: 7: Hoare triple {290#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {294#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv5 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:52,777 INFO L273 TraceCheckUtils]: 8: Hoare triple {294#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv5 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {268#false} is VALID [2018-11-23 10:28:52,777 INFO L273 TraceCheckUtils]: 9: Hoare triple {268#false} ~i~0 := 0bv32; {268#false} is VALID [2018-11-23 10:28:52,778 INFO L273 TraceCheckUtils]: 10: Hoare triple {268#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {268#false} is VALID [2018-11-23 10:28:52,778 INFO L273 TraceCheckUtils]: 11: Hoare triple {268#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {268#false} is VALID [2018-11-23 10:28:52,778 INFO L256 TraceCheckUtils]: 12: Hoare triple {268#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {268#false} is VALID [2018-11-23 10:28:52,779 INFO L273 TraceCheckUtils]: 13: Hoare triple {268#false} ~cond := #in~cond; {268#false} is VALID [2018-11-23 10:28:52,779 INFO L273 TraceCheckUtils]: 14: Hoare triple {268#false} assume 0bv32 == ~cond; {268#false} is VALID [2018-11-23 10:28:52,779 INFO L273 TraceCheckUtils]: 15: Hoare triple {268#false} assume !false; {268#false} is VALID [2018-11-23 10:28:52,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:52,781 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:28:52,785 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:28:52,785 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 10:28:52,788 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-11-23 10:28:52,788 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:52,789 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-23 10:28:52,841 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:52,841 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 10:28:52,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 10:28:52,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:28:52,842 INFO L87 Difference]: Start difference. First operand 30 states and 34 transitions. Second operand 4 states. [2018-11-23 10:28:53,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:53,917 INFO L93 Difference]: Finished difference Result 52 states and 60 transitions. [2018-11-23 10:28:53,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 10:28:53,917 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-11-23 10:28:53,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:53,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:28:53,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 50 transitions. [2018-11-23 10:28:53,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:28:53,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 50 transitions. [2018-11-23 10:28:53,924 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 50 transitions. [2018-11-23 10:28:54,196 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 50 edges. 50 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:54,199 INFO L225 Difference]: With dead ends: 52 [2018-11-23 10:28:54,200 INFO L226 Difference]: Without dead ends: 35 [2018-11-23 10:28:54,201 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:28:54,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-11-23 10:28:54,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 31. [2018-11-23 10:28:54,272 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:54,272 INFO L82 GeneralOperation]: Start isEquivalent. First operand 35 states. Second operand 31 states. [2018-11-23 10:28:54,272 INFO L74 IsIncluded]: Start isIncluded. First operand 35 states. Second operand 31 states. [2018-11-23 10:28:54,272 INFO L87 Difference]: Start difference. First operand 35 states. Second operand 31 states. [2018-11-23 10:28:54,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:54,276 INFO L93 Difference]: Finished difference Result 35 states and 41 transitions. [2018-11-23 10:28:54,276 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 41 transitions. [2018-11-23 10:28:54,276 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:54,277 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:54,277 INFO L74 IsIncluded]: Start isIncluded. First operand 31 states. Second operand 35 states. [2018-11-23 10:28:54,277 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 35 states. [2018-11-23 10:28:54,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:54,280 INFO L93 Difference]: Finished difference Result 35 states and 41 transitions. [2018-11-23 10:28:54,281 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 41 transitions. [2018-11-23 10:28:54,281 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:54,282 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:54,282 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:54,282 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:54,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-11-23 10:28:54,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 35 transitions. [2018-11-23 10:28:54,285 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 35 transitions. Word has length 16 [2018-11-23 10:28:54,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:54,285 INFO L480 AbstractCegarLoop]: Abstraction has 31 states and 35 transitions. [2018-11-23 10:28:54,285 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 10:28:54,286 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2018-11-23 10:28:54,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-11-23 10:28:54,287 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:54,287 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:54,287 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:54,287 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:54,288 INFO L82 PathProgramCache]: Analyzing trace with hash -2089835012, now seen corresponding path program 1 times [2018-11-23 10:28:54,288 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:54,288 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:54,305 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:54,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:54,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:54,445 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:54,497 INFO L256 TraceCheckUtils]: 0: Hoare triple {501#true} call ULTIMATE.init(); {501#true} is VALID [2018-11-23 10:28:54,498 INFO L273 TraceCheckUtils]: 1: Hoare triple {501#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {501#true} is VALID [2018-11-23 10:28:54,498 INFO L273 TraceCheckUtils]: 2: Hoare triple {501#true} assume true; {501#true} is VALID [2018-11-23 10:28:54,498 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {501#true} {501#true} #83#return; {501#true} is VALID [2018-11-23 10:28:54,499 INFO L256 TraceCheckUtils]: 4: Hoare triple {501#true} call #t~ret8 := main(); {501#true} is VALID [2018-11-23 10:28:54,499 INFO L273 TraceCheckUtils]: 5: Hoare triple {501#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {501#true} is VALID [2018-11-23 10:28:54,499 INFO L273 TraceCheckUtils]: 6: Hoare triple {501#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {501#true} is VALID [2018-11-23 10:28:54,499 INFO L273 TraceCheckUtils]: 7: Hoare triple {501#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {501#true} is VALID [2018-11-23 10:28:54,500 INFO L273 TraceCheckUtils]: 8: Hoare triple {501#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {530#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:54,501 INFO L273 TraceCheckUtils]: 9: Hoare triple {530#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume !~bvsge32(~j~0, 1bv32); {502#false} is VALID [2018-11-23 10:28:54,501 INFO L273 TraceCheckUtils]: 10: Hoare triple {502#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {502#false} is VALID [2018-11-23 10:28:54,501 INFO L273 TraceCheckUtils]: 11: Hoare triple {502#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {502#false} is VALID [2018-11-23 10:28:54,502 INFO L273 TraceCheckUtils]: 12: Hoare triple {502#false} ~i~0 := 0bv32; {502#false} is VALID [2018-11-23 10:28:54,502 INFO L273 TraceCheckUtils]: 13: Hoare triple {502#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {502#false} is VALID [2018-11-23 10:28:54,502 INFO L273 TraceCheckUtils]: 14: Hoare triple {502#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {502#false} is VALID [2018-11-23 10:28:54,503 INFO L256 TraceCheckUtils]: 15: Hoare triple {502#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {502#false} is VALID [2018-11-23 10:28:54,503 INFO L273 TraceCheckUtils]: 16: Hoare triple {502#false} ~cond := #in~cond; {502#false} is VALID [2018-11-23 10:28:54,503 INFO L273 TraceCheckUtils]: 17: Hoare triple {502#false} assume 0bv32 == ~cond; {502#false} is VALID [2018-11-23 10:28:54,503 INFO L273 TraceCheckUtils]: 18: Hoare triple {502#false} assume !false; {502#false} is VALID [2018-11-23 10:28:54,504 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:54,505 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:28:54,509 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:28:54,509 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 10:28:54,509 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2018-11-23 10:28:54,510 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:54,510 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-23 10:28:54,609 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 19 edges. 19 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:54,610 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 10:28:54,610 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 10:28:54,610 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:28:54,611 INFO L87 Difference]: Start difference. First operand 31 states and 35 transitions. Second operand 3 states. [2018-11-23 10:28:54,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:54,845 INFO L93 Difference]: Finished difference Result 56 states and 66 transitions. [2018-11-23 10:28:54,846 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 10:28:54,846 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2018-11-23 10:28:54,846 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:54,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:28:54,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 55 transitions. [2018-11-23 10:28:54,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:28:54,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 55 transitions. [2018-11-23 10:28:54,852 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 55 transitions. [2018-11-23 10:28:55,029 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 55 edges. 55 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:55,032 INFO L225 Difference]: With dead ends: 56 [2018-11-23 10:28:55,032 INFO L226 Difference]: Without dead ends: 34 [2018-11-23 10:28:55,033 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:28:55,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-11-23 10:28:55,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 32. [2018-11-23 10:28:55,064 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:55,065 INFO L82 GeneralOperation]: Start isEquivalent. First operand 34 states. Second operand 32 states. [2018-11-23 10:28:55,065 INFO L74 IsIncluded]: Start isIncluded. First operand 34 states. Second operand 32 states. [2018-11-23 10:28:55,065 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 32 states. [2018-11-23 10:28:55,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:55,068 INFO L93 Difference]: Finished difference Result 34 states and 39 transitions. [2018-11-23 10:28:55,068 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 39 transitions. [2018-11-23 10:28:55,069 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:55,069 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:55,069 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand 34 states. [2018-11-23 10:28:55,069 INFO L87 Difference]: Start difference. First operand 32 states. Second operand 34 states. [2018-11-23 10:28:55,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:55,072 INFO L93 Difference]: Finished difference Result 34 states and 39 transitions. [2018-11-23 10:28:55,073 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 39 transitions. [2018-11-23 10:28:55,073 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:55,074 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:55,074 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:55,074 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:55,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2018-11-23 10:28:55,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 36 transitions. [2018-11-23 10:28:55,077 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 36 transitions. Word has length 19 [2018-11-23 10:28:55,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:55,077 INFO L480 AbstractCegarLoop]: Abstraction has 32 states and 36 transitions. [2018-11-23 10:28:55,077 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 10:28:55,077 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 36 transitions. [2018-11-23 10:28:55,078 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-23 10:28:55,078 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:55,079 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:55,079 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:55,079 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:55,079 INFO L82 PathProgramCache]: Analyzing trace with hash 1382648830, now seen corresponding path program 1 times [2018-11-23 10:28:55,080 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:55,080 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:55,114 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:55,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:55,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:55,225 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:55,327 INFO L256 TraceCheckUtils]: 0: Hoare triple {749#true} call ULTIMATE.init(); {749#true} is VALID [2018-11-23 10:28:55,327 INFO L273 TraceCheckUtils]: 1: Hoare triple {749#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {749#true} is VALID [2018-11-23 10:28:55,328 INFO L273 TraceCheckUtils]: 2: Hoare triple {749#true} assume true; {749#true} is VALID [2018-11-23 10:28:55,328 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {749#true} {749#true} #83#return; {749#true} is VALID [2018-11-23 10:28:55,328 INFO L256 TraceCheckUtils]: 4: Hoare triple {749#true} call #t~ret8 := main(); {749#true} is VALID [2018-11-23 10:28:55,329 INFO L273 TraceCheckUtils]: 5: Hoare triple {749#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {749#true} is VALID [2018-11-23 10:28:55,344 INFO L273 TraceCheckUtils]: 6: Hoare triple {749#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {772#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,358 INFO L273 TraceCheckUtils]: 7: Hoare triple {772#(= (_ bv2 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {772#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,367 INFO L273 TraceCheckUtils]: 8: Hoare triple {772#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {779#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:55,380 INFO L273 TraceCheckUtils]: 9: Hoare triple {779#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {779#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:55,394 INFO L273 TraceCheckUtils]: 10: Hoare triple {779#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {750#false} is VALID [2018-11-23 10:28:55,394 INFO L273 TraceCheckUtils]: 11: Hoare triple {750#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {750#false} is VALID [2018-11-23 10:28:55,395 INFO L273 TraceCheckUtils]: 12: Hoare triple {750#false} assume !~bvsge32(~j~0, 1bv32); {750#false} is VALID [2018-11-23 10:28:55,395 INFO L273 TraceCheckUtils]: 13: Hoare triple {750#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {750#false} is VALID [2018-11-23 10:28:55,395 INFO L273 TraceCheckUtils]: 14: Hoare triple {750#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {750#false} is VALID [2018-11-23 10:28:55,395 INFO L273 TraceCheckUtils]: 15: Hoare triple {750#false} ~i~0 := 0bv32; {750#false} is VALID [2018-11-23 10:28:55,396 INFO L273 TraceCheckUtils]: 16: Hoare triple {750#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {750#false} is VALID [2018-11-23 10:28:55,396 INFO L273 TraceCheckUtils]: 17: Hoare triple {750#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {750#false} is VALID [2018-11-23 10:28:55,396 INFO L256 TraceCheckUtils]: 18: Hoare triple {750#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {750#false} is VALID [2018-11-23 10:28:55,397 INFO L273 TraceCheckUtils]: 19: Hoare triple {750#false} ~cond := #in~cond; {750#false} is VALID [2018-11-23 10:28:55,397 INFO L273 TraceCheckUtils]: 20: Hoare triple {750#false} assume 0bv32 == ~cond; {750#false} is VALID [2018-11-23 10:28:55,397 INFO L273 TraceCheckUtils]: 21: Hoare triple {750#false} assume !false; {750#false} is VALID [2018-11-23 10:28:55,399 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:55,399 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:28:55,404 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:28:55,405 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 10:28:55,405 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 22 [2018-11-23 10:28:55,405 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:55,406 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-23 10:28:55,523 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 22 edges. 22 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:55,523 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 10:28:55,524 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 10:28:55,524 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:28:55,524 INFO L87 Difference]: Start difference. First operand 32 states and 36 transitions. Second operand 4 states. [2018-11-23 10:28:55,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:55,872 INFO L93 Difference]: Finished difference Result 57 states and 66 transitions. [2018-11-23 10:28:55,873 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 10:28:55,873 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 22 [2018-11-23 10:28:55,873 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:55,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:28:55,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 54 transitions. [2018-11-23 10:28:55,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:28:55,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 54 transitions. [2018-11-23 10:28:55,878 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 54 transitions. [2018-11-23 10:28:56,057 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 54 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:56,059 INFO L225 Difference]: With dead ends: 57 [2018-11-23 10:28:56,059 INFO L226 Difference]: Without dead ends: 34 [2018-11-23 10:28:56,060 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:28:56,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-11-23 10:28:56,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 33. [2018-11-23 10:28:56,100 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:56,100 INFO L82 GeneralOperation]: Start isEquivalent. First operand 34 states. Second operand 33 states. [2018-11-23 10:28:56,100 INFO L74 IsIncluded]: Start isIncluded. First operand 34 states. Second operand 33 states. [2018-11-23 10:28:56,101 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 33 states. [2018-11-23 10:28:56,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:56,103 INFO L93 Difference]: Finished difference Result 34 states and 38 transitions. [2018-11-23 10:28:56,103 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 38 transitions. [2018-11-23 10:28:56,104 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:56,104 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:56,104 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand 34 states. [2018-11-23 10:28:56,104 INFO L87 Difference]: Start difference. First operand 33 states. Second operand 34 states. [2018-11-23 10:28:56,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:56,107 INFO L93 Difference]: Finished difference Result 34 states and 38 transitions. [2018-11-23 10:28:56,107 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 38 transitions. [2018-11-23 10:28:56,108 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:56,108 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:56,108 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:56,108 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:56,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-11-23 10:28:56,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 37 transitions. [2018-11-23 10:28:56,110 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 37 transitions. Word has length 22 [2018-11-23 10:28:56,110 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:56,111 INFO L480 AbstractCegarLoop]: Abstraction has 33 states and 37 transitions. [2018-11-23 10:28:56,111 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 10:28:56,111 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 37 transitions. [2018-11-23 10:28:56,112 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-23 10:28:56,112 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:56,112 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:56,112 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:56,113 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:56,113 INFO L82 PathProgramCache]: Analyzing trace with hash 1124483392, now seen corresponding path program 1 times [2018-11-23 10:28:56,113 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:56,113 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:56,137 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:56,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:56,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:56,268 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:56,372 INFO L256 TraceCheckUtils]: 0: Hoare triple {1010#true} call ULTIMATE.init(); {1010#true} is VALID [2018-11-23 10:28:56,372 INFO L273 TraceCheckUtils]: 1: Hoare triple {1010#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1010#true} is VALID [2018-11-23 10:28:56,372 INFO L273 TraceCheckUtils]: 2: Hoare triple {1010#true} assume true; {1010#true} is VALID [2018-11-23 10:28:56,373 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1010#true} {1010#true} #83#return; {1010#true} is VALID [2018-11-23 10:28:56,373 INFO L256 TraceCheckUtils]: 4: Hoare triple {1010#true} call #t~ret8 := main(); {1010#true} is VALID [2018-11-23 10:28:56,373 INFO L273 TraceCheckUtils]: 5: Hoare triple {1010#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1010#true} is VALID [2018-11-23 10:28:56,373 INFO L273 TraceCheckUtils]: 6: Hoare triple {1010#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1010#true} is VALID [2018-11-23 10:28:56,374 INFO L273 TraceCheckUtils]: 7: Hoare triple {1010#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1010#true} is VALID [2018-11-23 10:28:56,377 INFO L273 TraceCheckUtils]: 8: Hoare triple {1010#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {1039#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:56,378 INFO L273 TraceCheckUtils]: 9: Hoare triple {1039#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {1039#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:56,379 INFO L273 TraceCheckUtils]: 10: Hoare triple {1039#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1039#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:56,381 INFO L273 TraceCheckUtils]: 11: Hoare triple {1039#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1049#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:56,383 INFO L273 TraceCheckUtils]: 12: Hoare triple {1049#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume !~bvsge32(~j~0, 1bv32); {1011#false} is VALID [2018-11-23 10:28:56,383 INFO L273 TraceCheckUtils]: 13: Hoare triple {1011#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1011#false} is VALID [2018-11-23 10:28:56,383 INFO L273 TraceCheckUtils]: 14: Hoare triple {1011#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {1011#false} is VALID [2018-11-23 10:28:56,383 INFO L273 TraceCheckUtils]: 15: Hoare triple {1011#false} ~i~0 := 0bv32; {1011#false} is VALID [2018-11-23 10:28:56,384 INFO L273 TraceCheckUtils]: 16: Hoare triple {1011#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1011#false} is VALID [2018-11-23 10:28:56,384 INFO L273 TraceCheckUtils]: 17: Hoare triple {1011#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1011#false} is VALID [2018-11-23 10:28:56,384 INFO L256 TraceCheckUtils]: 18: Hoare triple {1011#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1011#false} is VALID [2018-11-23 10:28:56,384 INFO L273 TraceCheckUtils]: 19: Hoare triple {1011#false} ~cond := #in~cond; {1011#false} is VALID [2018-11-23 10:28:56,385 INFO L273 TraceCheckUtils]: 20: Hoare triple {1011#false} assume 0bv32 == ~cond; {1011#false} is VALID [2018-11-23 10:28:56,385 INFO L273 TraceCheckUtils]: 21: Hoare triple {1011#false} assume !false; {1011#false} is VALID [2018-11-23 10:28:56,386 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:56,386 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:28:56,603 INFO L273 TraceCheckUtils]: 21: Hoare triple {1011#false} assume !false; {1011#false} is VALID [2018-11-23 10:28:56,603 INFO L273 TraceCheckUtils]: 20: Hoare triple {1011#false} assume 0bv32 == ~cond; {1011#false} is VALID [2018-11-23 10:28:56,604 INFO L273 TraceCheckUtils]: 19: Hoare triple {1011#false} ~cond := #in~cond; {1011#false} is VALID [2018-11-23 10:28:56,604 INFO L256 TraceCheckUtils]: 18: Hoare triple {1011#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1011#false} is VALID [2018-11-23 10:28:56,605 INFO L273 TraceCheckUtils]: 17: Hoare triple {1011#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1011#false} is VALID [2018-11-23 10:28:56,605 INFO L273 TraceCheckUtils]: 16: Hoare triple {1011#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1011#false} is VALID [2018-11-23 10:28:56,605 INFO L273 TraceCheckUtils]: 15: Hoare triple {1011#false} ~i~0 := 0bv32; {1011#false} is VALID [2018-11-23 10:28:56,605 INFO L273 TraceCheckUtils]: 14: Hoare triple {1011#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {1011#false} is VALID [2018-11-23 10:28:56,606 INFO L273 TraceCheckUtils]: 13: Hoare triple {1011#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1011#false} is VALID [2018-11-23 10:28:56,618 INFO L273 TraceCheckUtils]: 12: Hoare triple {1107#(bvsge main_~j~0 (_ bv1 32))} assume !~bvsge32(~j~0, 1bv32); {1011#false} is VALID [2018-11-23 10:28:56,637 INFO L273 TraceCheckUtils]: 11: Hoare triple {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1107#(bvsge main_~j~0 (_ bv1 32))} is VALID [2018-11-23 10:28:56,647 INFO L273 TraceCheckUtils]: 10: Hoare triple {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:56,659 INFO L273 TraceCheckUtils]: 9: Hoare triple {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume !!~bvsge32(~j~0, 1bv32); {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:56,673 INFO L273 TraceCheckUtils]: 8: Hoare triple {1010#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:56,673 INFO L273 TraceCheckUtils]: 7: Hoare triple {1010#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1010#true} is VALID [2018-11-23 10:28:56,673 INFO L273 TraceCheckUtils]: 6: Hoare triple {1010#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1010#true} is VALID [2018-11-23 10:28:56,674 INFO L273 TraceCheckUtils]: 5: Hoare triple {1010#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1010#true} is VALID [2018-11-23 10:28:56,674 INFO L256 TraceCheckUtils]: 4: Hoare triple {1010#true} call #t~ret8 := main(); {1010#true} is VALID [2018-11-23 10:28:56,674 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1010#true} {1010#true} #83#return; {1010#true} is VALID [2018-11-23 10:28:56,675 INFO L273 TraceCheckUtils]: 2: Hoare triple {1010#true} assume true; {1010#true} is VALID [2018-11-23 10:28:56,675 INFO L273 TraceCheckUtils]: 1: Hoare triple {1010#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1010#true} is VALID [2018-11-23 10:28:56,675 INFO L256 TraceCheckUtils]: 0: Hoare triple {1010#true} call ULTIMATE.init(); {1010#true} is VALID [2018-11-23 10:28:56,677 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:56,679 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:28:56,680 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 6 [2018-11-23 10:28:56,680 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-11-23 10:28:56,681 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:56,681 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states. [2018-11-23 10:28:56,861 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 27 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:56,862 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 10:28:56,862 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 10:28:56,862 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-23 10:28:56,863 INFO L87 Difference]: Start difference. First operand 33 states and 37 transitions. Second operand 6 states. [2018-11-23 10:28:57,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:57,435 INFO L93 Difference]: Finished difference Result 65 states and 78 transitions. [2018-11-23 10:28:57,435 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 10:28:57,435 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-11-23 10:28:57,436 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:57,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-23 10:28:57,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 65 transitions. [2018-11-23 10:28:57,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-23 10:28:57,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 65 transitions. [2018-11-23 10:28:57,441 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 65 transitions. [2018-11-23 10:28:57,685 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 65 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:57,686 INFO L225 Difference]: With dead ends: 65 [2018-11-23 10:28:57,686 INFO L226 Difference]: Without dead ends: 41 [2018-11-23 10:28:57,687 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2018-11-23 10:28:57,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2018-11-23 10:28:57,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 41. [2018-11-23 10:28:57,724 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:57,724 INFO L82 GeneralOperation]: Start isEquivalent. First operand 41 states. Second operand 41 states. [2018-11-23 10:28:57,724 INFO L74 IsIncluded]: Start isIncluded. First operand 41 states. Second operand 41 states. [2018-11-23 10:28:57,725 INFO L87 Difference]: Start difference. First operand 41 states. Second operand 41 states. [2018-11-23 10:28:57,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:57,727 INFO L93 Difference]: Finished difference Result 41 states and 47 transitions. [2018-11-23 10:28:57,727 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 47 transitions. [2018-11-23 10:28:57,728 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:57,728 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:57,728 INFO L74 IsIncluded]: Start isIncluded. First operand 41 states. Second operand 41 states. [2018-11-23 10:28:57,728 INFO L87 Difference]: Start difference. First operand 41 states. Second operand 41 states. [2018-11-23 10:28:57,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:57,731 INFO L93 Difference]: Finished difference Result 41 states and 47 transitions. [2018-11-23 10:28:57,731 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 47 transitions. [2018-11-23 10:28:57,731 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:57,732 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:57,732 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:57,732 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:57,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-11-23 10:28:57,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 47 transitions. [2018-11-23 10:28:57,734 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 47 transitions. Word has length 22 [2018-11-23 10:28:57,735 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:57,735 INFO L480 AbstractCegarLoop]: Abstraction has 41 states and 47 transitions. [2018-11-23 10:28:57,735 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 10:28:57,735 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 47 transitions. [2018-11-23 10:28:57,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-11-23 10:28:57,736 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:57,736 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:57,736 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:57,737 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:57,737 INFO L82 PathProgramCache]: Analyzing trace with hash 1422556282, now seen corresponding path program 1 times [2018-11-23 10:28:57,737 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:57,738 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:57,759 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:57,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:57,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:57,881 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:57,967 INFO L256 TraceCheckUtils]: 0: Hoare triple {1377#true} call ULTIMATE.init(); {1377#true} is VALID [2018-11-23 10:28:57,968 INFO L273 TraceCheckUtils]: 1: Hoare triple {1377#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1377#true} is VALID [2018-11-23 10:28:57,968 INFO L273 TraceCheckUtils]: 2: Hoare triple {1377#true} assume true; {1377#true} is VALID [2018-11-23 10:28:57,969 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1377#true} {1377#true} #83#return; {1377#true} is VALID [2018-11-23 10:28:57,969 INFO L256 TraceCheckUtils]: 4: Hoare triple {1377#true} call #t~ret8 := main(); {1377#true} is VALID [2018-11-23 10:28:57,970 INFO L273 TraceCheckUtils]: 5: Hoare triple {1377#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1377#true} is VALID [2018-11-23 10:28:57,979 INFO L273 TraceCheckUtils]: 6: Hoare triple {1377#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1400#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:57,986 INFO L273 TraceCheckUtils]: 7: Hoare triple {1400#(= (_ bv2 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1400#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:57,987 INFO L273 TraceCheckUtils]: 8: Hoare triple {1400#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {1407#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:57,988 INFO L273 TraceCheckUtils]: 9: Hoare triple {1407#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {1407#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:57,989 INFO L273 TraceCheckUtils]: 10: Hoare triple {1407#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1407#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:57,992 INFO L273 TraceCheckUtils]: 11: Hoare triple {1407#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1417#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:57,993 INFO L273 TraceCheckUtils]: 12: Hoare triple {1417#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {1417#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:57,994 INFO L273 TraceCheckUtils]: 13: Hoare triple {1417#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1378#false} is VALID [2018-11-23 10:28:57,994 INFO L273 TraceCheckUtils]: 14: Hoare triple {1378#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1378#false} is VALID [2018-11-23 10:28:57,994 INFO L273 TraceCheckUtils]: 15: Hoare triple {1378#false} assume !!~bvsge32(~j~0, 1bv32); {1378#false} is VALID [2018-11-23 10:28:57,995 INFO L273 TraceCheckUtils]: 16: Hoare triple {1378#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1378#false} is VALID [2018-11-23 10:28:57,995 INFO L273 TraceCheckUtils]: 17: Hoare triple {1378#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1378#false} is VALID [2018-11-23 10:28:57,995 INFO L273 TraceCheckUtils]: 18: Hoare triple {1378#false} assume !!~bvsge32(~j~0, 1bv32); {1378#false} is VALID [2018-11-23 10:28:57,995 INFO L273 TraceCheckUtils]: 19: Hoare triple {1378#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1378#false} is VALID [2018-11-23 10:28:57,995 INFO L273 TraceCheckUtils]: 20: Hoare triple {1378#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1378#false} is VALID [2018-11-23 10:28:57,996 INFO L273 TraceCheckUtils]: 21: Hoare triple {1378#false} assume !~bvsge32(~j~0, 1bv32); {1378#false} is VALID [2018-11-23 10:28:57,996 INFO L273 TraceCheckUtils]: 22: Hoare triple {1378#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1378#false} is VALID [2018-11-23 10:28:57,996 INFO L273 TraceCheckUtils]: 23: Hoare triple {1378#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {1378#false} is VALID [2018-11-23 10:28:57,996 INFO L273 TraceCheckUtils]: 24: Hoare triple {1378#false} ~i~0 := 0bv32; {1378#false} is VALID [2018-11-23 10:28:57,996 INFO L273 TraceCheckUtils]: 25: Hoare triple {1378#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1378#false} is VALID [2018-11-23 10:28:57,997 INFO L273 TraceCheckUtils]: 26: Hoare triple {1378#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1378#false} is VALID [2018-11-23 10:28:57,997 INFO L256 TraceCheckUtils]: 27: Hoare triple {1378#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1378#false} is VALID [2018-11-23 10:28:57,997 INFO L273 TraceCheckUtils]: 28: Hoare triple {1378#false} ~cond := #in~cond; {1378#false} is VALID [2018-11-23 10:28:57,997 INFO L273 TraceCheckUtils]: 29: Hoare triple {1378#false} assume 0bv32 == ~cond; {1378#false} is VALID [2018-11-23 10:28:57,998 INFO L273 TraceCheckUtils]: 30: Hoare triple {1378#false} assume !false; {1378#false} is VALID [2018-11-23 10:28:58,000 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 14 proven. 2 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-23 10:28:58,000 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:28:58,138 INFO L273 TraceCheckUtils]: 30: Hoare triple {1378#false} assume !false; {1378#false} is VALID [2018-11-23 10:28:58,138 INFO L273 TraceCheckUtils]: 29: Hoare triple {1378#false} assume 0bv32 == ~cond; {1378#false} is VALID [2018-11-23 10:28:58,139 INFO L273 TraceCheckUtils]: 28: Hoare triple {1378#false} ~cond := #in~cond; {1378#false} is VALID [2018-11-23 10:28:58,139 INFO L256 TraceCheckUtils]: 27: Hoare triple {1378#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1378#false} is VALID [2018-11-23 10:28:58,139 INFO L273 TraceCheckUtils]: 26: Hoare triple {1378#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1378#false} is VALID [2018-11-23 10:28:58,140 INFO L273 TraceCheckUtils]: 25: Hoare triple {1378#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1378#false} is VALID [2018-11-23 10:28:58,140 INFO L273 TraceCheckUtils]: 24: Hoare triple {1378#false} ~i~0 := 0bv32; {1378#false} is VALID [2018-11-23 10:28:58,140 INFO L273 TraceCheckUtils]: 23: Hoare triple {1378#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {1378#false} is VALID [2018-11-23 10:28:58,140 INFO L273 TraceCheckUtils]: 22: Hoare triple {1378#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1378#false} is VALID [2018-11-23 10:28:58,140 INFO L273 TraceCheckUtils]: 21: Hoare triple {1378#false} assume !~bvsge32(~j~0, 1bv32); {1378#false} is VALID [2018-11-23 10:28:58,141 INFO L273 TraceCheckUtils]: 20: Hoare triple {1378#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1378#false} is VALID [2018-11-23 10:28:58,141 INFO L273 TraceCheckUtils]: 19: Hoare triple {1378#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1378#false} is VALID [2018-11-23 10:28:58,141 INFO L273 TraceCheckUtils]: 18: Hoare triple {1378#false} assume !!~bvsge32(~j~0, 1bv32); {1378#false} is VALID [2018-11-23 10:28:58,141 INFO L273 TraceCheckUtils]: 17: Hoare triple {1378#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1378#false} is VALID [2018-11-23 10:28:58,141 INFO L273 TraceCheckUtils]: 16: Hoare triple {1378#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1378#false} is VALID [2018-11-23 10:28:58,142 INFO L273 TraceCheckUtils]: 15: Hoare triple {1378#false} assume !!~bvsge32(~j~0, 1bv32); {1378#false} is VALID [2018-11-23 10:28:58,142 INFO L273 TraceCheckUtils]: 14: Hoare triple {1378#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1378#false} is VALID [2018-11-23 10:28:58,142 INFO L273 TraceCheckUtils]: 13: Hoare triple {1526#(bvsge main_~j~0 main_~MINVAL~0)} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1378#false} is VALID [2018-11-23 10:28:58,143 INFO L273 TraceCheckUtils]: 12: Hoare triple {1526#(bvsge main_~j~0 main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {1526#(bvsge main_~j~0 main_~MINVAL~0)} is VALID [2018-11-23 10:28:58,144 INFO L273 TraceCheckUtils]: 11: Hoare triple {1533#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1526#(bvsge main_~j~0 main_~MINVAL~0)} is VALID [2018-11-23 10:28:58,145 INFO L273 TraceCheckUtils]: 10: Hoare triple {1533#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1533#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} is VALID [2018-11-23 10:28:58,145 INFO L273 TraceCheckUtils]: 9: Hoare triple {1533#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {1533#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} is VALID [2018-11-23 10:28:58,146 INFO L273 TraceCheckUtils]: 8: Hoare triple {1543#(bvsge (_ bv4 32) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {1533#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} is VALID [2018-11-23 10:28:58,147 INFO L273 TraceCheckUtils]: 7: Hoare triple {1543#(bvsge (_ bv4 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1543#(bvsge (_ bv4 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:58,148 INFO L273 TraceCheckUtils]: 6: Hoare triple {1377#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1543#(bvsge (_ bv4 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:58,148 INFO L273 TraceCheckUtils]: 5: Hoare triple {1377#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1377#true} is VALID [2018-11-23 10:28:58,148 INFO L256 TraceCheckUtils]: 4: Hoare triple {1377#true} call #t~ret8 := main(); {1377#true} is VALID [2018-11-23 10:28:58,149 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1377#true} {1377#true} #83#return; {1377#true} is VALID [2018-11-23 10:28:58,149 INFO L273 TraceCheckUtils]: 2: Hoare triple {1377#true} assume true; {1377#true} is VALID [2018-11-23 10:28:58,150 INFO L273 TraceCheckUtils]: 1: Hoare triple {1377#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1377#true} is VALID [2018-11-23 10:28:58,150 INFO L256 TraceCheckUtils]: 0: Hoare triple {1377#true} call ULTIMATE.init(); {1377#true} is VALID [2018-11-23 10:28:58,153 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 14 proven. 2 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-23 10:28:58,156 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:28:58,156 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 8 [2018-11-23 10:28:58,157 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 31 [2018-11-23 10:28:58,157 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:58,157 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 8 states. [2018-11-23 10:28:58,304 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 35 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:58,304 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 10:28:58,305 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 10:28:58,305 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 10:28:58,305 INFO L87 Difference]: Start difference. First operand 41 states and 47 transitions. Second operand 8 states. [2018-11-23 10:28:58,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:58,960 INFO L93 Difference]: Finished difference Result 75 states and 88 transitions. [2018-11-23 10:28:58,960 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 10:28:58,960 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 31 [2018-11-23 10:28:58,961 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:58,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2018-11-23 10:28:58,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 65 transitions. [2018-11-23 10:28:58,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2018-11-23 10:28:58,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 65 transitions. [2018-11-23 10:28:58,970 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 7 states and 65 transitions. [2018-11-23 10:28:59,140 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 65 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:59,142 INFO L225 Difference]: With dead ends: 75 [2018-11-23 10:28:59,142 INFO L226 Difference]: Without dead ends: 43 [2018-11-23 10:28:59,143 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-11-23 10:28:59,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-11-23 10:28:59,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 42. [2018-11-23 10:28:59,207 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:59,208 INFO L82 GeneralOperation]: Start isEquivalent. First operand 43 states. Second operand 42 states. [2018-11-23 10:28:59,208 INFO L74 IsIncluded]: Start isIncluded. First operand 43 states. Second operand 42 states. [2018-11-23 10:28:59,208 INFO L87 Difference]: Start difference. First operand 43 states. Second operand 42 states. [2018-11-23 10:28:59,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:59,210 INFO L93 Difference]: Finished difference Result 43 states and 47 transitions. [2018-11-23 10:28:59,210 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 47 transitions. [2018-11-23 10:28:59,211 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:59,211 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:59,211 INFO L74 IsIncluded]: Start isIncluded. First operand 42 states. Second operand 43 states. [2018-11-23 10:28:59,211 INFO L87 Difference]: Start difference. First operand 42 states. Second operand 43 states. [2018-11-23 10:28:59,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:59,214 INFO L93 Difference]: Finished difference Result 43 states and 47 transitions. [2018-11-23 10:28:59,214 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 47 transitions. [2018-11-23 10:28:59,214 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:59,215 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:59,215 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:59,215 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:59,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-11-23 10:28:59,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 46 transitions. [2018-11-23 10:28:59,217 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 46 transitions. Word has length 31 [2018-11-23 10:28:59,217 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:59,217 INFO L480 AbstractCegarLoop]: Abstraction has 42 states and 46 transitions. [2018-11-23 10:28:59,217 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 10:28:59,218 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 46 transitions. [2018-11-23 10:28:59,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-11-23 10:28:59,218 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:59,219 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:59,219 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:59,219 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:59,219 INFO L82 PathProgramCache]: Analyzing trace with hash 143431932, now seen corresponding path program 2 times [2018-11-23 10:28:59,220 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:59,220 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:59,251 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 10:28:59,502 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 10:28:59,502 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:28:59,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:59,547 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:59,638 INFO L256 TraceCheckUtils]: 0: Hoare triple {1820#true} call ULTIMATE.init(); {1820#true} is VALID [2018-11-23 10:28:59,638 INFO L273 TraceCheckUtils]: 1: Hoare triple {1820#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1820#true} is VALID [2018-11-23 10:28:59,639 INFO L273 TraceCheckUtils]: 2: Hoare triple {1820#true} assume true; {1820#true} is VALID [2018-11-23 10:28:59,639 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1820#true} {1820#true} #83#return; {1820#true} is VALID [2018-11-23 10:28:59,639 INFO L256 TraceCheckUtils]: 4: Hoare triple {1820#true} call #t~ret8 := main(); {1820#true} is VALID [2018-11-23 10:28:59,640 INFO L273 TraceCheckUtils]: 5: Hoare triple {1820#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1820#true} is VALID [2018-11-23 10:28:59,640 INFO L273 TraceCheckUtils]: 6: Hoare triple {1820#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1820#true} is VALID [2018-11-23 10:28:59,640 INFO L273 TraceCheckUtils]: 7: Hoare triple {1820#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1820#true} is VALID [2018-11-23 10:28:59,641 INFO L273 TraceCheckUtils]: 8: Hoare triple {1820#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {1849#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:59,641 INFO L273 TraceCheckUtils]: 9: Hoare triple {1849#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {1849#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:59,642 INFO L273 TraceCheckUtils]: 10: Hoare triple {1849#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1849#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:59,643 INFO L273 TraceCheckUtils]: 11: Hoare triple {1849#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1859#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:59,643 INFO L273 TraceCheckUtils]: 12: Hoare triple {1859#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {1859#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:59,645 INFO L273 TraceCheckUtils]: 13: Hoare triple {1859#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1859#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:59,646 INFO L273 TraceCheckUtils]: 14: Hoare triple {1859#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1869#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:59,647 INFO L273 TraceCheckUtils]: 15: Hoare triple {1869#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {1869#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:59,648 INFO L273 TraceCheckUtils]: 16: Hoare triple {1869#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1869#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:59,649 INFO L273 TraceCheckUtils]: 17: Hoare triple {1869#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1879#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:59,659 INFO L273 TraceCheckUtils]: 18: Hoare triple {1879#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {1879#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:59,660 INFO L273 TraceCheckUtils]: 19: Hoare triple {1879#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1879#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:59,662 INFO L273 TraceCheckUtils]: 20: Hoare triple {1879#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1889#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:59,663 INFO L273 TraceCheckUtils]: 21: Hoare triple {1889#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !~bvsge32(~j~0, 1bv32); {1821#false} is VALID [2018-11-23 10:28:59,663 INFO L273 TraceCheckUtils]: 22: Hoare triple {1821#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1821#false} is VALID [2018-11-23 10:28:59,663 INFO L273 TraceCheckUtils]: 23: Hoare triple {1821#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {1821#false} is VALID [2018-11-23 10:28:59,664 INFO L273 TraceCheckUtils]: 24: Hoare triple {1821#false} ~i~0 := 0bv32; {1821#false} is VALID [2018-11-23 10:28:59,664 INFO L273 TraceCheckUtils]: 25: Hoare triple {1821#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1821#false} is VALID [2018-11-23 10:28:59,664 INFO L273 TraceCheckUtils]: 26: Hoare triple {1821#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1821#false} is VALID [2018-11-23 10:28:59,665 INFO L256 TraceCheckUtils]: 27: Hoare triple {1821#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1821#false} is VALID [2018-11-23 10:28:59,665 INFO L273 TraceCheckUtils]: 28: Hoare triple {1821#false} ~cond := #in~cond; {1821#false} is VALID [2018-11-23 10:28:59,666 INFO L273 TraceCheckUtils]: 29: Hoare triple {1821#false} assume 0bv32 == ~cond; {1821#false} is VALID [2018-11-23 10:28:59,666 INFO L273 TraceCheckUtils]: 30: Hoare triple {1821#false} assume !false; {1821#false} is VALID [2018-11-23 10:28:59,668 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 1 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:59,668 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:28:59,877 INFO L273 TraceCheckUtils]: 30: Hoare triple {1821#false} assume !false; {1821#false} is VALID [2018-11-23 10:28:59,877 INFO L273 TraceCheckUtils]: 29: Hoare triple {1821#false} assume 0bv32 == ~cond; {1821#false} is VALID [2018-11-23 10:28:59,878 INFO L273 TraceCheckUtils]: 28: Hoare triple {1821#false} ~cond := #in~cond; {1821#false} is VALID [2018-11-23 10:28:59,878 INFO L256 TraceCheckUtils]: 27: Hoare triple {1821#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1821#false} is VALID [2018-11-23 10:28:59,878 INFO L273 TraceCheckUtils]: 26: Hoare triple {1821#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1821#false} is VALID [2018-11-23 10:28:59,879 INFO L273 TraceCheckUtils]: 25: Hoare triple {1821#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1821#false} is VALID [2018-11-23 10:28:59,879 INFO L273 TraceCheckUtils]: 24: Hoare triple {1821#false} ~i~0 := 0bv32; {1821#false} is VALID [2018-11-23 10:28:59,879 INFO L273 TraceCheckUtils]: 23: Hoare triple {1821#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {1821#false} is VALID [2018-11-23 10:28:59,879 INFO L273 TraceCheckUtils]: 22: Hoare triple {1821#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1821#false} is VALID [2018-11-23 10:28:59,880 INFO L273 TraceCheckUtils]: 21: Hoare triple {1947#(bvsge main_~j~0 (_ bv1 32))} assume !~bvsge32(~j~0, 1bv32); {1821#false} is VALID [2018-11-23 10:28:59,882 INFO L273 TraceCheckUtils]: 20: Hoare triple {1951#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1947#(bvsge main_~j~0 (_ bv1 32))} is VALID [2018-11-23 10:28:59,883 INFO L273 TraceCheckUtils]: 19: Hoare triple {1951#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1951#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:59,883 INFO L273 TraceCheckUtils]: 18: Hoare triple {1951#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume !!~bvsge32(~j~0, 1bv32); {1951#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:59,887 INFO L273 TraceCheckUtils]: 17: Hoare triple {1961#(bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1951#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:59,888 INFO L273 TraceCheckUtils]: 16: Hoare triple {1961#(bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1961#(bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:59,888 INFO L273 TraceCheckUtils]: 15: Hoare triple {1961#(bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32))} assume !!~bvsge32(~j~0, 1bv32); {1961#(bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:59,893 INFO L273 TraceCheckUtils]: 14: Hoare triple {1971#(bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1961#(bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:59,894 INFO L273 TraceCheckUtils]: 13: Hoare triple {1971#(bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1971#(bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:59,895 INFO L273 TraceCheckUtils]: 12: Hoare triple {1971#(bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32))} assume !!~bvsge32(~j~0, 1bv32); {1971#(bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:59,899 INFO L273 TraceCheckUtils]: 11: Hoare triple {1981#(bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1971#(bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:59,901 INFO L273 TraceCheckUtils]: 10: Hoare triple {1981#(bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1981#(bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:59,902 INFO L273 TraceCheckUtils]: 9: Hoare triple {1981#(bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32))} assume !!~bvsge32(~j~0, 1bv32); {1981#(bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:59,903 INFO L273 TraceCheckUtils]: 8: Hoare triple {1820#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {1981#(bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:59,904 INFO L273 TraceCheckUtils]: 7: Hoare triple {1820#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1820#true} is VALID [2018-11-23 10:28:59,904 INFO L273 TraceCheckUtils]: 6: Hoare triple {1820#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1820#true} is VALID [2018-11-23 10:28:59,904 INFO L273 TraceCheckUtils]: 5: Hoare triple {1820#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1820#true} is VALID [2018-11-23 10:28:59,905 INFO L256 TraceCheckUtils]: 4: Hoare triple {1820#true} call #t~ret8 := main(); {1820#true} is VALID [2018-11-23 10:28:59,905 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1820#true} {1820#true} #83#return; {1820#true} is VALID [2018-11-23 10:28:59,905 INFO L273 TraceCheckUtils]: 2: Hoare triple {1820#true} assume true; {1820#true} is VALID [2018-11-23 10:28:59,906 INFO L273 TraceCheckUtils]: 1: Hoare triple {1820#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1820#true} is VALID [2018-11-23 10:28:59,906 INFO L256 TraceCheckUtils]: 0: Hoare triple {1820#true} call ULTIMATE.init(); {1820#true} is VALID [2018-11-23 10:28:59,908 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 1 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:59,911 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:28:59,911 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-11-23 10:28:59,912 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 31 [2018-11-23 10:28:59,912 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:59,912 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states. [2018-11-23 10:29:00,064 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 45 edges. 45 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:00,064 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-23 10:29:00,065 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-23 10:29:00,065 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2018-11-23 10:29:00,065 INFO L87 Difference]: Start difference. First operand 42 states and 46 transitions. Second operand 12 states. [2018-11-23 10:29:01,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:01,665 INFO L93 Difference]: Finished difference Result 79 states and 89 transitions. [2018-11-23 10:29:01,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 10:29:01,665 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 31 [2018-11-23 10:29:01,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:29:01,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-23 10:29:01,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 67 transitions. [2018-11-23 10:29:01,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-23 10:29:01,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 67 transitions. [2018-11-23 10:29:01,670 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 8 states and 67 transitions. [2018-11-23 10:29:01,871 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 67 edges. 67 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:01,872 INFO L225 Difference]: With dead ends: 79 [2018-11-23 10:29:01,872 INFO L226 Difference]: Without dead ends: 46 [2018-11-23 10:29:01,873 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 51 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2018-11-23 10:29:01,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-11-23 10:29:01,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 44. [2018-11-23 10:29:01,958 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:29:01,958 INFO L82 GeneralOperation]: Start isEquivalent. First operand 46 states. Second operand 44 states. [2018-11-23 10:29:01,958 INFO L74 IsIncluded]: Start isIncluded. First operand 46 states. Second operand 44 states. [2018-11-23 10:29:01,959 INFO L87 Difference]: Start difference. First operand 46 states. Second operand 44 states. [2018-11-23 10:29:01,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:01,960 INFO L93 Difference]: Finished difference Result 46 states and 51 transitions. [2018-11-23 10:29:01,960 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 51 transitions. [2018-11-23 10:29:01,961 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:29:01,963 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:29:01,963 INFO L74 IsIncluded]: Start isIncluded. First operand 44 states. Second operand 46 states. [2018-11-23 10:29:01,963 INFO L87 Difference]: Start difference. First operand 44 states. Second operand 46 states. [2018-11-23 10:29:01,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:01,965 INFO L93 Difference]: Finished difference Result 46 states and 51 transitions. [2018-11-23 10:29:01,965 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 51 transitions. [2018-11-23 10:29:01,965 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:29:01,965 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:29:01,965 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:29:01,965 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:29:01,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-11-23 10:29:01,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 48 transitions. [2018-11-23 10:29:01,967 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 48 transitions. Word has length 31 [2018-11-23 10:29:01,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:29:01,967 INFO L480 AbstractCegarLoop]: Abstraction has 44 states and 48 transitions. [2018-11-23 10:29:01,967 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-23 10:29:01,967 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 48 transitions. [2018-11-23 10:29:01,968 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-23 10:29:01,968 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:29:01,968 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:29:01,968 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:29:01,968 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:29:01,969 INFO L82 PathProgramCache]: Analyzing trace with hash -700204802, now seen corresponding path program 2 times [2018-11-23 10:29:01,969 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:29:01,969 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:29:01,985 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 10:29:02,345 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 10:29:02,345 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:29:02,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:29:02,416 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:29:02,577 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 16 [2018-11-23 10:29:02,585 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-11-23 10:29:02,590 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:02,594 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:02,620 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:02,621 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:36, output treesize:32 [2018-11-23 10:29:02,947 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 34 [2018-11-23 10:29:03,030 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,031 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,032 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 75 [2018-11-23 10:29:03,035 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:03,045 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:03,087 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:03,088 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:55, output treesize:51 [2018-11-23 10:29:03,295 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 51 [2018-11-23 10:29:03,360 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,362 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,365 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,367 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,369 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,372 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,374 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 190 [2018-11-23 10:29:03,377 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:03,405 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:03,443 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:03,444 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:74, output treesize:70 [2018-11-23 10:29:03,694 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 77 treesize of output 68 [2018-11-23 10:29:03,805 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,807 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,815 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,817 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,820 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,822 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,824 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,827 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,830 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,832 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,834 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,837 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:03,838 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 361 [2018-11-23 10:29:03,841 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:03,896 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:03,938 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:03,939 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:93, output treesize:89 [2018-11-23 10:29:04,393 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-11-23 10:29:04,509 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,511 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,514 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,519 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,521 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,524 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,527 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,530 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,533 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,535 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,537 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,540 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,543 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,545 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,548 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,550 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,553 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,556 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,558 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,561 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:04,563 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 20 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 244 [2018-11-23 10:29:04,566 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:04,628 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:04,652 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:04,653 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:54, output treesize:50 [2018-11-23 10:29:04,843 INFO L256 TraceCheckUtils]: 0: Hoare triple {2277#true} call ULTIMATE.init(); {2277#true} is VALID [2018-11-23 10:29:04,844 INFO L273 TraceCheckUtils]: 1: Hoare triple {2277#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2277#true} is VALID [2018-11-23 10:29:04,844 INFO L273 TraceCheckUtils]: 2: Hoare triple {2277#true} assume true; {2277#true} is VALID [2018-11-23 10:29:04,844 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2277#true} {2277#true} #83#return; {2277#true} is VALID [2018-11-23 10:29:04,844 INFO L256 TraceCheckUtils]: 4: Hoare triple {2277#true} call #t~ret8 := main(); {2277#true} is VALID [2018-11-23 10:29:04,845 INFO L273 TraceCheckUtils]: 5: Hoare triple {2277#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2277#true} is VALID [2018-11-23 10:29:04,846 INFO L273 TraceCheckUtils]: 6: Hoare triple {2277#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2300#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:04,847 INFO L273 TraceCheckUtils]: 7: Hoare triple {2300#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2304#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,847 INFO L273 TraceCheckUtils]: 8: Hoare triple {2304#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {2308#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,848 INFO L273 TraceCheckUtils]: 9: Hoare triple {2308#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {2308#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,851 INFO L273 TraceCheckUtils]: 10: Hoare triple {2308#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2315#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,854 INFO L273 TraceCheckUtils]: 11: Hoare triple {2315#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2319#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,855 INFO L273 TraceCheckUtils]: 12: Hoare triple {2319#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {2319#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,861 INFO L273 TraceCheckUtils]: 13: Hoare triple {2319#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2326#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,883 INFO L273 TraceCheckUtils]: 14: Hoare triple {2326#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2330#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,893 INFO L273 TraceCheckUtils]: 15: Hoare triple {2330#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {2330#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,908 INFO L273 TraceCheckUtils]: 16: Hoare triple {2330#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2337#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,921 INFO L273 TraceCheckUtils]: 17: Hoare triple {2337#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2341#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,927 INFO L273 TraceCheckUtils]: 18: Hoare triple {2341#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {2341#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,934 INFO L273 TraceCheckUtils]: 19: Hoare triple {2341#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2348#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,946 INFO L273 TraceCheckUtils]: 20: Hoare triple {2348#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2352#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,951 INFO L273 TraceCheckUtils]: 21: Hoare triple {2352#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {2352#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:04,961 INFO L273 TraceCheckUtils]: 22: Hoare triple {2352#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2359#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:04,963 INFO L273 TraceCheckUtils]: 23: Hoare triple {2359#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2359#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:04,964 INFO L273 TraceCheckUtils]: 24: Hoare triple {2359#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, 1bv32); {2359#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:04,966 INFO L273 TraceCheckUtils]: 25: Hoare triple {2359#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2359#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:04,982 INFO L273 TraceCheckUtils]: 26: Hoare triple {2359#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {2359#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:04,983 INFO L273 TraceCheckUtils]: 27: Hoare triple {2359#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 0bv32; {2375#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:04,985 INFO L273 TraceCheckUtils]: 28: Hoare triple {2375#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2379#|main_#t~short7|} is VALID [2018-11-23 10:29:04,985 INFO L273 TraceCheckUtils]: 29: Hoare triple {2379#|main_#t~short7|} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {2278#false} is VALID [2018-11-23 10:29:04,986 INFO L256 TraceCheckUtils]: 30: Hoare triple {2278#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2278#false} is VALID [2018-11-23 10:29:04,986 INFO L273 TraceCheckUtils]: 31: Hoare triple {2278#false} ~cond := #in~cond; {2278#false} is VALID [2018-11-23 10:29:04,986 INFO L273 TraceCheckUtils]: 32: Hoare triple {2278#false} assume 0bv32 == ~cond; {2278#false} is VALID [2018-11-23 10:29:04,987 INFO L273 TraceCheckUtils]: 33: Hoare triple {2278#false} assume !false; {2278#false} is VALID [2018-11-23 10:29:04,995 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:29:04,995 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:29:06,109 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 74 [2018-11-23 10:29:06,119 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 78 [2018-11-23 10:29:06,134 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,135 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,137 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 78 treesize of output 117 [2018-11-23 10:29:06,176 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,176 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,177 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,178 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,180 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 96 treesize of output 196 [2018-11-23 10:29:06,289 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,292 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,292 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,294 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,296 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,298 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,301 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 131 treesize of output 315 [2018-11-23 10:29:06,824 WARN L180 SmtUtils]: Spent 352.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 52 [2018-11-23 10:29:06,935 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,960 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,961 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,968 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,969 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,991 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:06,993 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,010 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,011 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,016 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,018 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,028 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,029 INFO L303 Elim1Store]: Index analysis took 104 ms [2018-11-23 10:29:07,112 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 12 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 4 case distinctions, treesize of input 74 treesize of output 248 [2018-11-23 10:29:07,136 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 5 xjuncts. [2018-11-23 10:29:07,320 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,332 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,347 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,356 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,370 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,379 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,392 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,400 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,401 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,402 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,403 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,404 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:07,406 INFO L303 Elim1Store]: Index analysis took 115 ms [2018-11-23 10:29:07,408 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 12 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 82 treesize of output 182 [2018-11-23 10:29:07,412 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:07,963 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 11 xjuncts. [2018-11-23 10:29:08,374 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 7 xjuncts. [2018-11-23 10:29:08,728 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 7 xjuncts. [2018-11-23 10:29:09,078 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 7 xjuncts. [2018-11-23 10:29:09,405 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 7 xjuncts. [2018-11-23 10:29:09,728 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 7 xjuncts. [2018-11-23 10:29:09,729 INFO L202 ElimStorePlain]: Needed 8 recursive calls to eliminate 2 variables, input treesize:76, output treesize:361 [2018-11-23 10:29:09,748 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:29:09,749 WARN L384 uantifierElimination]: Input elimination task: ∀ [|#memory_int|, |main_~#volArray~0.base|]. (bvsge (select (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (store (let ((.cse3 (bvadd main_~j~0 (_ bv4294967293 32)))) (store (let ((.cse2 (bvadd main_~j~0 (_ bv4294967294 32)))) (store (let ((.cse1 (bvadd main_~j~0 (_ bv4294967295 32)))) (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg .cse1)) |main_~#volArray~0.offset| .cse0) .cse1)) (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg .cse2))) .cse2)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg .cse3)) .cse0) .cse3)) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) |main_~#volArray~0.offset| .cse0) (_ bv0 32))) |main_~#volArray~0.offset|) main_~MINVAL~0) [2018-11-23 10:29:09,749 WARN L385 uantifierElimination]: ElimStorePlain result: ∀ [v_arrayElimCell_7, v_prenex_1]. (let ((.cse2 (bvadd main_~j~0 (_ bv4294967294 32))) (.cse6 (bvadd main_~j~0 (_ bv4294967295 32))) (.cse8 (bvadd main_~j~0 (_ bv4294967293 32))) (.cse9 (bvmul (_ bv20 32) main_~i~0))) (let ((.cse3 (= |main_~#volArray~0.offset| (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg .cse8)) .cse9))) (.cse0 (= |main_~#volArray~0.offset| (bvadd (bvmul (_ bv4 32) (bvneg .cse6)) |main_~#volArray~0.offset| .cse9))) (.cse5 (= (bvadd |main_~#volArray~0.offset| .cse9 (bvmul (_ bv4 32) (bvneg .cse2))) |main_~#volArray~0.offset|)) (.cse4 (= |main_~#volArray~0.offset| (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse9))) (.cse7 (bvsge (_ bv0 32) main_~MINVAL~0)) (.cse1 (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) .cse9)))) (and (or .cse0 .cse1 (bvsge .cse2 main_~MINVAL~0) .cse3 .cse4) (or .cse1 .cse5 (bvsge .cse6 main_~MINVAL~0) .cse3 .cse4) (or .cse0 .cse1 .cse5 .cse3 .cse4 (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (or (bvsge main_~j~0 main_~MINVAL~0) .cse0 .cse1 .cse5 .cse3) (or .cse0 .cse5 .cse3 .cse4 (bvsge v_prenex_1 main_~MINVAL~0) .cse7) (or .cse0 .cse1 .cse5 .cse4 (bvsge .cse8 main_~MINVAL~0)) (or .cse7 (not .cse1))))) [2018-11-23 10:29:10,771 WARN L180 SmtUtils]: Spent 701.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 51 [2018-11-23 10:29:11,472 WARN L180 SmtUtils]: Spent 219.00 ms on a formula simplification. DAG size of input: 40 DAG size of output: 39 [2018-11-23 10:29:11,617 INFO L273 TraceCheckUtils]: 33: Hoare triple {2278#false} assume !false; {2278#false} is VALID [2018-11-23 10:29:11,617 INFO L273 TraceCheckUtils]: 32: Hoare triple {2278#false} assume 0bv32 == ~cond; {2278#false} is VALID [2018-11-23 10:29:11,617 INFO L273 TraceCheckUtils]: 31: Hoare triple {2278#false} ~cond := #in~cond; {2278#false} is VALID [2018-11-23 10:29:11,617 INFO L256 TraceCheckUtils]: 30: Hoare triple {2278#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2278#false} is VALID [2018-11-23 10:29:11,618 INFO L273 TraceCheckUtils]: 29: Hoare triple {2379#|main_#t~short7|} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {2278#false} is VALID [2018-11-23 10:29:11,619 INFO L273 TraceCheckUtils]: 28: Hoare triple {2410#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2379#|main_#t~short7|} is VALID [2018-11-23 10:29:11,620 INFO L273 TraceCheckUtils]: 27: Hoare triple {2414#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} ~i~0 := 0bv32; {2410#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-23 10:29:11,625 INFO L273 TraceCheckUtils]: 26: Hoare triple {2414#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {2414#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:11,625 INFO L273 TraceCheckUtils]: 25: Hoare triple {2414#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2414#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:11,627 INFO L273 TraceCheckUtils]: 24: Hoare triple {2414#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~j~0, 1bv32); {2414#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:11,627 INFO L273 TraceCheckUtils]: 23: Hoare triple {2414#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2414#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:11,861 INFO L273 TraceCheckUtils]: 22: Hoare triple {2430#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2414#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:11,861 INFO L273 TraceCheckUtils]: 21: Hoare triple {2430#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {2430#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:11,899 INFO L273 TraceCheckUtils]: 20: Hoare triple {2437#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2430#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:12,067 INFO L273 TraceCheckUtils]: 19: Hoare triple {2441#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2437#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:12,068 INFO L273 TraceCheckUtils]: 18: Hoare triple {2441#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {2441#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:12,657 INFO L273 TraceCheckUtils]: 17: Hoare triple {2448#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2441#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:12,809 INFO L273 TraceCheckUtils]: 16: Hoare triple {2452#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2448#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:12,810 INFO L273 TraceCheckUtils]: 15: Hoare triple {2452#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {2452#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:14,517 INFO L273 TraceCheckUtils]: 14: Hoare triple {2459#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2452#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:14,738 INFO L273 TraceCheckUtils]: 13: Hoare triple {2463#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2459#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:14,739 INFO L273 TraceCheckUtils]: 12: Hoare triple {2463#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {2463#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:15,932 INFO L273 TraceCheckUtils]: 11: Hoare triple {2470#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967293 32))) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2463#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:16,494 INFO L273 TraceCheckUtils]: 10: Hoare triple {2474#(and (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) main_~MINVAL~0)) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))) (or (bvsge (_ bv0 32) main_~MINVAL~0) (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2470#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967293 32))) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:16,496 INFO L273 TraceCheckUtils]: 9: Hoare triple {2474#(and (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) main_~MINVAL~0)) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))) (or (bvsge (_ bv0 32) main_~MINVAL~0) (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))))} assume !!~bvsge32(~j~0, 1bv32); {2474#(and (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) main_~MINVAL~0)) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))) (or (bvsge (_ bv0 32) main_~MINVAL~0) (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))))} is VALID [2018-11-23 10:29:16,520 INFO L273 TraceCheckUtils]: 8: Hoare triple {2481#(and (or (not (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32))) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (bvsge (_ bv5 32) main_~MINVAL~0) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (or (bvsge (_ bv4 32) main_~MINVAL~0) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {2474#(and (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) main_~MINVAL~0)) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))) (or (bvsge (_ bv0 32) main_~MINVAL~0) (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)))))} is VALID [2018-11-23 10:29:16,523 INFO L273 TraceCheckUtils]: 7: Hoare triple {2485#(bvsge (_ bv5 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2481#(and (or (not (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32))) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (bvsge (_ bv5 32) main_~MINVAL~0) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (or (bvsge (_ bv4 32) main_~MINVAL~0) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0)))} is VALID [2018-11-23 10:29:16,528 INFO L273 TraceCheckUtils]: 6: Hoare triple {2277#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2485#(bvsge (_ bv5 32) main_~MINVAL~0)} is VALID [2018-11-23 10:29:16,528 INFO L273 TraceCheckUtils]: 5: Hoare triple {2277#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2277#true} is VALID [2018-11-23 10:29:16,528 INFO L256 TraceCheckUtils]: 4: Hoare triple {2277#true} call #t~ret8 := main(); {2277#true} is VALID [2018-11-23 10:29:16,528 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2277#true} {2277#true} #83#return; {2277#true} is VALID [2018-11-23 10:29:16,529 INFO L273 TraceCheckUtils]: 2: Hoare triple {2277#true} assume true; {2277#true} is VALID [2018-11-23 10:29:16,529 INFO L273 TraceCheckUtils]: 1: Hoare triple {2277#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2277#true} is VALID [2018-11-23 10:29:16,529 INFO L256 TraceCheckUtils]: 0: Hoare triple {2277#true} call ULTIMATE.init(); {2277#true} is VALID [2018-11-23 10:29:16,535 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:29:16,537 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:29:16,537 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 29 [2018-11-23 10:29:16,538 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 34 [2018-11-23 10:29:16,538 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:29:16,538 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 29 states. [2018-11-23 10:29:18,878 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 57 edges. 57 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:18,878 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-23 10:29:18,878 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-23 10:29:18,879 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=622, Unknown=0, NotChecked=0, Total=812 [2018-11-23 10:29:18,879 INFO L87 Difference]: Start difference. First operand 44 states and 48 transitions. Second operand 29 states. [2018-11-23 10:29:22,907 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 44 [2018-11-23 10:29:23,546 WARN L180 SmtUtils]: Spent 327.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 80 [2018-11-23 10:29:25,751 WARN L180 SmtUtils]: Spent 212.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 60 [2018-11-23 10:29:26,721 WARN L180 SmtUtils]: Spent 228.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 64 [2018-11-23 10:29:28,419 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 50 [2018-11-23 10:29:28,834 WARN L180 SmtUtils]: Spent 195.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 54 [2018-11-23 10:29:31,328 WARN L180 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 41 [2018-11-23 10:29:31,751 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 45 [2018-11-23 10:29:33,670 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 36 [2018-11-23 10:29:40,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:40,119 INFO L93 Difference]: Finished difference Result 216 states and 269 transitions. [2018-11-23 10:29:40,119 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-11-23 10:29:40,120 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 34 [2018-11-23 10:29:40,120 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:29:40,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2018-11-23 10:29:40,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 211 transitions. [2018-11-23 10:29:40,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2018-11-23 10:29:40,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 211 transitions. [2018-11-23 10:29:40,134 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 40 states and 211 transitions. [2018-11-23 10:29:45,487 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 211 edges. 209 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:45,493 INFO L225 Difference]: With dead ends: 216 [2018-11-23 10:29:45,493 INFO L226 Difference]: Without dead ends: 181 [2018-11-23 10:29:45,495 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 92 GetRequests, 40 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 799 ImplicationChecksByTransitivity, 8.8s TimeCoverageRelationStatistics Valid=684, Invalid=2178, Unknown=0, NotChecked=0, Total=2862 [2018-11-23 10:29:45,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2018-11-23 10:29:45,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 107. [2018-11-23 10:29:45,731 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:29:45,731 INFO L82 GeneralOperation]: Start isEquivalent. First operand 181 states. Second operand 107 states. [2018-11-23 10:29:45,731 INFO L74 IsIncluded]: Start isIncluded. First operand 181 states. Second operand 107 states. [2018-11-23 10:29:45,732 INFO L87 Difference]: Start difference. First operand 181 states. Second operand 107 states. [2018-11-23 10:29:45,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:45,741 INFO L93 Difference]: Finished difference Result 181 states and 225 transitions. [2018-11-23 10:29:45,741 INFO L276 IsEmpty]: Start isEmpty. Operand 181 states and 225 transitions. [2018-11-23 10:29:45,741 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:29:45,742 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:29:45,742 INFO L74 IsIncluded]: Start isIncluded. First operand 107 states. Second operand 181 states. [2018-11-23 10:29:45,742 INFO L87 Difference]: Start difference. First operand 107 states. Second operand 181 states. [2018-11-23 10:29:45,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:45,750 INFO L93 Difference]: Finished difference Result 181 states and 225 transitions. [2018-11-23 10:29:45,750 INFO L276 IsEmpty]: Start isEmpty. Operand 181 states and 225 transitions. [2018-11-23 10:29:45,750 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:29:45,751 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:29:45,751 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:29:45,751 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:29:45,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-11-23 10:29:45,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 127 transitions. [2018-11-23 10:29:45,755 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 127 transitions. Word has length 34 [2018-11-23 10:29:45,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:29:45,755 INFO L480 AbstractCegarLoop]: Abstraction has 107 states and 127 transitions. [2018-11-23 10:29:45,755 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-23 10:29:45,756 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 127 transitions. [2018-11-23 10:29:45,756 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-23 10:29:45,756 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:29:45,757 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 4, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:29:45,757 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:29:45,757 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:29:45,757 INFO L82 PathProgramCache]: Analyzing trace with hash 331970743, now seen corresponding path program 1 times [2018-11-23 10:29:45,757 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:29:45,758 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:29:45,779 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 10:29:45,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:29:45,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:29:45,920 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:29:46,016 INFO L256 TraceCheckUtils]: 0: Hoare triple {3358#true} call ULTIMATE.init(); {3358#true} is VALID [2018-11-23 10:29:46,017 INFO L273 TraceCheckUtils]: 1: Hoare triple {3358#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3358#true} is VALID [2018-11-23 10:29:46,017 INFO L273 TraceCheckUtils]: 2: Hoare triple {3358#true} assume true; {3358#true} is VALID [2018-11-23 10:29:46,017 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3358#true} {3358#true} #83#return; {3358#true} is VALID [2018-11-23 10:29:46,017 INFO L256 TraceCheckUtils]: 4: Hoare triple {3358#true} call #t~ret8 := main(); {3358#true} is VALID [2018-11-23 10:29:46,018 INFO L273 TraceCheckUtils]: 5: Hoare triple {3358#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3358#true} is VALID [2018-11-23 10:29:46,018 INFO L273 TraceCheckUtils]: 6: Hoare triple {3358#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {3358#true} is VALID [2018-11-23 10:29:46,018 INFO L273 TraceCheckUtils]: 7: Hoare triple {3358#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {3358#true} is VALID [2018-11-23 10:29:46,018 INFO L273 TraceCheckUtils]: 8: Hoare triple {3358#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {3387#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,019 INFO L273 TraceCheckUtils]: 9: Hoare triple {3387#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {3387#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,019 INFO L273 TraceCheckUtils]: 10: Hoare triple {3387#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3387#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,020 INFO L273 TraceCheckUtils]: 11: Hoare triple {3387#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3397#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,020 INFO L273 TraceCheckUtils]: 12: Hoare triple {3397#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {3397#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,021 INFO L273 TraceCheckUtils]: 13: Hoare triple {3397#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3397#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,021 INFO L273 TraceCheckUtils]: 14: Hoare triple {3397#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3407#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,022 INFO L273 TraceCheckUtils]: 15: Hoare triple {3407#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {3407#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,023 INFO L273 TraceCheckUtils]: 16: Hoare triple {3407#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3407#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,023 INFO L273 TraceCheckUtils]: 17: Hoare triple {3407#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3417#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,024 INFO L273 TraceCheckUtils]: 18: Hoare triple {3417#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {3417#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,025 INFO L273 TraceCheckUtils]: 19: Hoare triple {3417#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3417#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,026 INFO L273 TraceCheckUtils]: 20: Hoare triple {3417#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3427#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,026 INFO L273 TraceCheckUtils]: 21: Hoare triple {3427#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {3427#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,027 INFO L273 TraceCheckUtils]: 22: Hoare triple {3427#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3427#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:46,028 INFO L273 TraceCheckUtils]: 23: Hoare triple {3427#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3437#(= main_~j~0 (_ bv0 32))} is VALID [2018-11-23 10:29:46,029 INFO L273 TraceCheckUtils]: 24: Hoare triple {3437#(= main_~j~0 (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {3359#false} is VALID [2018-11-23 10:29:46,029 INFO L273 TraceCheckUtils]: 25: Hoare triple {3359#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3359#false} is VALID [2018-11-23 10:29:46,029 INFO L273 TraceCheckUtils]: 26: Hoare triple {3359#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3359#false} is VALID [2018-11-23 10:29:46,030 INFO L273 TraceCheckUtils]: 27: Hoare triple {3359#false} assume !~bvsge32(~j~0, 1bv32); {3359#false} is VALID [2018-11-23 10:29:46,030 INFO L273 TraceCheckUtils]: 28: Hoare triple {3359#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3359#false} is VALID [2018-11-23 10:29:46,030 INFO L273 TraceCheckUtils]: 29: Hoare triple {3359#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {3359#false} is VALID [2018-11-23 10:29:46,031 INFO L273 TraceCheckUtils]: 30: Hoare triple {3359#false} ~i~0 := 0bv32; {3359#false} is VALID [2018-11-23 10:29:46,031 INFO L273 TraceCheckUtils]: 31: Hoare triple {3359#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3359#false} is VALID [2018-11-23 10:29:46,031 INFO L273 TraceCheckUtils]: 32: Hoare triple {3359#false} assume #t~short7; {3359#false} is VALID [2018-11-23 10:29:46,031 INFO L256 TraceCheckUtils]: 33: Hoare triple {3359#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3359#false} is VALID [2018-11-23 10:29:46,032 INFO L273 TraceCheckUtils]: 34: Hoare triple {3359#false} ~cond := #in~cond; {3359#false} is VALID [2018-11-23 10:29:46,032 INFO L273 TraceCheckUtils]: 35: Hoare triple {3359#false} assume !(0bv32 == ~cond); {3359#false} is VALID [2018-11-23 10:29:46,032 INFO L273 TraceCheckUtils]: 36: Hoare triple {3359#false} assume true; {3359#false} is VALID [2018-11-23 10:29:46,033 INFO L268 TraceCheckUtils]: 37: Hoare quadruple {3359#false} {3359#false} #87#return; {3359#false} is VALID [2018-11-23 10:29:46,033 INFO L273 TraceCheckUtils]: 38: Hoare triple {3359#false} havoc #t~mem6;havoc #t~short7;havoc #t~mem5; {3359#false} is VALID [2018-11-23 10:29:46,033 INFO L273 TraceCheckUtils]: 39: Hoare triple {3359#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3359#false} is VALID [2018-11-23 10:29:46,033 INFO L273 TraceCheckUtils]: 40: Hoare triple {3359#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3359#false} is VALID [2018-11-23 10:29:46,033 INFO L273 TraceCheckUtils]: 41: Hoare triple {3359#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {3359#false} is VALID [2018-11-23 10:29:46,034 INFO L256 TraceCheckUtils]: 42: Hoare triple {3359#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3359#false} is VALID [2018-11-23 10:29:46,034 INFO L273 TraceCheckUtils]: 43: Hoare triple {3359#false} ~cond := #in~cond; {3359#false} is VALID [2018-11-23 10:29:46,034 INFO L273 TraceCheckUtils]: 44: Hoare triple {3359#false} assume 0bv32 == ~cond; {3359#false} is VALID [2018-11-23 10:29:46,034 INFO L273 TraceCheckUtils]: 45: Hoare triple {3359#false} assume !false; {3359#false} is VALID [2018-11-23 10:29:46,037 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 17 proven. 35 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-23 10:29:46,037 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:29:46,383 INFO L273 TraceCheckUtils]: 45: Hoare triple {3359#false} assume !false; {3359#false} is VALID [2018-11-23 10:29:46,383 INFO L273 TraceCheckUtils]: 44: Hoare triple {3359#false} assume 0bv32 == ~cond; {3359#false} is VALID [2018-11-23 10:29:46,384 INFO L273 TraceCheckUtils]: 43: Hoare triple {3359#false} ~cond := #in~cond; {3359#false} is VALID [2018-11-23 10:29:46,384 INFO L256 TraceCheckUtils]: 42: Hoare triple {3359#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3359#false} is VALID [2018-11-23 10:29:46,384 INFO L273 TraceCheckUtils]: 41: Hoare triple {3359#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {3359#false} is VALID [2018-11-23 10:29:46,385 INFO L273 TraceCheckUtils]: 40: Hoare triple {3359#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3359#false} is VALID [2018-11-23 10:29:46,385 INFO L273 TraceCheckUtils]: 39: Hoare triple {3359#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3359#false} is VALID [2018-11-23 10:29:46,385 INFO L273 TraceCheckUtils]: 38: Hoare triple {3359#false} havoc #t~mem6;havoc #t~short7;havoc #t~mem5; {3359#false} is VALID [2018-11-23 10:29:46,385 INFO L268 TraceCheckUtils]: 37: Hoare quadruple {3358#true} {3359#false} #87#return; {3359#false} is VALID [2018-11-23 10:29:46,386 INFO L273 TraceCheckUtils]: 36: Hoare triple {3358#true} assume true; {3358#true} is VALID [2018-11-23 10:29:46,386 INFO L273 TraceCheckUtils]: 35: Hoare triple {3358#true} assume !(0bv32 == ~cond); {3358#true} is VALID [2018-11-23 10:29:46,386 INFO L273 TraceCheckUtils]: 34: Hoare triple {3358#true} ~cond := #in~cond; {3358#true} is VALID [2018-11-23 10:29:46,386 INFO L256 TraceCheckUtils]: 33: Hoare triple {3359#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3358#true} is VALID [2018-11-23 10:29:46,386 INFO L273 TraceCheckUtils]: 32: Hoare triple {3359#false} assume #t~short7; {3359#false} is VALID [2018-11-23 10:29:46,386 INFO L273 TraceCheckUtils]: 31: Hoare triple {3359#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3359#false} is VALID [2018-11-23 10:29:46,387 INFO L273 TraceCheckUtils]: 30: Hoare triple {3359#false} ~i~0 := 0bv32; {3359#false} is VALID [2018-11-23 10:29:46,387 INFO L273 TraceCheckUtils]: 29: Hoare triple {3359#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {3359#false} is VALID [2018-11-23 10:29:46,387 INFO L273 TraceCheckUtils]: 28: Hoare triple {3359#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3359#false} is VALID [2018-11-23 10:29:46,387 INFO L273 TraceCheckUtils]: 27: Hoare triple {3359#false} assume !~bvsge32(~j~0, 1bv32); {3359#false} is VALID [2018-11-23 10:29:46,387 INFO L273 TraceCheckUtils]: 26: Hoare triple {3359#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3359#false} is VALID [2018-11-23 10:29:46,387 INFO L273 TraceCheckUtils]: 25: Hoare triple {3359#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3359#false} is VALID [2018-11-23 10:29:46,388 INFO L273 TraceCheckUtils]: 24: Hoare triple {3567#(not (bvsge main_~j~0 (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {3359#false} is VALID [2018-11-23 10:29:46,388 INFO L273 TraceCheckUtils]: 23: Hoare triple {3571#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3567#(not (bvsge main_~j~0 (_ bv1 32)))} is VALID [2018-11-23 10:29:46,389 INFO L273 TraceCheckUtils]: 22: Hoare triple {3571#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3571#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,390 INFO L273 TraceCheckUtils]: 21: Hoare triple {3571#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {3571#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,394 INFO L273 TraceCheckUtils]: 20: Hoare triple {3581#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3571#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,395 INFO L273 TraceCheckUtils]: 19: Hoare triple {3581#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3581#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,395 INFO L273 TraceCheckUtils]: 18: Hoare triple {3581#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {3581#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,400 INFO L273 TraceCheckUtils]: 17: Hoare triple {3591#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3581#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,402 INFO L273 TraceCheckUtils]: 16: Hoare triple {3591#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3591#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,403 INFO L273 TraceCheckUtils]: 15: Hoare triple {3591#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {3591#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,406 INFO L273 TraceCheckUtils]: 14: Hoare triple {3601#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3591#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,407 INFO L273 TraceCheckUtils]: 13: Hoare triple {3601#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3601#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,407 INFO L273 TraceCheckUtils]: 12: Hoare triple {3601#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {3601#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,411 INFO L273 TraceCheckUtils]: 11: Hoare triple {3611#(not (bvsge (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3601#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,412 INFO L273 TraceCheckUtils]: 10: Hoare triple {3611#(not (bvsge (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv1 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3611#(not (bvsge (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,412 INFO L273 TraceCheckUtils]: 9: Hoare triple {3611#(not (bvsge (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {3611#(not (bvsge (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,413 INFO L273 TraceCheckUtils]: 8: Hoare triple {3358#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {3611#(not (bvsge (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:46,413 INFO L273 TraceCheckUtils]: 7: Hoare triple {3358#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {3358#true} is VALID [2018-11-23 10:29:46,413 INFO L273 TraceCheckUtils]: 6: Hoare triple {3358#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {3358#true} is VALID [2018-11-23 10:29:46,413 INFO L273 TraceCheckUtils]: 5: Hoare triple {3358#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3358#true} is VALID [2018-11-23 10:29:46,413 INFO L256 TraceCheckUtils]: 4: Hoare triple {3358#true} call #t~ret8 := main(); {3358#true} is VALID [2018-11-23 10:29:46,414 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3358#true} {3358#true} #83#return; {3358#true} is VALID [2018-11-23 10:29:46,414 INFO L273 TraceCheckUtils]: 2: Hoare triple {3358#true} assume true; {3358#true} is VALID [2018-11-23 10:29:46,414 INFO L273 TraceCheckUtils]: 1: Hoare triple {3358#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3358#true} is VALID [2018-11-23 10:29:46,414 INFO L256 TraceCheckUtils]: 0: Hoare triple {3358#true} call ULTIMATE.init(); {3358#true} is VALID [2018-11-23 10:29:46,418 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 19 proven. 35 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-23 10:29:46,422 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:29:46,422 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 14 [2018-11-23 10:29:46,423 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 46 [2018-11-23 10:29:46,423 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:29:46,423 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 14 states. [2018-11-23 10:29:46,590 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 65 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:46,590 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-23 10:29:46,590 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-23 10:29:46,591 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=136, Unknown=0, NotChecked=0, Total=182 [2018-11-23 10:29:46,591 INFO L87 Difference]: Start difference. First operand 107 states and 127 transitions. Second operand 14 states. [2018-11-23 10:29:48,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:48,430 INFO L93 Difference]: Finished difference Result 163 states and 190 transitions. [2018-11-23 10:29:48,430 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 10:29:48,430 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 46 [2018-11-23 10:29:48,430 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:29:48,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-11-23 10:29:48,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 64 transitions. [2018-11-23 10:29:48,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-11-23 10:29:48,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 64 transitions. [2018-11-23 10:29:48,433 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 8 states and 64 transitions. [2018-11-23 10:29:48,630 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 64 edges. 64 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:48,631 INFO L225 Difference]: With dead ends: 163 [2018-11-23 10:29:48,632 INFO L226 Difference]: Without dead ends: 94 [2018-11-23 10:29:48,632 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=46, Invalid=136, Unknown=0, NotChecked=0, Total=182 [2018-11-23 10:29:48,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-11-23 10:29:48,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 94. [2018-11-23 10:29:48,834 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:29:48,834 INFO L82 GeneralOperation]: Start isEquivalent. First operand 94 states. Second operand 94 states. [2018-11-23 10:29:48,834 INFO L74 IsIncluded]: Start isIncluded. First operand 94 states. Second operand 94 states. [2018-11-23 10:29:48,834 INFO L87 Difference]: Start difference. First operand 94 states. Second operand 94 states. [2018-11-23 10:29:48,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:48,837 INFO L93 Difference]: Finished difference Result 94 states and 102 transitions. [2018-11-23 10:29:48,837 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 102 transitions. [2018-11-23 10:29:48,838 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:29:48,838 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:29:48,838 INFO L74 IsIncluded]: Start isIncluded. First operand 94 states. Second operand 94 states. [2018-11-23 10:29:48,838 INFO L87 Difference]: Start difference. First operand 94 states. Second operand 94 states. [2018-11-23 10:29:48,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:48,842 INFO L93 Difference]: Finished difference Result 94 states and 102 transitions. [2018-11-23 10:29:48,842 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 102 transitions. [2018-11-23 10:29:48,842 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:29:48,842 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:29:48,842 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:29:48,843 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:29:48,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-11-23 10:29:48,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 102 transitions. [2018-11-23 10:29:48,846 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 102 transitions. Word has length 46 [2018-11-23 10:29:48,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:29:48,846 INFO L480 AbstractCegarLoop]: Abstraction has 94 states and 102 transitions. [2018-11-23 10:29:48,846 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-23 10:29:48,846 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 102 transitions. [2018-11-23 10:29:48,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-11-23 10:29:48,847 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:29:48,847 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 8, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:29:48,847 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:29:48,848 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:29:48,848 INFO L82 PathProgramCache]: Analyzing trace with hash 1201101877, now seen corresponding path program 3 times [2018-11-23 10:29:48,848 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:29:48,848 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:29:48,865 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2018-11-23 10:29:51,524 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-11-23 10:29:51,524 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:29:51,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:29:51,680 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:29:51,765 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 16 [2018-11-23 10:29:51,771 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-11-23 10:29:51,772 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:51,776 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:51,798 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:51,798 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:36, output treesize:32 [2018-11-23 10:29:51,928 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 34 [2018-11-23 10:29:51,968 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:51,970 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:51,971 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 75 [2018-11-23 10:29:51,973 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:51,987 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:52,026 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:52,027 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:55, output treesize:51 [2018-11-23 10:29:52,218 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 51 [2018-11-23 10:29:52,287 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,289 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,292 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,295 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,297 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,299 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,300 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 190 [2018-11-23 10:29:52,304 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:52,331 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:52,376 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:52,376 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:74, output treesize:70 [2018-11-23 10:29:52,709 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 44 [2018-11-23 10:29:52,722 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,724 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,727 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,730 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,734 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,742 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,744 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,746 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,748 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,761 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,763 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,766 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:52,767 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 238 [2018-11-23 10:29:52,770 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:52,808 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:52,841 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:52,841 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:64, output treesize:60 [2018-11-23 10:29:53,134 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 72 treesize of output 61 [2018-11-23 10:29:53,154 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,158 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,161 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,166 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,172 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,175 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,178 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,181 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,184 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,186 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,189 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,192 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,194 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,197 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,200 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,202 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,205 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,208 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,211 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,214 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,217 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 20 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 404 [2018-11-23 10:29:53,228 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:53,314 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:53,384 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 10:29:53,385 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:90, output treesize:86 [2018-11-23 10:29:53,422 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:29:53,423 WARN L384 uantifierElimination]: Input elimination task: ∃ [main_~j~0, |v_#memory_int_38|]. (let ((.cse0 (select |v_#memory_int_38| |main_~#volArray~0.base|)) (.cse1 (bvmul (_ bv20 32) main_~i~0))) (and (= (bvadd (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967276 32))) (_ bv4294967291 32)) (_ bv0 32)) (bvsge main_~j~0 (_ bv1 32)) (= (store |v_#memory_int_38| |main_~#volArray~0.base| (store .cse0 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse1) (_ bv0 32))) |#memory_int|) (= (bvadd (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967280 32))) (_ bv4294967292 32)) (_ bv0 32)) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967284 32))) (_ bv3 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967288 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))) [2018-11-23 10:29:53,423 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ [main_~j~0]. (let ((.cse0 (select |#memory_int| |main_~#volArray~0.base|)) (.cse1 (bvmul (_ bv20 32) main_~i~0))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select .cse0 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse1))) (= (bvadd (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967276 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967284 32)))) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967280 32))) (_ bv4294967292 32))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967288 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))) [2018-11-23 10:29:53,906 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 88 treesize of output 75 [2018-11-23 10:29:53,924 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,925 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,928 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,929 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,934 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,936 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,938 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,942 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,945 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,949 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,959 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,961 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,964 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,968 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,974 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,976 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,980 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,986 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,989 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:53,996 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:01,149 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 20 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 10 case distinctions, treesize of input 75 treesize of output 363 [2018-11-23 10:30:01,149 WARN L138 XnfTransformerHelper]: expecting exponential blowup for input size 6 [2018-11-23 10:30:01,193 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 48 xjuncts. [2018-11-23 10:30:01,991 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 6 xjuncts. [2018-11-23 10:30:02,296 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 6 dim-0 vars, and 6 xjuncts. [2018-11-23 10:30:02,296 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:104, output treesize:597 [2018-11-23 10:30:02,438 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:30:02,439 WARN L384 uantifierElimination]: Input elimination task: ∃ [|v_#memory_int_39|, v_prenex_2]. (let ((.cse0 (select |v_#memory_int_39| |main_~#volArray~0.base|)) (.cse1 (bvmul (_ bv20 32) main_~i~0))) (and (bvsge v_prenex_2 (_ bv1 32)) (not (bvsge v_prenex_2 main_~MINVAL~0)) (= (_ bv0 32) (select .cse0 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_2)) |main_~#volArray~0.offset| .cse1 (_ bv4294967276 32)))) (= (store |v_#memory_int_39| |main_~#volArray~0.base| (store .cse0 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse1) main_~j~0)) |#memory_int|) (= (_ bv2 32) (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967268 32)))) (= (bvadd (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967264 32))) (_ bv3 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))) [2018-11-23 10:30:02,439 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ [v_prenex_6, v_prenex_3, v_prenex_5, v_prenex_4, v_prenex_7, v_prenex_2]. (let ((.cse4 (bvmul (_ bv20 32) main_~i~0))) (let ((.cse11 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse4)) (.cse13 (bvadd |main_~#volArray~0.offset| .cse4 (_ bv4294967260 32))) (.cse12 (bvadd |main_~#volArray~0.offset| .cse4 (_ bv4294967256 32))) (.cse10 (bvadd |main_~#volArray~0.offset| .cse4 (_ bv4294967264 32))) (.cse3 (select |#memory_int| |main_~#volArray~0.base|)) (.cse14 (bvadd |main_~#volArray~0.offset| .cse4 (_ bv4294967268 32)))) (let ((.cse0 (= (_ bv2 32) (select .cse3 .cse14))) (.cse1 (= (_ bv3 32) (select .cse3 .cse10))) (.cse2 (= (_ bv5 32) (select .cse3 .cse12))) (.cse5 (= (select .cse3 .cse13) (_ bv4 32))) (.cse6 (= main_~j~0 (select .cse3 .cse11))) (.cse7 (= |main_~#volArray~0.offset| (_ bv0 32))) (.cse8 (= (_ bv2 32) main_~i~0)) (.cse9 (= (_ bv2 32) main_~MINVAL~0))) (or (and (bvsge v_prenex_6 (_ bv1 32)) .cse0 (not (bvsge v_prenex_6 main_~MINVAL~0)) .cse1 .cse2 (= (select .cse3 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_6)) |main_~#volArray~0.offset| .cse4 (_ bv4294967276 32))) (_ bv0 32)) .cse5 .cse6 .cse7 .cse8 .cse9) (and (= .cse10 .cse11) (bvsge v_prenex_3 (_ bv1 32)) .cse0 (not (bvsge v_prenex_3 main_~MINVAL~0)) .cse2 (= (select .cse3 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_3)) |main_~#volArray~0.offset| .cse4 (_ bv4294967276 32))) (_ bv0 32)) .cse5 .cse6 .cse7 .cse8 .cse9) (and (bvsge v_prenex_5 (_ bv1 32)) .cse0 (not (bvsge v_prenex_5 main_~MINVAL~0)) .cse1 (= (select .cse3 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_5)) |main_~#volArray~0.offset| .cse4 (_ bv4294967276 32))) (_ bv0 32)) .cse5 .cse6 (= .cse12 .cse11) .cse7 .cse8 .cse9) (and (bvsge v_prenex_4 (_ bv1 32)) .cse0 (not (bvsge v_prenex_4 main_~MINVAL~0)) .cse1 .cse2 (= (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_4)) |main_~#volArray~0.offset| .cse4 (_ bv4294967276 32)) .cse11) .cse5 .cse6 .cse7 .cse8 .cse9) (and (= .cse13 .cse11) (bvsge v_prenex_7 (_ bv1 32)) .cse0 (not (bvsge v_prenex_7 main_~MINVAL~0)) .cse1 .cse2 (= (select .cse3 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| .cse4 (_ bv4294967276 32))) (_ bv0 32)) .cse6 .cse7 .cse8 .cse9) (and (bvsge v_prenex_2 (_ bv1 32)) (not (bvsge v_prenex_2 main_~MINVAL~0)) .cse1 .cse2 (= (select .cse3 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_2)) |main_~#volArray~0.offset| .cse4 (_ bv4294967276 32))) (_ bv0 32)) .cse5 (= .cse14 .cse11) .cse6 .cse7 .cse8 .cse9))))) [2018-11-23 10:30:03,625 WARN L180 SmtUtils]: Spent 927.00 ms on a formula simplification that was a NOOP. DAG size: 118 [2018-11-23 10:30:05,085 WARN L180 SmtUtils]: Spent 1.04 s on a formula simplification that was a NOOP. DAG size: 127 [2018-11-23 10:30:05,795 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,797 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 119 treesize of output 120 [2018-11-23 10:30:05,844 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,846 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,850 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,851 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,853 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,855 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,860 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,862 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,864 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,869 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,870 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,870 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:05,875 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,877 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,880 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,885 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,887 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,888 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,890 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,895 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,896 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,898 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,904 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,906 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,911 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,917 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,918 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:05,921 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 25 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 94 treesize of output 566 [2018-11-23 10:30:05,934 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:30:06,175 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:30:30,822 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 118 treesize of output 105 [2018-11-23 10:30:30,877 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,879 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,881 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,883 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,885 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,888 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,890 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,892 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,895 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,897 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,900 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,902 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,904 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,906 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,909 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,912 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,914 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,916 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,919 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,921 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,923 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,925 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,927 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,932 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,935 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,937 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,939 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,942 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,944 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:30,948 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 29 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 632 [2018-11-23 10:30:30,971 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 10:30:31,285 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:30:47,838 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,840 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 117 treesize of output 118 [2018-11-23 10:30:47,907 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,910 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,913 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,915 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,918 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,921 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,923 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,926 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,927 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,930 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,932 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,933 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:47,935 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,940 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,945 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,950 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,955 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,958 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,961 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,964 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,967 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,970 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,975 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,978 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,984 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,986 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,990 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:47,994 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 25 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 596 [2018-11-23 10:30:48,007 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-11-23 10:30:48,260 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:30:57,843 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,845 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 119 treesize of output 120 [2018-11-23 10:30:57,911 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:57,914 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,919 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,923 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,927 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,930 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,933 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,937 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,939 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,944 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,946 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,950 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,955 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,960 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,965 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,968 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,972 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,977 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,981 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,985 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,990 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,994 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:57,999 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:58,004 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:58,009 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:58,012 INFO L303 Elim1Store]: Index analysis took 112 ms [2018-11-23 10:30:58,014 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 25 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 94 treesize of output 552 [2018-11-23 10:30:58,027 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-11-23 10:30:58,253 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:31:04,024 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,026 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 119 treesize of output 120 [2018-11-23 10:31:04,096 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,103 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,107 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,111 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,116 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,124 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,128 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,131 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,135 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,139 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,143 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,143 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:04,148 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,156 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,159 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,162 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,166 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,171 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,175 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,179 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,183 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,186 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,189 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,193 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,198 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,202 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,205 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:04,206 INFO L303 Elim1Store]: Index analysis took 124 ms [2018-11-23 10:31:04,208 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 25 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 94 treesize of output 594 [2018-11-23 10:31:04,222 INFO L267 ElimStorePlain]: Start of recursive call 11: End of recursive call: and 1 xjuncts. [2018-11-23 10:31:04,464 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:31:08,192 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 121 treesize of output 106 [2018-11-23 10:31:08,249 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,254 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,261 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,266 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,271 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,276 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,281 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,285 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,289 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,294 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,298 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,302 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,306 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,309 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,323 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,328 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,334 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,338 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,342 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,347 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,354 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,357 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,369 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,373 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,385 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,395 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,399 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,422 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,426 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,431 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,457 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,465 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:08,483 INFO L303 Elim1Store]: Index analysis took 251 ms [2018-11-23 10:31:08,911 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 32 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 90 treesize of output 689 [2018-11-23 10:31:08,927 INFO L267 ElimStorePlain]: Start of recursive call 13: End of recursive call: and 2 xjuncts. [2018-11-23 10:31:16,065 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-23 10:31:17,475 INFO L267 ElimStorePlain]: Start of recursive call 1: 6 dim-0 vars, 6 dim-2 vars, End of recursive call: 7 dim-0 vars, and 7 xjuncts. [2018-11-23 10:31:17,475 INFO L202 ElimStorePlain]: Needed 13 recursive calls to eliminate 12 variables, input treesize:714, output treesize:779 [2018-11-23 10:31:19,509 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:31:19,510 WARN L384 uantifierElimination]: Input elimination task: ∃ [|v_#memory_int_40|, v_prenex_7, v_prenex_12, v_prenex_2, v_prenex_8, v_prenex_5, v_prenex_10, v_prenex_6, v_prenex_11, v_prenex_4, v_prenex_9, v_prenex_3]. (let ((.cse6 (bvadd main_~j~0 (_ bv1 32)))) (let ((.cse5 (bvmul (_ bv4 32) (bvneg .cse6))) (.cse4 (bvmul (_ bv20 32) main_~i~0))) (let ((.cse9 (bvadd |main_~#volArray~0.offset| .cse4 (_ bv4294967264 32))) (.cse1 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse4)) (.cse7 (bvadd .cse5 |main_~#volArray~0.offset| .cse4)) (.cse13 (bvadd |main_~#volArray~0.offset| .cse4 (_ bv4294967260 32))) (.cse2 (bvadd |main_~#volArray~0.offset| .cse4 (_ bv4294967268 32))) (.cse3 (bvadd |main_~#volArray~0.offset| .cse4 (_ bv4294967256 32))) (.cse8 (= |main_~#volArray~0.offset| (_ bv0 32))) (.cse10 (= (_ bv2 32) main_~i~0)) (.cse11 (= (_ bv2 32) main_~MINVAL~0))) (or (let ((.cse0 (select |v_#memory_int_40| |main_~#volArray~0.base|))) (and (= (store |v_#memory_int_40| |main_~#volArray~0.base| (store .cse0 .cse1 main_~j~0)) |#memory_int|) (= (select .cse0 .cse2) (_ bv2 32)) (= (_ bv5 32) (select .cse0 .cse3)) (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select .cse0 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| .cse4 (_ bv4294967276 32)))) (= (bvadd .cse5 (_ bv36 32)) (_ bv0 32)) (= .cse6 (select .cse0 .cse7)) .cse8 (= (_ bv3 32) (select .cse0 .cse9)) (bvsge v_prenex_7 (_ bv1 32)) .cse10 .cse11)) (let ((.cse12 (select v_prenex_12 |main_~#volArray~0.base|))) (and (= (bvadd .cse5 (_ bv28 32)) (_ bv0 32)) (bvsge v_prenex_2 (_ bv1 32)) (= (_ bv5 32) (select .cse12 .cse3)) (not (bvsge v_prenex_2 main_~MINVAL~0)) (= (_ bv3 32) (select .cse12 .cse9)) (= (store v_prenex_12 |main_~#volArray~0.base| (store .cse12 .cse1 main_~j~0)) |#memory_int|) (= (select .cse12 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_2)) |main_~#volArray~0.offset| .cse4 (_ bv4294967276 32))) (_ bv0 32)) (= .cse6 (select .cse12 .cse7)) .cse8 (= (_ bv0 32) (bvadd (select .cse12 .cse13) (_ bv4294967292 32))) .cse10 .cse11)) (let ((.cse14 (select v_prenex_8 |main_~#volArray~0.base|))) (and (= (select .cse14 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_5)) |main_~#volArray~0.offset| .cse4 (_ bv4294967276 32))) (_ bv0 32)) (= (store v_prenex_8 |main_~#volArray~0.base| (store .cse14 .cse1 main_~j~0)) |#memory_int|) (= (bvadd .cse5 (_ bv40 32)) (_ bv0 32)) (= (_ bv3 32) (select .cse14 .cse9)) (not (bvsge v_prenex_5 main_~MINVAL~0)) (= .cse6 (select .cse14 .cse7)) .cse8 (= (_ bv0 32) (bvadd (select .cse14 .cse13) (_ bv4294967292 32))) (= (select .cse14 .cse2) (_ bv2 32)) (bvsge v_prenex_5 (_ bv1 32)) .cse10 .cse11)) (let ((.cse15 (select v_prenex_10 |main_~#volArray~0.base|))) (and (= (store v_prenex_10 |main_~#volArray~0.base| (store .cse15 .cse1 main_~j~0)) |#memory_int|) (bvsge v_prenex_6 (_ bv1 32)) (= (select .cse15 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_6)) |main_~#volArray~0.offset| .cse4 (_ bv4294967276 32))) (_ bv0 32)) (= (_ bv3 32) (select .cse15 .cse9)) (not (bvsge v_prenex_6 main_~MINVAL~0)) (= (_ bv5 32) (select .cse15 .cse3)) (= (select .cse15 .cse2) (_ bv2 32)) .cse8 (= (_ bv0 32) (bvadd (select .cse15 .cse13) (_ bv4294967292 32))) (= .cse6 (select .cse15 .cse7)) .cse10 .cse11)) (let ((.cse16 (select v_prenex_11 |main_~#volArray~0.base|))) (and (= (store v_prenex_11 |main_~#volArray~0.base| (store .cse16 .cse1 main_~j~0)) |#memory_int|) (= (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_4)) (_ bv4294967276 32)) .cse5) (= (_ bv5 32) (select .cse16 .cse3)) (= (select .cse16 .cse2) (_ bv2 32)) (= (_ bv3 32) (select .cse16 .cse9)) (not (bvsge v_prenex_4 main_~MINVAL~0)) (= .cse6 (select .cse16 .cse7)) (= (_ bv0 32) (bvadd (select .cse16 .cse13) (_ bv4294967292 32))) (bvsge v_prenex_4 (_ bv1 32)) .cse8 .cse10 .cse11)) (let ((.cse17 (select v_prenex_9 |main_~#volArray~0.base|))) (and (= (store v_prenex_9 |main_~#volArray~0.base| (store .cse17 .cse1 main_~j~0)) |#memory_int|) (= .cse6 (select .cse17 .cse7)) (= (select .cse17 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_3)) |main_~#volArray~0.offset| .cse4 (_ bv4294967276 32))) (_ bv0 32)) (not (bvsge v_prenex_3 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (select .cse17 .cse13) (_ bv4294967292 32))) (= (bvadd .cse5 (_ bv32 32)) (_ bv0 32)) (= (select .cse17 .cse2) (_ bv2 32)) (= (_ bv5 32) (select .cse17 .cse3)) .cse8 (bvsge v_prenex_3 (_ bv1 32)) .cse10 .cse11)))))) [2018-11-23 10:31:19,510 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ [v_prenex_2, v_prenex_6, v_prenex_13, v_prenex_5, v_prenex_7, v_prenex_3, v_prenex_4]. (let ((.cse16 (bvadd main_~j~0 (_ bv1 32))) (.cse3 (bvmul (_ bv20 32) main_~i~0))) (let ((.cse4 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse3)) (.cse13 (bvadd |main_~#volArray~0.offset| .cse3 (_ bv4294967260 32))) (.cse12 (bvadd |main_~#volArray~0.offset| .cse3 (_ bv4294967256 32))) (.cse14 (bvmul (_ bv4 32) (bvneg .cse16))) (.cse11 (select |#memory_int| |main_~#volArray~0.base|)) (.cse15 (bvadd |main_~#volArray~0.offset| .cse3 (_ bv4294967268 32)))) (let ((.cse10 (= (_ bv2 32) (select .cse11 .cse15))) (.cse0 (= (_ bv3 32) (select .cse11 (bvadd |main_~#volArray~0.offset| .cse3 (_ bv4294967264 32))))) (.cse1 (= .cse16 (select .cse11 (bvadd .cse14 |main_~#volArray~0.offset| .cse3)))) (.cse2 (= (_ bv5 32) (select .cse11 .cse12))) (.cse5 (= (bvadd (select .cse11 .cse13) (_ bv4294967292 32)) (_ bv0 32))) (.cse6 (= main_~j~0 (select .cse11 .cse4))) (.cse7 (= |main_~#volArray~0.offset| (_ bv0 32))) (.cse8 (= (_ bv2 32) main_~i~0)) (.cse9 (= (_ bv2 32) main_~MINVAL~0))) (or (and (bvsge v_prenex_2 (_ bv1 32)) (not (bvsge v_prenex_2 main_~MINVAL~0)) .cse0 .cse1 .cse2 (= (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_2)) |main_~#volArray~0.offset| .cse3 (_ bv4294967276 32)) .cse4) .cse5 .cse6 .cse7 .cse8 .cse9) (and (bvsge v_prenex_6 (_ bv1 32)) .cse10 .cse0 .cse1 .cse2 (not (bvsge v_prenex_6 main_~MINVAL~0)) .cse5 .cse6 (= (select .cse11 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_6)) |main_~#volArray~0.offset| .cse3 (_ bv4294967276 32))) (_ bv0 32)) .cse7 .cse8 .cse9) (and (bvsge v_prenex_13 (_ bv1 32)) .cse10 .cse0 .cse1 (not (bvsge v_prenex_13 main_~MINVAL~0)) .cse5 (= .cse12 .cse4) .cse6 (= (select .cse11 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_13)) |main_~#volArray~0.offset| .cse3 (_ bv4294967276 32))) (_ bv0 32)) .cse7 .cse8 .cse9) (and (= .cse13 .cse4) (= (_ bv0 32) (select .cse11 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_5)) |main_~#volArray~0.offset| .cse3 (_ bv4294967276 32)))) .cse10 .cse0 .cse1 (not (bvsge v_prenex_5 main_~MINVAL~0)) .cse6 .cse7 (bvsge v_prenex_5 (_ bv1 32)) .cse8 .cse9) (and .cse10 .cse1 .cse2 (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (bvadd .cse14 (_ bv36 32)) (_ bv0 32)) .cse6 .cse7 (bvsge v_prenex_7 (_ bv1 32)) .cse8 (= (_ bv0 32) (select .cse11 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| .cse3 (_ bv4294967276 32)))) .cse9) (and .cse1 (not (bvsge v_prenex_3 main_~MINVAL~0)) .cse2 (= (select .cse11 (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_3)) |main_~#volArray~0.offset| .cse3 (_ bv4294967276 32))) (_ bv0 32)) .cse5 (= .cse15 .cse4) .cse6 .cse7 (bvsge v_prenex_3 (_ bv1 32)) .cse8 .cse9) (and (= (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_4)) (_ bv4294967276 32)) .cse14) .cse10 .cse0 .cse1 .cse2 (not (bvsge v_prenex_4 main_~MINVAL~0)) .cse5 .cse6 (bvsge v_prenex_4 (_ bv1 32)) .cse7 .cse8 .cse9))))) [2018-11-23 10:31:21,409 WARN L180 SmtUtils]: Spent 1.41 s on a formula simplification that was a NOOP. DAG size: 137 [2018-11-23 10:31:23,659 WARN L180 SmtUtils]: Spent 1.59 s on a formula simplification that was a NOOP. DAG size: 143 [2018-11-23 10:31:24,027 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,032 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 126 treesize of output 127 [2018-11-23 10:31:24,119 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,123 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,126 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,132 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,137 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,141 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,145 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,151 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,156 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,159 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,164 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,168 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,174 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,175 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:24,179 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,182 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,185 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,192 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,196 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,200 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,203 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,210 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,214 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,219 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,226 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,230 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,238 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,246 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:24,247 INFO L303 Elim1Store]: Index analysis took 141 ms [2018-11-23 10:31:24,249 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 25 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 101 treesize of output 641 [2018-11-23 10:31:24,264 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:31:24,572 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:32:14,912 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:14,914 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 138 treesize of output 137 [2018-11-23 10:32:15,020 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,021 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:15,024 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,028 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,030 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,034 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,038 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,041 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,044 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,046 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,050 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,054 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,058 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,061 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,064 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,068 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,073 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,076 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,080 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,084 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,089 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,093 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,099 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,102 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,107 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,112 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,116 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,120 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,126 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,130 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,135 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,141 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,145 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,151 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,155 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,159 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:15,162 INFO L303 Elim1Store]: Index analysis took 156 ms [2018-11-23 10:32:15,165 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 36 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 111 treesize of output 828 [2018-11-23 10:32:15,181 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 10:32:15,535 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts.