java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerCInline_WitnessPrinter.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf -i ../../../trunk/examples/svcomp/array-tiling/rewnifrev2_true-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-61f4311 [2018-11-23 10:31:33,996 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 10:31:33,998 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 10:31:34,016 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 10:31:34,016 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 10:31:34,018 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 10:31:34,019 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 10:31:34,021 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 10:31:34,024 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 10:31:34,025 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 10:31:34,029 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 10:31:34,029 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 10:31:34,030 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 10:31:34,034 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 10:31:34,035 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 10:31:34,039 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 10:31:34,040 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 10:31:34,044 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 10:31:34,046 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 10:31:34,047 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 10:31:34,049 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 10:31:34,050 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 10:31:34,052 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-11-23 10:31:34,057 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 10:31:34,058 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 10:31:34,059 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 10:31:34,059 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 10:31:34,059 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-23 10:31:34,085 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 10:31:34,086 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 10:31:34,090 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 10:31:34,090 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 10:31:34,091 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 10:31:34,091 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 10:31:34,091 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 10:31:34,091 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 10:31:34,093 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 10:31:34,093 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 10:31:34,094 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 10:31:34,094 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 10:31:34,094 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 10:31:34,094 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 10:31:34,094 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-23 10:31:34,095 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-23 10:31:34,095 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 10:31:34,095 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 10:31:34,095 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 10:31:34,095 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 10:31:34,096 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 10:31:34,096 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 10:31:34,096 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 10:31:34,096 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 10:31:34,096 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:31:34,097 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 10:31:34,097 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 10:31:34,097 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 10:31:34,097 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-23 10:31:34,097 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 10:31:34,097 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-23 10:31:34,098 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-23 10:31:34,098 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 10:31:34,142 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 10:31:34,157 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 10:31:34,162 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 10:31:34,164 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 10:31:34,165 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 10:31:34,165 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-tiling/rewnifrev2_true-unreach-call.i [2018-11-23 10:31:34,232 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a1319ba47/18bc980c74c042b388b25b49af51ace9/FLAG53cb08d79 [2018-11-23 10:31:34,722 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 10:31:34,723 INFO L161 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-tiling/rewnifrev2_true-unreach-call.i [2018-11-23 10:31:34,730 INFO L355 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a1319ba47/18bc980c74c042b388b25b49af51ace9/FLAG53cb08d79 [2018-11-23 10:31:35,087 INFO L363 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a1319ba47/18bc980c74c042b388b25b49af51ace9 [2018-11-23 10:31:35,098 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 10:31:35,099 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 10:31:35,100 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 10:31:35,100 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 10:31:35,104 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 10:31:35,106 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:31:35" (1/1) ... [2018-11-23 10:31:35,109 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@99430e6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:31:35, skipping insertion in model container [2018-11-23 10:31:35,109 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:31:35" (1/1) ... [2018-11-23 10:31:35,120 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 10:31:35,143 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 10:31:35,403 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:31:35,409 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 10:31:35,436 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:31:35,469 INFO L195 MainTranslator]: Completed translation [2018-11-23 10:31:35,470 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:31:35 WrapperNode [2018-11-23 10:31:35,470 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 10:31:35,471 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 10:31:35,471 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 10:31:35,471 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 10:31:35,482 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:31:35" (1/1) ... [2018-11-23 10:31:35,490 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:31:35" (1/1) ... [2018-11-23 10:31:35,497 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 10:31:35,497 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 10:31:35,498 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 10:31:35,498 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 10:31:35,505 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:31:35" (1/1) ... [2018-11-23 10:31:35,506 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:31:35" (1/1) ... [2018-11-23 10:31:35,508 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:31:35" (1/1) ... [2018-11-23 10:31:35,508 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:31:35" (1/1) ... [2018-11-23 10:31:35,520 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:31:35" (1/1) ... [2018-11-23 10:31:35,527 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:31:35" (1/1) ... [2018-11-23 10:31:35,529 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:31:35" (1/1) ... [2018-11-23 10:31:35,531 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 10:31:35,532 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 10:31:35,532 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 10:31:35,532 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 10:31:35,533 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:31:35" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:31:35,664 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 10:31:35,664 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 10:31:35,664 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 10:31:35,664 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-23 10:31:35,664 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 10:31:35,664 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 10:31:35,664 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 10:31:35,665 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 10:31:35,665 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-23 10:31:35,665 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-23 10:31:35,665 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 10:31:35,665 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-23 10:31:36,184 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 10:31:36,184 INFO L280 CfgBuilder]: Removed 2 assue(true) statements. [2018-11-23 10:31:36,185 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:31:36 BoogieIcfgContainer [2018-11-23 10:31:36,185 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 10:31:36,186 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 10:31:36,186 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 10:31:36,190 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 10:31:36,190 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 10:31:35" (1/3) ... [2018-11-23 10:31:36,191 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@34728d81 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:31:36, skipping insertion in model container [2018-11-23 10:31:36,191 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:31:35" (2/3) ... [2018-11-23 10:31:36,192 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@34728d81 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:31:36, skipping insertion in model container [2018-11-23 10:31:36,192 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:31:36" (3/3) ... [2018-11-23 10:31:36,194 INFO L112 eAbstractionObserver]: Analyzing ICFG rewnifrev2_true-unreach-call.i [2018-11-23 10:31:36,205 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 10:31:36,214 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 10:31:36,232 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 10:31:36,265 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 10:31:36,266 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 10:31:36,266 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 10:31:36,266 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 10:31:36,267 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 10:31:36,267 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 10:31:36,267 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 10:31:36,267 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 10:31:36,267 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 10:31:36,286 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states. [2018-11-23 10:31:36,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-23 10:31:36,292 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:31:36,293 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:31:36,296 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:31:36,301 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:31:36,301 INFO L82 PathProgramCache]: Analyzing trace with hash 1279113652, now seen corresponding path program 1 times [2018-11-23 10:31:36,305 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:31:36,306 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:31:36,337 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:31:36,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:31:36,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:31:36,424 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:31:36,514 INFO L256 TraceCheckUtils]: 0: Hoare triple {29#true} call ULTIMATE.init(); {29#true} is VALID [2018-11-23 10:31:36,518 INFO L273 TraceCheckUtils]: 1: Hoare triple {29#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {29#true} is VALID [2018-11-23 10:31:36,519 INFO L273 TraceCheckUtils]: 2: Hoare triple {29#true} assume true; {29#true} is VALID [2018-11-23 10:31:36,520 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {29#true} {29#true} #56#return; {29#true} is VALID [2018-11-23 10:31:36,520 INFO L256 TraceCheckUtils]: 4: Hoare triple {29#true} call #t~ret5 := main(); {29#true} is VALID [2018-11-23 10:31:36,521 INFO L273 TraceCheckUtils]: 5: Hoare triple {29#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1;havoc ~i~0; {29#true} is VALID [2018-11-23 10:31:36,521 INFO L273 TraceCheckUtils]: 6: Hoare triple {29#true} assume ~bvsgt32(~SIZE~0, 1bv32);call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~i~0 := ~bvsub32(~SIZE~0, 2bv32); {29#true} is VALID [2018-11-23 10:31:36,535 INFO L273 TraceCheckUtils]: 7: Hoare triple {29#true} assume !true; {30#false} is VALID [2018-11-23 10:31:36,536 INFO L273 TraceCheckUtils]: 8: Hoare triple {30#false} ~i~0 := 0bv32; {30#false} is VALID [2018-11-23 10:31:36,536 INFO L273 TraceCheckUtils]: 9: Hoare triple {30#false} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {30#false} is VALID [2018-11-23 10:31:36,536 INFO L256 TraceCheckUtils]: 10: Hoare triple {30#false} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {30#false} is VALID [2018-11-23 10:31:36,537 INFO L273 TraceCheckUtils]: 11: Hoare triple {30#false} ~cond := #in~cond; {30#false} is VALID [2018-11-23 10:31:36,537 INFO L273 TraceCheckUtils]: 12: Hoare triple {30#false} assume 0bv32 == ~cond; {30#false} is VALID [2018-11-23 10:31:36,537 INFO L273 TraceCheckUtils]: 13: Hoare triple {30#false} assume !false; {30#false} is VALID [2018-11-23 10:31:36,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:31:36,541 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:31:36,551 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:31:36,551 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 10:31:36,557 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 14 [2018-11-23 10:31:36,561 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:31:36,564 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states. [2018-11-23 10:31:36,661 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 14 edges. 14 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:31:36,662 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-23 10:31:36,673 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-23 10:31:36,674 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-23 10:31:36,677 INFO L87 Difference]: Start difference. First operand 26 states. Second operand 2 states. [2018-11-23 10:31:36,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:31:36,954 INFO L93 Difference]: Finished difference Result 43 states and 51 transitions. [2018-11-23 10:31:36,954 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-23 10:31:36,955 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 14 [2018-11-23 10:31:36,955 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:31:36,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-23 10:31:36,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 51 transitions. [2018-11-23 10:31:36,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-23 10:31:36,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 51 transitions. [2018-11-23 10:31:36,972 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states and 51 transitions. [2018-11-23 10:31:37,118 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:31:37,129 INFO L225 Difference]: With dead ends: 43 [2018-11-23 10:31:37,129 INFO L226 Difference]: Without dead ends: 20 [2018-11-23 10:31:37,133 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-23 10:31:37,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2018-11-23 10:31:37,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2018-11-23 10:31:37,214 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:31:37,215 INFO L82 GeneralOperation]: Start isEquivalent. First operand 20 states. Second operand 20 states. [2018-11-23 10:31:37,215 INFO L74 IsIncluded]: Start isIncluded. First operand 20 states. Second operand 20 states. [2018-11-23 10:31:37,216 INFO L87 Difference]: Start difference. First operand 20 states. Second operand 20 states. [2018-11-23 10:31:37,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:31:37,220 INFO L93 Difference]: Finished difference Result 20 states and 21 transitions. [2018-11-23 10:31:37,222 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 21 transitions. [2018-11-23 10:31:37,223 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:31:37,223 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:31:37,224 INFO L74 IsIncluded]: Start isIncluded. First operand 20 states. Second operand 20 states. [2018-11-23 10:31:37,224 INFO L87 Difference]: Start difference. First operand 20 states. Second operand 20 states. [2018-11-23 10:31:37,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:31:37,229 INFO L93 Difference]: Finished difference Result 20 states and 21 transitions. [2018-11-23 10:31:37,229 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 21 transitions. [2018-11-23 10:31:37,230 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:31:37,231 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:31:37,232 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:31:37,232 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:31:37,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-11-23 10:31:37,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 21 transitions. [2018-11-23 10:31:37,236 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 21 transitions. Word has length 14 [2018-11-23 10:31:37,237 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:31:37,237 INFO L480 AbstractCegarLoop]: Abstraction has 20 states and 21 transitions. [2018-11-23 10:31:37,237 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-23 10:31:37,237 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 21 transitions. [2018-11-23 10:31:37,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-23 10:31:37,240 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:31:37,241 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:31:37,241 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:31:37,242 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:31:37,242 INFO L82 PathProgramCache]: Analyzing trace with hash 249058862, now seen corresponding path program 1 times [2018-11-23 10:31:37,243 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:31:37,243 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:31:37,272 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:31:37,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:31:37,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:31:37,336 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:31:37,426 INFO L256 TraceCheckUtils]: 0: Hoare triple {194#true} call ULTIMATE.init(); {194#true} is VALID [2018-11-23 10:31:37,426 INFO L273 TraceCheckUtils]: 1: Hoare triple {194#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {194#true} is VALID [2018-11-23 10:31:37,427 INFO L273 TraceCheckUtils]: 2: Hoare triple {194#true} assume true; {194#true} is VALID [2018-11-23 10:31:37,427 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {194#true} {194#true} #56#return; {194#true} is VALID [2018-11-23 10:31:37,427 INFO L256 TraceCheckUtils]: 4: Hoare triple {194#true} call #t~ret5 := main(); {194#true} is VALID [2018-11-23 10:31:37,428 INFO L273 TraceCheckUtils]: 5: Hoare triple {194#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1;havoc ~i~0; {194#true} is VALID [2018-11-23 10:31:37,431 INFO L273 TraceCheckUtils]: 6: Hoare triple {194#true} assume ~bvsgt32(~SIZE~0, 1bv32);call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~i~0 := ~bvsub32(~SIZE~0, 2bv32); {217#(bvsgt (bvadd main_~i~0 (_ bv2 32)) (_ bv1 32))} is VALID [2018-11-23 10:31:37,448 INFO L273 TraceCheckUtils]: 7: Hoare triple {217#(bvsgt (bvadd main_~i~0 (_ bv2 32)) (_ bv1 32))} assume !~bvsge32(~i~0, 0bv32); {195#false} is VALID [2018-11-23 10:31:37,449 INFO L273 TraceCheckUtils]: 8: Hoare triple {195#false} ~i~0 := 0bv32; {195#false} is VALID [2018-11-23 10:31:37,449 INFO L273 TraceCheckUtils]: 9: Hoare triple {195#false} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {195#false} is VALID [2018-11-23 10:31:37,449 INFO L256 TraceCheckUtils]: 10: Hoare triple {195#false} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {195#false} is VALID [2018-11-23 10:31:37,450 INFO L273 TraceCheckUtils]: 11: Hoare triple {195#false} ~cond := #in~cond; {195#false} is VALID [2018-11-23 10:31:37,450 INFO L273 TraceCheckUtils]: 12: Hoare triple {195#false} assume 0bv32 == ~cond; {195#false} is VALID [2018-11-23 10:31:37,450 INFO L273 TraceCheckUtils]: 13: Hoare triple {195#false} assume !false; {195#false} is VALID [2018-11-23 10:31:37,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:31:37,452 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (3)] Exception during sending of exit command (exit): Broken pipe [2018-11-23 10:31:37,457 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:31:37,457 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 10:31:37,459 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 14 [2018-11-23 10:31:37,459 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:31:37,459 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-23 10:31:37,506 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 14 edges. 14 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:31:37,506 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 10:31:37,507 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 10:31:37,507 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:31:37,507 INFO L87 Difference]: Start difference. First operand 20 states and 21 transitions. Second operand 3 states. [2018-11-23 10:31:37,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:31:37,706 INFO L93 Difference]: Finished difference Result 37 states and 40 transitions. [2018-11-23 10:31:37,706 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 10:31:37,706 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 14 [2018-11-23 10:31:37,707 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:31:37,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:31:37,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 40 transitions. [2018-11-23 10:31:37,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:31:37,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 40 transitions. [2018-11-23 10:31:37,713 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 40 transitions. [2018-11-23 10:31:38,116 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:31:38,118 INFO L225 Difference]: With dead ends: 37 [2018-11-23 10:31:38,119 INFO L226 Difference]: Without dead ends: 26 [2018-11-23 10:31:38,120 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:31:38,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2018-11-23 10:31:38,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 21. [2018-11-23 10:31:38,218 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:31:38,219 INFO L82 GeneralOperation]: Start isEquivalent. First operand 26 states. Second operand 21 states. [2018-11-23 10:31:38,219 INFO L74 IsIncluded]: Start isIncluded. First operand 26 states. Second operand 21 states. [2018-11-23 10:31:38,219 INFO L87 Difference]: Start difference. First operand 26 states. Second operand 21 states. [2018-11-23 10:31:38,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:31:38,223 INFO L93 Difference]: Finished difference Result 26 states and 28 transitions. [2018-11-23 10:31:38,223 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 28 transitions. [2018-11-23 10:31:38,223 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:31:38,223 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:31:38,224 INFO L74 IsIncluded]: Start isIncluded. First operand 21 states. Second operand 26 states. [2018-11-23 10:31:38,224 INFO L87 Difference]: Start difference. First operand 21 states. Second operand 26 states. [2018-11-23 10:31:38,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:31:38,227 INFO L93 Difference]: Finished difference Result 26 states and 28 transitions. [2018-11-23 10:31:38,227 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 28 transitions. [2018-11-23 10:31:38,227 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:31:38,228 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:31:38,228 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:31:38,228 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:31:38,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-11-23 10:31:38,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 22 transitions. [2018-11-23 10:31:38,230 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 22 transitions. Word has length 14 [2018-11-23 10:31:38,231 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:31:38,231 INFO L480 AbstractCegarLoop]: Abstraction has 21 states and 22 transitions. [2018-11-23 10:31:38,231 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 10:31:38,231 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 22 transitions. [2018-11-23 10:31:38,232 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-11-23 10:31:38,232 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:31:38,232 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:31:38,232 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:31:38,233 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:31:38,233 INFO L82 PathProgramCache]: Analyzing trace with hash -1260861268, now seen corresponding path program 1 times [2018-11-23 10:31:38,233 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:31:38,234 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:31:38,254 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:31:38,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:31:38,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:31:38,328 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:31:38,538 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 22 [2018-11-23 10:31:38,577 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 25 [2018-11-23 10:31:38,593 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:38,597 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:38,599 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 53 [2018-11-23 10:31:38,606 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-23 10:31:38,628 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:31:38,644 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:31:38,674 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:31:38,675 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:32, output treesize:32 [2018-11-23 10:31:40,032 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 30 [2018-11-23 10:31:40,060 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:40,062 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:40,064 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:40,067 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 2 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 31 [2018-11-23 10:31:40,073 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:31:40,098 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:31:40,126 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:31:40,126 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:48, output treesize:13 [2018-11-23 10:31:40,139 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:31:40,139 WARN L384 uantifierElimination]: Input elimination task: ∃ [|#memory_int|, |main_~#a~0.base|, v_prenex_1]. (let ((.cse0 (select |#memory_int| |main_~#a~0.base|)) (.cse1 (bvmul (_ bv4 32) v_prenex_1))) (and (= (bvadd (select .cse0 (bvadd .cse1 (_ bv8 32))) (_ bv4294967294 32)) v_prenex_1) (not (bvsge v_prenex_1 (_ bv0 32))) (bvsge (bvadd v_prenex_1 (_ bv1 32)) (_ bv0 32)) (= |main_#t~mem4| (select .cse0 (bvmul (_ bv4 32) main_~i~0))) (= main_~i~0 (_ bv0 32)) (= v_prenex_1 (bvadd (select .cse0 (bvadd .cse1 (_ bv4 32))) (_ bv4294967295 32))))) [2018-11-23 10:31:40,139 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ []. (and (not (bvsge (bvadd |main_#t~mem4| (_ bv4294967295 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge |main_#t~mem4| (_ bv0 32))) [2018-11-23 10:31:40,316 INFO L256 TraceCheckUtils]: 0: Hoare triple {371#true} call ULTIMATE.init(); {371#true} is VALID [2018-11-23 10:31:40,316 INFO L273 TraceCheckUtils]: 1: Hoare triple {371#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {371#true} is VALID [2018-11-23 10:31:40,317 INFO L273 TraceCheckUtils]: 2: Hoare triple {371#true} assume true; {371#true} is VALID [2018-11-23 10:31:40,317 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {371#true} {371#true} #56#return; {371#true} is VALID [2018-11-23 10:31:40,317 INFO L256 TraceCheckUtils]: 4: Hoare triple {371#true} call #t~ret5 := main(); {371#true} is VALID [2018-11-23 10:31:40,318 INFO L273 TraceCheckUtils]: 5: Hoare triple {371#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1;havoc ~i~0; {371#true} is VALID [2018-11-23 10:31:40,319 INFO L273 TraceCheckUtils]: 6: Hoare triple {371#true} assume ~bvsgt32(~SIZE~0, 1bv32);call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~i~0 := ~bvsub32(~SIZE~0, 2bv32); {394#(= |main_~#a~0.offset| (_ bv0 32))} is VALID [2018-11-23 10:31:40,323 INFO L273 TraceCheckUtils]: 7: Hoare triple {394#(= |main_~#a~0.offset| (_ bv0 32))} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {398#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)) (= main_~i~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:31:42,329 INFO L273 TraceCheckUtils]: 8: Hoare triple {398#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)) (= main_~i~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= |main_~#a~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {402#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= |main_~#a~0.offset| (_ bv0 32)))} is UNKNOWN [2018-11-23 10:31:42,332 INFO L273 TraceCheckUtils]: 9: Hoare triple {402#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= |main_~#a~0.offset| (_ bv0 32)))} assume !~bvsge32(~i~0, 0bv32); {406#(and (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:31:42,336 INFO L273 TraceCheckUtils]: 10: Hoare triple {406#(and (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0))) (= |main_~#a~0.offset| (_ bv0 32)))} ~i~0 := 0bv32; {410#(and (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_1 (_ BitVec 32))) (and (not (bvsge v_prenex_1 (_ bv0 32))) (bvsge (bvadd v_prenex_1 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_1) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_1) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_1) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_1))))} is VALID [2018-11-23 10:31:42,341 INFO L273 TraceCheckUtils]: 11: Hoare triple {410#(and (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_1 (_ BitVec 32))) (and (not (bvsge v_prenex_1 (_ bv0 32))) (bvsge (bvadd v_prenex_1 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_1) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_1) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_1) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_1))))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {414#(and (not (bvsge (bvadd |main_#t~mem4| (_ bv4294967295 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge |main_#t~mem4| (_ bv0 32)))} is VALID [2018-11-23 10:31:42,343 INFO L256 TraceCheckUtils]: 12: Hoare triple {414#(and (not (bvsge (bvadd |main_#t~mem4| (_ bv4294967295 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge |main_#t~mem4| (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {418#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:31:42,344 INFO L273 TraceCheckUtils]: 13: Hoare triple {418#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {422#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:31:42,351 INFO L273 TraceCheckUtils]: 14: Hoare triple {422#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {372#false} is VALID [2018-11-23 10:31:42,352 INFO L273 TraceCheckUtils]: 15: Hoare triple {372#false} assume !false; {372#false} is VALID [2018-11-23 10:31:42,354 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:31:42,354 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:31:42,356 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:31:42,357 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-23 10:31:42,357 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 16 [2018-11-23 10:31:42,358 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:31:42,358 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 10 states. [2018-11-23 10:31:44,420 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 15 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-23 10:31:44,420 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 10:31:44,420 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 10:31:44,421 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-11-23 10:31:44,421 INFO L87 Difference]: Start difference. First operand 21 states and 22 transitions. Second operand 10 states. [2018-11-23 10:31:46,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:31:46,041 INFO L93 Difference]: Finished difference Result 32 states and 33 transitions. [2018-11-23 10:31:46,041 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 10:31:46,042 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 16 [2018-11-23 10:31:46,042 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:31:46,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2018-11-23 10:31:46,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 33 transitions. [2018-11-23 10:31:46,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2018-11-23 10:31:46,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 33 transitions. [2018-11-23 10:31:46,048 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states and 33 transitions. [2018-11-23 10:31:50,333 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 33 edges. 31 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-23 10:31:50,335 INFO L225 Difference]: With dead ends: 32 [2018-11-23 10:31:50,335 INFO L226 Difference]: Without dead ends: 30 [2018-11-23 10:31:50,336 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=44, Invalid=138, Unknown=0, NotChecked=0, Total=182 [2018-11-23 10:31:50,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2018-11-23 10:31:50,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 27. [2018-11-23 10:31:50,417 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:31:50,417 INFO L82 GeneralOperation]: Start isEquivalent. First operand 30 states. Second operand 27 states. [2018-11-23 10:31:50,417 INFO L74 IsIncluded]: Start isIncluded. First operand 30 states. Second operand 27 states. [2018-11-23 10:31:50,417 INFO L87 Difference]: Start difference. First operand 30 states. Second operand 27 states. [2018-11-23 10:31:50,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:31:50,420 INFO L93 Difference]: Finished difference Result 30 states and 31 transitions. [2018-11-23 10:31:50,420 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 31 transitions. [2018-11-23 10:31:50,421 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:31:50,421 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:31:50,421 INFO L74 IsIncluded]: Start isIncluded. First operand 27 states. Second operand 30 states. [2018-11-23 10:31:50,421 INFO L87 Difference]: Start difference. First operand 27 states. Second operand 30 states. [2018-11-23 10:31:50,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:31:50,427 INFO L93 Difference]: Finished difference Result 30 states and 31 transitions. [2018-11-23 10:31:50,427 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 31 transitions. [2018-11-23 10:31:50,429 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:31:50,429 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:31:50,429 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:31:50,429 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:31:50,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-11-23 10:31:50,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2018-11-23 10:31:50,432 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 28 transitions. Word has length 16 [2018-11-23 10:31:50,432 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:31:50,432 INFO L480 AbstractCegarLoop]: Abstraction has 27 states and 28 transitions. [2018-11-23 10:31:50,432 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 10:31:50,433 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 28 transitions. [2018-11-23 10:31:50,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-11-23 10:31:50,434 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:31:50,434 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:31:50,434 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:31:50,434 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:31:50,434 INFO L82 PathProgramCache]: Analyzing trace with hash 1302703327, now seen corresponding path program 1 times [2018-11-23 10:31:50,435 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:31:50,435 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:31:50,451 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:31:50,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:31:50,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:31:50,518 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:31:50,583 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 22 [2018-11-23 10:31:50,592 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 25 [2018-11-23 10:31:50,603 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:50,605 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:50,606 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 53 [2018-11-23 10:31:50,611 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-23 10:31:50,635 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:31:50,652 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:31:50,675 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:31:50,676 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:32, output treesize:32 [2018-11-23 10:31:54,933 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 30 [2018-11-23 10:31:54,951 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:54,953 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:54,956 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:54,959 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 2 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 33 [2018-11-23 10:31:54,969 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:31:54,982 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:31:55,001 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:31:55,001 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:50, output treesize:17 [2018-11-23 10:31:55,012 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:31:55,012 WARN L384 uantifierElimination]: Input elimination task: ∃ [|#memory_int|, |main_~#a~0.base|, v_prenex_2]. (let ((.cse0 (select |#memory_int| |main_~#a~0.base|)) (.cse1 (bvmul (_ bv4 32) v_prenex_2))) (and (= (bvadd (select .cse0 (bvadd .cse1 (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32)) (= |main_#t~mem4| (select .cse0 (bvmul (_ bv4 32) main_~i~0))) (= (bvadd (select .cse0 (bvadd .cse1 (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))) [2018-11-23 10:31:55,012 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ []. (and (bvsge (bvadd |main_#t~mem4| (_ bv4294967295 32)) (_ bv0 32)) (not (bvsge (bvadd |main_#t~mem4| (_ bv4294967294 32)) (_ bv0 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) [2018-11-23 10:31:55,138 INFO L256 TraceCheckUtils]: 0: Hoare triple {579#true} call ULTIMATE.init(); {579#true} is VALID [2018-11-23 10:31:55,138 INFO L273 TraceCheckUtils]: 1: Hoare triple {579#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {579#true} is VALID [2018-11-23 10:31:55,139 INFO L273 TraceCheckUtils]: 2: Hoare triple {579#true} assume true; {579#true} is VALID [2018-11-23 10:31:55,139 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {579#true} {579#true} #56#return; {579#true} is VALID [2018-11-23 10:31:55,139 INFO L256 TraceCheckUtils]: 4: Hoare triple {579#true} call #t~ret5 := main(); {579#true} is VALID [2018-11-23 10:31:55,139 INFO L273 TraceCheckUtils]: 5: Hoare triple {579#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1;havoc ~i~0; {579#true} is VALID [2018-11-23 10:31:55,140 INFO L273 TraceCheckUtils]: 6: Hoare triple {579#true} assume ~bvsgt32(~SIZE~0, 1bv32);call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~i~0 := ~bvsub32(~SIZE~0, 2bv32); {602#(= |main_~#a~0.offset| (_ bv0 32))} is VALID [2018-11-23 10:31:55,145 INFO L273 TraceCheckUtils]: 7: Hoare triple {602#(= |main_~#a~0.offset| (_ bv0 32))} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {606#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)) (= main_~i~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:31:57,150 INFO L273 TraceCheckUtils]: 8: Hoare triple {606#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)) (= main_~i~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= |main_~#a~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {610#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= |main_~#a~0.offset| (_ bv0 32)))} is UNKNOWN [2018-11-23 10:31:57,154 INFO L273 TraceCheckUtils]: 9: Hoare triple {610#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= |main_~#a~0.offset| (_ bv0 32)))} assume !~bvsge32(~i~0, 0bv32); {614#(and (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:31:57,157 INFO L273 TraceCheckUtils]: 10: Hoare triple {614#(and (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0))) (= |main_~#a~0.offset| (_ bv0 32)))} ~i~0 := 0bv32; {618#(and (exists ((v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:31:57,159 INFO L273 TraceCheckUtils]: 11: Hoare triple {618#(and (exists ((v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {618#(and (exists ((v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:31:57,163 INFO L256 TraceCheckUtils]: 12: Hoare triple {618#(and (exists ((v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {625#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32))))} is VALID [2018-11-23 10:31:57,164 INFO L273 TraceCheckUtils]: 13: Hoare triple {625#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32))))} ~cond := #in~cond; {625#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32))))} is VALID [2018-11-23 10:31:57,165 INFO L273 TraceCheckUtils]: 14: Hoare triple {625#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32))))} assume !(0bv32 == ~cond); {625#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32))))} is VALID [2018-11-23 10:31:57,165 INFO L273 TraceCheckUtils]: 15: Hoare triple {625#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32))))} assume true; {625#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32))))} is VALID [2018-11-23 10:31:57,166 INFO L268 TraceCheckUtils]: 16: Hoare quadruple {625#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32))))} {618#(and (exists ((v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} #60#return; {618#(and (exists ((v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:31:57,167 INFO L273 TraceCheckUtils]: 17: Hoare triple {618#(and (exists ((v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} havoc #t~mem4; {618#(and (exists ((v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:31:57,171 INFO L273 TraceCheckUtils]: 18: Hoare triple {618#(and (exists ((v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {644#(and (exists ((v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:31:57,175 INFO L273 TraceCheckUtils]: 19: Hoare triple {644#(and (exists ((v_prenex_2 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_2) (not (bvsge v_prenex_2 (_ bv0 32))) (bvsge (bvadd v_prenex_2 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_2) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_2))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {648#(and (bvsge (bvadd |main_#t~mem4| (_ bv4294967295 32)) (_ bv0 32)) (not (bvsge (bvadd |main_#t~mem4| (_ bv4294967294 32)) (_ bv0 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:31:57,178 INFO L256 TraceCheckUtils]: 20: Hoare triple {648#(and (bvsge (bvadd |main_#t~mem4| (_ bv4294967295 32)) (_ bv0 32)) (not (bvsge (bvadd |main_#t~mem4| (_ bv4294967294 32)) (_ bv0 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {652#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:31:57,179 INFO L273 TraceCheckUtils]: 21: Hoare triple {652#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {656#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:31:57,196 INFO L273 TraceCheckUtils]: 22: Hoare triple {656#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {580#false} is VALID [2018-11-23 10:31:57,196 INFO L273 TraceCheckUtils]: 23: Hoare triple {580#false} assume !false; {580#false} is VALID [2018-11-23 10:31:57,203 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:31:57,203 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:31:57,901 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-11-23 10:31:57,902 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-23 10:31:57,903 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:31:57,903 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:36, output treesize:1 [2018-11-23 10:31:57,927 INFO L273 TraceCheckUtils]: 23: Hoare triple {580#false} assume !false; {580#false} is VALID [2018-11-23 10:31:57,927 INFO L273 TraceCheckUtils]: 22: Hoare triple {666#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume 0bv32 == ~cond; {580#false} is VALID [2018-11-23 10:31:57,928 INFO L273 TraceCheckUtils]: 21: Hoare triple {670#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {666#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-23 10:31:57,929 INFO L256 TraceCheckUtils]: 20: Hoare triple {674#(bvsge |main_#t~mem4| main_~i~0)} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {670#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-23 10:31:57,930 INFO L273 TraceCheckUtils]: 19: Hoare triple {678#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~i~0)} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {674#(bvsge |main_#t~mem4| main_~i~0)} is VALID [2018-11-23 10:31:59,945 INFO L273 TraceCheckUtils]: 18: Hoare triple {682#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {678#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~i~0)} is UNKNOWN [2018-11-23 10:31:59,946 INFO L273 TraceCheckUtils]: 17: Hoare triple {682#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} havoc #t~mem4; {682#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} is VALID [2018-11-23 10:31:59,947 INFO L268 TraceCheckUtils]: 16: Hoare quadruple {579#true} {682#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} #60#return; {682#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} is VALID [2018-11-23 10:31:59,948 INFO L273 TraceCheckUtils]: 15: Hoare triple {579#true} assume true; {579#true} is VALID [2018-11-23 10:31:59,948 INFO L273 TraceCheckUtils]: 14: Hoare triple {579#true} assume !(0bv32 == ~cond); {579#true} is VALID [2018-11-23 10:31:59,948 INFO L273 TraceCheckUtils]: 13: Hoare triple {579#true} ~cond := #in~cond; {579#true} is VALID [2018-11-23 10:31:59,948 INFO L256 TraceCheckUtils]: 12: Hoare triple {682#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {579#true} is VALID [2018-11-23 10:31:59,949 INFO L273 TraceCheckUtils]: 11: Hoare triple {682#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {682#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} is VALID [2018-11-23 10:31:59,950 INFO L273 TraceCheckUtils]: 10: Hoare triple {707#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv4 32))) (_ bv1 32))} ~i~0 := 0bv32; {682#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} is VALID [2018-11-23 10:31:59,950 INFO L273 TraceCheckUtils]: 9: Hoare triple {711#(or (bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv4 32))) (_ bv1 32)) (bvsge main_~i~0 (_ bv0 32)))} assume !~bvsge32(~i~0, 0bv32); {707#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv4 32))) (_ bv1 32))} is VALID [2018-11-23 10:31:59,955 INFO L273 TraceCheckUtils]: 8: Hoare triple {715#(or (bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv4 32))) (_ bv1 32)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {711#(or (bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv4 32))) (_ bv1 32)) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:31:59,967 INFO L273 TraceCheckUtils]: 7: Hoare triple {579#true} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {715#(or (bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv4 32))) (_ bv1 32)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:31:59,968 INFO L273 TraceCheckUtils]: 6: Hoare triple {579#true} assume ~bvsgt32(~SIZE~0, 1bv32);call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~i~0 := ~bvsub32(~SIZE~0, 2bv32); {579#true} is VALID [2018-11-23 10:31:59,968 INFO L273 TraceCheckUtils]: 5: Hoare triple {579#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1;havoc ~i~0; {579#true} is VALID [2018-11-23 10:31:59,968 INFO L256 TraceCheckUtils]: 4: Hoare triple {579#true} call #t~ret5 := main(); {579#true} is VALID [2018-11-23 10:31:59,968 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {579#true} {579#true} #56#return; {579#true} is VALID [2018-11-23 10:31:59,969 INFO L273 TraceCheckUtils]: 2: Hoare triple {579#true} assume true; {579#true} is VALID [2018-11-23 10:31:59,969 INFO L273 TraceCheckUtils]: 1: Hoare triple {579#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {579#true} is VALID [2018-11-23 10:31:59,970 INFO L256 TraceCheckUtils]: 0: Hoare triple {579#true} call ULTIMATE.init(); {579#true} is VALID [2018-11-23 10:31:59,971 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 3 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:31:59,973 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:31:59,973 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 10] total 20 [2018-11-23 10:31:59,974 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 24 [2018-11-23 10:31:59,974 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:31:59,975 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 20 states. [2018-11-23 10:32:04,205 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 41 edges. 39 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-23 10:32:04,205 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-23 10:32:04,206 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-23 10:32:04,206 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=306, Unknown=0, NotChecked=0, Total=380 [2018-11-23 10:32:04,207 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. Second operand 20 states. [2018-11-23 10:32:16,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:32:16,255 INFO L93 Difference]: Finished difference Result 40 states and 41 transitions. [2018-11-23 10:32:16,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 10:32:16,255 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 24 [2018-11-23 10:32:16,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:32:16,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-11-23 10:32:16,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 38 transitions. [2018-11-23 10:32:16,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-11-23 10:32:16,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 38 transitions. [2018-11-23 10:32:16,261 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 16 states and 38 transitions. [2018-11-23 10:32:20,618 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 36 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-23 10:32:20,620 INFO L225 Difference]: With dead ends: 40 [2018-11-23 10:32:20,620 INFO L226 Difference]: Without dead ends: 38 [2018-11-23 10:32:20,622 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 29 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 146 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=149, Invalid=607, Unknown=0, NotChecked=0, Total=756 [2018-11-23 10:32:20,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2018-11-23 10:32:20,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 35. [2018-11-23 10:32:20,822 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:32:20,823 INFO L82 GeneralOperation]: Start isEquivalent. First operand 38 states. Second operand 35 states. [2018-11-23 10:32:20,823 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand 35 states. [2018-11-23 10:32:20,823 INFO L87 Difference]: Start difference. First operand 38 states. Second operand 35 states. [2018-11-23 10:32:20,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:32:20,826 INFO L93 Difference]: Finished difference Result 38 states and 39 transitions. [2018-11-23 10:32:20,826 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 39 transitions. [2018-11-23 10:32:20,826 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:32:20,827 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:32:20,827 INFO L74 IsIncluded]: Start isIncluded. First operand 35 states. Second operand 38 states. [2018-11-23 10:32:20,827 INFO L87 Difference]: Start difference. First operand 35 states. Second operand 38 states. [2018-11-23 10:32:20,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:32:20,830 INFO L93 Difference]: Finished difference Result 38 states and 39 transitions. [2018-11-23 10:32:20,830 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 39 transitions. [2018-11-23 10:32:20,830 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:32:20,831 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:32:20,831 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:32:20,831 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:32:20,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35 states. [2018-11-23 10:32:20,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 36 transitions. [2018-11-23 10:32:20,833 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 36 transitions. Word has length 24 [2018-11-23 10:32:20,833 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:32:20,833 INFO L480 AbstractCegarLoop]: Abstraction has 35 states and 36 transitions. [2018-11-23 10:32:20,834 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-23 10:32:20,834 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 36 transitions. [2018-11-23 10:32:20,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-23 10:32:20,835 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:32:20,835 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:32:20,836 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:32:20,836 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:32:20,836 INFO L82 PathProgramCache]: Analyzing trace with hash -688869870, now seen corresponding path program 2 times [2018-11-23 10:32:20,836 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:32:20,836 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:32:20,862 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 10:32:20,913 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 10:32:20,913 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:32:20,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:32:20,929 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:32:21,283 INFO L256 TraceCheckUtils]: 0: Hoare triple {940#true} call ULTIMATE.init(); {940#true} is VALID [2018-11-23 10:32:21,284 INFO L273 TraceCheckUtils]: 1: Hoare triple {940#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {940#true} is VALID [2018-11-23 10:32:21,284 INFO L273 TraceCheckUtils]: 2: Hoare triple {940#true} assume true; {940#true} is VALID [2018-11-23 10:32:21,284 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {940#true} {940#true} #56#return; {940#true} is VALID [2018-11-23 10:32:21,284 INFO L256 TraceCheckUtils]: 4: Hoare triple {940#true} call #t~ret5 := main(); {940#true} is VALID [2018-11-23 10:32:21,285 INFO L273 TraceCheckUtils]: 5: Hoare triple {940#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1;havoc ~i~0; {940#true} is VALID [2018-11-23 10:32:21,296 INFO L273 TraceCheckUtils]: 6: Hoare triple {940#true} assume ~bvsgt32(~SIZE~0, 1bv32);call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~i~0 := ~bvsub32(~SIZE~0, 2bv32); {963#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} is VALID [2018-11-23 10:32:21,296 INFO L273 TraceCheckUtils]: 7: Hoare triple {963#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {967#(and (= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:32:21,351 INFO L273 TraceCheckUtils]: 8: Hoare triple {967#(and (= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {971#(and (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0))} is VALID [2018-11-23 10:32:21,354 INFO L273 TraceCheckUtils]: 9: Hoare triple {971#(and (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0))} assume !~bvsge32(~i~0, 0bv32); {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,355 INFO L273 TraceCheckUtils]: 10: Hoare triple {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} ~i~0 := 0bv32; {979#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,356 INFO L273 TraceCheckUtils]: 11: Hoare triple {979#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {979#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,357 INFO L256 TraceCheckUtils]: 12: Hoare triple {979#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,362 INFO L273 TraceCheckUtils]: 13: Hoare triple {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} ~cond := #in~cond; {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,363 INFO L273 TraceCheckUtils]: 14: Hoare triple {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume !(0bv32 == ~cond); {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,364 INFO L273 TraceCheckUtils]: 15: Hoare triple {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume true; {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,364 INFO L268 TraceCheckUtils]: 16: Hoare quadruple {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} {979#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} #60#return; {979#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,365 INFO L273 TraceCheckUtils]: 17: Hoare triple {979#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} havoc #t~mem4; {979#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,366 INFO L273 TraceCheckUtils]: 18: Hoare triple {979#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1004#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,367 INFO L273 TraceCheckUtils]: 19: Hoare triple {1004#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1004#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,368 INFO L256 TraceCheckUtils]: 20: Hoare triple {1004#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,369 INFO L273 TraceCheckUtils]: 21: Hoare triple {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} ~cond := #in~cond; {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,370 INFO L273 TraceCheckUtils]: 22: Hoare triple {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume !(0bv32 == ~cond); {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,371 INFO L273 TraceCheckUtils]: 23: Hoare triple {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume true; {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,375 INFO L268 TraceCheckUtils]: 24: Hoare quadruple {975#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} {1004#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #60#return; {1004#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,375 INFO L273 TraceCheckUtils]: 25: Hoare triple {1004#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem4; {1004#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,376 INFO L273 TraceCheckUtils]: 26: Hoare triple {1004#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1029#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:32:21,378 INFO L273 TraceCheckUtils]: 27: Hoare triple {1029#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {941#false} is VALID [2018-11-23 10:32:21,378 INFO L256 TraceCheckUtils]: 28: Hoare triple {941#false} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {941#false} is VALID [2018-11-23 10:32:21,379 INFO L273 TraceCheckUtils]: 29: Hoare triple {941#false} ~cond := #in~cond; {941#false} is VALID [2018-11-23 10:32:21,379 INFO L273 TraceCheckUtils]: 30: Hoare triple {941#false} assume 0bv32 == ~cond; {941#false} is VALID [2018-11-23 10:32:21,379 INFO L273 TraceCheckUtils]: 31: Hoare triple {941#false} assume !false; {941#false} is VALID [2018-11-23 10:32:21,382 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 6 proven. 7 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-23 10:32:21,383 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:32:21,903 INFO L273 TraceCheckUtils]: 31: Hoare triple {941#false} assume !false; {941#false} is VALID [2018-11-23 10:32:21,903 INFO L273 TraceCheckUtils]: 30: Hoare triple {941#false} assume 0bv32 == ~cond; {941#false} is VALID [2018-11-23 10:32:21,903 INFO L273 TraceCheckUtils]: 29: Hoare triple {941#false} ~cond := #in~cond; {941#false} is VALID [2018-11-23 10:32:21,904 INFO L256 TraceCheckUtils]: 28: Hoare triple {941#false} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {941#false} is VALID [2018-11-23 10:32:21,908 INFO L273 TraceCheckUtils]: 27: Hoare triple {1057#(not (bvslt main_~i~0 ~SIZE~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {941#false} is VALID [2018-11-23 10:32:21,909 INFO L273 TraceCheckUtils]: 26: Hoare triple {1061#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1057#(not (bvslt main_~i~0 ~SIZE~0))} is VALID [2018-11-23 10:32:21,910 INFO L273 TraceCheckUtils]: 25: Hoare triple {1061#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} havoc #t~mem4; {1061#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-23 10:32:21,911 INFO L268 TraceCheckUtils]: 24: Hoare quadruple {940#true} {1061#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} #60#return; {1061#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-23 10:32:21,911 INFO L273 TraceCheckUtils]: 23: Hoare triple {940#true} assume true; {940#true} is VALID [2018-11-23 10:32:21,911 INFO L273 TraceCheckUtils]: 22: Hoare triple {940#true} assume !(0bv32 == ~cond); {940#true} is VALID [2018-11-23 10:32:21,912 INFO L273 TraceCheckUtils]: 21: Hoare triple {940#true} ~cond := #in~cond; {940#true} is VALID [2018-11-23 10:32:21,912 INFO L256 TraceCheckUtils]: 20: Hoare triple {1061#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {940#true} is VALID [2018-11-23 10:32:21,913 INFO L273 TraceCheckUtils]: 19: Hoare triple {1061#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1061#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-23 10:32:21,935 INFO L273 TraceCheckUtils]: 18: Hoare triple {1086#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1061#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-23 10:32:21,935 INFO L273 TraceCheckUtils]: 17: Hoare triple {1086#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} havoc #t~mem4; {1086#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-23 10:32:21,936 INFO L268 TraceCheckUtils]: 16: Hoare quadruple {940#true} {1086#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} #60#return; {1086#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-23 10:32:21,936 INFO L273 TraceCheckUtils]: 15: Hoare triple {940#true} assume true; {940#true} is VALID [2018-11-23 10:32:21,936 INFO L273 TraceCheckUtils]: 14: Hoare triple {940#true} assume !(0bv32 == ~cond); {940#true} is VALID [2018-11-23 10:32:21,937 INFO L273 TraceCheckUtils]: 13: Hoare triple {940#true} ~cond := #in~cond; {940#true} is VALID [2018-11-23 10:32:21,937 INFO L256 TraceCheckUtils]: 12: Hoare triple {1086#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {940#true} is VALID [2018-11-23 10:32:21,937 INFO L273 TraceCheckUtils]: 11: Hoare triple {1086#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1086#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-23 10:32:21,938 INFO L273 TraceCheckUtils]: 10: Hoare triple {1111#(not (bvslt (_ bv2 32) ~SIZE~0))} ~i~0 := 0bv32; {1086#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-23 10:32:21,938 INFO L273 TraceCheckUtils]: 9: Hoare triple {1115#(or (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} assume !~bvsge32(~i~0, 0bv32); {1111#(not (bvslt (_ bv2 32) ~SIZE~0))} is VALID [2018-11-23 10:32:21,939 INFO L273 TraceCheckUtils]: 8: Hoare triple {1119#(or (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1115#(or (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:32:21,939 INFO L273 TraceCheckUtils]: 7: Hoare triple {1123#(or (not (bvsge main_~i~0 (_ bv0 32))) (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1119#(or (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,943 INFO L273 TraceCheckUtils]: 6: Hoare triple {940#true} assume ~bvsgt32(~SIZE~0, 1bv32);call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~i~0 := ~bvsub32(~SIZE~0, 2bv32); {1123#(or (not (bvsge main_~i~0 (_ bv0 32))) (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:21,943 INFO L273 TraceCheckUtils]: 5: Hoare triple {940#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1;havoc ~i~0; {940#true} is VALID [2018-11-23 10:32:21,944 INFO L256 TraceCheckUtils]: 4: Hoare triple {940#true} call #t~ret5 := main(); {940#true} is VALID [2018-11-23 10:32:21,944 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {940#true} {940#true} #56#return; {940#true} is VALID [2018-11-23 10:32:21,944 INFO L273 TraceCheckUtils]: 2: Hoare triple {940#true} assume true; {940#true} is VALID [2018-11-23 10:32:21,945 INFO L273 TraceCheckUtils]: 1: Hoare triple {940#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {940#true} is VALID [2018-11-23 10:32:21,945 INFO L256 TraceCheckUtils]: 0: Hoare triple {940#true} call ULTIMATE.init(); {940#true} is VALID [2018-11-23 10:32:21,946 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 6 proven. 7 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-23 10:32:21,948 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:32:21,948 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 16 [2018-11-23 10:32:21,948 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 32 [2018-11-23 10:32:21,949 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:32:21,949 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 16 states. [2018-11-23 10:32:22,132 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 48 edges. 48 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:32:22,132 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-23 10:32:22,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-23 10:32:22,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=161, Unknown=0, NotChecked=0, Total=240 [2018-11-23 10:32:22,133 INFO L87 Difference]: Start difference. First operand 35 states and 36 transitions. Second operand 16 states. [2018-11-23 10:32:23,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:32:23,934 INFO L93 Difference]: Finished difference Result 72 states and 75 transitions. [2018-11-23 10:32:23,934 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 10:32:23,934 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 32 [2018-11-23 10:32:23,935 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:32:23,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-23 10:32:23,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 66 transitions. [2018-11-23 10:32:23,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-23 10:32:23,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 66 transitions. [2018-11-23 10:32:23,943 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 13 states and 66 transitions. [2018-11-23 10:32:24,114 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 66 edges. 66 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:32:24,115 INFO L225 Difference]: With dead ends: 72 [2018-11-23 10:32:24,116 INFO L226 Difference]: Without dead ends: 44 [2018-11-23 10:32:24,117 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 56 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=87, Invalid=185, Unknown=0, NotChecked=0, Total=272 [2018-11-23 10:32:24,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-11-23 10:32:24,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 37. [2018-11-23 10:32:24,252 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:32:24,252 INFO L82 GeneralOperation]: Start isEquivalent. First operand 44 states. Second operand 37 states. [2018-11-23 10:32:24,252 INFO L74 IsIncluded]: Start isIncluded. First operand 44 states. Second operand 37 states. [2018-11-23 10:32:24,252 INFO L87 Difference]: Start difference. First operand 44 states. Second operand 37 states. [2018-11-23 10:32:24,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:32:24,256 INFO L93 Difference]: Finished difference Result 44 states and 46 transitions. [2018-11-23 10:32:24,256 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 46 transitions. [2018-11-23 10:32:24,257 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:32:24,257 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:32:24,257 INFO L74 IsIncluded]: Start isIncluded. First operand 37 states. Second operand 44 states. [2018-11-23 10:32:24,257 INFO L87 Difference]: Start difference. First operand 37 states. Second operand 44 states. [2018-11-23 10:32:24,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:32:24,260 INFO L93 Difference]: Finished difference Result 44 states and 46 transitions. [2018-11-23 10:32:24,260 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 46 transitions. [2018-11-23 10:32:24,261 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:32:24,261 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:32:24,261 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:32:24,261 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:32:24,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-11-23 10:32:24,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 38 transitions. [2018-11-23 10:32:24,264 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 38 transitions. Word has length 32 [2018-11-23 10:32:24,264 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:32:24,264 INFO L480 AbstractCegarLoop]: Abstraction has 37 states and 38 transitions. [2018-11-23 10:32:24,264 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-23 10:32:24,264 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 38 transitions. [2018-11-23 10:32:24,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-23 10:32:24,265 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:32:24,265 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:32:24,265 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:32:24,266 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:32:24,266 INFO L82 PathProgramCache]: Analyzing trace with hash 374652176, now seen corresponding path program 3 times [2018-11-23 10:32:24,266 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:32:24,266 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:32:24,300 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2018-11-23 10:32:24,405 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-11-23 10:32:24,405 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:32:24,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:32:24,447 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:32:24,509 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 22 [2018-11-23 10:32:24,515 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 25 [2018-11-23 10:32:24,523 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:24,526 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:24,527 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 53 [2018-11-23 10:32:24,528 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-23 10:32:24,549 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:32:24,566 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:32:24,590 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:32:24,591 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:32, output treesize:32 [2018-11-23 10:32:24,741 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 47 [2018-11-23 10:32:24,802 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:24,807 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:24,810 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:24,814 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:24,816 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:24,819 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:24,821 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 129 [2018-11-23 10:32:24,897 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 89 treesize of output 114 [2018-11-23 10:32:24,907 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-23 10:32:24,954 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:32:24,978 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:32:25,023 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:32:25,023 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:65, output treesize:51 [2018-11-23 10:32:30,571 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 41 [2018-11-23 10:32:30,581 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:30,582 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:30,583 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:30,584 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:30,585 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:30,587 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:30,588 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:30,591 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:32:30,593 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 81 [2018-11-23 10:32:30,595 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:32:30,625 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:32:30,646 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:32:30,647 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:66, output treesize:15 [2018-11-23 10:32:30,662 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:32:30,663 WARN L384 uantifierElimination]: Input elimination task: ∃ [|#memory_int|, |main_~#a~0.base|, v_prenex_4]. (let ((.cse0 (select |#memory_int| |main_~#a~0.base|)) (.cse1 (bvmul (_ bv4 32) v_prenex_4))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (= (select .cse0 (bvadd .cse1 (_ bv12 32))) (bvadd v_prenex_4 (_ bv3 32))) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= v_prenex_4 (bvadd (select .cse0 (bvadd .cse1 (_ bv4 32))) (_ bv4294967295 32))) (= |main_#t~mem4| (select .cse0 (bvmul (_ bv4 32) main_~i~0))) (= (bvadd (select .cse0 (bvadd .cse1 (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (_ bv2 32) main_~i~0))) [2018-11-23 10:32:30,663 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ []. (and (bvsge (bvadd |main_#t~mem4| (_ bv4294967294 32)) (_ bv0 32)) (not (bvsge (bvadd |main_#t~mem4| (_ bv4294967293 32)) (_ bv0 32))) (= (_ bv2 32) main_~i~0)) [2018-11-23 10:32:30,809 INFO L256 TraceCheckUtils]: 0: Hoare triple {1390#true} call ULTIMATE.init(); {1390#true} is VALID [2018-11-23 10:32:30,809 INFO L273 TraceCheckUtils]: 1: Hoare triple {1390#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {1390#true} is VALID [2018-11-23 10:32:30,809 INFO L273 TraceCheckUtils]: 2: Hoare triple {1390#true} assume true; {1390#true} is VALID [2018-11-23 10:32:30,809 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1390#true} {1390#true} #56#return; {1390#true} is VALID [2018-11-23 10:32:30,810 INFO L256 TraceCheckUtils]: 4: Hoare triple {1390#true} call #t~ret5 := main(); {1390#true} is VALID [2018-11-23 10:32:30,810 INFO L273 TraceCheckUtils]: 5: Hoare triple {1390#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1;havoc ~i~0; {1390#true} is VALID [2018-11-23 10:32:30,810 INFO L273 TraceCheckUtils]: 6: Hoare triple {1390#true} assume ~bvsgt32(~SIZE~0, 1bv32);call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~i~0 := ~bvsub32(~SIZE~0, 2bv32); {1413#(= |main_~#a~0.offset| (_ bv0 32))} is VALID [2018-11-23 10:32:30,814 INFO L273 TraceCheckUtils]: 7: Hoare triple {1413#(= |main_~#a~0.offset| (_ bv0 32))} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1417#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)) (= main_~i~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:32,818 INFO L273 TraceCheckUtils]: 8: Hoare triple {1417#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)) (= main_~i~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= |main_~#a~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1421#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= |main_~#a~0.offset| (_ bv0 32)))} is UNKNOWN [2018-11-23 10:32:32,858 INFO L273 TraceCheckUtils]: 9: Hoare triple {1421#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= |main_~#a~0.offset| (_ bv0 32)))} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1425#(and (= (bvadd main_~i~0 (_ bv2 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv0 32)) (= main_~i~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:34,862 INFO L273 TraceCheckUtils]: 10: Hoare triple {1425#(and (= (bvadd main_~i~0 (_ bv2 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv0 32)) (= main_~i~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= |main_~#a~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1429#(and (= (bvadd main_~i~0 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= |main_~#a~0.offset| (_ bv0 32)))} is UNKNOWN [2018-11-23 10:32:34,867 INFO L273 TraceCheckUtils]: 11: Hoare triple {1429#(and (= (bvadd main_~i~0 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= |main_~#a~0.offset| (_ bv0 32)))} assume !~bvsge32(~i~0, 0bv32); {1433#(and (exists ((main_~i~0 (_ BitVec 32))) (and (= (bvadd main_~i~0 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:34,873 INFO L273 TraceCheckUtils]: 12: Hoare triple {1433#(and (exists ((main_~i~0 (_ BitVec 32))) (and (= (bvadd main_~i~0 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0))) (= |main_~#a~0.offset| (_ bv0 32)))} ~i~0 := 0bv32; {1437#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:32:34,874 INFO L273 TraceCheckUtils]: 13: Hoare triple {1437#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1437#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:32:34,881 INFO L256 TraceCheckUtils]: 14: Hoare triple {1437#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} is VALID [2018-11-23 10:32:34,882 INFO L273 TraceCheckUtils]: 15: Hoare triple {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} ~cond := #in~cond; {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} is VALID [2018-11-23 10:32:34,882 INFO L273 TraceCheckUtils]: 16: Hoare triple {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} assume !(0bv32 == ~cond); {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} is VALID [2018-11-23 10:32:34,883 INFO L273 TraceCheckUtils]: 17: Hoare triple {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} assume true; {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} is VALID [2018-11-23 10:32:34,884 INFO L268 TraceCheckUtils]: 18: Hoare quadruple {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} {1437#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} #60#return; {1437#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:32:34,885 INFO L273 TraceCheckUtils]: 19: Hoare triple {1437#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} havoc #t~mem4; {1437#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:32:34,887 INFO L273 TraceCheckUtils]: 20: Hoare triple {1437#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1463#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:34,888 INFO L273 TraceCheckUtils]: 21: Hoare triple {1463#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1463#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:34,896 INFO L256 TraceCheckUtils]: 22: Hoare triple {1463#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} is VALID [2018-11-23 10:32:34,897 INFO L273 TraceCheckUtils]: 23: Hoare triple {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} ~cond := #in~cond; {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} is VALID [2018-11-23 10:32:34,897 INFO L273 TraceCheckUtils]: 24: Hoare triple {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} assume !(0bv32 == ~cond); {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} is VALID [2018-11-23 10:32:34,898 INFO L273 TraceCheckUtils]: 25: Hoare triple {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} assume true; {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} is VALID [2018-11-23 10:32:34,898 INFO L268 TraceCheckUtils]: 26: Hoare quadruple {1444#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_4 (_ BitVec 32))) (and (= (bvadd v_prenex_4 (_ bv2 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32)))) (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd v_prenex_4 (_ bv1 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32)))) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32))))))} {1463#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #60#return; {1463#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:34,899 INFO L273 TraceCheckUtils]: 27: Hoare triple {1463#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem4; {1463#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:34,900 INFO L273 TraceCheckUtils]: 28: Hoare triple {1463#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1488#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:32:34,908 INFO L273 TraceCheckUtils]: 29: Hoare triple {1488#(and (exists ((v_prenex_4 (_ BitVec 32))) (and (not (bvsge v_prenex_4 (_ bv0 32))) (bvsge (bvadd v_prenex_4 (_ bv2 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_4 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_4) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_4) (= (bvadd v_prenex_4 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_4) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1492#(and (bvsge (bvadd |main_#t~mem4| (_ bv4294967294 32)) (_ bv0 32)) (not (bvsge (bvadd |main_#t~mem4| (_ bv4294967293 32)) (_ bv0 32))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:32:34,911 INFO L256 TraceCheckUtils]: 30: Hoare triple {1492#(and (bvsge (bvadd |main_#t~mem4| (_ bv4294967294 32)) (_ bv0 32)) (not (bvsge (bvadd |main_#t~mem4| (_ bv4294967293 32)) (_ bv0 32))) (= (_ bv2 32) main_~i~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {1496#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:32:34,912 INFO L273 TraceCheckUtils]: 31: Hoare triple {1496#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {1500#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:32:34,913 INFO L273 TraceCheckUtils]: 32: Hoare triple {1500#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {1391#false} is VALID [2018-11-23 10:32:34,913 INFO L273 TraceCheckUtils]: 33: Hoare triple {1391#false} assume !false; {1391#false} is VALID [2018-11-23 10:32:34,922 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 4 proven. 12 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-23 10:32:34,922 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:32:40,292 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-11-23 10:32:40,293 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-23 10:32:40,294 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:32:40,294 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:59, output treesize:1 [2018-11-23 10:32:40,305 INFO L273 TraceCheckUtils]: 33: Hoare triple {1391#false} assume !false; {1391#false} is VALID [2018-11-23 10:32:40,306 INFO L273 TraceCheckUtils]: 32: Hoare triple {1510#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume 0bv32 == ~cond; {1391#false} is VALID [2018-11-23 10:32:40,306 INFO L273 TraceCheckUtils]: 31: Hoare triple {1514#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {1510#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-23 10:32:40,307 INFO L256 TraceCheckUtils]: 30: Hoare triple {1518#(bvsge |main_#t~mem4| main_~i~0)} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {1514#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-23 10:32:40,307 INFO L273 TraceCheckUtils]: 29: Hoare triple {1522#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~i~0)} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1518#(bvsge |main_#t~mem4| main_~i~0)} is VALID [2018-11-23 10:32:42,322 INFO L273 TraceCheckUtils]: 28: Hoare triple {1526#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1522#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~i~0)} is UNKNOWN [2018-11-23 10:32:42,323 INFO L273 TraceCheckUtils]: 27: Hoare triple {1526#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} havoc #t~mem4; {1526#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} is VALID [2018-11-23 10:32:42,324 INFO L268 TraceCheckUtils]: 26: Hoare quadruple {1390#true} {1526#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} #60#return; {1526#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} is VALID [2018-11-23 10:32:42,324 INFO L273 TraceCheckUtils]: 25: Hoare triple {1390#true} assume true; {1390#true} is VALID [2018-11-23 10:32:42,324 INFO L273 TraceCheckUtils]: 24: Hoare triple {1390#true} assume !(0bv32 == ~cond); {1390#true} is VALID [2018-11-23 10:32:42,324 INFO L273 TraceCheckUtils]: 23: Hoare triple {1390#true} ~cond := #in~cond; {1390#true} is VALID [2018-11-23 10:32:42,324 INFO L256 TraceCheckUtils]: 22: Hoare triple {1526#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {1390#true} is VALID [2018-11-23 10:32:42,331 INFO L273 TraceCheckUtils]: 21: Hoare triple {1526#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1526#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} is VALID [2018-11-23 10:32:44,339 INFO L273 TraceCheckUtils]: 20: Hoare triple {1551#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1526#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} is UNKNOWN [2018-11-23 10:32:44,339 INFO L273 TraceCheckUtils]: 19: Hoare triple {1551#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} havoc #t~mem4; {1551#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} is VALID [2018-11-23 10:32:44,341 INFO L268 TraceCheckUtils]: 18: Hoare quadruple {1390#true} {1551#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} #60#return; {1551#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} is VALID [2018-11-23 10:32:44,341 INFO L273 TraceCheckUtils]: 17: Hoare triple {1390#true} assume true; {1390#true} is VALID [2018-11-23 10:32:44,341 INFO L273 TraceCheckUtils]: 16: Hoare triple {1390#true} assume !(0bv32 == ~cond); {1390#true} is VALID [2018-11-23 10:32:44,342 INFO L273 TraceCheckUtils]: 15: Hoare triple {1390#true} ~cond := #in~cond; {1390#true} is VALID [2018-11-23 10:32:44,342 INFO L256 TraceCheckUtils]: 14: Hoare triple {1551#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {1390#true} is VALID [2018-11-23 10:32:44,342 INFO L273 TraceCheckUtils]: 13: Hoare triple {1551#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1551#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} is VALID [2018-11-23 10:32:44,345 INFO L273 TraceCheckUtils]: 12: Hoare triple {1576#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv8 32))) (_ bv2 32))} ~i~0 := 0bv32; {1551#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} is VALID [2018-11-23 10:32:44,346 INFO L273 TraceCheckUtils]: 11: Hoare triple {1580#(or (bvsge main_~i~0 (_ bv0 32)) (bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv8 32))) (_ bv2 32)))} assume !~bvsge32(~i~0, 0bv32); {1576#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv8 32))) (_ bv2 32))} is VALID [2018-11-23 10:32:44,347 INFO L273 TraceCheckUtils]: 10: Hoare triple {1584#(or (bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv8 32))) (_ bv2 32)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1580#(or (bvsge main_~i~0 (_ bv0 32)) (bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv8 32))) (_ bv2 32)))} is VALID [2018-11-23 10:32:44,355 INFO L273 TraceCheckUtils]: 9: Hoare triple {1588#(or (not (bvsge main_~i~0 (_ bv0 32))) (bvsge (select (store (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~i~0) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) (bvadd main_~i~0 (_ bv1 32))) (bvadd |main_~#a~0.offset| (_ bv8 32))) (_ bv2 32)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1584#(or (bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv8 32))) (_ bv2 32)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:44,363 INFO L273 TraceCheckUtils]: 8: Hoare triple {1592#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (select (store (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4294967292 32)) (bvadd main_~i~0 (_ bv4294967295 32))) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~i~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) (_ bv2 32)) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1588#(or (not (bvsge main_~i~0 (_ bv0 32))) (bvsge (select (store (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~i~0) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) (bvadd main_~i~0 (_ bv1 32))) (bvadd |main_~#a~0.offset| (_ bv8 32))) (_ bv2 32)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:44,378 INFO L273 TraceCheckUtils]: 7: Hoare triple {1390#true} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1592#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (select (store (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4294967292 32)) (bvadd main_~i~0 (_ bv4294967295 32))) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~i~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) (_ bv2 32)) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:44,378 INFO L273 TraceCheckUtils]: 6: Hoare triple {1390#true} assume ~bvsgt32(~SIZE~0, 1bv32);call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~i~0 := ~bvsub32(~SIZE~0, 2bv32); {1390#true} is VALID [2018-11-23 10:32:44,379 INFO L273 TraceCheckUtils]: 5: Hoare triple {1390#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1;havoc ~i~0; {1390#true} is VALID [2018-11-23 10:32:44,379 INFO L256 TraceCheckUtils]: 4: Hoare triple {1390#true} call #t~ret5 := main(); {1390#true} is VALID [2018-11-23 10:32:44,379 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1390#true} {1390#true} #56#return; {1390#true} is VALID [2018-11-23 10:32:44,379 INFO L273 TraceCheckUtils]: 2: Hoare triple {1390#true} assume true; {1390#true} is VALID [2018-11-23 10:32:44,379 INFO L273 TraceCheckUtils]: 1: Hoare triple {1390#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {1390#true} is VALID [2018-11-23 10:32:44,379 INFO L256 TraceCheckUtils]: 0: Hoare triple {1390#true} call ULTIMATE.init(); {1390#true} is VALID [2018-11-23 10:32:44,382 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-23 10:32:44,386 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:32:44,386 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 13] total 26 [2018-11-23 10:32:44,387 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 34 [2018-11-23 10:32:44,387 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:32:44,392 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 26 states. [2018-11-23 10:32:53,225 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 55 edges. 51 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2018-11-23 10:32:53,225 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-23 10:32:53,226 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-23 10:32:53,226 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=518, Unknown=2, NotChecked=0, Total=650 [2018-11-23 10:32:53,226 INFO L87 Difference]: Start difference. First operand 37 states and 38 transitions. Second operand 26 states. [2018-11-23 10:33:08,100 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 34 [2018-11-23 10:33:08,484 WARN L180 SmtUtils]: Spent 185.00 ms on a formula simplification. DAG size of input: 37 DAG size of output: 37 [2018-11-23 10:33:17,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:33:17,142 INFO L93 Difference]: Finished difference Result 50 states and 51 transitions. [2018-11-23 10:33:17,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-23 10:33:17,142 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 34 [2018-11-23 10:33:17,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:33:17,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-11-23 10:33:17,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 45 transitions. [2018-11-23 10:33:17,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-11-23 10:33:17,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 45 transitions. [2018-11-23 10:33:17,147 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 20 states and 45 transitions. [2018-11-23 10:33:24,128 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 45 edges. 42 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2018-11-23 10:33:24,129 INFO L225 Difference]: With dead ends: 50 [2018-11-23 10:33:24,130 INFO L226 Difference]: Without dead ends: 48 [2018-11-23 10:33:24,131 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 41 SyntacticMatches, 3 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 303 ImplicationChecksByTransitivity, 7.3s TimeCoverageRelationStatistics Valid=239, Invalid=949, Unknown=2, NotChecked=0, Total=1190 [2018-11-23 10:33:24,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-11-23 10:33:24,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 45. [2018-11-23 10:33:24,276 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:33:24,276 INFO L82 GeneralOperation]: Start isEquivalent. First operand 48 states. Second operand 45 states. [2018-11-23 10:33:24,276 INFO L74 IsIncluded]: Start isIncluded. First operand 48 states. Second operand 45 states. [2018-11-23 10:33:24,276 INFO L87 Difference]: Start difference. First operand 48 states. Second operand 45 states. [2018-11-23 10:33:24,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:33:24,280 INFO L93 Difference]: Finished difference Result 48 states and 49 transitions. [2018-11-23 10:33:24,280 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 49 transitions. [2018-11-23 10:33:24,281 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:33:24,281 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:33:24,281 INFO L74 IsIncluded]: Start isIncluded. First operand 45 states. Second operand 48 states. [2018-11-23 10:33:24,281 INFO L87 Difference]: Start difference. First operand 45 states. Second operand 48 states. [2018-11-23 10:33:24,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:33:24,283 INFO L93 Difference]: Finished difference Result 48 states and 49 transitions. [2018-11-23 10:33:24,284 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 49 transitions. [2018-11-23 10:33:24,284 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:33:24,284 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:33:24,284 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:33:24,285 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:33:24,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-11-23 10:33:24,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 46 transitions. [2018-11-23 10:33:24,287 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 46 transitions. Word has length 34 [2018-11-23 10:33:24,287 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:33:24,287 INFO L480 AbstractCegarLoop]: Abstraction has 45 states and 46 transitions. [2018-11-23 10:33:24,287 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-23 10:33:24,287 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 46 transitions. [2018-11-23 10:33:24,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 10:33:24,288 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:33:24,288 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:33:24,289 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:33:24,289 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:33:24,289 INFO L82 PathProgramCache]: Analyzing trace with hash 682163523, now seen corresponding path program 4 times [2018-11-23 10:33:24,289 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:33:24,289 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:33:24,314 INFO L101 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 10:33:24,359 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 10:33:24,359 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:33:24,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:33:24,378 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:33:24,723 INFO L256 TraceCheckUtils]: 0: Hoare triple {1867#true} call ULTIMATE.init(); {1867#true} is VALID [2018-11-23 10:33:24,724 INFO L273 TraceCheckUtils]: 1: Hoare triple {1867#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {1867#true} is VALID [2018-11-23 10:33:24,724 INFO L273 TraceCheckUtils]: 2: Hoare triple {1867#true} assume true; {1867#true} is VALID [2018-11-23 10:33:24,724 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1867#true} {1867#true} #56#return; {1867#true} is VALID [2018-11-23 10:33:24,724 INFO L256 TraceCheckUtils]: 4: Hoare triple {1867#true} call #t~ret5 := main(); {1867#true} is VALID [2018-11-23 10:33:24,724 INFO L273 TraceCheckUtils]: 5: Hoare triple {1867#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1;havoc ~i~0; {1867#true} is VALID [2018-11-23 10:33:24,735 INFO L273 TraceCheckUtils]: 6: Hoare triple {1867#true} assume ~bvsgt32(~SIZE~0, 1bv32);call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~i~0 := ~bvsub32(~SIZE~0, 2bv32); {1890#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} is VALID [2018-11-23 10:33:24,736 INFO L273 TraceCheckUtils]: 7: Hoare triple {1890#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1890#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} is VALID [2018-11-23 10:33:24,756 INFO L273 TraceCheckUtils]: 8: Hoare triple {1890#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1897#(= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0)} is VALID [2018-11-23 10:33:24,757 INFO L273 TraceCheckUtils]: 9: Hoare triple {1897#(= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0)} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1901#(and (bvsge main_~i~0 (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0))} is VALID [2018-11-23 10:33:24,780 INFO L273 TraceCheckUtils]: 10: Hoare triple {1901#(and (bvsge main_~i~0 (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1905#(and (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967292 32)) main_~i~0))} is VALID [2018-11-23 10:33:24,783 INFO L273 TraceCheckUtils]: 11: Hoare triple {1905#(and (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967292 32)) main_~i~0))} assume !~bvsge32(~i~0, 0bv32); {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,784 INFO L273 TraceCheckUtils]: 12: Hoare triple {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} ~i~0 := 0bv32; {1913#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,784 INFO L273 TraceCheckUtils]: 13: Hoare triple {1913#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1913#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,785 INFO L256 TraceCheckUtils]: 14: Hoare triple {1913#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,786 INFO L273 TraceCheckUtils]: 15: Hoare triple {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} ~cond := #in~cond; {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,786 INFO L273 TraceCheckUtils]: 16: Hoare triple {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume !(0bv32 == ~cond); {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,787 INFO L273 TraceCheckUtils]: 17: Hoare triple {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume true; {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,788 INFO L268 TraceCheckUtils]: 18: Hoare quadruple {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} {1913#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} #60#return; {1913#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,788 INFO L273 TraceCheckUtils]: 19: Hoare triple {1913#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} havoc #t~mem4; {1913#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,789 INFO L273 TraceCheckUtils]: 20: Hoare triple {1913#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1938#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,790 INFO L273 TraceCheckUtils]: 21: Hoare triple {1938#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1938#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,792 INFO L256 TraceCheckUtils]: 22: Hoare triple {1938#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,792 INFO L273 TraceCheckUtils]: 23: Hoare triple {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} ~cond := #in~cond; {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,793 INFO L273 TraceCheckUtils]: 24: Hoare triple {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume !(0bv32 == ~cond); {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,794 INFO L273 TraceCheckUtils]: 25: Hoare triple {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume true; {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,795 INFO L268 TraceCheckUtils]: 26: Hoare quadruple {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} {1938#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #60#return; {1938#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,796 INFO L273 TraceCheckUtils]: 27: Hoare triple {1938#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem4; {1938#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,798 INFO L273 TraceCheckUtils]: 28: Hoare triple {1938#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1963#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:33:24,799 INFO L273 TraceCheckUtils]: 29: Hoare triple {1963#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1963#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:33:24,802 INFO L256 TraceCheckUtils]: 30: Hoare triple {1963#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,806 INFO L273 TraceCheckUtils]: 31: Hoare triple {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} ~cond := #in~cond; {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,825 INFO L273 TraceCheckUtils]: 32: Hoare triple {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume !(0bv32 == ~cond); {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,831 INFO L273 TraceCheckUtils]: 33: Hoare triple {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume true; {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,832 INFO L268 TraceCheckUtils]: 34: Hoare quadruple {1909#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} {1963#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} #60#return; {1963#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:33:24,833 INFO L273 TraceCheckUtils]: 35: Hoare triple {1963#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} havoc #t~mem4; {1963#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:33:24,834 INFO L273 TraceCheckUtils]: 36: Hoare triple {1963#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1988#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:24,837 INFO L273 TraceCheckUtils]: 37: Hoare triple {1988#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1868#false} is VALID [2018-11-23 10:33:24,838 INFO L256 TraceCheckUtils]: 38: Hoare triple {1868#false} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {1868#false} is VALID [2018-11-23 10:33:24,838 INFO L273 TraceCheckUtils]: 39: Hoare triple {1868#false} ~cond := #in~cond; {1868#false} is VALID [2018-11-23 10:33:24,838 INFO L273 TraceCheckUtils]: 40: Hoare triple {1868#false} assume 0bv32 == ~cond; {1868#false} is VALID [2018-11-23 10:33:24,838 INFO L273 TraceCheckUtils]: 41: Hoare triple {1868#false} assume !false; {1868#false} is VALID [2018-11-23 10:33:24,845 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 9 proven. 19 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 10:33:24,845 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:33:25,371 INFO L273 TraceCheckUtils]: 41: Hoare triple {1868#false} assume !false; {1868#false} is VALID [2018-11-23 10:33:25,371 INFO L273 TraceCheckUtils]: 40: Hoare triple {1868#false} assume 0bv32 == ~cond; {1868#false} is VALID [2018-11-23 10:33:25,371 INFO L273 TraceCheckUtils]: 39: Hoare triple {1868#false} ~cond := #in~cond; {1868#false} is VALID [2018-11-23 10:33:25,371 INFO L256 TraceCheckUtils]: 38: Hoare triple {1868#false} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {1868#false} is VALID [2018-11-23 10:33:25,372 INFO L273 TraceCheckUtils]: 37: Hoare triple {2016#(not (bvslt main_~i~0 ~SIZE~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1868#false} is VALID [2018-11-23 10:33:25,373 INFO L273 TraceCheckUtils]: 36: Hoare triple {2020#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2016#(not (bvslt main_~i~0 ~SIZE~0))} is VALID [2018-11-23 10:33:25,373 INFO L273 TraceCheckUtils]: 35: Hoare triple {2020#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} havoc #t~mem4; {2020#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-23 10:33:25,374 INFO L268 TraceCheckUtils]: 34: Hoare quadruple {1867#true} {2020#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} #60#return; {2020#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-23 10:33:25,374 INFO L273 TraceCheckUtils]: 33: Hoare triple {1867#true} assume true; {1867#true} is VALID [2018-11-23 10:33:25,374 INFO L273 TraceCheckUtils]: 32: Hoare triple {1867#true} assume !(0bv32 == ~cond); {1867#true} is VALID [2018-11-23 10:33:25,375 INFO L273 TraceCheckUtils]: 31: Hoare triple {1867#true} ~cond := #in~cond; {1867#true} is VALID [2018-11-23 10:33:25,375 INFO L256 TraceCheckUtils]: 30: Hoare triple {2020#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {1867#true} is VALID [2018-11-23 10:33:25,375 INFO L273 TraceCheckUtils]: 29: Hoare triple {2020#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2020#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-23 10:33:25,398 INFO L273 TraceCheckUtils]: 28: Hoare triple {2045#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2020#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-23 10:33:25,398 INFO L273 TraceCheckUtils]: 27: Hoare triple {2045#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} havoc #t~mem4; {2045#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-23 10:33:25,399 INFO L268 TraceCheckUtils]: 26: Hoare quadruple {1867#true} {2045#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} #60#return; {2045#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-23 10:33:25,399 INFO L273 TraceCheckUtils]: 25: Hoare triple {1867#true} assume true; {1867#true} is VALID [2018-11-23 10:33:25,399 INFO L273 TraceCheckUtils]: 24: Hoare triple {1867#true} assume !(0bv32 == ~cond); {1867#true} is VALID [2018-11-23 10:33:25,399 INFO L273 TraceCheckUtils]: 23: Hoare triple {1867#true} ~cond := #in~cond; {1867#true} is VALID [2018-11-23 10:33:25,400 INFO L256 TraceCheckUtils]: 22: Hoare triple {2045#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {1867#true} is VALID [2018-11-23 10:33:25,400 INFO L273 TraceCheckUtils]: 21: Hoare triple {2045#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2045#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-23 10:33:25,430 INFO L273 TraceCheckUtils]: 20: Hoare triple {2070#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2045#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-23 10:33:25,431 INFO L273 TraceCheckUtils]: 19: Hoare triple {2070#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} havoc #t~mem4; {2070#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} is VALID [2018-11-23 10:33:25,431 INFO L268 TraceCheckUtils]: 18: Hoare quadruple {1867#true} {2070#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} #60#return; {2070#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} is VALID [2018-11-23 10:33:25,432 INFO L273 TraceCheckUtils]: 17: Hoare triple {1867#true} assume true; {1867#true} is VALID [2018-11-23 10:33:25,432 INFO L273 TraceCheckUtils]: 16: Hoare triple {1867#true} assume !(0bv32 == ~cond); {1867#true} is VALID [2018-11-23 10:33:25,432 INFO L273 TraceCheckUtils]: 15: Hoare triple {1867#true} ~cond := #in~cond; {1867#true} is VALID [2018-11-23 10:33:25,432 INFO L256 TraceCheckUtils]: 14: Hoare triple {2070#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {1867#true} is VALID [2018-11-23 10:33:25,432 INFO L273 TraceCheckUtils]: 13: Hoare triple {2070#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2070#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} is VALID [2018-11-23 10:33:25,433 INFO L273 TraceCheckUtils]: 12: Hoare triple {2095#(not (bvslt (_ bv3 32) ~SIZE~0))} ~i~0 := 0bv32; {2070#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} is VALID [2018-11-23 10:33:25,434 INFO L273 TraceCheckUtils]: 11: Hoare triple {2099#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} assume !~bvsge32(~i~0, 0bv32); {2095#(not (bvslt (_ bv3 32) ~SIZE~0))} is VALID [2018-11-23 10:33:25,436 INFO L273 TraceCheckUtils]: 10: Hoare triple {2103#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2099#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:33:25,437 INFO L273 TraceCheckUtils]: 9: Hoare triple {2107#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge main_~i~0 (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2103#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:25,440 INFO L273 TraceCheckUtils]: 8: Hoare triple {2111#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2107#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge main_~i~0 (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:25,440 INFO L273 TraceCheckUtils]: 7: Hoare triple {2111#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2111#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:25,445 INFO L273 TraceCheckUtils]: 6: Hoare triple {1867#true} assume ~bvsgt32(~SIZE~0, 1bv32);call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~i~0 := ~bvsub32(~SIZE~0, 2bv32); {2111#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:25,445 INFO L273 TraceCheckUtils]: 5: Hoare triple {1867#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1;havoc ~i~0; {1867#true} is VALID [2018-11-23 10:33:25,445 INFO L256 TraceCheckUtils]: 4: Hoare triple {1867#true} call #t~ret5 := main(); {1867#true} is VALID [2018-11-23 10:33:25,445 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1867#true} {1867#true} #56#return; {1867#true} is VALID [2018-11-23 10:33:25,446 INFO L273 TraceCheckUtils]: 2: Hoare triple {1867#true} assume true; {1867#true} is VALID [2018-11-23 10:33:25,446 INFO L273 TraceCheckUtils]: 1: Hoare triple {1867#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {1867#true} is VALID [2018-11-23 10:33:25,446 INFO L256 TraceCheckUtils]: 0: Hoare triple {1867#true} call ULTIMATE.init(); {1867#true} is VALID [2018-11-23 10:33:25,448 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 9 proven. 19 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 10:33:25,450 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:33:25,450 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 20 [2018-11-23 10:33:25,450 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 42 [2018-11-23 10:33:25,451 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:33:25,451 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 20 states. [2018-11-23 10:33:25,699 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:33:25,699 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-23 10:33:25,700 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-23 10:33:25,700 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=114, Invalid=266, Unknown=0, NotChecked=0, Total=380 [2018-11-23 10:33:25,700 INFO L87 Difference]: Start difference. First operand 45 states and 46 transitions. Second operand 20 states. [2018-11-23 10:33:28,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:33:28,850 INFO L93 Difference]: Finished difference Result 90 states and 93 transitions. [2018-11-23 10:33:28,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-23 10:33:28,850 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 42 [2018-11-23 10:33:28,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:33:28,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-11-23 10:33:28,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 78 transitions. [2018-11-23 10:33:28,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-11-23 10:33:28,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 78 transitions. [2018-11-23 10:33:28,858 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 18 states and 78 transitions. [2018-11-23 10:33:29,070 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 78 edges. 78 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:33:29,073 INFO L225 Difference]: With dead ends: 90 [2018-11-23 10:33:29,073 INFO L226 Difference]: Without dead ends: 54 [2018-11-23 10:33:29,074 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 116 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=153, Invalid=353, Unknown=0, NotChecked=0, Total=506 [2018-11-23 10:33:29,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-11-23 10:33:29,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 47. [2018-11-23 10:33:29,190 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:33:29,190 INFO L82 GeneralOperation]: Start isEquivalent. First operand 54 states. Second operand 47 states. [2018-11-23 10:33:29,190 INFO L74 IsIncluded]: Start isIncluded. First operand 54 states. Second operand 47 states. [2018-11-23 10:33:29,190 INFO L87 Difference]: Start difference. First operand 54 states. Second operand 47 states. [2018-11-23 10:33:29,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:33:29,193 INFO L93 Difference]: Finished difference Result 54 states and 56 transitions. [2018-11-23 10:33:29,194 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 56 transitions. [2018-11-23 10:33:29,194 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:33:29,194 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:33:29,194 INFO L74 IsIncluded]: Start isIncluded. First operand 47 states. Second operand 54 states. [2018-11-23 10:33:29,194 INFO L87 Difference]: Start difference. First operand 47 states. Second operand 54 states. [2018-11-23 10:33:29,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:33:29,197 INFO L93 Difference]: Finished difference Result 54 states and 56 transitions. [2018-11-23 10:33:29,197 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 56 transitions. [2018-11-23 10:33:29,197 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:33:29,197 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:33:29,198 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:33:29,198 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:33:29,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-11-23 10:33:29,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 48 transitions. [2018-11-23 10:33:29,200 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 48 transitions. Word has length 42 [2018-11-23 10:33:29,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:33:29,200 INFO L480 AbstractCegarLoop]: Abstraction has 47 states and 48 transitions. [2018-11-23 10:33:29,200 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-23 10:33:29,200 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 48 transitions. [2018-11-23 10:33:29,201 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-11-23 10:33:29,201 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:33:29,201 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:33:29,201 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:33:29,202 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:33:29,202 INFO L82 PathProgramCache]: Analyzing trace with hash -1212356927, now seen corresponding path program 5 times [2018-11-23 10:33:29,202 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:33:29,202 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:33:29,224 INFO L101 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2018-11-23 10:33:29,515 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2018-11-23 10:33:29,515 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:33:29,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:33:29,564 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:33:29,595 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 22 [2018-11-23 10:33:29,601 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 25 [2018-11-23 10:33:29,613 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:29,615 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:29,616 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 53 [2018-11-23 10:33:29,620 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-23 10:33:29,640 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:33:29,655 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:33:29,678 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:33:29,678 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:32, output treesize:32 [2018-11-23 10:33:29,843 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 47 [2018-11-23 10:33:29,917 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:29,922 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:29,925 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:29,929 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:29,931 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:29,934 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:29,937 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 129 [2018-11-23 10:33:30,003 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 89 treesize of output 114 [2018-11-23 10:33:30,010 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-23 10:33:30,055 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:33:30,078 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:33:30,120 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:33:30,121 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:62, output treesize:48 [2018-11-23 10:33:30,459 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 59 [2018-11-23 10:33:30,544 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:30,549 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:30,554 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:30,560 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:30,566 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:30,571 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:30,576 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:30,583 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:30,587 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:30,591 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:30,595 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:30,599 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:30,601 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 229 [2018-11-23 10:33:30,666 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 12 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 148 treesize of output 219 [2018-11-23 10:33:30,691 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-23 10:33:30,798 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:33:30,840 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:33:30,904 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:33:30,904 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:79, output treesize:65 [2018-11-23 10:33:47,284 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 62 treesize of output 52 [2018-11-23 10:33:47,330 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:47,332 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:47,333 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:47,334 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:47,373 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:47,384 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:33:47,386 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:47,387 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:47,390 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:47,392 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:47,394 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:47,396 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:47,409 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:47,410 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:33:47,413 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 12 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 139 [2018-11-23 10:33:47,417 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:33:47,464 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:33:47,484 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:33:47,485 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:81, output treesize:17 [2018-11-23 10:33:47,513 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:33:47,514 WARN L384 uantifierElimination]: Input elimination task: ∃ [|#memory_int|, |main_~#a~0.base|, v_prenex_7]. (let ((.cse0 (bvadd v_prenex_7 (_ bv3 32))) (.cse1 (select |#memory_int| |main_~#a~0.base|)) (.cse2 (bvmul (_ bv4 32) v_prenex_7))) (and (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= .cse0 (select .cse1 (bvadd .cse2 (_ bv12 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select .cse1 (bvadd .cse2 (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (bvsge .cse0 (_ bv0 32)) (= |main_#t~mem4| (select .cse1 (bvmul (_ bv4 32) main_~i~0))) (= (bvadd (select .cse1 (bvadd .cse2 (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (= v_prenex_7 (bvadd (select .cse1 (bvadd .cse2 (_ bv8 32))) (_ bv4294967294 32))))) [2018-11-23 10:33:47,514 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ []. (and (not (bvsge (bvadd |main_#t~mem4| (_ bv4294967292 32)) (_ bv0 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd |main_#t~mem4| (_ bv4294967293 32)) (_ bv0 32))) [2018-11-23 10:33:47,766 INFO L256 TraceCheckUtils]: 0: Hoare triple {2444#true} call ULTIMATE.init(); {2444#true} is VALID [2018-11-23 10:33:47,766 INFO L273 TraceCheckUtils]: 1: Hoare triple {2444#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {2444#true} is VALID [2018-11-23 10:33:47,767 INFO L273 TraceCheckUtils]: 2: Hoare triple {2444#true} assume true; {2444#true} is VALID [2018-11-23 10:33:47,767 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2444#true} {2444#true} #56#return; {2444#true} is VALID [2018-11-23 10:33:47,767 INFO L256 TraceCheckUtils]: 4: Hoare triple {2444#true} call #t~ret5 := main(); {2444#true} is VALID [2018-11-23 10:33:47,767 INFO L273 TraceCheckUtils]: 5: Hoare triple {2444#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1;havoc ~i~0; {2444#true} is VALID [2018-11-23 10:33:47,769 INFO L273 TraceCheckUtils]: 6: Hoare triple {2444#true} assume ~bvsgt32(~SIZE~0, 1bv32);call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~i~0 := ~bvsub32(~SIZE~0, 2bv32); {2467#(= |main_~#a~0.offset| (_ bv0 32))} is VALID [2018-11-23 10:33:47,773 INFO L273 TraceCheckUtils]: 7: Hoare triple {2467#(= |main_~#a~0.offset| (_ bv0 32))} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2471#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)) (= main_~i~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:33:49,778 INFO L273 TraceCheckUtils]: 8: Hoare triple {2471#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)) (= main_~i~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= |main_~#a~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2475#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= |main_~#a~0.offset| (_ bv0 32)))} is UNKNOWN [2018-11-23 10:33:49,801 INFO L273 TraceCheckUtils]: 9: Hoare triple {2475#(and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= |main_~#a~0.offset| (_ bv0 32)))} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2479#(and (= (bvadd main_~i~0 (_ bv2 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= main_~i~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:33:51,806 INFO L273 TraceCheckUtils]: 10: Hoare triple {2479#(and (= (bvadd main_~i~0 (_ bv2 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= main_~i~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= |main_~#a~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2483#(and (= (bvadd main_~i~0 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= |main_~#a~0.offset| (_ bv0 32)))} is UNKNOWN [2018-11-23 10:33:52,023 INFO L273 TraceCheckUtils]: 11: Hoare triple {2483#(and (= (bvadd main_~i~0 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= |main_~#a~0.offset| (_ bv0 32)))} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2487#(and (= (bvadd main_~i~0 (_ bv2 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:33:54,028 INFO L273 TraceCheckUtils]: 12: Hoare triple {2487#(and (= (bvadd main_~i~0 (_ bv2 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= |main_~#a~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2491#(and (= (bvadd main_~i~0 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (bvsge (bvadd main_~i~0 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) (_ bv4294967292 32)) main_~i~0))} is UNKNOWN [2018-11-23 10:33:54,034 INFO L273 TraceCheckUtils]: 13: Hoare triple {2491#(and (= (bvadd main_~i~0 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (bvsge (bvadd main_~i~0 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) (_ bv4294967292 32)) main_~i~0))} assume !~bvsge32(~i~0, 0bv32); {2495#(and (exists ((main_~i~0 (_ BitVec 32))) (and (= (bvadd main_~i~0 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (bvsge (bvadd main_~i~0 (_ bv3 32)) (_ bv0 32)) (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) (_ bv4294967292 32)) main_~i~0))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:33:54,040 INFO L273 TraceCheckUtils]: 14: Hoare triple {2495#(and (exists ((main_~i~0 (_ BitVec 32))) (and (= (bvadd main_~i~0 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (bvsge (bvadd main_~i~0 (_ bv3 32)) (_ bv0 32)) (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967295 32)) main_~i~0) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (_ bv4294967294 32)) main_~i~0) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) (_ bv4294967292 32)) main_~i~0))) (= |main_~#a~0.offset| (_ bv0 32)))} ~i~0 := 0bv32; {2499#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:33:54,041 INFO L273 TraceCheckUtils]: 15: Hoare triple {2499#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2499#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:33:54,048 INFO L256 TraceCheckUtils]: 16: Hoare triple {2499#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} is VALID [2018-11-23 10:33:54,048 INFO L273 TraceCheckUtils]: 17: Hoare triple {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} ~cond := #in~cond; {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} is VALID [2018-11-23 10:33:54,049 INFO L273 TraceCheckUtils]: 18: Hoare triple {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} assume !(0bv32 == ~cond); {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} is VALID [2018-11-23 10:33:54,050 INFO L273 TraceCheckUtils]: 19: Hoare triple {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} assume true; {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} is VALID [2018-11-23 10:33:54,051 INFO L268 TraceCheckUtils]: 20: Hoare quadruple {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} {2499#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} #60#return; {2499#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:33:54,052 INFO L273 TraceCheckUtils]: 21: Hoare triple {2499#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} havoc #t~mem4; {2499#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} is VALID [2018-11-23 10:33:54,053 INFO L273 TraceCheckUtils]: 22: Hoare triple {2499#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2525#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:54,055 INFO L273 TraceCheckUtils]: 23: Hoare triple {2525#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2525#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:54,062 INFO L256 TraceCheckUtils]: 24: Hoare triple {2525#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} is VALID [2018-11-23 10:33:54,063 INFO L273 TraceCheckUtils]: 25: Hoare triple {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} ~cond := #in~cond; {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} is VALID [2018-11-23 10:33:54,064 INFO L273 TraceCheckUtils]: 26: Hoare triple {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} assume !(0bv32 == ~cond); {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} is VALID [2018-11-23 10:33:54,064 INFO L273 TraceCheckUtils]: 27: Hoare triple {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} assume true; {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} is VALID [2018-11-23 10:33:54,065 INFO L268 TraceCheckUtils]: 28: Hoare quadruple {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} {2525#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #60#return; {2525#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:54,067 INFO L273 TraceCheckUtils]: 29: Hoare triple {2525#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem4; {2525#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:54,069 INFO L273 TraceCheckUtils]: 30: Hoare triple {2525#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2550#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:33:54,075 INFO L273 TraceCheckUtils]: 31: Hoare triple {2550#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2550#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:33:54,082 INFO L256 TraceCheckUtils]: 32: Hoare triple {2550#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} is VALID [2018-11-23 10:33:54,089 INFO L273 TraceCheckUtils]: 33: Hoare triple {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} ~cond := #in~cond; {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} is VALID [2018-11-23 10:33:54,090 INFO L273 TraceCheckUtils]: 34: Hoare triple {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} assume !(0bv32 == ~cond); {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} is VALID [2018-11-23 10:33:54,090 INFO L273 TraceCheckUtils]: 35: Hoare triple {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} assume true; {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} is VALID [2018-11-23 10:33:54,091 INFO L268 TraceCheckUtils]: 36: Hoare quadruple {2506#(exists ((v_prenex_7 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7)))} {2550#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} #60#return; {2550#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:33:54,096 INFO L273 TraceCheckUtils]: 37: Hoare triple {2550#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} havoc #t~mem4; {2550#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:33:54,100 INFO L273 TraceCheckUtils]: 38: Hoare triple {2550#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= |main_~#a~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2575#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:33:54,107 INFO L273 TraceCheckUtils]: 39: Hoare triple {2575#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv16 32))) (_ bv4294967292 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_7 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv8 32))) (_ bv4294967294 32)) v_prenex_7) (bvsge (bvadd v_prenex_7 (_ bv3 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv4 32))) (_ bv4294967295 32)) v_prenex_7) (= (bvadd v_prenex_7 (_ bv3 32)) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_7) (_ bv12 32)))))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2579#(and (not (bvsge (bvadd |main_#t~mem4| (_ bv4294967292 32)) (_ bv0 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd |main_#t~mem4| (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-23 10:33:54,111 INFO L256 TraceCheckUtils]: 40: Hoare triple {2579#(and (not (bvsge (bvadd |main_#t~mem4| (_ bv4294967292 32)) (_ bv0 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd |main_#t~mem4| (_ bv4294967293 32)) (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {2583#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:33:54,111 INFO L273 TraceCheckUtils]: 41: Hoare triple {2583#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {2587#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:33:54,112 INFO L273 TraceCheckUtils]: 42: Hoare triple {2587#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {2445#false} is VALID [2018-11-23 10:33:54,112 INFO L273 TraceCheckUtils]: 43: Hoare triple {2445#false} assume !false; {2445#false} is VALID [2018-11-23 10:33:54,134 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 7 proven. 26 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 10:33:54,135 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:34:04,077 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-11-23 10:34:04,078 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-23 10:34:04,078 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:34:04,079 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:62, output treesize:1 [2018-11-23 10:34:04,092 INFO L273 TraceCheckUtils]: 43: Hoare triple {2445#false} assume !false; {2445#false} is VALID [2018-11-23 10:34:04,093 INFO L273 TraceCheckUtils]: 42: Hoare triple {2597#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume 0bv32 == ~cond; {2445#false} is VALID [2018-11-23 10:34:04,094 INFO L273 TraceCheckUtils]: 41: Hoare triple {2601#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {2597#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-23 10:34:04,095 INFO L256 TraceCheckUtils]: 40: Hoare triple {2605#(bvsge |main_#t~mem4| main_~i~0)} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {2601#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-23 10:34:04,096 INFO L273 TraceCheckUtils]: 39: Hoare triple {2609#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~i~0)} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2605#(bvsge |main_#t~mem4| main_~i~0)} is VALID [2018-11-23 10:34:06,114 INFO L273 TraceCheckUtils]: 38: Hoare triple {2613#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2609#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~i~0)} is UNKNOWN [2018-11-23 10:34:06,115 INFO L273 TraceCheckUtils]: 37: Hoare triple {2613#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} havoc #t~mem4; {2613#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} is VALID [2018-11-23 10:34:06,116 INFO L268 TraceCheckUtils]: 36: Hoare quadruple {2444#true} {2613#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} #60#return; {2613#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} is VALID [2018-11-23 10:34:06,116 INFO L273 TraceCheckUtils]: 35: Hoare triple {2444#true} assume true; {2444#true} is VALID [2018-11-23 10:34:06,116 INFO L273 TraceCheckUtils]: 34: Hoare triple {2444#true} assume !(0bv32 == ~cond); {2444#true} is VALID [2018-11-23 10:34:06,116 INFO L273 TraceCheckUtils]: 33: Hoare triple {2444#true} ~cond := #in~cond; {2444#true} is VALID [2018-11-23 10:34:06,116 INFO L256 TraceCheckUtils]: 32: Hoare triple {2613#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {2444#true} is VALID [2018-11-23 10:34:06,117 INFO L273 TraceCheckUtils]: 31: Hoare triple {2613#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2613#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} is VALID [2018-11-23 10:34:08,125 INFO L273 TraceCheckUtils]: 30: Hoare triple {2638#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2613#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (bvadd main_~i~0 (_ bv1 32)))} is UNKNOWN [2018-11-23 10:34:08,126 INFO L273 TraceCheckUtils]: 29: Hoare triple {2638#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} havoc #t~mem4; {2638#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} is VALID [2018-11-23 10:34:08,126 INFO L268 TraceCheckUtils]: 28: Hoare quadruple {2444#true} {2638#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} #60#return; {2638#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} is VALID [2018-11-23 10:34:08,127 INFO L273 TraceCheckUtils]: 27: Hoare triple {2444#true} assume true; {2444#true} is VALID [2018-11-23 10:34:08,127 INFO L273 TraceCheckUtils]: 26: Hoare triple {2444#true} assume !(0bv32 == ~cond); {2444#true} is VALID [2018-11-23 10:34:08,127 INFO L273 TraceCheckUtils]: 25: Hoare triple {2444#true} ~cond := #in~cond; {2444#true} is VALID [2018-11-23 10:34:08,127 INFO L256 TraceCheckUtils]: 24: Hoare triple {2638#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {2444#true} is VALID [2018-11-23 10:34:08,127 INFO L273 TraceCheckUtils]: 23: Hoare triple {2638#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2638#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} is VALID [2018-11-23 10:34:10,138 INFO L273 TraceCheckUtils]: 22: Hoare triple {2663#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (bvadd main_~i~0 (_ bv3 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2638#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) (bvadd main_~i~0 (_ bv2 32)))} is UNKNOWN [2018-11-23 10:34:10,139 INFO L273 TraceCheckUtils]: 21: Hoare triple {2663#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (bvadd main_~i~0 (_ bv3 32)))} havoc #t~mem4; {2663#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (bvadd main_~i~0 (_ bv3 32)))} is VALID [2018-11-23 10:34:10,139 INFO L268 TraceCheckUtils]: 20: Hoare quadruple {2444#true} {2663#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (bvadd main_~i~0 (_ bv3 32)))} #60#return; {2663#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (bvadd main_~i~0 (_ bv3 32)))} is VALID [2018-11-23 10:34:10,140 INFO L273 TraceCheckUtils]: 19: Hoare triple {2444#true} assume true; {2444#true} is VALID [2018-11-23 10:34:10,140 INFO L273 TraceCheckUtils]: 18: Hoare triple {2444#true} assume !(0bv32 == ~cond); {2444#true} is VALID [2018-11-23 10:34:10,140 INFO L273 TraceCheckUtils]: 17: Hoare triple {2444#true} ~cond := #in~cond; {2444#true} is VALID [2018-11-23 10:34:10,140 INFO L256 TraceCheckUtils]: 16: Hoare triple {2663#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (bvadd main_~i~0 (_ bv3 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~i~0) then 1bv32 else 0bv32)); {2444#true} is VALID [2018-11-23 10:34:10,143 INFO L273 TraceCheckUtils]: 15: Hoare triple {2663#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (bvadd main_~i~0 (_ bv3 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2663#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (bvadd main_~i~0 (_ bv3 32)))} is VALID [2018-11-23 10:34:10,144 INFO L273 TraceCheckUtils]: 14: Hoare triple {2688#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv12 32))) (_ bv3 32))} ~i~0 := 0bv32; {2663#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (bvadd main_~i~0 (_ bv3 32)))} is VALID [2018-11-23 10:34:10,145 INFO L273 TraceCheckUtils]: 13: Hoare triple {2692#(or (bvsge main_~i~0 (_ bv0 32)) (bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv12 32))) (_ bv3 32)))} assume !~bvsge32(~i~0, 0bv32); {2688#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv12 32))) (_ bv3 32))} is VALID [2018-11-23 10:34:10,147 INFO L273 TraceCheckUtils]: 12: Hoare triple {2696#(or (bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv12 32))) (_ bv3 32)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2692#(or (bvsge main_~i~0 (_ bv0 32)) (bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv12 32))) (_ bv3 32)))} is VALID [2018-11-23 10:34:10,159 INFO L273 TraceCheckUtils]: 11: Hoare triple {2700#(or (not (bvsge main_~i~0 (_ bv0 32))) (bvsge (select (store (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~i~0) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) (bvadd main_~i~0 (_ bv1 32))) (bvadd |main_~#a~0.offset| (_ bv12 32))) (_ bv3 32)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2696#(or (bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv12 32))) (_ bv3 32)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:34:10,165 INFO L273 TraceCheckUtils]: 10: Hoare triple {2704#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)) (bvsge (select (store (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4294967292 32)) (bvadd main_~i~0 (_ bv4294967295 32))) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~i~0) (bvadd |main_~#a~0.offset| (_ bv12 32))) (_ bv3 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2700#(or (not (bvsge main_~i~0 (_ bv0 32))) (bvsge (select (store (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~i~0) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) (bvadd main_~i~0 (_ bv1 32))) (bvadd |main_~#a~0.offset| (_ bv12 32))) (_ bv3 32)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:34:10,174 INFO L273 TraceCheckUtils]: 9: Hoare triple {2704#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)) (bvsge (select (store (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4294967292 32)) (bvadd main_~i~0 (_ bv4294967295 32))) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~i~0) (bvadd |main_~#a~0.offset| (_ bv12 32))) (_ bv3 32)))} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2704#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)) (bvsge (select (store (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4294967292 32)) (bvadd main_~i~0 (_ bv4294967295 32))) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~i~0) (bvadd |main_~#a~0.offset| (_ bv12 32))) (_ bv3 32)))} is VALID [2018-11-23 10:34:10,182 INFO L273 TraceCheckUtils]: 8: Hoare triple {2711#(or (bvsge (select (store (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4294967288 32)) (bvadd main_~i~0 (_ bv4294967294 32))) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4294967292 32)) (bvadd main_~i~0 (_ bv4294967295 32))) (bvadd |main_~#a~0.offset| (_ bv12 32))) (_ bv3 32)) (bvsge (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32))))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2704#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)) (bvsge (select (store (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4294967292 32)) (bvadd main_~i~0 (_ bv4294967295 32))) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~i~0) (bvadd |main_~#a~0.offset| (_ bv12 32))) (_ bv3 32)))} is VALID [2018-11-23 10:34:10,199 INFO L273 TraceCheckUtils]: 7: Hoare triple {2444#true} assume !!~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~i~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(1bv32, ~i~0), ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2711#(or (bvsge (select (store (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4294967288 32)) (bvadd main_~i~0 (_ bv4294967294 32))) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4294967292 32)) (bvadd main_~i~0 (_ bv4294967295 32))) (bvadd |main_~#a~0.offset| (_ bv12 32))) (_ bv3 32)) (bvsge (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32))))} is VALID [2018-11-23 10:34:10,199 INFO L273 TraceCheckUtils]: 6: Hoare triple {2444#true} assume ~bvsgt32(~SIZE~0, 1bv32);call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~i~0 := ~bvsub32(~SIZE~0, 2bv32); {2444#true} is VALID [2018-11-23 10:34:10,199 INFO L273 TraceCheckUtils]: 5: Hoare triple {2444#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1;havoc ~i~0; {2444#true} is VALID [2018-11-23 10:34:10,200 INFO L256 TraceCheckUtils]: 4: Hoare triple {2444#true} call #t~ret5 := main(); {2444#true} is VALID [2018-11-23 10:34:10,200 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2444#true} {2444#true} #56#return; {2444#true} is VALID [2018-11-23 10:34:10,200 INFO L273 TraceCheckUtils]: 2: Hoare triple {2444#true} assume true; {2444#true} is VALID [2018-11-23 10:34:10,200 INFO L273 TraceCheckUtils]: 1: Hoare triple {2444#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {2444#true} is VALID [2018-11-23 10:34:10,200 INFO L256 TraceCheckUtils]: 0: Hoare triple {2444#true} call ULTIMATE.init(); {2444#true} is VALID [2018-11-23 10:34:10,206 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 9 proven. 24 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 10:34:10,209 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:34:10,209 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 15] total 31 [2018-11-23 10:34:10,210 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 44 [2018-11-23 10:34:10,210 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:34:10,210 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 31 states. [2018-11-23 10:34:25,035 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 69 edges. 62 inductive. 0 not inductive. 7 times theorem prover too weak to decide inductivity. [2018-11-23 10:34:25,035 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-11-23 10:34:25,035 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-11-23 10:34:25,036 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=185, Invalid=742, Unknown=3, NotChecked=0, Total=930 [2018-11-23 10:34:25,036 INFO L87 Difference]: Start difference. First operand 47 states and 48 transitions. Second operand 31 states. [2018-11-23 10:34:50,585 WARN L180 SmtUtils]: Spent 207.00 ms on a formula simplification. DAG size of input: 45 DAG size of output: 38 [2018-11-23 10:34:51,187 WARN L180 SmtUtils]: Spent 247.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 41 [2018-11-23 10:35:10,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:35:10,699 INFO L93 Difference]: Finished difference Result 60 states and 61 transitions. [2018-11-23 10:35:10,699 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-23 10:35:10,699 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 44 [2018-11-23 10:35:10,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:35:10,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-11-23 10:35:10,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 52 transitions. [2018-11-23 10:35:10,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-11-23 10:35:10,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 52 transitions. [2018-11-23 10:35:10,704 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 24 states and 52 transitions.