java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerCInline_WitnessPrinter.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf -i ../../../trunk/examples/svcomp/array-examples/standard_copyInitSum3_true-unreach-call_ground.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-61f4311 [2018-11-23 10:05:57,592 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 10:05:57,594 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 10:05:57,606 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 10:05:57,607 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 10:05:57,608 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 10:05:57,609 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 10:05:57,611 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 10:05:57,612 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 10:05:57,613 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 10:05:57,614 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 10:05:57,614 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 10:05:57,615 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 10:05:57,618 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 10:05:57,622 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 10:05:57,623 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 10:05:57,624 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 10:05:57,626 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 10:05:57,628 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 10:05:57,629 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 10:05:57,631 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 10:05:57,632 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 10:05:57,634 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 10:05:57,635 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 10:05:57,635 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 10:05:57,636 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 10:05:57,637 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 10:05:57,638 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 10:05:57,639 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 10:05:57,640 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 10:05:57,640 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 10:05:57,641 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 10:05:57,641 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 10:05:57,641 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 10:05:57,642 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 10:05:57,643 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 10:05:57,643 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-23 10:05:57,659 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 10:05:57,660 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 10:05:57,661 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 10:05:57,661 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 10:05:57,661 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 10:05:57,662 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 10:05:57,662 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 10:05:57,662 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 10:05:57,662 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 10:05:57,662 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 10:05:57,663 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 10:05:57,663 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 10:05:57,663 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 10:05:57,663 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 10:05:57,663 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-23 10:05:57,664 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-23 10:05:57,664 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 10:05:57,664 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 10:05:57,664 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 10:05:57,664 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 10:05:57,665 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 10:05:57,665 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 10:05:57,665 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 10:05:57,665 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 10:05:57,665 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:05:57,666 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 10:05:57,666 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 10:05:57,666 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 10:05:57,666 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-23 10:05:57,666 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 10:05:57,666 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-23 10:05:57,667 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-23 10:05:57,667 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 10:05:57,723 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 10:05:57,736 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 10:05:57,740 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 10:05:57,742 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 10:05:57,742 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 10:05:57,743 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/standard_copyInitSum3_true-unreach-call_ground.i [2018-11-23 10:05:57,813 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7c7a92368/7554025e3a7748d1b51ba437c49b88b3/FLAGb116f9d09 [2018-11-23 10:05:58,218 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 10:05:58,219 INFO L161 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-examples/standard_copyInitSum3_true-unreach-call_ground.i [2018-11-23 10:05:58,224 INFO L355 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7c7a92368/7554025e3a7748d1b51ba437c49b88b3/FLAGb116f9d09 [2018-11-23 10:05:58,597 INFO L363 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7c7a92368/7554025e3a7748d1b51ba437c49b88b3 [2018-11-23 10:05:58,606 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 10:05:58,608 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 10:05:58,609 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 10:05:58,609 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 10:05:58,613 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 10:05:58,615 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:05:58" (1/1) ... [2018-11-23 10:05:58,618 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@64ba7b22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:05:58, skipping insertion in model container [2018-11-23 10:05:58,619 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:05:58" (1/1) ... [2018-11-23 10:05:58,629 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 10:05:58,657 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 10:05:58,929 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:05:58,934 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 10:05:58,964 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:05:58,989 INFO L195 MainTranslator]: Completed translation [2018-11-23 10:05:58,989 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:05:58 WrapperNode [2018-11-23 10:05:58,990 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 10:05:58,991 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 10:05:58,991 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 10:05:58,991 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 10:05:59,000 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:05:58" (1/1) ... [2018-11-23 10:05:59,011 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:05:58" (1/1) ... [2018-11-23 10:05:59,019 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 10:05:59,020 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 10:05:59,020 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 10:05:59,020 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 10:05:59,031 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:05:58" (1/1) ... [2018-11-23 10:05:59,031 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:05:58" (1/1) ... [2018-11-23 10:05:59,034 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:05:58" (1/1) ... [2018-11-23 10:05:59,034 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:05:58" (1/1) ... [2018-11-23 10:05:59,049 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:05:58" (1/1) ... [2018-11-23 10:05:59,057 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:05:58" (1/1) ... [2018-11-23 10:05:59,059 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:05:58" (1/1) ... [2018-11-23 10:05:59,062 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 10:05:59,062 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 10:05:59,063 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 10:05:59,063 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 10:05:59,064 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:05:58" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:05:59,191 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 10:05:59,191 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 10:05:59,191 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 10:05:59,191 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-23 10:05:59,191 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 10:05:59,192 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 10:05:59,192 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 10:05:59,192 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 10:05:59,192 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-23 10:05:59,192 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-23 10:05:59,192 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 10:05:59,193 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-23 10:05:59,819 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 10:05:59,819 INFO L280 CfgBuilder]: Removed 5 assue(true) statements. [2018-11-23 10:05:59,820 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:05:59 BoogieIcfgContainer [2018-11-23 10:05:59,820 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 10:05:59,821 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 10:05:59,821 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 10:05:59,825 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 10:05:59,825 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 10:05:58" (1/3) ... [2018-11-23 10:05:59,826 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@f2ba922 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:05:59, skipping insertion in model container [2018-11-23 10:05:59,826 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:05:58" (2/3) ... [2018-11-23 10:05:59,827 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@f2ba922 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:05:59, skipping insertion in model container [2018-11-23 10:05:59,827 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:05:59" (3/3) ... [2018-11-23 10:05:59,829 INFO L112 eAbstractionObserver]: Analyzing ICFG standard_copyInitSum3_true-unreach-call_ground.i [2018-11-23 10:05:59,838 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 10:05:59,846 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 10:05:59,861 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 10:05:59,895 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 10:05:59,896 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 10:05:59,897 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 10:05:59,897 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 10:05:59,898 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 10:05:59,898 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 10:05:59,898 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 10:05:59,899 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 10:05:59,899 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 10:05:59,923 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states. [2018-11-23 10:05:59,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-11-23 10:05:59,939 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:05:59,939 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:05:59,941 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:05:59,947 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:05:59,948 INFO L82 PathProgramCache]: Analyzing trace with hash 656367922, now seen corresponding path program 1 times [2018-11-23 10:05:59,951 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:05:59,952 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:05:59,969 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:06:00,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:06:00,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:06:00,039 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:06:00,340 INFO L256 TraceCheckUtils]: 0: Hoare triple {35#true} call ULTIMATE.init(); {35#true} is VALID [2018-11-23 10:06:00,344 INFO L273 TraceCheckUtils]: 1: Hoare triple {35#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {35#true} is VALID [2018-11-23 10:06:00,344 INFO L273 TraceCheckUtils]: 2: Hoare triple {35#true} assume true; {35#true} is VALID [2018-11-23 10:06:00,345 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {35#true} {35#true} #90#return; {35#true} is VALID [2018-11-23 10:06:00,345 INFO L256 TraceCheckUtils]: 4: Hoare triple {35#true} call #t~ret9 := main(); {35#true} is VALID [2018-11-23 10:06:00,345 INFO L273 TraceCheckUtils]: 5: Hoare triple {35#true} call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(400000bv32);call ~#b~0.base, ~#b~0.offset := #Ultimate.alloc(400000bv32);~i~0 := 0bv32; {35#true} is VALID [2018-11-23 10:06:00,346 INFO L273 TraceCheckUtils]: 6: Hoare triple {35#true} assume !true; {36#false} is VALID [2018-11-23 10:06:00,346 INFO L273 TraceCheckUtils]: 7: Hoare triple {36#false} ~i~0 := 0bv32; {36#false} is VALID [2018-11-23 10:06:00,347 INFO L273 TraceCheckUtils]: 8: Hoare triple {36#false} assume !~bvslt32(~i~0, 100000bv32); {36#false} is VALID [2018-11-23 10:06:00,347 INFO L273 TraceCheckUtils]: 9: Hoare triple {36#false} ~i~0 := 0bv32; {36#false} is VALID [2018-11-23 10:06:00,347 INFO L273 TraceCheckUtils]: 10: Hoare triple {36#false} assume !~bvslt32(~i~0, 100000bv32); {36#false} is VALID [2018-11-23 10:06:00,347 INFO L273 TraceCheckUtils]: 11: Hoare triple {36#false} ~i~0 := 0bv32; {36#false} is VALID [2018-11-23 10:06:00,348 INFO L273 TraceCheckUtils]: 12: Hoare triple {36#false} assume !~bvslt32(~i~0, 100000bv32); {36#false} is VALID [2018-11-23 10:06:00,348 INFO L273 TraceCheckUtils]: 13: Hoare triple {36#false} havoc ~x~0;~x~0 := 0bv32; {36#false} is VALID [2018-11-23 10:06:00,349 INFO L273 TraceCheckUtils]: 14: Hoare triple {36#false} assume !!~bvslt32(~x~0, 100000bv32);call #t~mem8 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {36#false} is VALID [2018-11-23 10:06:00,349 INFO L256 TraceCheckUtils]: 15: Hoare triple {36#false} call __VERIFIER_assert((if #t~mem8 == ~x~0 then 1bv32 else 0bv32)); {36#false} is VALID [2018-11-23 10:06:00,349 INFO L273 TraceCheckUtils]: 16: Hoare triple {36#false} ~cond := #in~cond; {36#false} is VALID [2018-11-23 10:06:00,350 INFO L273 TraceCheckUtils]: 17: Hoare triple {36#false} assume 0bv32 == ~cond; {36#false} is VALID [2018-11-23 10:06:00,350 INFO L273 TraceCheckUtils]: 18: Hoare triple {36#false} assume !false; {36#false} is VALID [2018-11-23 10:06:00,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:06:00,354 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:06:00,365 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:06:00,365 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 10:06:00,373 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 19 [2018-11-23 10:06:00,376 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:06:00,380 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states. [2018-11-23 10:06:00,559 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 19 edges. 19 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:06:00,559 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-23 10:06:00,567 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-23 10:06:00,567 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-23 10:06:00,570 INFO L87 Difference]: Start difference. First operand 32 states. Second operand 2 states. [2018-11-23 10:06:00,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:00,684 INFO L93 Difference]: Finished difference Result 57 states and 76 transitions. [2018-11-23 10:06:00,684 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-23 10:06:00,684 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 19 [2018-11-23 10:06:00,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:06:00,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-23 10:06:00,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 76 transitions. [2018-11-23 10:06:00,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-23 10:06:00,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 76 transitions. [2018-11-23 10:06:00,704 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states and 76 transitions. [2018-11-23 10:06:00,999 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 76 edges. 76 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:06:01,010 INFO L225 Difference]: With dead ends: 57 [2018-11-23 10:06:01,011 INFO L226 Difference]: Without dead ends: 27 [2018-11-23 10:06:01,014 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 18 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-23 10:06:01,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2018-11-23 10:06:01,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2018-11-23 10:06:01,062 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:06:01,063 INFO L82 GeneralOperation]: Start isEquivalent. First operand 27 states. Second operand 27 states. [2018-11-23 10:06:01,063 INFO L74 IsIncluded]: Start isIncluded. First operand 27 states. Second operand 27 states. [2018-11-23 10:06:01,064 INFO L87 Difference]: Start difference. First operand 27 states. Second operand 27 states. [2018-11-23 10:06:01,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:01,068 INFO L93 Difference]: Finished difference Result 27 states and 31 transitions. [2018-11-23 10:06:01,069 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 31 transitions. [2018-11-23 10:06:01,069 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:06:01,070 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:06:01,070 INFO L74 IsIncluded]: Start isIncluded. First operand 27 states. Second operand 27 states. [2018-11-23 10:06:01,070 INFO L87 Difference]: Start difference. First operand 27 states. Second operand 27 states. [2018-11-23 10:06:01,075 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:01,075 INFO L93 Difference]: Finished difference Result 27 states and 31 transitions. [2018-11-23 10:06:01,075 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 31 transitions. [2018-11-23 10:06:01,076 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:06:01,076 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:06:01,076 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:06:01,077 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:06:01,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-11-23 10:06:01,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 31 transitions. [2018-11-23 10:06:01,081 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 31 transitions. Word has length 19 [2018-11-23 10:06:01,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:06:01,082 INFO L480 AbstractCegarLoop]: Abstraction has 27 states and 31 transitions. [2018-11-23 10:06:01,082 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-23 10:06:01,082 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 31 transitions. [2018-11-23 10:06:01,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-11-23 10:06:01,084 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:06:01,084 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:06:01,084 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:06:01,085 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:06:01,085 INFO L82 PathProgramCache]: Analyzing trace with hash 1829979950, now seen corresponding path program 1 times [2018-11-23 10:06:01,085 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:06:01,086 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:06:01,116 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:06:01,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:06:01,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:06:01,181 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:06:01,351 INFO L256 TraceCheckUtils]: 0: Hoare triple {259#true} call ULTIMATE.init(); {259#true} is VALID [2018-11-23 10:06:01,352 INFO L273 TraceCheckUtils]: 1: Hoare triple {259#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {259#true} is VALID [2018-11-23 10:06:01,352 INFO L273 TraceCheckUtils]: 2: Hoare triple {259#true} assume true; {259#true} is VALID [2018-11-23 10:06:01,353 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {259#true} {259#true} #90#return; {259#true} is VALID [2018-11-23 10:06:01,353 INFO L256 TraceCheckUtils]: 4: Hoare triple {259#true} call #t~ret9 := main(); {259#true} is VALID [2018-11-23 10:06:01,363 INFO L273 TraceCheckUtils]: 5: Hoare triple {259#true} call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(400000bv32);call ~#b~0.base, ~#b~0.offset := #Ultimate.alloc(400000bv32);~i~0 := 0bv32; {279#(= main_~i~0 (_ bv0 32))} is VALID [2018-11-23 10:06:01,376 INFO L273 TraceCheckUtils]: 6: Hoare triple {279#(= main_~i~0 (_ bv0 32))} assume !~bvslt32(~i~0, 100000bv32); {260#false} is VALID [2018-11-23 10:06:01,377 INFO L273 TraceCheckUtils]: 7: Hoare triple {260#false} ~i~0 := 0bv32; {260#false} is VALID [2018-11-23 10:06:01,377 INFO L273 TraceCheckUtils]: 8: Hoare triple {260#false} assume !~bvslt32(~i~0, 100000bv32); {260#false} is VALID [2018-11-23 10:06:01,377 INFO L273 TraceCheckUtils]: 9: Hoare triple {260#false} ~i~0 := 0bv32; {260#false} is VALID [2018-11-23 10:06:01,378 INFO L273 TraceCheckUtils]: 10: Hoare triple {260#false} assume !~bvslt32(~i~0, 100000bv32); {260#false} is VALID [2018-11-23 10:06:01,378 INFO L273 TraceCheckUtils]: 11: Hoare triple {260#false} ~i~0 := 0bv32; {260#false} is VALID [2018-11-23 10:06:01,379 INFO L273 TraceCheckUtils]: 12: Hoare triple {260#false} assume !~bvslt32(~i~0, 100000bv32); {260#false} is VALID [2018-11-23 10:06:01,379 INFO L273 TraceCheckUtils]: 13: Hoare triple {260#false} havoc ~x~0;~x~0 := 0bv32; {260#false} is VALID [2018-11-23 10:06:01,379 INFO L273 TraceCheckUtils]: 14: Hoare triple {260#false} assume !!~bvslt32(~x~0, 100000bv32);call #t~mem8 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {260#false} is VALID [2018-11-23 10:06:01,380 INFO L256 TraceCheckUtils]: 15: Hoare triple {260#false} call __VERIFIER_assert((if #t~mem8 == ~x~0 then 1bv32 else 0bv32)); {260#false} is VALID [2018-11-23 10:06:01,380 INFO L273 TraceCheckUtils]: 16: Hoare triple {260#false} ~cond := #in~cond; {260#false} is VALID [2018-11-23 10:06:01,380 INFO L273 TraceCheckUtils]: 17: Hoare triple {260#false} assume 0bv32 == ~cond; {260#false} is VALID [2018-11-23 10:06:01,381 INFO L273 TraceCheckUtils]: 18: Hoare triple {260#false} assume !false; {260#false} is VALID [2018-11-23 10:06:01,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:06:01,386 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:06:01,391 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:06:01,391 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 10:06:01,394 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2018-11-23 10:06:01,398 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:06:01,400 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-23 10:06:01,602 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 19 edges. 19 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:06:01,603 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 10:06:01,603 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 10:06:01,603 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:06:01,604 INFO L87 Difference]: Start difference. First operand 27 states and 31 transitions. Second operand 3 states. [2018-11-23 10:06:01,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:01,936 INFO L93 Difference]: Finished difference Result 54 states and 65 transitions. [2018-11-23 10:06:01,936 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 10:06:01,936 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2018-11-23 10:06:01,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:06:01,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:06:01,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 65 transitions. [2018-11-23 10:06:01,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:06:01,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 65 transitions. [2018-11-23 10:06:01,944 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 65 transitions. [2018-11-23 10:06:02,098 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 65 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:06:02,099 INFO L225 Difference]: With dead ends: 54 [2018-11-23 10:06:02,100 INFO L226 Difference]: Without dead ends: 34 [2018-11-23 10:06:02,101 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:06:02,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-11-23 10:06:02,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 31. [2018-11-23 10:06:02,114 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:06:02,115 INFO L82 GeneralOperation]: Start isEquivalent. First operand 34 states. Second operand 31 states. [2018-11-23 10:06:02,115 INFO L74 IsIncluded]: Start isIncluded. First operand 34 states. Second operand 31 states. [2018-11-23 10:06:02,115 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 31 states. [2018-11-23 10:06:02,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:02,118 INFO L93 Difference]: Finished difference Result 34 states and 38 transitions. [2018-11-23 10:06:02,118 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 38 transitions. [2018-11-23 10:06:02,119 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:06:02,119 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:06:02,119 INFO L74 IsIncluded]: Start isIncluded. First operand 31 states. Second operand 34 states. [2018-11-23 10:06:02,119 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 34 states. [2018-11-23 10:06:02,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:02,122 INFO L93 Difference]: Finished difference Result 34 states and 38 transitions. [2018-11-23 10:06:02,122 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 38 transitions. [2018-11-23 10:06:02,123 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:06:02,123 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:06:02,123 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:06:02,124 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:06:02,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-11-23 10:06:02,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 35 transitions. [2018-11-23 10:06:02,126 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 35 transitions. Word has length 19 [2018-11-23 10:06:02,127 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:06:02,127 INFO L480 AbstractCegarLoop]: Abstraction has 31 states and 35 transitions. [2018-11-23 10:06:02,127 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 10:06:02,127 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2018-11-23 10:06:02,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-11-23 10:06:02,129 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:06:02,129 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:06:02,129 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:06:02,129 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:06:02,130 INFO L82 PathProgramCache]: Analyzing trace with hash 1442018896, now seen corresponding path program 1 times [2018-11-23 10:06:02,130 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:06:02,130 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:06:02,147 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:06:02,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:06:02,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:06:02,203 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:06:02,299 INFO L256 TraceCheckUtils]: 0: Hoare triple {507#true} call ULTIMATE.init(); {507#true} is VALID [2018-11-23 10:06:02,300 INFO L273 TraceCheckUtils]: 1: Hoare triple {507#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {507#true} is VALID [2018-11-23 10:06:02,301 INFO L273 TraceCheckUtils]: 2: Hoare triple {507#true} assume true; {507#true} is VALID [2018-11-23 10:06:02,301 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {507#true} {507#true} #90#return; {507#true} is VALID [2018-11-23 10:06:02,302 INFO L256 TraceCheckUtils]: 4: Hoare triple {507#true} call #t~ret9 := main(); {507#true} is VALID [2018-11-23 10:06:02,302 INFO L273 TraceCheckUtils]: 5: Hoare triple {507#true} call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(400000bv32);call ~#b~0.base, ~#b~0.offset := #Ultimate.alloc(400000bv32);~i~0 := 0bv32; {527#(= main_~i~0 (_ bv0 32))} is VALID [2018-11-23 10:06:02,304 INFO L273 TraceCheckUtils]: 6: Hoare triple {527#(= main_~i~0 (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {531#(= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:02,306 INFO L273 TraceCheckUtils]: 7: Hoare triple {531#(= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))} assume !~bvslt32(~i~0, 100000bv32); {508#false} is VALID [2018-11-23 10:06:02,306 INFO L273 TraceCheckUtils]: 8: Hoare triple {508#false} ~i~0 := 0bv32; {508#false} is VALID [2018-11-23 10:06:02,306 INFO L273 TraceCheckUtils]: 9: Hoare triple {508#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {508#false} is VALID [2018-11-23 10:06:02,307 INFO L273 TraceCheckUtils]: 10: Hoare triple {508#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {508#false} is VALID [2018-11-23 10:06:02,307 INFO L273 TraceCheckUtils]: 11: Hoare triple {508#false} assume !~bvslt32(~i~0, 100000bv32); {508#false} is VALID [2018-11-23 10:06:02,307 INFO L273 TraceCheckUtils]: 12: Hoare triple {508#false} ~i~0 := 0bv32; {508#false} is VALID [2018-11-23 10:06:02,308 INFO L273 TraceCheckUtils]: 13: Hoare triple {508#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {508#false} is VALID [2018-11-23 10:06:02,308 INFO L273 TraceCheckUtils]: 14: Hoare triple {508#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {508#false} is VALID [2018-11-23 10:06:02,309 INFO L273 TraceCheckUtils]: 15: Hoare triple {508#false} assume !~bvslt32(~i~0, 100000bv32); {508#false} is VALID [2018-11-23 10:06:02,309 INFO L273 TraceCheckUtils]: 16: Hoare triple {508#false} ~i~0 := 0bv32; {508#false} is VALID [2018-11-23 10:06:02,309 INFO L273 TraceCheckUtils]: 17: Hoare triple {508#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {508#false} is VALID [2018-11-23 10:06:02,310 INFO L273 TraceCheckUtils]: 18: Hoare triple {508#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {508#false} is VALID [2018-11-23 10:06:02,310 INFO L273 TraceCheckUtils]: 19: Hoare triple {508#false} assume !~bvslt32(~i~0, 100000bv32); {508#false} is VALID [2018-11-23 10:06:02,311 INFO L273 TraceCheckUtils]: 20: Hoare triple {508#false} havoc ~x~0;~x~0 := 0bv32; {508#false} is VALID [2018-11-23 10:06:02,311 INFO L273 TraceCheckUtils]: 21: Hoare triple {508#false} assume !!~bvslt32(~x~0, 100000bv32);call #t~mem8 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {508#false} is VALID [2018-11-23 10:06:02,311 INFO L256 TraceCheckUtils]: 22: Hoare triple {508#false} call __VERIFIER_assert((if #t~mem8 == ~x~0 then 1bv32 else 0bv32)); {508#false} is VALID [2018-11-23 10:06:02,311 INFO L273 TraceCheckUtils]: 23: Hoare triple {508#false} ~cond := #in~cond; {508#false} is VALID [2018-11-23 10:06:02,312 INFO L273 TraceCheckUtils]: 24: Hoare triple {508#false} assume 0bv32 == ~cond; {508#false} is VALID [2018-11-23 10:06:02,312 INFO L273 TraceCheckUtils]: 25: Hoare triple {508#false} assume !false; {508#false} is VALID [2018-11-23 10:06:02,314 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-23 10:06:02,314 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:06:02,439 INFO L273 TraceCheckUtils]: 25: Hoare triple {508#false} assume !false; {508#false} is VALID [2018-11-23 10:06:02,440 INFO L273 TraceCheckUtils]: 24: Hoare triple {508#false} assume 0bv32 == ~cond; {508#false} is VALID [2018-11-23 10:06:02,440 INFO L273 TraceCheckUtils]: 23: Hoare triple {508#false} ~cond := #in~cond; {508#false} is VALID [2018-11-23 10:06:02,441 INFO L256 TraceCheckUtils]: 22: Hoare triple {508#false} call __VERIFIER_assert((if #t~mem8 == ~x~0 then 1bv32 else 0bv32)); {508#false} is VALID [2018-11-23 10:06:02,441 INFO L273 TraceCheckUtils]: 21: Hoare triple {508#false} assume !!~bvslt32(~x~0, 100000bv32);call #t~mem8 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {508#false} is VALID [2018-11-23 10:06:02,441 INFO L273 TraceCheckUtils]: 20: Hoare triple {508#false} havoc ~x~0;~x~0 := 0bv32; {508#false} is VALID [2018-11-23 10:06:02,442 INFO L273 TraceCheckUtils]: 19: Hoare triple {508#false} assume !~bvslt32(~i~0, 100000bv32); {508#false} is VALID [2018-11-23 10:06:02,442 INFO L273 TraceCheckUtils]: 18: Hoare triple {508#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {508#false} is VALID [2018-11-23 10:06:02,442 INFO L273 TraceCheckUtils]: 17: Hoare triple {508#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {508#false} is VALID [2018-11-23 10:06:02,443 INFO L273 TraceCheckUtils]: 16: Hoare triple {508#false} ~i~0 := 0bv32; {508#false} is VALID [2018-11-23 10:06:02,443 INFO L273 TraceCheckUtils]: 15: Hoare triple {508#false} assume !~bvslt32(~i~0, 100000bv32); {508#false} is VALID [2018-11-23 10:06:02,443 INFO L273 TraceCheckUtils]: 14: Hoare triple {508#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {508#false} is VALID [2018-11-23 10:06:02,443 INFO L273 TraceCheckUtils]: 13: Hoare triple {508#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {508#false} is VALID [2018-11-23 10:06:02,444 INFO L273 TraceCheckUtils]: 12: Hoare triple {508#false} ~i~0 := 0bv32; {508#false} is VALID [2018-11-23 10:06:02,444 INFO L273 TraceCheckUtils]: 11: Hoare triple {508#false} assume !~bvslt32(~i~0, 100000bv32); {508#false} is VALID [2018-11-23 10:06:02,444 INFO L273 TraceCheckUtils]: 10: Hoare triple {508#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {508#false} is VALID [2018-11-23 10:06:02,445 INFO L273 TraceCheckUtils]: 9: Hoare triple {508#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {508#false} is VALID [2018-11-23 10:06:02,445 INFO L273 TraceCheckUtils]: 8: Hoare triple {508#false} ~i~0 := 0bv32; {508#false} is VALID [2018-11-23 10:06:02,449 INFO L273 TraceCheckUtils]: 7: Hoare triple {643#(bvslt main_~i~0 (_ bv100000 32))} assume !~bvslt32(~i~0, 100000bv32); {508#false} is VALID [2018-11-23 10:06:02,450 INFO L273 TraceCheckUtils]: 6: Hoare triple {647#(bvslt (bvadd main_~i~0 (_ bv1 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {643#(bvslt main_~i~0 (_ bv100000 32))} is VALID [2018-11-23 10:06:02,456 INFO L273 TraceCheckUtils]: 5: Hoare triple {507#true} call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(400000bv32);call ~#b~0.base, ~#b~0.offset := #Ultimate.alloc(400000bv32);~i~0 := 0bv32; {647#(bvslt (bvadd main_~i~0 (_ bv1 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:02,456 INFO L256 TraceCheckUtils]: 4: Hoare triple {507#true} call #t~ret9 := main(); {507#true} is VALID [2018-11-23 10:06:02,456 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {507#true} {507#true} #90#return; {507#true} is VALID [2018-11-23 10:06:02,457 INFO L273 TraceCheckUtils]: 2: Hoare triple {507#true} assume true; {507#true} is VALID [2018-11-23 10:06:02,457 INFO L273 TraceCheckUtils]: 1: Hoare triple {507#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {507#true} is VALID [2018-11-23 10:06:02,457 INFO L256 TraceCheckUtils]: 0: Hoare triple {507#true} call ULTIMATE.init(); {507#true} is VALID [2018-11-23 10:06:02,459 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-23 10:06:02,460 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:06:02,461 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 6 [2018-11-23 10:06:02,461 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 26 [2018-11-23 10:06:02,462 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:06:02,462 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states. [2018-11-23 10:06:02,566 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 29 edges. 29 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:06:02,566 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 10:06:02,566 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 10:06:02,567 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-23 10:06:02,567 INFO L87 Difference]: Start difference. First operand 31 states and 35 transitions. Second operand 6 states. [2018-11-23 10:06:03,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:03,346 INFO L93 Difference]: Finished difference Result 75 states and 94 transitions. [2018-11-23 10:06:03,346 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 10:06:03,346 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 26 [2018-11-23 10:06:03,346 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:06:03,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-23 10:06:03,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 91 transitions. [2018-11-23 10:06:03,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-23 10:06:03,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 91 transitions. [2018-11-23 10:06:03,354 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 91 transitions. [2018-11-23 10:06:03,545 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 91 edges. 91 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:06:03,547 INFO L225 Difference]: With dead ends: 75 [2018-11-23 10:06:03,547 INFO L226 Difference]: Without dead ends: 52 [2018-11-23 10:06:03,548 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 47 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2018-11-23 10:06:03,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-11-23 10:06:03,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. [2018-11-23 10:06:03,587 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:06:03,587 INFO L82 GeneralOperation]: Start isEquivalent. First operand 52 states. Second operand 52 states. [2018-11-23 10:06:03,588 INFO L74 IsIncluded]: Start isIncluded. First operand 52 states. Second operand 52 states. [2018-11-23 10:06:03,588 INFO L87 Difference]: Start difference. First operand 52 states. Second operand 52 states. [2018-11-23 10:06:03,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:03,591 INFO L93 Difference]: Finished difference Result 52 states and 56 transitions. [2018-11-23 10:06:03,591 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 56 transitions. [2018-11-23 10:06:03,592 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:06:03,592 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:06:03,593 INFO L74 IsIncluded]: Start isIncluded. First operand 52 states. Second operand 52 states. [2018-11-23 10:06:03,593 INFO L87 Difference]: Start difference. First operand 52 states. Second operand 52 states. [2018-11-23 10:06:03,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:03,597 INFO L93 Difference]: Finished difference Result 52 states and 56 transitions. [2018-11-23 10:06:03,597 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 56 transitions. [2018-11-23 10:06:03,598 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:06:03,598 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:06:03,598 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:06:03,598 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:06:03,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-11-23 10:06:03,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 56 transitions. [2018-11-23 10:06:03,602 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 56 transitions. Word has length 26 [2018-11-23 10:06:03,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:06:03,602 INFO L480 AbstractCegarLoop]: Abstraction has 52 states and 56 transitions. [2018-11-23 10:06:03,602 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 10:06:03,602 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 56 transitions. [2018-11-23 10:06:03,604 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-23 10:06:03,604 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:06:03,604 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:06:03,604 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:06:03,605 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:06:03,605 INFO L82 PathProgramCache]: Analyzing trace with hash -1161905130, now seen corresponding path program 2 times [2018-11-23 10:06:03,606 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:06:03,606 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:06:03,623 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 10:06:03,714 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 10:06:03,715 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:06:03,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:06:03,779 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:06:03,981 INFO L256 TraceCheckUtils]: 0: Hoare triple {964#true} call ULTIMATE.init(); {964#true} is VALID [2018-11-23 10:06:03,981 INFO L273 TraceCheckUtils]: 1: Hoare triple {964#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {964#true} is VALID [2018-11-23 10:06:03,982 INFO L273 TraceCheckUtils]: 2: Hoare triple {964#true} assume true; {964#true} is VALID [2018-11-23 10:06:03,982 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {964#true} {964#true} #90#return; {964#true} is VALID [2018-11-23 10:06:03,982 INFO L256 TraceCheckUtils]: 4: Hoare triple {964#true} call #t~ret9 := main(); {964#true} is VALID [2018-11-23 10:06:03,987 INFO L273 TraceCheckUtils]: 5: Hoare triple {964#true} call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(400000bv32);call ~#b~0.base, ~#b~0.offset := #Ultimate.alloc(400000bv32);~i~0 := 0bv32; {984#(= main_~i~0 (_ bv0 32))} is VALID [2018-11-23 10:06:03,988 INFO L273 TraceCheckUtils]: 6: Hoare triple {984#(= main_~i~0 (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {988#(= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:03,989 INFO L273 TraceCheckUtils]: 7: Hoare triple {988#(= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {992#(= (_ bv2 32) main_~i~0)} is VALID [2018-11-23 10:06:03,990 INFO L273 TraceCheckUtils]: 8: Hoare triple {992#(= (_ bv2 32) main_~i~0)} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {996#(= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:03,990 INFO L273 TraceCheckUtils]: 9: Hoare triple {996#(= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1000#(= (bvadd main_~i~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:03,992 INFO L273 TraceCheckUtils]: 10: Hoare triple {1000#(= (bvadd main_~i~0 (_ bv4294967292 32)) (_ bv0 32))} assume !~bvslt32(~i~0, 100000bv32); {965#false} is VALID [2018-11-23 10:06:03,992 INFO L273 TraceCheckUtils]: 11: Hoare triple {965#false} ~i~0 := 0bv32; {965#false} is VALID [2018-11-23 10:06:03,992 INFO L273 TraceCheckUtils]: 12: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {965#false} is VALID [2018-11-23 10:06:03,992 INFO L273 TraceCheckUtils]: 13: Hoare triple {965#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {965#false} is VALID [2018-11-23 10:06:03,993 INFO L273 TraceCheckUtils]: 14: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {965#false} is VALID [2018-11-23 10:06:03,993 INFO L273 TraceCheckUtils]: 15: Hoare triple {965#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {965#false} is VALID [2018-11-23 10:06:03,993 INFO L273 TraceCheckUtils]: 16: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {965#false} is VALID [2018-11-23 10:06:03,994 INFO L273 TraceCheckUtils]: 17: Hoare triple {965#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {965#false} is VALID [2018-11-23 10:06:03,995 INFO L273 TraceCheckUtils]: 18: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {965#false} is VALID [2018-11-23 10:06:03,995 INFO L273 TraceCheckUtils]: 19: Hoare triple {965#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {965#false} is VALID [2018-11-23 10:06:03,996 INFO L273 TraceCheckUtils]: 20: Hoare triple {965#false} assume !~bvslt32(~i~0, 100000bv32); {965#false} is VALID [2018-11-23 10:06:03,996 INFO L273 TraceCheckUtils]: 21: Hoare triple {965#false} ~i~0 := 0bv32; {965#false} is VALID [2018-11-23 10:06:03,996 INFO L273 TraceCheckUtils]: 22: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {965#false} is VALID [2018-11-23 10:06:03,997 INFO L273 TraceCheckUtils]: 23: Hoare triple {965#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {965#false} is VALID [2018-11-23 10:06:03,997 INFO L273 TraceCheckUtils]: 24: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {965#false} is VALID [2018-11-23 10:06:03,997 INFO L273 TraceCheckUtils]: 25: Hoare triple {965#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {965#false} is VALID [2018-11-23 10:06:03,997 INFO L273 TraceCheckUtils]: 26: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {965#false} is VALID [2018-11-23 10:06:03,998 INFO L273 TraceCheckUtils]: 27: Hoare triple {965#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {965#false} is VALID [2018-11-23 10:06:03,998 INFO L273 TraceCheckUtils]: 28: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {965#false} is VALID [2018-11-23 10:06:03,998 INFO L273 TraceCheckUtils]: 29: Hoare triple {965#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {965#false} is VALID [2018-11-23 10:06:03,999 INFO L273 TraceCheckUtils]: 30: Hoare triple {965#false} assume !~bvslt32(~i~0, 100000bv32); {965#false} is VALID [2018-11-23 10:06:03,999 INFO L273 TraceCheckUtils]: 31: Hoare triple {965#false} ~i~0 := 0bv32; {965#false} is VALID [2018-11-23 10:06:03,999 INFO L273 TraceCheckUtils]: 32: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {965#false} is VALID [2018-11-23 10:06:04,000 INFO L273 TraceCheckUtils]: 33: Hoare triple {965#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {965#false} is VALID [2018-11-23 10:06:04,000 INFO L273 TraceCheckUtils]: 34: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {965#false} is VALID [2018-11-23 10:06:04,000 INFO L273 TraceCheckUtils]: 35: Hoare triple {965#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {965#false} is VALID [2018-11-23 10:06:04,001 INFO L273 TraceCheckUtils]: 36: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {965#false} is VALID [2018-11-23 10:06:04,001 INFO L273 TraceCheckUtils]: 37: Hoare triple {965#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {965#false} is VALID [2018-11-23 10:06:04,001 INFO L273 TraceCheckUtils]: 38: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {965#false} is VALID [2018-11-23 10:06:04,002 INFO L273 TraceCheckUtils]: 39: Hoare triple {965#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {965#false} is VALID [2018-11-23 10:06:04,002 INFO L273 TraceCheckUtils]: 40: Hoare triple {965#false} assume !~bvslt32(~i~0, 100000bv32); {965#false} is VALID [2018-11-23 10:06:04,002 INFO L273 TraceCheckUtils]: 41: Hoare triple {965#false} havoc ~x~0;~x~0 := 0bv32; {965#false} is VALID [2018-11-23 10:06:04,002 INFO L273 TraceCheckUtils]: 42: Hoare triple {965#false} assume !!~bvslt32(~x~0, 100000bv32);call #t~mem8 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {965#false} is VALID [2018-11-23 10:06:04,003 INFO L256 TraceCheckUtils]: 43: Hoare triple {965#false} call __VERIFIER_assert((if #t~mem8 == ~x~0 then 1bv32 else 0bv32)); {965#false} is VALID [2018-11-23 10:06:04,003 INFO L273 TraceCheckUtils]: 44: Hoare triple {965#false} ~cond := #in~cond; {965#false} is VALID [2018-11-23 10:06:04,003 INFO L273 TraceCheckUtils]: 45: Hoare triple {965#false} assume 0bv32 == ~cond; {965#false} is VALID [2018-11-23 10:06:04,004 INFO L273 TraceCheckUtils]: 46: Hoare triple {965#false} assume !false; {965#false} is VALID [2018-11-23 10:06:04,007 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-11-23 10:06:04,008 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:06:04,395 INFO L273 TraceCheckUtils]: 46: Hoare triple {965#false} assume !false; {965#false} is VALID [2018-11-23 10:06:04,395 INFO L273 TraceCheckUtils]: 45: Hoare triple {965#false} assume 0bv32 == ~cond; {965#false} is VALID [2018-11-23 10:06:04,396 INFO L273 TraceCheckUtils]: 44: Hoare triple {965#false} ~cond := #in~cond; {965#false} is VALID [2018-11-23 10:06:04,396 INFO L256 TraceCheckUtils]: 43: Hoare triple {965#false} call __VERIFIER_assert((if #t~mem8 == ~x~0 then 1bv32 else 0bv32)); {965#false} is VALID [2018-11-23 10:06:04,397 INFO L273 TraceCheckUtils]: 42: Hoare triple {965#false} assume !!~bvslt32(~x~0, 100000bv32);call #t~mem8 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {965#false} is VALID [2018-11-23 10:06:04,397 INFO L273 TraceCheckUtils]: 41: Hoare triple {965#false} havoc ~x~0;~x~0 := 0bv32; {965#false} is VALID [2018-11-23 10:06:04,397 INFO L273 TraceCheckUtils]: 40: Hoare triple {965#false} assume !~bvslt32(~i~0, 100000bv32); {965#false} is VALID [2018-11-23 10:06:04,398 INFO L273 TraceCheckUtils]: 39: Hoare triple {965#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {965#false} is VALID [2018-11-23 10:06:04,398 INFO L273 TraceCheckUtils]: 38: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {965#false} is VALID [2018-11-23 10:06:04,398 INFO L273 TraceCheckUtils]: 37: Hoare triple {965#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {965#false} is VALID [2018-11-23 10:06:04,399 INFO L273 TraceCheckUtils]: 36: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {965#false} is VALID [2018-11-23 10:06:04,399 INFO L273 TraceCheckUtils]: 35: Hoare triple {965#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {965#false} is VALID [2018-11-23 10:06:04,399 INFO L273 TraceCheckUtils]: 34: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {965#false} is VALID [2018-11-23 10:06:04,399 INFO L273 TraceCheckUtils]: 33: Hoare triple {965#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {965#false} is VALID [2018-11-23 10:06:04,400 INFO L273 TraceCheckUtils]: 32: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {965#false} is VALID [2018-11-23 10:06:04,400 INFO L273 TraceCheckUtils]: 31: Hoare triple {965#false} ~i~0 := 0bv32; {965#false} is VALID [2018-11-23 10:06:04,400 INFO L273 TraceCheckUtils]: 30: Hoare triple {965#false} assume !~bvslt32(~i~0, 100000bv32); {965#false} is VALID [2018-11-23 10:06:04,401 INFO L273 TraceCheckUtils]: 29: Hoare triple {965#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {965#false} is VALID [2018-11-23 10:06:04,401 INFO L273 TraceCheckUtils]: 28: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {965#false} is VALID [2018-11-23 10:06:04,401 INFO L273 TraceCheckUtils]: 27: Hoare triple {965#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {965#false} is VALID [2018-11-23 10:06:04,401 INFO L273 TraceCheckUtils]: 26: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {965#false} is VALID [2018-11-23 10:06:04,402 INFO L273 TraceCheckUtils]: 25: Hoare triple {965#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {965#false} is VALID [2018-11-23 10:06:04,402 INFO L273 TraceCheckUtils]: 24: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {965#false} is VALID [2018-11-23 10:06:04,402 INFO L273 TraceCheckUtils]: 23: Hoare triple {965#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {965#false} is VALID [2018-11-23 10:06:04,402 INFO L273 TraceCheckUtils]: 22: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {965#false} is VALID [2018-11-23 10:06:04,403 INFO L273 TraceCheckUtils]: 21: Hoare triple {965#false} ~i~0 := 0bv32; {965#false} is VALID [2018-11-23 10:06:04,403 INFO L273 TraceCheckUtils]: 20: Hoare triple {965#false} assume !~bvslt32(~i~0, 100000bv32); {965#false} is VALID [2018-11-23 10:06:04,403 INFO L273 TraceCheckUtils]: 19: Hoare triple {965#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {965#false} is VALID [2018-11-23 10:06:04,403 INFO L273 TraceCheckUtils]: 18: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {965#false} is VALID [2018-11-23 10:06:04,403 INFO L273 TraceCheckUtils]: 17: Hoare triple {965#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {965#false} is VALID [2018-11-23 10:06:04,404 INFO L273 TraceCheckUtils]: 16: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {965#false} is VALID [2018-11-23 10:06:04,404 INFO L273 TraceCheckUtils]: 15: Hoare triple {965#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {965#false} is VALID [2018-11-23 10:06:04,404 INFO L273 TraceCheckUtils]: 14: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {965#false} is VALID [2018-11-23 10:06:04,404 INFO L273 TraceCheckUtils]: 13: Hoare triple {965#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {965#false} is VALID [2018-11-23 10:06:04,404 INFO L273 TraceCheckUtils]: 12: Hoare triple {965#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {965#false} is VALID [2018-11-23 10:06:04,405 INFO L273 TraceCheckUtils]: 11: Hoare triple {965#false} ~i~0 := 0bv32; {965#false} is VALID [2018-11-23 10:06:04,405 INFO L273 TraceCheckUtils]: 10: Hoare triple {1220#(bvslt main_~i~0 (_ bv100000 32))} assume !~bvslt32(~i~0, 100000bv32); {965#false} is VALID [2018-11-23 10:06:04,406 INFO L273 TraceCheckUtils]: 9: Hoare triple {1224#(bvslt (bvadd main_~i~0 (_ bv1 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1220#(bvslt main_~i~0 (_ bv100000 32))} is VALID [2018-11-23 10:06:04,410 INFO L273 TraceCheckUtils]: 8: Hoare triple {1228#(bvslt (bvadd main_~i~0 (_ bv2 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1224#(bvslt (bvadd main_~i~0 (_ bv1 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:04,415 INFO L273 TraceCheckUtils]: 7: Hoare triple {1232#(bvslt (bvadd main_~i~0 (_ bv3 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1228#(bvslt (bvadd main_~i~0 (_ bv2 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:04,420 INFO L273 TraceCheckUtils]: 6: Hoare triple {1236#(bvslt (bvadd main_~i~0 (_ bv4 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1232#(bvslt (bvadd main_~i~0 (_ bv3 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:04,421 INFO L273 TraceCheckUtils]: 5: Hoare triple {964#true} call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(400000bv32);call ~#b~0.base, ~#b~0.offset := #Ultimate.alloc(400000bv32);~i~0 := 0bv32; {1236#(bvslt (bvadd main_~i~0 (_ bv4 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:04,421 INFO L256 TraceCheckUtils]: 4: Hoare triple {964#true} call #t~ret9 := main(); {964#true} is VALID [2018-11-23 10:06:04,422 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {964#true} {964#true} #90#return; {964#true} is VALID [2018-11-23 10:06:04,422 INFO L273 TraceCheckUtils]: 2: Hoare triple {964#true} assume true; {964#true} is VALID [2018-11-23 10:06:04,422 INFO L273 TraceCheckUtils]: 1: Hoare triple {964#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {964#true} is VALID [2018-11-23 10:06:04,422 INFO L256 TraceCheckUtils]: 0: Hoare triple {964#true} call ULTIMATE.init(); {964#true} is VALID [2018-11-23 10:06:04,427 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-11-23 10:06:04,438 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:06:04,438 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-11-23 10:06:04,440 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 47 [2018-11-23 10:06:04,440 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:06:04,440 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states. [2018-11-23 10:06:04,530 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 35 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:06:04,531 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-23 10:06:04,531 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-23 10:06:04,531 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-11-23 10:06:04,532 INFO L87 Difference]: Start difference. First operand 52 states and 56 transitions. Second operand 12 states. [2018-11-23 10:06:07,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:07,076 INFO L93 Difference]: Finished difference Result 135 states and 166 transitions. [2018-11-23 10:06:07,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 10:06:07,077 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 47 [2018-11-23 10:06:07,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:06:07,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-23 10:06:07,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 145 transitions. [2018-11-23 10:06:07,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-23 10:06:07,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 145 transitions. [2018-11-23 10:06:07,087 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states and 145 transitions. [2018-11-23 10:06:07,441 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 145 edges. 145 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:06:07,445 INFO L225 Difference]: With dead ends: 135 [2018-11-23 10:06:07,445 INFO L226 Difference]: Without dead ends: 94 [2018-11-23 10:06:07,446 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=94, Invalid=146, Unknown=0, NotChecked=0, Total=240 [2018-11-23 10:06:07,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-11-23 10:06:07,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 94. [2018-11-23 10:06:07,568 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:06:07,568 INFO L82 GeneralOperation]: Start isEquivalent. First operand 94 states. Second operand 94 states. [2018-11-23 10:06:07,568 INFO L74 IsIncluded]: Start isIncluded. First operand 94 states. Second operand 94 states. [2018-11-23 10:06:07,568 INFO L87 Difference]: Start difference. First operand 94 states. Second operand 94 states. [2018-11-23 10:06:07,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:07,573 INFO L93 Difference]: Finished difference Result 94 states and 98 transitions. [2018-11-23 10:06:07,573 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 98 transitions. [2018-11-23 10:06:07,574 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:06:07,574 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:06:07,574 INFO L74 IsIncluded]: Start isIncluded. First operand 94 states. Second operand 94 states. [2018-11-23 10:06:07,574 INFO L87 Difference]: Start difference. First operand 94 states. Second operand 94 states. [2018-11-23 10:06:07,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:07,579 INFO L93 Difference]: Finished difference Result 94 states and 98 transitions. [2018-11-23 10:06:07,579 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 98 transitions. [2018-11-23 10:06:07,581 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:06:07,581 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:06:07,581 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:06:07,581 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:06:07,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-11-23 10:06:07,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 98 transitions. [2018-11-23 10:06:07,586 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 98 transitions. Word has length 47 [2018-11-23 10:06:07,586 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:06:07,586 INFO L480 AbstractCegarLoop]: Abstraction has 94 states and 98 transitions. [2018-11-23 10:06:07,586 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-23 10:06:07,587 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 98 transitions. [2018-11-23 10:06:07,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-11-23 10:06:07,590 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:06:07,590 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:06:07,590 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:06:07,590 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:06:07,591 INFO L82 PathProgramCache]: Analyzing trace with hash 1732223602, now seen corresponding path program 3 times [2018-11-23 10:06:07,591 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:06:07,592 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:06:07,620 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2018-11-23 10:06:08,372 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-11-23 10:06:08,372 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:06:08,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:06:08,426 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:06:08,755 INFO L256 TraceCheckUtils]: 0: Hoare triple {1802#true} call ULTIMATE.init(); {1802#true} is VALID [2018-11-23 10:06:08,755 INFO L273 TraceCheckUtils]: 1: Hoare triple {1802#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {1802#true} is VALID [2018-11-23 10:06:08,756 INFO L273 TraceCheckUtils]: 2: Hoare triple {1802#true} assume true; {1802#true} is VALID [2018-11-23 10:06:08,756 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1802#true} {1802#true} #90#return; {1802#true} is VALID [2018-11-23 10:06:08,757 INFO L256 TraceCheckUtils]: 4: Hoare triple {1802#true} call #t~ret9 := main(); {1802#true} is VALID [2018-11-23 10:06:08,758 INFO L273 TraceCheckUtils]: 5: Hoare triple {1802#true} call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(400000bv32);call ~#b~0.base, ~#b~0.offset := #Ultimate.alloc(400000bv32);~i~0 := 0bv32; {1822#(= main_~i~0 (_ bv0 32))} is VALID [2018-11-23 10:06:08,759 INFO L273 TraceCheckUtils]: 6: Hoare triple {1822#(= main_~i~0 (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1826#(= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:08,760 INFO L273 TraceCheckUtils]: 7: Hoare triple {1826#(= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1830#(= (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:08,765 INFO L273 TraceCheckUtils]: 8: Hoare triple {1830#(= (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1834#(= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:08,766 INFO L273 TraceCheckUtils]: 9: Hoare triple {1834#(= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1838#(= (bvadd main_~i~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:08,767 INFO L273 TraceCheckUtils]: 10: Hoare triple {1838#(= (bvadd main_~i~0 (_ bv4294967292 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1842#(= (bvadd main_~i~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:08,768 INFO L273 TraceCheckUtils]: 11: Hoare triple {1842#(= (bvadd main_~i~0 (_ bv4294967291 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1846#(= (bvadd main_~i~0 (_ bv4294967290 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:08,768 INFO L273 TraceCheckUtils]: 12: Hoare triple {1846#(= (bvadd main_~i~0 (_ bv4294967290 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1850#(= (_ bv7 32) main_~i~0)} is VALID [2018-11-23 10:06:08,769 INFO L273 TraceCheckUtils]: 13: Hoare triple {1850#(= (_ bv7 32) main_~i~0)} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1854#(= (bvadd main_~i~0 (_ bv4294967288 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:08,770 INFO L273 TraceCheckUtils]: 14: Hoare triple {1854#(= (bvadd main_~i~0 (_ bv4294967288 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1858#(= (bvadd main_~i~0 (_ bv4294967287 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:08,772 INFO L273 TraceCheckUtils]: 15: Hoare triple {1858#(= (bvadd main_~i~0 (_ bv4294967287 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {1862#(= (bvadd main_~i~0 (_ bv4294967286 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:08,772 INFO L273 TraceCheckUtils]: 16: Hoare triple {1862#(= (bvadd main_~i~0 (_ bv4294967286 32)) (_ bv0 32))} assume !~bvslt32(~i~0, 100000bv32); {1803#false} is VALID [2018-11-23 10:06:08,773 INFO L273 TraceCheckUtils]: 17: Hoare triple {1803#false} ~i~0 := 0bv32; {1803#false} is VALID [2018-11-23 10:06:08,773 INFO L273 TraceCheckUtils]: 18: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:08,773 INFO L273 TraceCheckUtils]: 19: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:08,774 INFO L273 TraceCheckUtils]: 20: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:08,774 INFO L273 TraceCheckUtils]: 21: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:08,775 INFO L273 TraceCheckUtils]: 22: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:08,775 INFO L273 TraceCheckUtils]: 23: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:08,776 INFO L273 TraceCheckUtils]: 24: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:08,776 INFO L273 TraceCheckUtils]: 25: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:08,777 INFO L273 TraceCheckUtils]: 26: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:08,777 INFO L273 TraceCheckUtils]: 27: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:08,777 INFO L273 TraceCheckUtils]: 28: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:08,778 INFO L273 TraceCheckUtils]: 29: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:08,778 INFO L273 TraceCheckUtils]: 30: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:08,778 INFO L273 TraceCheckUtils]: 31: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:08,779 INFO L273 TraceCheckUtils]: 32: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:08,779 INFO L273 TraceCheckUtils]: 33: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:08,779 INFO L273 TraceCheckUtils]: 34: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:08,779 INFO L273 TraceCheckUtils]: 35: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:08,780 INFO L273 TraceCheckUtils]: 36: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:08,780 INFO L273 TraceCheckUtils]: 37: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:08,780 INFO L273 TraceCheckUtils]: 38: Hoare triple {1803#false} assume !~bvslt32(~i~0, 100000bv32); {1803#false} is VALID [2018-11-23 10:06:08,780 INFO L273 TraceCheckUtils]: 39: Hoare triple {1803#false} ~i~0 := 0bv32; {1803#false} is VALID [2018-11-23 10:06:08,781 INFO L273 TraceCheckUtils]: 40: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:08,781 INFO L273 TraceCheckUtils]: 41: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:08,781 INFO L273 TraceCheckUtils]: 42: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:08,781 INFO L273 TraceCheckUtils]: 43: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:08,782 INFO L273 TraceCheckUtils]: 44: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:08,782 INFO L273 TraceCheckUtils]: 45: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:08,782 INFO L273 TraceCheckUtils]: 46: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:08,783 INFO L273 TraceCheckUtils]: 47: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:08,783 INFO L273 TraceCheckUtils]: 48: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:08,783 INFO L273 TraceCheckUtils]: 49: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:08,783 INFO L273 TraceCheckUtils]: 50: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:08,784 INFO L273 TraceCheckUtils]: 51: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:08,784 INFO L273 TraceCheckUtils]: 52: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:08,784 INFO L273 TraceCheckUtils]: 53: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:08,784 INFO L273 TraceCheckUtils]: 54: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:08,785 INFO L273 TraceCheckUtils]: 55: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:08,785 INFO L273 TraceCheckUtils]: 56: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:08,785 INFO L273 TraceCheckUtils]: 57: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:08,786 INFO L273 TraceCheckUtils]: 58: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:08,786 INFO L273 TraceCheckUtils]: 59: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:08,786 INFO L273 TraceCheckUtils]: 60: Hoare triple {1803#false} assume !~bvslt32(~i~0, 100000bv32); {1803#false} is VALID [2018-11-23 10:06:08,786 INFO L273 TraceCheckUtils]: 61: Hoare triple {1803#false} ~i~0 := 0bv32; {1803#false} is VALID [2018-11-23 10:06:08,787 INFO L273 TraceCheckUtils]: 62: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:08,787 INFO L273 TraceCheckUtils]: 63: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:08,787 INFO L273 TraceCheckUtils]: 64: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:08,787 INFO L273 TraceCheckUtils]: 65: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:08,788 INFO L273 TraceCheckUtils]: 66: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:08,788 INFO L273 TraceCheckUtils]: 67: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:08,788 INFO L273 TraceCheckUtils]: 68: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:08,789 INFO L273 TraceCheckUtils]: 69: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:08,789 INFO L273 TraceCheckUtils]: 70: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:08,789 INFO L273 TraceCheckUtils]: 71: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:08,789 INFO L273 TraceCheckUtils]: 72: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:08,790 INFO L273 TraceCheckUtils]: 73: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:08,790 INFO L273 TraceCheckUtils]: 74: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:08,790 INFO L273 TraceCheckUtils]: 75: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:08,791 INFO L273 TraceCheckUtils]: 76: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:08,791 INFO L273 TraceCheckUtils]: 77: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:08,791 INFO L273 TraceCheckUtils]: 78: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:08,791 INFO L273 TraceCheckUtils]: 79: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:08,792 INFO L273 TraceCheckUtils]: 80: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:08,792 INFO L273 TraceCheckUtils]: 81: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:08,792 INFO L273 TraceCheckUtils]: 82: Hoare triple {1803#false} assume !~bvslt32(~i~0, 100000bv32); {1803#false} is VALID [2018-11-23 10:06:08,792 INFO L273 TraceCheckUtils]: 83: Hoare triple {1803#false} havoc ~x~0;~x~0 := 0bv32; {1803#false} is VALID [2018-11-23 10:06:08,793 INFO L273 TraceCheckUtils]: 84: Hoare triple {1803#false} assume !!~bvslt32(~x~0, 100000bv32);call #t~mem8 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {1803#false} is VALID [2018-11-23 10:06:08,793 INFO L256 TraceCheckUtils]: 85: Hoare triple {1803#false} call __VERIFIER_assert((if #t~mem8 == ~x~0 then 1bv32 else 0bv32)); {1803#false} is VALID [2018-11-23 10:06:08,793 INFO L273 TraceCheckUtils]: 86: Hoare triple {1803#false} ~cond := #in~cond; {1803#false} is VALID [2018-11-23 10:06:08,794 INFO L273 TraceCheckUtils]: 87: Hoare triple {1803#false} assume 0bv32 == ~cond; {1803#false} is VALID [2018-11-23 10:06:08,794 INFO L273 TraceCheckUtils]: 88: Hoare triple {1803#false} assume !false; {1803#false} is VALID [2018-11-23 10:06:08,805 INFO L134 CoverageAnalysis]: Checked inductivity of 355 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 300 trivial. 0 not checked. [2018-11-23 10:06:08,805 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:06:09,771 INFO L273 TraceCheckUtils]: 88: Hoare triple {1803#false} assume !false; {1803#false} is VALID [2018-11-23 10:06:09,772 INFO L273 TraceCheckUtils]: 87: Hoare triple {1803#false} assume 0bv32 == ~cond; {1803#false} is VALID [2018-11-23 10:06:09,772 INFO L273 TraceCheckUtils]: 86: Hoare triple {1803#false} ~cond := #in~cond; {1803#false} is VALID [2018-11-23 10:06:09,772 INFO L256 TraceCheckUtils]: 85: Hoare triple {1803#false} call __VERIFIER_assert((if #t~mem8 == ~x~0 then 1bv32 else 0bv32)); {1803#false} is VALID [2018-11-23 10:06:09,772 INFO L273 TraceCheckUtils]: 84: Hoare triple {1803#false} assume !!~bvslt32(~x~0, 100000bv32);call #t~mem8 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {1803#false} is VALID [2018-11-23 10:06:09,773 INFO L273 TraceCheckUtils]: 83: Hoare triple {1803#false} havoc ~x~0;~x~0 := 0bv32; {1803#false} is VALID [2018-11-23 10:06:09,773 INFO L273 TraceCheckUtils]: 82: Hoare triple {1803#false} assume !~bvslt32(~i~0, 100000bv32); {1803#false} is VALID [2018-11-23 10:06:09,773 INFO L273 TraceCheckUtils]: 81: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:09,774 INFO L273 TraceCheckUtils]: 80: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:09,774 INFO L273 TraceCheckUtils]: 79: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:09,774 INFO L273 TraceCheckUtils]: 78: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:09,774 INFO L273 TraceCheckUtils]: 77: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:09,775 INFO L273 TraceCheckUtils]: 76: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:09,775 INFO L273 TraceCheckUtils]: 75: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:09,775 INFO L273 TraceCheckUtils]: 74: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:09,775 INFO L273 TraceCheckUtils]: 73: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:09,776 INFO L273 TraceCheckUtils]: 72: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:09,776 INFO L273 TraceCheckUtils]: 71: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:09,776 INFO L273 TraceCheckUtils]: 70: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:09,776 INFO L273 TraceCheckUtils]: 69: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:09,777 INFO L273 TraceCheckUtils]: 68: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:09,777 INFO L273 TraceCheckUtils]: 67: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:09,777 INFO L273 TraceCheckUtils]: 66: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:09,777 INFO L273 TraceCheckUtils]: 65: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:09,777 INFO L273 TraceCheckUtils]: 64: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:09,778 INFO L273 TraceCheckUtils]: 63: Hoare triple {1803#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {1803#false} is VALID [2018-11-23 10:06:09,778 INFO L273 TraceCheckUtils]: 62: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {1803#false} is VALID [2018-11-23 10:06:09,778 INFO L273 TraceCheckUtils]: 61: Hoare triple {1803#false} ~i~0 := 0bv32; {1803#false} is VALID [2018-11-23 10:06:09,778 INFO L273 TraceCheckUtils]: 60: Hoare triple {1803#false} assume !~bvslt32(~i~0, 100000bv32); {1803#false} is VALID [2018-11-23 10:06:09,778 INFO L273 TraceCheckUtils]: 59: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:09,778 INFO L273 TraceCheckUtils]: 58: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:09,778 INFO L273 TraceCheckUtils]: 57: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:09,779 INFO L273 TraceCheckUtils]: 56: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:09,779 INFO L273 TraceCheckUtils]: 55: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:09,779 INFO L273 TraceCheckUtils]: 54: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:09,779 INFO L273 TraceCheckUtils]: 53: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:09,780 INFO L273 TraceCheckUtils]: 52: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:09,780 INFO L273 TraceCheckUtils]: 51: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:09,780 INFO L273 TraceCheckUtils]: 50: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:09,780 INFO L273 TraceCheckUtils]: 49: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:09,780 INFO L273 TraceCheckUtils]: 48: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:09,781 INFO L273 TraceCheckUtils]: 47: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:09,781 INFO L273 TraceCheckUtils]: 46: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:09,781 INFO L273 TraceCheckUtils]: 45: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:09,781 INFO L273 TraceCheckUtils]: 44: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:09,781 INFO L273 TraceCheckUtils]: 43: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:09,781 INFO L273 TraceCheckUtils]: 42: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:09,781 INFO L273 TraceCheckUtils]: 41: Hoare triple {1803#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1803#false} is VALID [2018-11-23 10:06:09,782 INFO L273 TraceCheckUtils]: 40: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {1803#false} is VALID [2018-11-23 10:06:09,782 INFO L273 TraceCheckUtils]: 39: Hoare triple {1803#false} ~i~0 := 0bv32; {1803#false} is VALID [2018-11-23 10:06:09,782 INFO L273 TraceCheckUtils]: 38: Hoare triple {1803#false} assume !~bvslt32(~i~0, 100000bv32); {1803#false} is VALID [2018-11-23 10:06:09,782 INFO L273 TraceCheckUtils]: 37: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:09,782 INFO L273 TraceCheckUtils]: 36: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:09,782 INFO L273 TraceCheckUtils]: 35: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:09,782 INFO L273 TraceCheckUtils]: 34: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:09,783 INFO L273 TraceCheckUtils]: 33: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:09,783 INFO L273 TraceCheckUtils]: 32: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:09,783 INFO L273 TraceCheckUtils]: 31: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:09,783 INFO L273 TraceCheckUtils]: 30: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:09,783 INFO L273 TraceCheckUtils]: 29: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:09,783 INFO L273 TraceCheckUtils]: 28: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:09,783 INFO L273 TraceCheckUtils]: 27: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:09,784 INFO L273 TraceCheckUtils]: 26: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:09,784 INFO L273 TraceCheckUtils]: 25: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:09,784 INFO L273 TraceCheckUtils]: 24: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:09,784 INFO L273 TraceCheckUtils]: 23: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:09,784 INFO L273 TraceCheckUtils]: 22: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:09,784 INFO L273 TraceCheckUtils]: 21: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:09,785 INFO L273 TraceCheckUtils]: 20: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:09,785 INFO L273 TraceCheckUtils]: 19: Hoare triple {1803#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {1803#false} is VALID [2018-11-23 10:06:09,785 INFO L273 TraceCheckUtils]: 18: Hoare triple {1803#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {1803#false} is VALID [2018-11-23 10:06:09,785 INFO L273 TraceCheckUtils]: 17: Hoare triple {1803#false} ~i~0 := 0bv32; {1803#false} is VALID [2018-11-23 10:06:09,785 INFO L273 TraceCheckUtils]: 16: Hoare triple {2298#(bvslt main_~i~0 (_ bv100000 32))} assume !~bvslt32(~i~0, 100000bv32); {1803#false} is VALID [2018-11-23 10:06:09,786 INFO L273 TraceCheckUtils]: 15: Hoare triple {2302#(bvslt (bvadd main_~i~0 (_ bv1 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {2298#(bvslt main_~i~0 (_ bv100000 32))} is VALID [2018-11-23 10:06:09,791 INFO L273 TraceCheckUtils]: 14: Hoare triple {2306#(bvslt (bvadd main_~i~0 (_ bv2 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {2302#(bvslt (bvadd main_~i~0 (_ bv1 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:09,795 INFO L273 TraceCheckUtils]: 13: Hoare triple {2310#(bvslt (bvadd main_~i~0 (_ bv3 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {2306#(bvslt (bvadd main_~i~0 (_ bv2 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:09,800 INFO L273 TraceCheckUtils]: 12: Hoare triple {2314#(bvslt (bvadd main_~i~0 (_ bv4 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {2310#(bvslt (bvadd main_~i~0 (_ bv3 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:09,804 INFO L273 TraceCheckUtils]: 11: Hoare triple {2318#(bvslt (bvadd main_~i~0 (_ bv5 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {2314#(bvslt (bvadd main_~i~0 (_ bv4 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:09,811 INFO L273 TraceCheckUtils]: 10: Hoare triple {2322#(bvslt (bvadd main_~i~0 (_ bv6 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {2318#(bvslt (bvadd main_~i~0 (_ bv5 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:09,816 INFO L273 TraceCheckUtils]: 9: Hoare triple {2326#(bvslt (bvadd main_~i~0 (_ bv7 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {2322#(bvslt (bvadd main_~i~0 (_ bv6 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:09,822 INFO L273 TraceCheckUtils]: 8: Hoare triple {2330#(bvslt (bvadd main_~i~0 (_ bv8 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {2326#(bvslt (bvadd main_~i~0 (_ bv7 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:09,825 INFO L273 TraceCheckUtils]: 7: Hoare triple {2334#(bvslt (bvadd main_~i~0 (_ bv9 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {2330#(bvslt (bvadd main_~i~0 (_ bv8 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:09,833 INFO L273 TraceCheckUtils]: 6: Hoare triple {2338#(bvslt (bvadd main_~i~0 (_ bv10 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {2334#(bvslt (bvadd main_~i~0 (_ bv9 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:09,834 INFO L273 TraceCheckUtils]: 5: Hoare triple {1802#true} call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(400000bv32);call ~#b~0.base, ~#b~0.offset := #Ultimate.alloc(400000bv32);~i~0 := 0bv32; {2338#(bvslt (bvadd main_~i~0 (_ bv10 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:09,835 INFO L256 TraceCheckUtils]: 4: Hoare triple {1802#true} call #t~ret9 := main(); {1802#true} is VALID [2018-11-23 10:06:09,835 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1802#true} {1802#true} #90#return; {1802#true} is VALID [2018-11-23 10:06:09,835 INFO L273 TraceCheckUtils]: 2: Hoare triple {1802#true} assume true; {1802#true} is VALID [2018-11-23 10:06:09,835 INFO L273 TraceCheckUtils]: 1: Hoare triple {1802#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {1802#true} is VALID [2018-11-23 10:06:09,836 INFO L256 TraceCheckUtils]: 0: Hoare triple {1802#true} call ULTIMATE.init(); {1802#true} is VALID [2018-11-23 10:06:09,842 INFO L134 CoverageAnalysis]: Checked inductivity of 355 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 300 trivial. 0 not checked. [2018-11-23 10:06:09,847 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:06:09,847 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 24 [2018-11-23 10:06:09,848 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 89 [2018-11-23 10:06:09,848 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:06:09,848 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 24 states. [2018-11-23 10:06:09,933 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 47 edges. 47 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:06:09,933 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-23 10:06:09,933 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-23 10:06:09,934 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-11-23 10:06:09,934 INFO L87 Difference]: Start difference. First operand 94 states and 98 transitions. Second operand 24 states. [2018-11-23 10:06:19,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:19,928 INFO L93 Difference]: Finished difference Result 255 states and 310 transitions. [2018-11-23 10:06:19,928 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-23 10:06:19,928 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 89 [2018-11-23 10:06:19,928 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:06:19,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-11-23 10:06:19,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 253 transitions. [2018-11-23 10:06:19,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-11-23 10:06:19,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 253 transitions. [2018-11-23 10:06:19,939 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 24 states and 253 transitions. [2018-11-23 10:06:20,744 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 253 edges. 253 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:06:20,749 INFO L225 Difference]: With dead ends: 255 [2018-11-23 10:06:20,749 INFO L226 Difference]: Without dead ends: 178 [2018-11-23 10:06:20,751 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 187 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=406, Invalid=716, Unknown=0, NotChecked=0, Total=1122 [2018-11-23 10:06:20,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states. [2018-11-23 10:06:20,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2018-11-23 10:06:20,885 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:06:20,885 INFO L82 GeneralOperation]: Start isEquivalent. First operand 178 states. Second operand 178 states. [2018-11-23 10:06:20,885 INFO L74 IsIncluded]: Start isIncluded. First operand 178 states. Second operand 178 states. [2018-11-23 10:06:20,886 INFO L87 Difference]: Start difference. First operand 178 states. Second operand 178 states. [2018-11-23 10:06:20,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:20,893 INFO L93 Difference]: Finished difference Result 178 states and 182 transitions. [2018-11-23 10:06:20,893 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 182 transitions. [2018-11-23 10:06:20,894 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:06:20,894 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:06:20,895 INFO L74 IsIncluded]: Start isIncluded. First operand 178 states. Second operand 178 states. [2018-11-23 10:06:20,895 INFO L87 Difference]: Start difference. First operand 178 states. Second operand 178 states. [2018-11-23 10:06:20,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:06:20,902 INFO L93 Difference]: Finished difference Result 178 states and 182 transitions. [2018-11-23 10:06:20,902 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 182 transitions. [2018-11-23 10:06:20,903 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:06:20,903 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:06:20,903 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:06:20,903 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:06:20,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178 states. [2018-11-23 10:06:20,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 182 transitions. [2018-11-23 10:06:20,910 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 182 transitions. Word has length 89 [2018-11-23 10:06:20,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:06:20,911 INFO L480 AbstractCegarLoop]: Abstraction has 178 states and 182 transitions. [2018-11-23 10:06:20,911 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-23 10:06:20,911 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 182 transitions. [2018-11-23 10:06:20,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2018-11-23 10:06:20,917 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:06:20,917 INFO L402 BasicCegarLoop]: trace histogram [22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:06:20,917 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:06:20,918 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:06:20,918 INFO L82 PathProgramCache]: Analyzing trace with hash 28063018, now seen corresponding path program 4 times [2018-11-23 10:06:20,919 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:06:20,919 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:06:20,943 INFO L101 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 10:06:21,250 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 10:06:21,250 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:06:21,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:06:21,382 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:06:22,320 INFO L256 TraceCheckUtils]: 0: Hoare triple {3402#true} call ULTIMATE.init(); {3402#true} is VALID [2018-11-23 10:06:22,321 INFO L273 TraceCheckUtils]: 1: Hoare triple {3402#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {3402#true} is VALID [2018-11-23 10:06:22,321 INFO L273 TraceCheckUtils]: 2: Hoare triple {3402#true} assume true; {3402#true} is VALID [2018-11-23 10:06:22,321 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3402#true} {3402#true} #90#return; {3402#true} is VALID [2018-11-23 10:06:22,321 INFO L256 TraceCheckUtils]: 4: Hoare triple {3402#true} call #t~ret9 := main(); {3402#true} is VALID [2018-11-23 10:06:22,322 INFO L273 TraceCheckUtils]: 5: Hoare triple {3402#true} call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(400000bv32);call ~#b~0.base, ~#b~0.offset := #Ultimate.alloc(400000bv32);~i~0 := 0bv32; {3422#(= main_~i~0 (_ bv0 32))} is VALID [2018-11-23 10:06:22,323 INFO L273 TraceCheckUtils]: 6: Hoare triple {3422#(= main_~i~0 (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3426#(= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,323 INFO L273 TraceCheckUtils]: 7: Hoare triple {3426#(= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3430#(= (_ bv2 32) main_~i~0)} is VALID [2018-11-23 10:06:22,324 INFO L273 TraceCheckUtils]: 8: Hoare triple {3430#(= (_ bv2 32) main_~i~0)} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3434#(= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,324 INFO L273 TraceCheckUtils]: 9: Hoare triple {3434#(= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3438#(= (bvadd main_~i~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,325 INFO L273 TraceCheckUtils]: 10: Hoare triple {3438#(= (bvadd main_~i~0 (_ bv4294967292 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3442#(= (bvadd main_~i~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,326 INFO L273 TraceCheckUtils]: 11: Hoare triple {3442#(= (bvadd main_~i~0 (_ bv4294967291 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3446#(= (_ bv6 32) main_~i~0)} is VALID [2018-11-23 10:06:22,327 INFO L273 TraceCheckUtils]: 12: Hoare triple {3446#(= (_ bv6 32) main_~i~0)} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3450#(= (bvadd main_~i~0 (_ bv4294967289 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,329 INFO L273 TraceCheckUtils]: 13: Hoare triple {3450#(= (bvadd main_~i~0 (_ bv4294967289 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3454#(= (_ bv8 32) main_~i~0)} is VALID [2018-11-23 10:06:22,330 INFO L273 TraceCheckUtils]: 14: Hoare triple {3454#(= (_ bv8 32) main_~i~0)} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3458#(= (bvadd main_~i~0 (_ bv4294967287 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,330 INFO L273 TraceCheckUtils]: 15: Hoare triple {3458#(= (bvadd main_~i~0 (_ bv4294967287 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3462#(= (_ bv10 32) main_~i~0)} is VALID [2018-11-23 10:06:22,331 INFO L273 TraceCheckUtils]: 16: Hoare triple {3462#(= (_ bv10 32) main_~i~0)} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3466#(= (bvadd main_~i~0 (_ bv4294967285 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,332 INFO L273 TraceCheckUtils]: 17: Hoare triple {3466#(= (bvadd main_~i~0 (_ bv4294967285 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3470#(= (bvadd main_~i~0 (_ bv4294967284 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,333 INFO L273 TraceCheckUtils]: 18: Hoare triple {3470#(= (bvadd main_~i~0 (_ bv4294967284 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3474#(= (bvadd main_~i~0 (_ bv4294967283 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,335 INFO L273 TraceCheckUtils]: 19: Hoare triple {3474#(= (bvadd main_~i~0 (_ bv4294967283 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3478#(= (_ bv14 32) main_~i~0)} is VALID [2018-11-23 10:06:22,338 INFO L273 TraceCheckUtils]: 20: Hoare triple {3478#(= (_ bv14 32) main_~i~0)} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3482#(= (bvadd main_~i~0 (_ bv4294967281 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,342 INFO L273 TraceCheckUtils]: 21: Hoare triple {3482#(= (bvadd main_~i~0 (_ bv4294967281 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3486#(= (bvadd main_~i~0 (_ bv4294967280 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,345 INFO L273 TraceCheckUtils]: 22: Hoare triple {3486#(= (bvadd main_~i~0 (_ bv4294967280 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3490#(= (bvadd main_~i~0 (_ bv4294967279 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,346 INFO L273 TraceCheckUtils]: 23: Hoare triple {3490#(= (bvadd main_~i~0 (_ bv4294967279 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3494#(= (bvadd main_~i~0 (_ bv4294967278 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,346 INFO L273 TraceCheckUtils]: 24: Hoare triple {3494#(= (bvadd main_~i~0 (_ bv4294967278 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3498#(= (_ bv19 32) main_~i~0)} is VALID [2018-11-23 10:06:22,347 INFO L273 TraceCheckUtils]: 25: Hoare triple {3498#(= (_ bv19 32) main_~i~0)} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3502#(= (bvadd main_~i~0 (_ bv4294967276 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,347 INFO L273 TraceCheckUtils]: 26: Hoare triple {3502#(= (bvadd main_~i~0 (_ bv4294967276 32)) (_ bv0 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3506#(= (_ bv21 32) main_~i~0)} is VALID [2018-11-23 10:06:22,348 INFO L273 TraceCheckUtils]: 27: Hoare triple {3506#(= (_ bv21 32) main_~i~0)} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {3510#(= (bvadd main_~i~0 (_ bv4294967274 32)) (_ bv0 32))} is VALID [2018-11-23 10:06:22,348 INFO L273 TraceCheckUtils]: 28: Hoare triple {3510#(= (bvadd main_~i~0 (_ bv4294967274 32)) (_ bv0 32))} assume !~bvslt32(~i~0, 100000bv32); {3403#false} is VALID [2018-11-23 10:06:22,348 INFO L273 TraceCheckUtils]: 29: Hoare triple {3403#false} ~i~0 := 0bv32; {3403#false} is VALID [2018-11-23 10:06:22,348 INFO L273 TraceCheckUtils]: 30: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,349 INFO L273 TraceCheckUtils]: 31: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,349 INFO L273 TraceCheckUtils]: 32: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,349 INFO L273 TraceCheckUtils]: 33: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,349 INFO L273 TraceCheckUtils]: 34: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,350 INFO L273 TraceCheckUtils]: 35: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,350 INFO L273 TraceCheckUtils]: 36: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,350 INFO L273 TraceCheckUtils]: 37: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,351 INFO L273 TraceCheckUtils]: 38: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,351 INFO L273 TraceCheckUtils]: 39: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,351 INFO L273 TraceCheckUtils]: 40: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,352 INFO L273 TraceCheckUtils]: 41: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,352 INFO L273 TraceCheckUtils]: 42: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,352 INFO L273 TraceCheckUtils]: 43: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,352 INFO L273 TraceCheckUtils]: 44: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,352 INFO L273 TraceCheckUtils]: 45: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,352 INFO L273 TraceCheckUtils]: 46: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,352 INFO L273 TraceCheckUtils]: 47: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,353 INFO L273 TraceCheckUtils]: 48: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,353 INFO L273 TraceCheckUtils]: 49: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,353 INFO L273 TraceCheckUtils]: 50: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,353 INFO L273 TraceCheckUtils]: 51: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,353 INFO L273 TraceCheckUtils]: 52: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,353 INFO L273 TraceCheckUtils]: 53: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,353 INFO L273 TraceCheckUtils]: 54: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,354 INFO L273 TraceCheckUtils]: 55: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,354 INFO L273 TraceCheckUtils]: 56: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,354 INFO L273 TraceCheckUtils]: 57: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,354 INFO L273 TraceCheckUtils]: 58: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,354 INFO L273 TraceCheckUtils]: 59: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,354 INFO L273 TraceCheckUtils]: 60: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,354 INFO L273 TraceCheckUtils]: 61: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,354 INFO L273 TraceCheckUtils]: 62: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,355 INFO L273 TraceCheckUtils]: 63: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,355 INFO L273 TraceCheckUtils]: 64: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,355 INFO L273 TraceCheckUtils]: 65: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,355 INFO L273 TraceCheckUtils]: 66: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,355 INFO L273 TraceCheckUtils]: 67: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,355 INFO L273 TraceCheckUtils]: 68: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,355 INFO L273 TraceCheckUtils]: 69: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,356 INFO L273 TraceCheckUtils]: 70: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,356 INFO L273 TraceCheckUtils]: 71: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,356 INFO L273 TraceCheckUtils]: 72: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:22,356 INFO L273 TraceCheckUtils]: 73: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:22,356 INFO L273 TraceCheckUtils]: 74: Hoare triple {3403#false} assume !~bvslt32(~i~0, 100000bv32); {3403#false} is VALID [2018-11-23 10:06:22,356 INFO L273 TraceCheckUtils]: 75: Hoare triple {3403#false} ~i~0 := 0bv32; {3403#false} is VALID [2018-11-23 10:06:22,356 INFO L273 TraceCheckUtils]: 76: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,357 INFO L273 TraceCheckUtils]: 77: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,357 INFO L273 TraceCheckUtils]: 78: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,357 INFO L273 TraceCheckUtils]: 79: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,357 INFO L273 TraceCheckUtils]: 80: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,357 INFO L273 TraceCheckUtils]: 81: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,357 INFO L273 TraceCheckUtils]: 82: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,357 INFO L273 TraceCheckUtils]: 83: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,358 INFO L273 TraceCheckUtils]: 84: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,358 INFO L273 TraceCheckUtils]: 85: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,358 INFO L273 TraceCheckUtils]: 86: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,358 INFO L273 TraceCheckUtils]: 87: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,358 INFO L273 TraceCheckUtils]: 88: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,358 INFO L273 TraceCheckUtils]: 89: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,358 INFO L273 TraceCheckUtils]: 90: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,358 INFO L273 TraceCheckUtils]: 91: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,359 INFO L273 TraceCheckUtils]: 92: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,359 INFO L273 TraceCheckUtils]: 93: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,359 INFO L273 TraceCheckUtils]: 94: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,359 INFO L273 TraceCheckUtils]: 95: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,359 INFO L273 TraceCheckUtils]: 96: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,359 INFO L273 TraceCheckUtils]: 97: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,359 INFO L273 TraceCheckUtils]: 98: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,360 INFO L273 TraceCheckUtils]: 99: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,360 INFO L273 TraceCheckUtils]: 100: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,360 INFO L273 TraceCheckUtils]: 101: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,360 INFO L273 TraceCheckUtils]: 102: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,360 INFO L273 TraceCheckUtils]: 103: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,360 INFO L273 TraceCheckUtils]: 104: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,360 INFO L273 TraceCheckUtils]: 105: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,360 INFO L273 TraceCheckUtils]: 106: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,361 INFO L273 TraceCheckUtils]: 107: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,361 INFO L273 TraceCheckUtils]: 108: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,361 INFO L273 TraceCheckUtils]: 109: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,361 INFO L273 TraceCheckUtils]: 110: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,361 INFO L273 TraceCheckUtils]: 111: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,361 INFO L273 TraceCheckUtils]: 112: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,361 INFO L273 TraceCheckUtils]: 113: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,362 INFO L273 TraceCheckUtils]: 114: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,362 INFO L273 TraceCheckUtils]: 115: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,362 INFO L273 TraceCheckUtils]: 116: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,362 INFO L273 TraceCheckUtils]: 117: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,362 INFO L273 TraceCheckUtils]: 118: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:22,362 INFO L273 TraceCheckUtils]: 119: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:22,362 INFO L273 TraceCheckUtils]: 120: Hoare triple {3403#false} assume !~bvslt32(~i~0, 100000bv32); {3403#false} is VALID [2018-11-23 10:06:22,362 INFO L273 TraceCheckUtils]: 121: Hoare triple {3403#false} ~i~0 := 0bv32; {3403#false} is VALID [2018-11-23 10:06:22,363 INFO L273 TraceCheckUtils]: 122: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,363 INFO L273 TraceCheckUtils]: 123: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,363 INFO L273 TraceCheckUtils]: 124: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,363 INFO L273 TraceCheckUtils]: 125: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,363 INFO L273 TraceCheckUtils]: 126: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,363 INFO L273 TraceCheckUtils]: 127: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,364 INFO L273 TraceCheckUtils]: 128: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,364 INFO L273 TraceCheckUtils]: 129: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,364 INFO L273 TraceCheckUtils]: 130: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,364 INFO L273 TraceCheckUtils]: 131: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,364 INFO L273 TraceCheckUtils]: 132: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,365 INFO L273 TraceCheckUtils]: 133: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,365 INFO L273 TraceCheckUtils]: 134: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,365 INFO L273 TraceCheckUtils]: 135: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,365 INFO L273 TraceCheckUtils]: 136: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,365 INFO L273 TraceCheckUtils]: 137: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,365 INFO L273 TraceCheckUtils]: 138: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,365 INFO L273 TraceCheckUtils]: 139: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,365 INFO L273 TraceCheckUtils]: 140: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,366 INFO L273 TraceCheckUtils]: 141: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,366 INFO L273 TraceCheckUtils]: 142: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,366 INFO L273 TraceCheckUtils]: 143: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,366 INFO L273 TraceCheckUtils]: 144: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,366 INFO L273 TraceCheckUtils]: 145: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,366 INFO L273 TraceCheckUtils]: 146: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,366 INFO L273 TraceCheckUtils]: 147: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,367 INFO L273 TraceCheckUtils]: 148: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,367 INFO L273 TraceCheckUtils]: 149: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,367 INFO L273 TraceCheckUtils]: 150: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,367 INFO L273 TraceCheckUtils]: 151: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,367 INFO L273 TraceCheckUtils]: 152: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,368 INFO L273 TraceCheckUtils]: 153: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,368 INFO L273 TraceCheckUtils]: 154: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,368 INFO L273 TraceCheckUtils]: 155: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,368 INFO L273 TraceCheckUtils]: 156: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,368 INFO L273 TraceCheckUtils]: 157: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,369 INFO L273 TraceCheckUtils]: 158: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,369 INFO L273 TraceCheckUtils]: 159: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,369 INFO L273 TraceCheckUtils]: 160: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,369 INFO L273 TraceCheckUtils]: 161: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,369 INFO L273 TraceCheckUtils]: 162: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,370 INFO L273 TraceCheckUtils]: 163: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,370 INFO L273 TraceCheckUtils]: 164: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:22,370 INFO L273 TraceCheckUtils]: 165: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:22,370 INFO L273 TraceCheckUtils]: 166: Hoare triple {3403#false} assume !~bvslt32(~i~0, 100000bv32); {3403#false} is VALID [2018-11-23 10:06:22,370 INFO L273 TraceCheckUtils]: 167: Hoare triple {3403#false} havoc ~x~0;~x~0 := 0bv32; {3403#false} is VALID [2018-11-23 10:06:22,370 INFO L273 TraceCheckUtils]: 168: Hoare triple {3403#false} assume !!~bvslt32(~x~0, 100000bv32);call #t~mem8 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {3403#false} is VALID [2018-11-23 10:06:22,371 INFO L256 TraceCheckUtils]: 169: Hoare triple {3403#false} call __VERIFIER_assert((if #t~mem8 == ~x~0 then 1bv32 else 0bv32)); {3403#false} is VALID [2018-11-23 10:06:22,371 INFO L273 TraceCheckUtils]: 170: Hoare triple {3403#false} ~cond := #in~cond; {3403#false} is VALID [2018-11-23 10:06:22,371 INFO L273 TraceCheckUtils]: 171: Hoare triple {3403#false} assume 0bv32 == ~cond; {3403#false} is VALID [2018-11-23 10:06:22,371 INFO L273 TraceCheckUtils]: 172: Hoare triple {3403#false} assume !false; {3403#false} is VALID [2018-11-23 10:06:22,389 INFO L134 CoverageAnalysis]: Checked inductivity of 1705 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 1452 trivial. 0 not checked. [2018-11-23 10:06:22,389 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:06:24,163 INFO L273 TraceCheckUtils]: 172: Hoare triple {3403#false} assume !false; {3403#false} is VALID [2018-11-23 10:06:24,163 INFO L273 TraceCheckUtils]: 171: Hoare triple {3403#false} assume 0bv32 == ~cond; {3403#false} is VALID [2018-11-23 10:06:24,164 INFO L273 TraceCheckUtils]: 170: Hoare triple {3403#false} ~cond := #in~cond; {3403#false} is VALID [2018-11-23 10:06:24,164 INFO L256 TraceCheckUtils]: 169: Hoare triple {3403#false} call __VERIFIER_assert((if #t~mem8 == ~x~0 then 1bv32 else 0bv32)); {3403#false} is VALID [2018-11-23 10:06:24,164 INFO L273 TraceCheckUtils]: 168: Hoare triple {3403#false} assume !!~bvslt32(~x~0, 100000bv32);call #t~mem8 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {3403#false} is VALID [2018-11-23 10:06:24,164 INFO L273 TraceCheckUtils]: 167: Hoare triple {3403#false} havoc ~x~0;~x~0 := 0bv32; {3403#false} is VALID [2018-11-23 10:06:24,164 INFO L273 TraceCheckUtils]: 166: Hoare triple {3403#false} assume !~bvslt32(~i~0, 100000bv32); {3403#false} is VALID [2018-11-23 10:06:24,165 INFO L273 TraceCheckUtils]: 165: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,165 INFO L273 TraceCheckUtils]: 164: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,165 INFO L273 TraceCheckUtils]: 163: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,165 INFO L273 TraceCheckUtils]: 162: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,165 INFO L273 TraceCheckUtils]: 161: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,165 INFO L273 TraceCheckUtils]: 160: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,166 INFO L273 TraceCheckUtils]: 159: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,166 INFO L273 TraceCheckUtils]: 158: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,166 INFO L273 TraceCheckUtils]: 157: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,166 INFO L273 TraceCheckUtils]: 156: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,166 INFO L273 TraceCheckUtils]: 155: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,166 INFO L273 TraceCheckUtils]: 154: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,166 INFO L273 TraceCheckUtils]: 153: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,167 INFO L273 TraceCheckUtils]: 152: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,167 INFO L273 TraceCheckUtils]: 151: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,167 INFO L273 TraceCheckUtils]: 150: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,167 INFO L273 TraceCheckUtils]: 149: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,167 INFO L273 TraceCheckUtils]: 148: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,167 INFO L273 TraceCheckUtils]: 147: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,168 INFO L273 TraceCheckUtils]: 146: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,168 INFO L273 TraceCheckUtils]: 145: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,168 INFO L273 TraceCheckUtils]: 144: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,168 INFO L273 TraceCheckUtils]: 143: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,168 INFO L273 TraceCheckUtils]: 142: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,168 INFO L273 TraceCheckUtils]: 141: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,169 INFO L273 TraceCheckUtils]: 140: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,169 INFO L273 TraceCheckUtils]: 139: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,169 INFO L273 TraceCheckUtils]: 138: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,169 INFO L273 TraceCheckUtils]: 137: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,169 INFO L273 TraceCheckUtils]: 136: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,169 INFO L273 TraceCheckUtils]: 135: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,170 INFO L273 TraceCheckUtils]: 134: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,170 INFO L273 TraceCheckUtils]: 133: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,170 INFO L273 TraceCheckUtils]: 132: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,170 INFO L273 TraceCheckUtils]: 131: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,170 INFO L273 TraceCheckUtils]: 130: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,170 INFO L273 TraceCheckUtils]: 129: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,171 INFO L273 TraceCheckUtils]: 128: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,171 INFO L273 TraceCheckUtils]: 127: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,171 INFO L273 TraceCheckUtils]: 126: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,171 INFO L273 TraceCheckUtils]: 125: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,171 INFO L273 TraceCheckUtils]: 124: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,171 INFO L273 TraceCheckUtils]: 123: Hoare triple {3403#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3403#false} is VALID [2018-11-23 10:06:24,171 INFO L273 TraceCheckUtils]: 122: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem5 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call #t~mem6 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvsub32(#t~mem5, #t~mem6), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem6;havoc #t~mem5; {3403#false} is VALID [2018-11-23 10:06:24,172 INFO L273 TraceCheckUtils]: 121: Hoare triple {3403#false} ~i~0 := 0bv32; {3403#false} is VALID [2018-11-23 10:06:24,172 INFO L273 TraceCheckUtils]: 120: Hoare triple {3403#false} assume !~bvslt32(~i~0, 100000bv32); {3403#false} is VALID [2018-11-23 10:06:24,172 INFO L273 TraceCheckUtils]: 119: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,172 INFO L273 TraceCheckUtils]: 118: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,172 INFO L273 TraceCheckUtils]: 117: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,172 INFO L273 TraceCheckUtils]: 116: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,172 INFO L273 TraceCheckUtils]: 115: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,172 INFO L273 TraceCheckUtils]: 114: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,173 INFO L273 TraceCheckUtils]: 113: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,173 INFO L273 TraceCheckUtils]: 112: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,173 INFO L273 TraceCheckUtils]: 111: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,173 INFO L273 TraceCheckUtils]: 110: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,173 INFO L273 TraceCheckUtils]: 109: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,173 INFO L273 TraceCheckUtils]: 108: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,173 INFO L273 TraceCheckUtils]: 107: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,174 INFO L273 TraceCheckUtils]: 106: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,174 INFO L273 TraceCheckUtils]: 105: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,174 INFO L273 TraceCheckUtils]: 104: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,174 INFO L273 TraceCheckUtils]: 103: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,174 INFO L273 TraceCheckUtils]: 102: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,175 INFO L273 TraceCheckUtils]: 101: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,175 INFO L273 TraceCheckUtils]: 100: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,175 INFO L273 TraceCheckUtils]: 99: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,175 INFO L273 TraceCheckUtils]: 98: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,175 INFO L273 TraceCheckUtils]: 97: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,175 INFO L273 TraceCheckUtils]: 96: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,176 INFO L273 TraceCheckUtils]: 95: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,176 INFO L273 TraceCheckUtils]: 94: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,176 INFO L273 TraceCheckUtils]: 93: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,176 INFO L273 TraceCheckUtils]: 92: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,176 INFO L273 TraceCheckUtils]: 91: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,177 INFO L273 TraceCheckUtils]: 90: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,177 INFO L273 TraceCheckUtils]: 89: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,177 INFO L273 TraceCheckUtils]: 88: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,177 INFO L273 TraceCheckUtils]: 87: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,177 INFO L273 TraceCheckUtils]: 86: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,177 INFO L273 TraceCheckUtils]: 85: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,178 INFO L273 TraceCheckUtils]: 84: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,178 INFO L273 TraceCheckUtils]: 83: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,178 INFO L273 TraceCheckUtils]: 82: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,178 INFO L273 TraceCheckUtils]: 81: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,178 INFO L273 TraceCheckUtils]: 80: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,179 INFO L273 TraceCheckUtils]: 79: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,179 INFO L273 TraceCheckUtils]: 78: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,179 INFO L273 TraceCheckUtils]: 77: Hoare triple {3403#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3403#false} is VALID [2018-11-23 10:06:24,179 INFO L273 TraceCheckUtils]: 76: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem3 := read~intINTTYPE4(~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(~bvadd32(#t~mem3, ~i~0), ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem3; {3403#false} is VALID [2018-11-23 10:06:24,179 INFO L273 TraceCheckUtils]: 75: Hoare triple {3403#false} ~i~0 := 0bv32; {3403#false} is VALID [2018-11-23 10:06:24,179 INFO L273 TraceCheckUtils]: 74: Hoare triple {3403#false} assume !~bvslt32(~i~0, 100000bv32); {3403#false} is VALID [2018-11-23 10:06:24,180 INFO L273 TraceCheckUtils]: 73: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,180 INFO L273 TraceCheckUtils]: 72: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,180 INFO L273 TraceCheckUtils]: 71: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,180 INFO L273 TraceCheckUtils]: 70: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,180 INFO L273 TraceCheckUtils]: 69: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,180 INFO L273 TraceCheckUtils]: 68: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,181 INFO L273 TraceCheckUtils]: 67: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,181 INFO L273 TraceCheckUtils]: 66: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,181 INFO L273 TraceCheckUtils]: 65: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,181 INFO L273 TraceCheckUtils]: 64: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,181 INFO L273 TraceCheckUtils]: 63: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,181 INFO L273 TraceCheckUtils]: 62: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,182 INFO L273 TraceCheckUtils]: 61: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,182 INFO L273 TraceCheckUtils]: 60: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,182 INFO L273 TraceCheckUtils]: 59: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,182 INFO L273 TraceCheckUtils]: 58: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,182 INFO L273 TraceCheckUtils]: 57: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,182 INFO L273 TraceCheckUtils]: 56: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,183 INFO L273 TraceCheckUtils]: 55: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,183 INFO L273 TraceCheckUtils]: 54: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,183 INFO L273 TraceCheckUtils]: 53: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,183 INFO L273 TraceCheckUtils]: 52: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,183 INFO L273 TraceCheckUtils]: 51: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,183 INFO L273 TraceCheckUtils]: 50: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,184 INFO L273 TraceCheckUtils]: 49: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,184 INFO L273 TraceCheckUtils]: 48: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,184 INFO L273 TraceCheckUtils]: 47: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,184 INFO L273 TraceCheckUtils]: 46: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,184 INFO L273 TraceCheckUtils]: 45: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,185 INFO L273 TraceCheckUtils]: 44: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,185 INFO L273 TraceCheckUtils]: 43: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,185 INFO L273 TraceCheckUtils]: 42: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,185 INFO L273 TraceCheckUtils]: 41: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,185 INFO L273 TraceCheckUtils]: 40: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,185 INFO L273 TraceCheckUtils]: 39: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,186 INFO L273 TraceCheckUtils]: 38: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,186 INFO L273 TraceCheckUtils]: 37: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,186 INFO L273 TraceCheckUtils]: 36: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,186 INFO L273 TraceCheckUtils]: 35: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,186 INFO L273 TraceCheckUtils]: 34: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,186 INFO L273 TraceCheckUtils]: 33: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,187 INFO L273 TraceCheckUtils]: 32: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,187 INFO L273 TraceCheckUtils]: 31: Hoare triple {3403#false} #t~post0 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post0);havoc #t~post0; {3403#false} is VALID [2018-11-23 10:06:24,187 INFO L273 TraceCheckUtils]: 30: Hoare triple {3403#false} assume !!~bvslt32(~i~0, 100000bv32);call #t~mem1 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#b~0.base, ~bvadd32(~#b~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);havoc #t~mem1; {3403#false} is VALID [2018-11-23 10:06:24,187 INFO L273 TraceCheckUtils]: 29: Hoare triple {3403#false} ~i~0 := 0bv32; {3403#false} is VALID [2018-11-23 10:06:24,211 INFO L273 TraceCheckUtils]: 28: Hoare triple {4378#(bvslt main_~i~0 (_ bv100000 32))} assume !~bvslt32(~i~0, 100000bv32); {3403#false} is VALID [2018-11-23 10:06:24,225 INFO L273 TraceCheckUtils]: 27: Hoare triple {4382#(bvslt (bvadd main_~i~0 (_ bv1 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4378#(bvslt main_~i~0 (_ bv100000 32))} is VALID [2018-11-23 10:06:24,233 INFO L273 TraceCheckUtils]: 26: Hoare triple {4386#(bvslt (bvadd main_~i~0 (_ bv2 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4382#(bvslt (bvadd main_~i~0 (_ bv1 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,238 INFO L273 TraceCheckUtils]: 25: Hoare triple {4390#(bvslt (bvadd main_~i~0 (_ bv3 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4386#(bvslt (bvadd main_~i~0 (_ bv2 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,243 INFO L273 TraceCheckUtils]: 24: Hoare triple {4394#(bvslt (bvadd main_~i~0 (_ bv4 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4390#(bvslt (bvadd main_~i~0 (_ bv3 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,247 INFO L273 TraceCheckUtils]: 23: Hoare triple {4398#(bvslt (bvadd main_~i~0 (_ bv5 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4394#(bvslt (bvadd main_~i~0 (_ bv4 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,254 INFO L273 TraceCheckUtils]: 22: Hoare triple {4402#(bvslt (bvadd main_~i~0 (_ bv6 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4398#(bvslt (bvadd main_~i~0 (_ bv5 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,259 INFO L273 TraceCheckUtils]: 21: Hoare triple {4406#(bvslt (bvadd main_~i~0 (_ bv7 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4402#(bvslt (bvadd main_~i~0 (_ bv6 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,266 INFO L273 TraceCheckUtils]: 20: Hoare triple {4410#(bvslt (bvadd main_~i~0 (_ bv8 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4406#(bvslt (bvadd main_~i~0 (_ bv7 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,270 INFO L273 TraceCheckUtils]: 19: Hoare triple {4414#(bvslt (bvadd main_~i~0 (_ bv9 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4410#(bvslt (bvadd main_~i~0 (_ bv8 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,276 INFO L273 TraceCheckUtils]: 18: Hoare triple {4418#(bvslt (bvadd main_~i~0 (_ bv10 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4414#(bvslt (bvadd main_~i~0 (_ bv9 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,283 INFO L273 TraceCheckUtils]: 17: Hoare triple {4422#(bvslt (bvadd main_~i~0 (_ bv11 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4418#(bvslt (bvadd main_~i~0 (_ bv10 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,287 INFO L273 TraceCheckUtils]: 16: Hoare triple {4426#(bvslt (bvadd main_~i~0 (_ bv12 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4422#(bvslt (bvadd main_~i~0 (_ bv11 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,296 INFO L273 TraceCheckUtils]: 15: Hoare triple {4430#(bvslt (bvadd main_~i~0 (_ bv13 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4426#(bvslt (bvadd main_~i~0 (_ bv12 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,300 INFO L273 TraceCheckUtils]: 14: Hoare triple {4434#(bvslt (bvadd main_~i~0 (_ bv14 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4430#(bvslt (bvadd main_~i~0 (_ bv13 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,307 INFO L273 TraceCheckUtils]: 13: Hoare triple {4438#(bvslt (bvadd main_~i~0 (_ bv15 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4434#(bvslt (bvadd main_~i~0 (_ bv14 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,312 INFO L273 TraceCheckUtils]: 12: Hoare triple {4442#(bvslt (bvadd main_~i~0 (_ bv16 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4438#(bvslt (bvadd main_~i~0 (_ bv15 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,317 INFO L273 TraceCheckUtils]: 11: Hoare triple {4446#(bvslt (bvadd main_~i~0 (_ bv17 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4442#(bvslt (bvadd main_~i~0 (_ bv16 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,323 INFO L273 TraceCheckUtils]: 10: Hoare triple {4450#(bvslt (bvadd main_~i~0 (_ bv18 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4446#(bvslt (bvadd main_~i~0 (_ bv17 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,326 INFO L273 TraceCheckUtils]: 9: Hoare triple {4454#(bvslt (bvadd main_~i~0 (_ bv19 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4450#(bvslt (bvadd main_~i~0 (_ bv18 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,330 INFO L273 TraceCheckUtils]: 8: Hoare triple {4458#(bvslt (bvadd main_~i~0 (_ bv20 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4454#(bvslt (bvadd main_~i~0 (_ bv19 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,337 INFO L273 TraceCheckUtils]: 7: Hoare triple {4462#(bvslt (bvadd main_~i~0 (_ bv21 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4458#(bvslt (bvadd main_~i~0 (_ bv20 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,341 INFO L273 TraceCheckUtils]: 6: Hoare triple {4466#(bvslt (bvadd main_~i~0 (_ bv22 32)) (_ bv100000 32))} assume !!~bvslt32(~i~0, 100000bv32);call write~intINTTYPE4(42bv32, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(1bv32, ~i~0); {4462#(bvslt (bvadd main_~i~0 (_ bv21 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,342 INFO L273 TraceCheckUtils]: 5: Hoare triple {3402#true} call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(400000bv32);call ~#b~0.base, ~#b~0.offset := #Ultimate.alloc(400000bv32);~i~0 := 0bv32; {4466#(bvslt (bvadd main_~i~0 (_ bv22 32)) (_ bv100000 32))} is VALID [2018-11-23 10:06:24,342 INFO L256 TraceCheckUtils]: 4: Hoare triple {3402#true} call #t~ret9 := main(); {3402#true} is VALID [2018-11-23 10:06:24,342 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3402#true} {3402#true} #90#return; {3402#true} is VALID [2018-11-23 10:06:24,342 INFO L273 TraceCheckUtils]: 2: Hoare triple {3402#true} assume true; {3402#true} is VALID [2018-11-23 10:06:24,342 INFO L273 TraceCheckUtils]: 1: Hoare triple {3402#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {3402#true} is VALID [2018-11-23 10:06:24,342 INFO L256 TraceCheckUtils]: 0: Hoare triple {3402#true} call ULTIMATE.init(); {3402#true} is VALID [2018-11-23 10:06:24,361 INFO L134 CoverageAnalysis]: Checked inductivity of 1705 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 1452 trivial. 0 not checked. [2018-11-23 10:06:24,364 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:06:24,364 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 48 [2018-11-23 10:06:24,365 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 173 [2018-11-23 10:06:24,366 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:06:24,366 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 48 states. [2018-11-23 10:06:24,544 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 71 edges. 71 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:06:24,544 INFO L459 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-11-23 10:06:24,544 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-11-23 10:06:24,545 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-11-23 10:06:24,545 INFO L87 Difference]: Start difference. First operand 178 states and 182 transitions. Second operand 48 states. [2018-11-23 10:06:28,755 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 7 [2018-11-23 10:06:29,239 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 7 [2018-11-23 10:06:29,761 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 7 [2018-11-23 10:06:30,340 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 7 [2018-11-23 10:06:30,900 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 7 [2018-11-23 10:06:31,463 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 7 [2018-11-23 10:06:32,069 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 7 [2018-11-23 10:06:32,665 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 7 [2018-11-23 10:07:10,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:07:10,266 INFO L93 Difference]: Finished difference Result 495 states and 598 transitions. [2018-11-23 10:07:10,266 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-11-23 10:07:10,266 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 173 [2018-11-23 10:07:10,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:07:10,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-11-23 10:07:10,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 469 transitions. [2018-11-23 10:07:10,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-11-23 10:07:10,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 469 transitions. [2018-11-23 10:07:10,282 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 48 states and 469 transitions. [2018-11-23 10:07:11,692 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 469 edges. 469 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:07:11,702 INFO L225 Difference]: With dead ends: 495 [2018-11-23 10:07:11,702 INFO L226 Difference]: Without dead ends: 346 [2018-11-23 10:07:11,706 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 367 GetRequests, 299 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 231 ImplicationChecksByTransitivity, 11.8s TimeCoverageRelationStatistics Valid=1678, Invalid=3152, Unknown=0, NotChecked=0, Total=4830 [2018-11-23 10:07:11,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 346 states. [2018-11-23 10:07:12,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 346 to 346. [2018-11-23 10:07:12,077 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:07:12,077 INFO L82 GeneralOperation]: Start isEquivalent. First operand 346 states. Second operand 346 states. [2018-11-23 10:07:12,077 INFO L74 IsIncluded]: Start isIncluded. First operand 346 states. Second operand 346 states. [2018-11-23 10:07:12,078 INFO L87 Difference]: Start difference. First operand 346 states. Second operand 346 states. [2018-11-23 10:07:12,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:07:12,090 INFO L93 Difference]: Finished difference Result 346 states and 350 transitions. [2018-11-23 10:07:12,090 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 350 transitions. [2018-11-23 10:07:12,091 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:07:12,091 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:07:12,091 INFO L74 IsIncluded]: Start isIncluded. First operand 346 states. Second operand 346 states. [2018-11-23 10:07:12,091 INFO L87 Difference]: Start difference. First operand 346 states. Second operand 346 states. [2018-11-23 10:07:12,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:07:12,104 INFO L93 Difference]: Finished difference Result 346 states and 350 transitions. [2018-11-23 10:07:12,105 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 350 transitions. [2018-11-23 10:07:12,106 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:07:12,106 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:07:12,106 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:07:12,106 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:07:12,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 346 states. [2018-11-23 10:07:12,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 346 states to 346 states and 350 transitions. [2018-11-23 10:07:12,120 INFO L78 Accepts]: Start accepts. Automaton has 346 states and 350 transitions. Word has length 173 [2018-11-23 10:07:12,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:07:12,121 INFO L480 AbstractCegarLoop]: Abstraction has 346 states and 350 transitions. [2018-11-23 10:07:12,121 INFO L481 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-11-23 10:07:12,121 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 350 transitions. [2018-11-23 10:07:12,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 342 [2018-11-23 10:07:12,127 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:07:12,128 INFO L402 BasicCegarLoop]: trace histogram [46, 46, 46, 46, 46, 46, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:07:12,128 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:07:12,128 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:07:12,128 INFO L82 PathProgramCache]: Analyzing trace with hash -1179356518, now seen corresponding path program 5 times [2018-11-23 10:07:12,130 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:07:12,130 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:07:12,157 INFO L101 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1