java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerCInline_WitnessPrinter.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf -i ../../../trunk/examples/svcomp/array-examples/standard_partition_true-unreach-call_ground.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-61f4311 [2018-11-23 10:09:56,260 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 10:09:56,265 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 10:09:56,286 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 10:09:56,286 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 10:09:56,287 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 10:09:56,289 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 10:09:56,291 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 10:09:56,292 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 10:09:56,293 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 10:09:56,294 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 10:09:56,295 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 10:09:56,296 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 10:09:56,297 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 10:09:56,298 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 10:09:56,299 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 10:09:56,302 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 10:09:56,307 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 10:09:56,313 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 10:09:56,315 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 10:09:56,318 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 10:09:56,320 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 10:09:56,324 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-11-23 10:09:56,336 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 10:09:56,337 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 10:09:56,339 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 10:09:56,340 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 10:09:56,341 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-23 10:09:56,372 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 10:09:56,372 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 10:09:56,373 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 10:09:56,373 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 10:09:56,377 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 10:09:56,378 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 10:09:56,378 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 10:09:56,378 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 10:09:56,378 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 10:09:56,378 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 10:09:56,379 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 10:09:56,379 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 10:09:56,379 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 10:09:56,379 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 10:09:56,379 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-23 10:09:56,379 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-23 10:09:56,381 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 10:09:56,381 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 10:09:56,381 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 10:09:56,382 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 10:09:56,382 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 10:09:56,382 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 10:09:56,382 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 10:09:56,382 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 10:09:56,382 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:09:56,383 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 10:09:56,383 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 10:09:56,383 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 10:09:56,384 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-23 10:09:56,384 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 10:09:56,384 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-23 10:09:56,384 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-23 10:09:56,384 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 10:09:56,439 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 10:09:56,455 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 10:09:56,461 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 10:09:56,463 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 10:09:56,463 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 10:09:56,464 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/standard_partition_true-unreach-call_ground.i [2018-11-23 10:09:56,537 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/28f046212/02ade798a4454549b61fb40efde2f221/FLAG07bd362fb [2018-11-23 10:09:56,970 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 10:09:56,971 INFO L161 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-examples/standard_partition_true-unreach-call_ground.i [2018-11-23 10:09:56,981 INFO L355 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/28f046212/02ade798a4454549b61fb40efde2f221/FLAG07bd362fb [2018-11-23 10:09:57,343 INFO L363 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/28f046212/02ade798a4454549b61fb40efde2f221 [2018-11-23 10:09:57,354 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 10:09:57,356 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 10:09:57,357 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 10:09:57,357 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 10:09:57,362 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 10:09:57,364 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:09:57" (1/1) ... [2018-11-23 10:09:57,367 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@76d9d738 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:09:57, skipping insertion in model container [2018-11-23 10:09:57,368 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:09:57" (1/1) ... [2018-11-23 10:09:57,379 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 10:09:57,406 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 10:09:57,675 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:09:57,682 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 10:09:57,714 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:09:57,739 INFO L195 MainTranslator]: Completed translation [2018-11-23 10:09:57,739 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:09:57 WrapperNode [2018-11-23 10:09:57,740 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 10:09:57,741 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 10:09:57,741 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 10:09:57,741 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 10:09:57,752 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:09:57" (1/1) ... [2018-11-23 10:09:57,763 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:09:57" (1/1) ... [2018-11-23 10:09:57,772 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 10:09:57,772 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 10:09:57,772 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 10:09:57,773 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 10:09:57,783 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:09:57" (1/1) ... [2018-11-23 10:09:57,784 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:09:57" (1/1) ... [2018-11-23 10:09:57,786 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:09:57" (1/1) ... [2018-11-23 10:09:57,787 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:09:57" (1/1) ... [2018-11-23 10:09:57,800 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:09:57" (1/1) ... [2018-11-23 10:09:57,809 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:09:57" (1/1) ... [2018-11-23 10:09:57,811 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:09:57" (1/1) ... [2018-11-23 10:09:57,818 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 10:09:57,819 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 10:09:57,819 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 10:09:57,819 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 10:09:57,821 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:09:57" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:09:57,957 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 10:09:57,957 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 10:09:57,958 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 10:09:57,958 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-23 10:09:57,958 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 10:09:57,958 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 10:09:57,958 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 10:09:57,958 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 10:09:57,958 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-23 10:09:57,959 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-23 10:09:57,959 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 10:09:57,959 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-23 10:09:58,571 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 10:09:58,572 INFO L280 CfgBuilder]: Removed 3 assue(true) statements. [2018-11-23 10:09:58,572 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:09:58 BoogieIcfgContainer [2018-11-23 10:09:58,572 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 10:09:58,573 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 10:09:58,574 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 10:09:58,577 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 10:09:58,577 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 10:09:57" (1/3) ... [2018-11-23 10:09:58,578 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@56d6ad78 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:09:58, skipping insertion in model container [2018-11-23 10:09:58,579 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:09:57" (2/3) ... [2018-11-23 10:09:58,579 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@56d6ad78 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:09:58, skipping insertion in model container [2018-11-23 10:09:58,579 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:09:58" (3/3) ... [2018-11-23 10:09:58,581 INFO L112 eAbstractionObserver]: Analyzing ICFG standard_partition_true-unreach-call_ground.i [2018-11-23 10:09:58,593 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 10:09:58,604 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 10:09:58,623 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 10:09:58,656 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 10:09:58,657 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 10:09:58,657 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 10:09:58,657 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 10:09:58,658 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 10:09:58,658 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 10:09:58,658 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 10:09:58,658 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 10:09:58,658 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 10:09:58,678 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states. [2018-11-23 10:09:58,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-23 10:09:58,685 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:09:58,686 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:09:58,688 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:09:58,693 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:09:58,694 INFO L82 PathProgramCache]: Analyzing trace with hash 1738896191, now seen corresponding path program 1 times [2018-11-23 10:09:58,698 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:09:58,699 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:09:58,723 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:09:58,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:09:58,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:09:58,810 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:09:58,907 INFO L256 TraceCheckUtils]: 0: Hoare triple {32#true} call ULTIMATE.init(); {32#true} is VALID [2018-11-23 10:09:58,911 INFO L273 TraceCheckUtils]: 1: Hoare triple {32#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {32#true} is VALID [2018-11-23 10:09:58,911 INFO L273 TraceCheckUtils]: 2: Hoare triple {32#true} assume true; {32#true} is VALID [2018-11-23 10:09:58,912 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {32#true} {32#true} #75#return; {32#true} is VALID [2018-11-23 10:09:58,912 INFO L256 TraceCheckUtils]: 4: Hoare triple {32#true} call #t~ret6 := main(); {32#true} is VALID [2018-11-23 10:09:58,912 INFO L273 TraceCheckUtils]: 5: Hoare triple {32#true} call ~#aa~0.base, ~#aa~0.offset := #Ultimate.alloc(400000bv32);~a~0 := 0bv32;~b~0 := 0bv32;~c~0 := 0bv32;call ~#bb~0.base, ~#bb~0.offset := #Ultimate.alloc(400000bv32);havoc ~cc~0; {32#true} is VALID [2018-11-23 10:09:58,917 INFO L273 TraceCheckUtils]: 6: Hoare triple {32#true} assume !true; {33#false} is VALID [2018-11-23 10:09:58,917 INFO L273 TraceCheckUtils]: 7: Hoare triple {33#false} ~a~0 := 0bv32; {33#false} is VALID [2018-11-23 10:09:58,918 INFO L273 TraceCheckUtils]: 8: Hoare triple {33#false} assume !~bvslt32(~a~0, 100000bv32); {33#false} is VALID [2018-11-23 10:09:58,918 INFO L273 TraceCheckUtils]: 9: Hoare triple {33#false} havoc ~x~0;~x~0 := 0bv32; {33#false} is VALID [2018-11-23 10:09:58,918 INFO L273 TraceCheckUtils]: 10: Hoare triple {33#false} assume !!~bvslt32(~x~0, ~b~0);call #t~mem5 := read~intINTTYPE4(~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {33#false} is VALID [2018-11-23 10:09:58,918 INFO L256 TraceCheckUtils]: 11: Hoare triple {33#false} call __VERIFIER_assert((if ~bvsge32(#t~mem5, 0bv32) then 1bv32 else 0bv32)); {33#false} is VALID [2018-11-23 10:09:58,919 INFO L273 TraceCheckUtils]: 12: Hoare triple {33#false} ~cond := #in~cond; {33#false} is VALID [2018-11-23 10:09:58,919 INFO L273 TraceCheckUtils]: 13: Hoare triple {33#false} assume 0bv32 == ~cond; {33#false} is VALID [2018-11-23 10:09:58,919 INFO L273 TraceCheckUtils]: 14: Hoare triple {33#false} assume !false; {33#false} is VALID [2018-11-23 10:09:58,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:09:58,923 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:09:58,931 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:09:58,931 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 10:09:58,937 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 15 [2018-11-23 10:09:58,940 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:09:58,944 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states. [2018-11-23 10:09:59,093 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:09:59,093 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-23 10:09:59,101 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-23 10:09:59,102 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-23 10:09:59,104 INFO L87 Difference]: Start difference. First operand 29 states. Second operand 2 states. [2018-11-23 10:09:59,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:09:59,235 INFO L93 Difference]: Finished difference Result 49 states and 63 transitions. [2018-11-23 10:09:59,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-23 10:09:59,236 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 15 [2018-11-23 10:09:59,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:09:59,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-23 10:09:59,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 63 transitions. [2018-11-23 10:09:59,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-23 10:09:59,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 63 transitions. [2018-11-23 10:09:59,257 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states and 63 transitions. [2018-11-23 10:09:59,666 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 63 edges. 63 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:09:59,678 INFO L225 Difference]: With dead ends: 49 [2018-11-23 10:09:59,678 INFO L226 Difference]: Without dead ends: 24 [2018-11-23 10:09:59,682 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-23 10:09:59,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2018-11-23 10:09:59,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2018-11-23 10:09:59,726 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:09:59,727 INFO L82 GeneralOperation]: Start isEquivalent. First operand 24 states. Second operand 24 states. [2018-11-23 10:09:59,727 INFO L74 IsIncluded]: Start isIncluded. First operand 24 states. Second operand 24 states. [2018-11-23 10:09:59,727 INFO L87 Difference]: Start difference. First operand 24 states. Second operand 24 states. [2018-11-23 10:09:59,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:09:59,732 INFO L93 Difference]: Finished difference Result 24 states and 28 transitions. [2018-11-23 10:09:59,732 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 28 transitions. [2018-11-23 10:09:59,733 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:09:59,733 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:09:59,733 INFO L74 IsIncluded]: Start isIncluded. First operand 24 states. Second operand 24 states. [2018-11-23 10:09:59,734 INFO L87 Difference]: Start difference. First operand 24 states. Second operand 24 states. [2018-11-23 10:09:59,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:09:59,738 INFO L93 Difference]: Finished difference Result 24 states and 28 transitions. [2018-11-23 10:09:59,739 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 28 transitions. [2018-11-23 10:09:59,739 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:09:59,739 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:09:59,740 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:09:59,740 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:09:59,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-11-23 10:09:59,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 28 transitions. [2018-11-23 10:09:59,745 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 28 transitions. Word has length 15 [2018-11-23 10:09:59,746 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:09:59,746 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 28 transitions. [2018-11-23 10:09:59,746 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-23 10:09:59,746 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 28 transitions. [2018-11-23 10:09:59,747 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-23 10:09:59,747 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:09:59,747 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:09:59,748 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:09:59,748 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:09:59,749 INFO L82 PathProgramCache]: Analyzing trace with hash 146058804, now seen corresponding path program 1 times [2018-11-23 10:09:59,749 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:09:59,749 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:09:59,772 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:09:59,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:09:59,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:09:59,832 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:09:59,900 INFO L256 TraceCheckUtils]: 0: Hoare triple {221#true} call ULTIMATE.init(); {221#true} is VALID [2018-11-23 10:09:59,901 INFO L273 TraceCheckUtils]: 1: Hoare triple {221#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {221#true} is VALID [2018-11-23 10:09:59,901 INFO L273 TraceCheckUtils]: 2: Hoare triple {221#true} assume true; {221#true} is VALID [2018-11-23 10:09:59,901 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {221#true} {221#true} #75#return; {221#true} is VALID [2018-11-23 10:09:59,902 INFO L256 TraceCheckUtils]: 4: Hoare triple {221#true} call #t~ret6 := main(); {221#true} is VALID [2018-11-23 10:09:59,902 INFO L273 TraceCheckUtils]: 5: Hoare triple {221#true} call ~#aa~0.base, ~#aa~0.offset := #Ultimate.alloc(400000bv32);~a~0 := 0bv32;~b~0 := 0bv32;~c~0 := 0bv32;call ~#bb~0.base, ~#bb~0.offset := #Ultimate.alloc(400000bv32);havoc ~cc~0; {241#(= main_~a~0 (_ bv0 32))} is VALID [2018-11-23 10:09:59,920 INFO L273 TraceCheckUtils]: 6: Hoare triple {241#(= main_~a~0 (_ bv0 32))} assume !~bvslt32(~a~0, 100000bv32); {222#false} is VALID [2018-11-23 10:09:59,921 INFO L273 TraceCheckUtils]: 7: Hoare triple {222#false} ~a~0 := 0bv32; {222#false} is VALID [2018-11-23 10:09:59,921 INFO L273 TraceCheckUtils]: 8: Hoare triple {222#false} assume !~bvslt32(~a~0, 100000bv32); {222#false} is VALID [2018-11-23 10:09:59,921 INFO L273 TraceCheckUtils]: 9: Hoare triple {222#false} havoc ~x~0;~x~0 := 0bv32; {222#false} is VALID [2018-11-23 10:09:59,922 INFO L273 TraceCheckUtils]: 10: Hoare triple {222#false} assume !!~bvslt32(~x~0, ~b~0);call #t~mem5 := read~intINTTYPE4(~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {222#false} is VALID [2018-11-23 10:09:59,922 INFO L256 TraceCheckUtils]: 11: Hoare triple {222#false} call __VERIFIER_assert((if ~bvsge32(#t~mem5, 0bv32) then 1bv32 else 0bv32)); {222#false} is VALID [2018-11-23 10:09:59,923 INFO L273 TraceCheckUtils]: 12: Hoare triple {222#false} ~cond := #in~cond; {222#false} is VALID [2018-11-23 10:09:59,923 INFO L273 TraceCheckUtils]: 13: Hoare triple {222#false} assume 0bv32 == ~cond; {222#false} is VALID [2018-11-23 10:09:59,923 INFO L273 TraceCheckUtils]: 14: Hoare triple {222#false} assume !false; {222#false} is VALID [2018-11-23 10:09:59,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:09:59,925 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:09:59,932 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:09:59,932 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 10:09:59,934 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-11-23 10:09:59,937 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:09:59,937 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-23 10:10:00,001 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:10:00,001 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 10:10:00,002 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 10:10:00,002 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:10:00,002 INFO L87 Difference]: Start difference. First operand 24 states and 28 transitions. Second operand 3 states. [2018-11-23 10:10:00,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:10:00,841 INFO L93 Difference]: Finished difference Result 45 states and 55 transitions. [2018-11-23 10:10:00,841 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 10:10:00,841 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-11-23 10:10:00,841 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:10:00,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:10:00,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 55 transitions. [2018-11-23 10:10:00,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:10:00,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 55 transitions. [2018-11-23 10:10:00,848 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 55 transitions. [2018-11-23 10:10:00,994 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 55 edges. 55 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:10:00,997 INFO L225 Difference]: With dead ends: 45 [2018-11-23 10:10:00,997 INFO L226 Difference]: Without dead ends: 30 [2018-11-23 10:10:00,999 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:10:00,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2018-11-23 10:10:01,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 26. [2018-11-23 10:10:01,019 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:10:01,019 INFO L82 GeneralOperation]: Start isEquivalent. First operand 30 states. Second operand 26 states. [2018-11-23 10:10:01,020 INFO L74 IsIncluded]: Start isIncluded. First operand 30 states. Second operand 26 states. [2018-11-23 10:10:01,020 INFO L87 Difference]: Start difference. First operand 30 states. Second operand 26 states. [2018-11-23 10:10:01,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:10:01,023 INFO L93 Difference]: Finished difference Result 30 states and 36 transitions. [2018-11-23 10:10:01,023 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 36 transitions. [2018-11-23 10:10:01,024 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:10:01,024 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:10:01,024 INFO L74 IsIncluded]: Start isIncluded. First operand 26 states. Second operand 30 states. [2018-11-23 10:10:01,024 INFO L87 Difference]: Start difference. First operand 26 states. Second operand 30 states. [2018-11-23 10:10:01,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:10:01,028 INFO L93 Difference]: Finished difference Result 30 states and 36 transitions. [2018-11-23 10:10:01,028 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 36 transitions. [2018-11-23 10:10:01,029 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:10:01,029 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:10:01,029 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:10:01,029 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:10:01,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-11-23 10:10:01,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 30 transitions. [2018-11-23 10:10:01,032 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 30 transitions. Word has length 15 [2018-11-23 10:10:01,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:10:01,032 INFO L480 AbstractCegarLoop]: Abstraction has 26 states and 30 transitions. [2018-11-23 10:10:01,033 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 10:10:01,033 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 30 transitions. [2018-11-23 10:10:01,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-11-23 10:10:01,034 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:10:01,034 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:10:01,034 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:10:01,035 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:10:01,035 INFO L82 PathProgramCache]: Analyzing trace with hash -1176205862, now seen corresponding path program 1 times [2018-11-23 10:10:01,035 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:10:01,036 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:10:01,060 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:10:01,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:10:01,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:10:01,117 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:10:01,242 INFO L256 TraceCheckUtils]: 0: Hoare triple {425#true} call ULTIMATE.init(); {425#true} is VALID [2018-11-23 10:10:01,243 INFO L273 TraceCheckUtils]: 1: Hoare triple {425#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {425#true} is VALID [2018-11-23 10:10:01,244 INFO L273 TraceCheckUtils]: 2: Hoare triple {425#true} assume true; {425#true} is VALID [2018-11-23 10:10:01,244 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {425#true} {425#true} #75#return; {425#true} is VALID [2018-11-23 10:10:01,245 INFO L256 TraceCheckUtils]: 4: Hoare triple {425#true} call #t~ret6 := main(); {425#true} is VALID [2018-11-23 10:10:01,245 INFO L273 TraceCheckUtils]: 5: Hoare triple {425#true} call ~#aa~0.base, ~#aa~0.offset := #Ultimate.alloc(400000bv32);~a~0 := 0bv32;~b~0 := 0bv32;~c~0 := 0bv32;call ~#bb~0.base, ~#bb~0.offset := #Ultimate.alloc(400000bv32);havoc ~cc~0; {445#(= main_~a~0 (_ bv0 32))} is VALID [2018-11-23 10:10:01,246 INFO L273 TraceCheckUtils]: 6: Hoare triple {445#(= main_~a~0 (_ bv0 32))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {445#(= main_~a~0 (_ bv0 32))} is VALID [2018-11-23 10:10:01,249 INFO L273 TraceCheckUtils]: 7: Hoare triple {445#(= main_~a~0 (_ bv0 32))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {445#(= main_~a~0 (_ bv0 32))} is VALID [2018-11-23 10:10:01,250 INFO L273 TraceCheckUtils]: 8: Hoare triple {445#(= main_~a~0 (_ bv0 32))} ~a~0 := ~bvadd32(1bv32, ~a~0); {455#(= (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:10:01,251 INFO L273 TraceCheckUtils]: 9: Hoare triple {455#(= (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv0 32))} assume !~bvslt32(~a~0, 100000bv32); {426#false} is VALID [2018-11-23 10:10:01,251 INFO L273 TraceCheckUtils]: 10: Hoare triple {426#false} ~a~0 := 0bv32; {426#false} is VALID [2018-11-23 10:10:01,251 INFO L273 TraceCheckUtils]: 11: Hoare triple {426#false} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {426#false} is VALID [2018-11-23 10:10:01,252 INFO L273 TraceCheckUtils]: 12: Hoare triple {426#false} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {426#false} is VALID [2018-11-23 10:10:01,252 INFO L273 TraceCheckUtils]: 13: Hoare triple {426#false} ~a~0 := ~bvadd32(1bv32, ~a~0); {426#false} is VALID [2018-11-23 10:10:01,252 INFO L273 TraceCheckUtils]: 14: Hoare triple {426#false} assume !~bvslt32(~a~0, 100000bv32); {426#false} is VALID [2018-11-23 10:10:01,253 INFO L273 TraceCheckUtils]: 15: Hoare triple {426#false} havoc ~x~0;~x~0 := 0bv32; {426#false} is VALID [2018-11-23 10:10:01,253 INFO L273 TraceCheckUtils]: 16: Hoare triple {426#false} assume !!~bvslt32(~x~0, ~b~0);call #t~mem5 := read~intINTTYPE4(~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {426#false} is VALID [2018-11-23 10:10:01,253 INFO L256 TraceCheckUtils]: 17: Hoare triple {426#false} call __VERIFIER_assert((if ~bvsge32(#t~mem5, 0bv32) then 1bv32 else 0bv32)); {426#false} is VALID [2018-11-23 10:10:01,254 INFO L273 TraceCheckUtils]: 18: Hoare triple {426#false} ~cond := #in~cond; {426#false} is VALID [2018-11-23 10:10:01,254 INFO L273 TraceCheckUtils]: 19: Hoare triple {426#false} assume 0bv32 == ~cond; {426#false} is VALID [2018-11-23 10:10:01,254 INFO L273 TraceCheckUtils]: 20: Hoare triple {426#false} assume !false; {426#false} is VALID [2018-11-23 10:10:01,256 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-23 10:10:01,256 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:10:01,350 INFO L273 TraceCheckUtils]: 20: Hoare triple {426#false} assume !false; {426#false} is VALID [2018-11-23 10:10:01,351 INFO L273 TraceCheckUtils]: 19: Hoare triple {426#false} assume 0bv32 == ~cond; {426#false} is VALID [2018-11-23 10:10:01,351 INFO L273 TraceCheckUtils]: 18: Hoare triple {426#false} ~cond := #in~cond; {426#false} is VALID [2018-11-23 10:10:01,351 INFO L256 TraceCheckUtils]: 17: Hoare triple {426#false} call __VERIFIER_assert((if ~bvsge32(#t~mem5, 0bv32) then 1bv32 else 0bv32)); {426#false} is VALID [2018-11-23 10:10:01,352 INFO L273 TraceCheckUtils]: 16: Hoare triple {426#false} assume !!~bvslt32(~x~0, ~b~0);call #t~mem5 := read~intINTTYPE4(~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {426#false} is VALID [2018-11-23 10:10:01,352 INFO L273 TraceCheckUtils]: 15: Hoare triple {426#false} havoc ~x~0;~x~0 := 0bv32; {426#false} is VALID [2018-11-23 10:10:01,353 INFO L273 TraceCheckUtils]: 14: Hoare triple {426#false} assume !~bvslt32(~a~0, 100000bv32); {426#false} is VALID [2018-11-23 10:10:01,353 INFO L273 TraceCheckUtils]: 13: Hoare triple {426#false} ~a~0 := ~bvadd32(1bv32, ~a~0); {426#false} is VALID [2018-11-23 10:10:01,353 INFO L273 TraceCheckUtils]: 12: Hoare triple {426#false} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {426#false} is VALID [2018-11-23 10:10:01,354 INFO L273 TraceCheckUtils]: 11: Hoare triple {426#false} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {426#false} is VALID [2018-11-23 10:10:01,354 INFO L273 TraceCheckUtils]: 10: Hoare triple {426#false} ~a~0 := 0bv32; {426#false} is VALID [2018-11-23 10:10:01,361 INFO L273 TraceCheckUtils]: 9: Hoare triple {525#(bvslt main_~a~0 (_ bv100000 32))} assume !~bvslt32(~a~0, 100000bv32); {426#false} is VALID [2018-11-23 10:10:01,366 INFO L273 TraceCheckUtils]: 8: Hoare triple {529#(bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32))} ~a~0 := ~bvadd32(1bv32, ~a~0); {525#(bvslt main_~a~0 (_ bv100000 32))} is VALID [2018-11-23 10:10:01,367 INFO L273 TraceCheckUtils]: 7: Hoare triple {529#(bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {529#(bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:01,368 INFO L273 TraceCheckUtils]: 6: Hoare triple {529#(bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {529#(bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:01,369 INFO L273 TraceCheckUtils]: 5: Hoare triple {425#true} call ~#aa~0.base, ~#aa~0.offset := #Ultimate.alloc(400000bv32);~a~0 := 0bv32;~b~0 := 0bv32;~c~0 := 0bv32;call ~#bb~0.base, ~#bb~0.offset := #Ultimate.alloc(400000bv32);havoc ~cc~0; {529#(bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:01,369 INFO L256 TraceCheckUtils]: 4: Hoare triple {425#true} call #t~ret6 := main(); {425#true} is VALID [2018-11-23 10:10:01,370 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {425#true} {425#true} #75#return; {425#true} is VALID [2018-11-23 10:10:01,370 INFO L273 TraceCheckUtils]: 2: Hoare triple {425#true} assume true; {425#true} is VALID [2018-11-23 10:10:01,370 INFO L273 TraceCheckUtils]: 1: Hoare triple {425#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {425#true} is VALID [2018-11-23 10:10:01,370 INFO L256 TraceCheckUtils]: 0: Hoare triple {425#true} call ULTIMATE.init(); {425#true} is VALID [2018-11-23 10:10:01,372 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-23 10:10:01,375 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:10:01,375 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 6 [2018-11-23 10:10:01,376 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 21 [2018-11-23 10:10:01,376 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:10:01,376 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states. [2018-11-23 10:10:01,453 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 26 edges. 26 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:10:01,453 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 10:10:01,453 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 10:10:01,454 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-23 10:10:01,454 INFO L87 Difference]: Start difference. First operand 26 states and 30 transitions. Second operand 6 states. [2018-11-23 10:10:01,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:10:01,998 INFO L93 Difference]: Finished difference Result 60 states and 78 transitions. [2018-11-23 10:10:01,998 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 10:10:01,999 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 21 [2018-11-23 10:10:01,999 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:10:01,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-23 10:10:02,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 77 transitions. [2018-11-23 10:10:02,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-23 10:10:02,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 77 transitions. [2018-11-23 10:10:02,009 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 77 transitions. [2018-11-23 10:10:02,226 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 77 edges. 77 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:10:02,228 INFO L225 Difference]: With dead ends: 60 [2018-11-23 10:10:02,229 INFO L226 Difference]: Without dead ends: 44 [2018-11-23 10:10:02,229 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2018-11-23 10:10:02,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-11-23 10:10:02,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2018-11-23 10:10:02,251 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:10:02,251 INFO L82 GeneralOperation]: Start isEquivalent. First operand 44 states. Second operand 44 states. [2018-11-23 10:10:02,252 INFO L74 IsIncluded]: Start isIncluded. First operand 44 states. Second operand 44 states. [2018-11-23 10:10:02,252 INFO L87 Difference]: Start difference. First operand 44 states. Second operand 44 states. [2018-11-23 10:10:02,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:10:02,256 INFO L93 Difference]: Finished difference Result 44 states and 54 transitions. [2018-11-23 10:10:02,256 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 54 transitions. [2018-11-23 10:10:02,257 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:10:02,257 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:10:02,257 INFO L74 IsIncluded]: Start isIncluded. First operand 44 states. Second operand 44 states. [2018-11-23 10:10:02,257 INFO L87 Difference]: Start difference. First operand 44 states. Second operand 44 states. [2018-11-23 10:10:02,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:10:02,261 INFO L93 Difference]: Finished difference Result 44 states and 54 transitions. [2018-11-23 10:10:02,261 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 54 transitions. [2018-11-23 10:10:02,262 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:10:02,262 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:10:02,262 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:10:02,262 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:10:02,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-11-23 10:10:02,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 54 transitions. [2018-11-23 10:10:02,266 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 54 transitions. Word has length 21 [2018-11-23 10:10:02,266 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:10:02,267 INFO L480 AbstractCegarLoop]: Abstraction has 44 states and 54 transitions. [2018-11-23 10:10:02,267 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 10:10:02,267 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 54 transitions. [2018-11-23 10:10:02,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-11-23 10:10:02,268 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:10:02,269 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:10:02,269 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:10:02,269 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:10:02,269 INFO L82 PathProgramCache]: Analyzing trace with hash 1581243828, now seen corresponding path program 2 times [2018-11-23 10:10:02,270 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:10:02,270 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:10:02,287 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 10:10:02,380 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 10:10:02,380 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:10:02,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:10:02,422 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:10:02,667 INFO L256 TraceCheckUtils]: 0: Hoare triple {789#true} call ULTIMATE.init(); {789#true} is VALID [2018-11-23 10:10:02,667 INFO L273 TraceCheckUtils]: 1: Hoare triple {789#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {789#true} is VALID [2018-11-23 10:10:02,668 INFO L273 TraceCheckUtils]: 2: Hoare triple {789#true} assume true; {789#true} is VALID [2018-11-23 10:10:02,668 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {789#true} {789#true} #75#return; {789#true} is VALID [2018-11-23 10:10:02,669 INFO L256 TraceCheckUtils]: 4: Hoare triple {789#true} call #t~ret6 := main(); {789#true} is VALID [2018-11-23 10:10:02,670 INFO L273 TraceCheckUtils]: 5: Hoare triple {789#true} call ~#aa~0.base, ~#aa~0.offset := #Ultimate.alloc(400000bv32);~a~0 := 0bv32;~b~0 := 0bv32;~c~0 := 0bv32;call ~#bb~0.base, ~#bb~0.offset := #Ultimate.alloc(400000bv32);havoc ~cc~0; {809#(= main_~a~0 (_ bv0 32))} is VALID [2018-11-23 10:10:02,670 INFO L273 TraceCheckUtils]: 6: Hoare triple {809#(= main_~a~0 (_ bv0 32))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {809#(= main_~a~0 (_ bv0 32))} is VALID [2018-11-23 10:10:02,671 INFO L273 TraceCheckUtils]: 7: Hoare triple {809#(= main_~a~0 (_ bv0 32))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {809#(= main_~a~0 (_ bv0 32))} is VALID [2018-11-23 10:10:02,671 INFO L273 TraceCheckUtils]: 8: Hoare triple {809#(= main_~a~0 (_ bv0 32))} ~a~0 := ~bvadd32(1bv32, ~a~0); {819#(= (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:10:02,672 INFO L273 TraceCheckUtils]: 9: Hoare triple {819#(= (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv0 32))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {819#(= (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:10:02,673 INFO L273 TraceCheckUtils]: 10: Hoare triple {819#(= (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv0 32))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {819#(= (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:10:02,674 INFO L273 TraceCheckUtils]: 11: Hoare triple {819#(= (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv0 32))} ~a~0 := ~bvadd32(1bv32, ~a~0); {829#(= (bvadd main_~a~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:10:02,676 INFO L273 TraceCheckUtils]: 12: Hoare triple {829#(= (bvadd main_~a~0 (_ bv4294967294 32)) (_ bv0 32))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {829#(= (bvadd main_~a~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:10:02,677 INFO L273 TraceCheckUtils]: 13: Hoare triple {829#(= (bvadd main_~a~0 (_ bv4294967294 32)) (_ bv0 32))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {829#(= (bvadd main_~a~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:10:02,678 INFO L273 TraceCheckUtils]: 14: Hoare triple {829#(= (bvadd main_~a~0 (_ bv4294967294 32)) (_ bv0 32))} ~a~0 := ~bvadd32(1bv32, ~a~0); {839#(= (_ bv3 32) main_~a~0)} is VALID [2018-11-23 10:10:02,679 INFO L273 TraceCheckUtils]: 15: Hoare triple {839#(= (_ bv3 32) main_~a~0)} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {839#(= (_ bv3 32) main_~a~0)} is VALID [2018-11-23 10:10:02,680 INFO L273 TraceCheckUtils]: 16: Hoare triple {839#(= (_ bv3 32) main_~a~0)} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {839#(= (_ bv3 32) main_~a~0)} is VALID [2018-11-23 10:10:02,681 INFO L273 TraceCheckUtils]: 17: Hoare triple {839#(= (_ bv3 32) main_~a~0)} ~a~0 := ~bvadd32(1bv32, ~a~0); {849#(= (bvadd main_~a~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:10:02,682 INFO L273 TraceCheckUtils]: 18: Hoare triple {849#(= (bvadd main_~a~0 (_ bv4294967292 32)) (_ bv0 32))} assume !~bvslt32(~a~0, 100000bv32); {790#false} is VALID [2018-11-23 10:10:02,683 INFO L273 TraceCheckUtils]: 19: Hoare triple {790#false} ~a~0 := 0bv32; {790#false} is VALID [2018-11-23 10:10:02,683 INFO L273 TraceCheckUtils]: 20: Hoare triple {790#false} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {790#false} is VALID [2018-11-23 10:10:02,684 INFO L273 TraceCheckUtils]: 21: Hoare triple {790#false} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {790#false} is VALID [2018-11-23 10:10:02,684 INFO L273 TraceCheckUtils]: 22: Hoare triple {790#false} ~a~0 := ~bvadd32(1bv32, ~a~0); {790#false} is VALID [2018-11-23 10:10:02,685 INFO L273 TraceCheckUtils]: 23: Hoare triple {790#false} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {790#false} is VALID [2018-11-23 10:10:02,685 INFO L273 TraceCheckUtils]: 24: Hoare triple {790#false} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {790#false} is VALID [2018-11-23 10:10:02,686 INFO L273 TraceCheckUtils]: 25: Hoare triple {790#false} ~a~0 := ~bvadd32(1bv32, ~a~0); {790#false} is VALID [2018-11-23 10:10:02,686 INFO L273 TraceCheckUtils]: 26: Hoare triple {790#false} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {790#false} is VALID [2018-11-23 10:10:02,687 INFO L273 TraceCheckUtils]: 27: Hoare triple {790#false} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {790#false} is VALID [2018-11-23 10:10:02,687 INFO L273 TraceCheckUtils]: 28: Hoare triple {790#false} ~a~0 := ~bvadd32(1bv32, ~a~0); {790#false} is VALID [2018-11-23 10:10:02,688 INFO L273 TraceCheckUtils]: 29: Hoare triple {790#false} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {790#false} is VALID [2018-11-23 10:10:02,688 INFO L273 TraceCheckUtils]: 30: Hoare triple {790#false} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {790#false} is VALID [2018-11-23 10:10:02,688 INFO L273 TraceCheckUtils]: 31: Hoare triple {790#false} ~a~0 := ~bvadd32(1bv32, ~a~0); {790#false} is VALID [2018-11-23 10:10:02,689 INFO L273 TraceCheckUtils]: 32: Hoare triple {790#false} assume !~bvslt32(~a~0, 100000bv32); {790#false} is VALID [2018-11-23 10:10:02,689 INFO L273 TraceCheckUtils]: 33: Hoare triple {790#false} havoc ~x~0;~x~0 := 0bv32; {790#false} is VALID [2018-11-23 10:10:02,689 INFO L273 TraceCheckUtils]: 34: Hoare triple {790#false} assume !!~bvslt32(~x~0, ~b~0);call #t~mem5 := read~intINTTYPE4(~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {790#false} is VALID [2018-11-23 10:10:02,690 INFO L256 TraceCheckUtils]: 35: Hoare triple {790#false} call __VERIFIER_assert((if ~bvsge32(#t~mem5, 0bv32) then 1bv32 else 0bv32)); {790#false} is VALID [2018-11-23 10:10:02,690 INFO L273 TraceCheckUtils]: 36: Hoare triple {790#false} ~cond := #in~cond; {790#false} is VALID [2018-11-23 10:10:02,690 INFO L273 TraceCheckUtils]: 37: Hoare triple {790#false} assume 0bv32 == ~cond; {790#false} is VALID [2018-11-23 10:10:02,691 INFO L273 TraceCheckUtils]: 38: Hoare triple {790#false} assume !false; {790#false} is VALID [2018-11-23 10:10:02,694 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-23 10:10:02,694 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:10:02,935 INFO L273 TraceCheckUtils]: 38: Hoare triple {790#false} assume !false; {790#false} is VALID [2018-11-23 10:10:02,936 INFO L273 TraceCheckUtils]: 37: Hoare triple {790#false} assume 0bv32 == ~cond; {790#false} is VALID [2018-11-23 10:10:02,936 INFO L273 TraceCheckUtils]: 36: Hoare triple {790#false} ~cond := #in~cond; {790#false} is VALID [2018-11-23 10:10:02,936 INFO L256 TraceCheckUtils]: 35: Hoare triple {790#false} call __VERIFIER_assert((if ~bvsge32(#t~mem5, 0bv32) then 1bv32 else 0bv32)); {790#false} is VALID [2018-11-23 10:10:02,937 INFO L273 TraceCheckUtils]: 34: Hoare triple {790#false} assume !!~bvslt32(~x~0, ~b~0);call #t~mem5 := read~intINTTYPE4(~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {790#false} is VALID [2018-11-23 10:10:02,937 INFO L273 TraceCheckUtils]: 33: Hoare triple {790#false} havoc ~x~0;~x~0 := 0bv32; {790#false} is VALID [2018-11-23 10:10:02,938 INFO L273 TraceCheckUtils]: 32: Hoare triple {790#false} assume !~bvslt32(~a~0, 100000bv32); {790#false} is VALID [2018-11-23 10:10:02,938 INFO L273 TraceCheckUtils]: 31: Hoare triple {790#false} ~a~0 := ~bvadd32(1bv32, ~a~0); {790#false} is VALID [2018-11-23 10:10:02,938 INFO L273 TraceCheckUtils]: 30: Hoare triple {790#false} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {790#false} is VALID [2018-11-23 10:10:02,939 INFO L273 TraceCheckUtils]: 29: Hoare triple {790#false} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {790#false} is VALID [2018-11-23 10:10:02,939 INFO L273 TraceCheckUtils]: 28: Hoare triple {790#false} ~a~0 := ~bvadd32(1bv32, ~a~0); {790#false} is VALID [2018-11-23 10:10:02,939 INFO L273 TraceCheckUtils]: 27: Hoare triple {790#false} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {790#false} is VALID [2018-11-23 10:10:02,939 INFO L273 TraceCheckUtils]: 26: Hoare triple {790#false} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {790#false} is VALID [2018-11-23 10:10:02,940 INFO L273 TraceCheckUtils]: 25: Hoare triple {790#false} ~a~0 := ~bvadd32(1bv32, ~a~0); {790#false} is VALID [2018-11-23 10:10:02,940 INFO L273 TraceCheckUtils]: 24: Hoare triple {790#false} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {790#false} is VALID [2018-11-23 10:10:02,940 INFO L273 TraceCheckUtils]: 23: Hoare triple {790#false} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {790#false} is VALID [2018-11-23 10:10:02,941 INFO L273 TraceCheckUtils]: 22: Hoare triple {790#false} ~a~0 := ~bvadd32(1bv32, ~a~0); {790#false} is VALID [2018-11-23 10:10:02,941 INFO L273 TraceCheckUtils]: 21: Hoare triple {790#false} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {790#false} is VALID [2018-11-23 10:10:02,941 INFO L273 TraceCheckUtils]: 20: Hoare triple {790#false} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {790#false} is VALID [2018-11-23 10:10:02,942 INFO L273 TraceCheckUtils]: 19: Hoare triple {790#false} ~a~0 := 0bv32; {790#false} is VALID [2018-11-23 10:10:02,954 INFO L273 TraceCheckUtils]: 18: Hoare triple {973#(bvslt main_~a~0 (_ bv100000 32))} assume !~bvslt32(~a~0, 100000bv32); {790#false} is VALID [2018-11-23 10:10:02,956 INFO L273 TraceCheckUtils]: 17: Hoare triple {977#(bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32))} ~a~0 := ~bvadd32(1bv32, ~a~0); {973#(bvslt main_~a~0 (_ bv100000 32))} is VALID [2018-11-23 10:10:02,956 INFO L273 TraceCheckUtils]: 16: Hoare triple {977#(bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {977#(bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:02,958 INFO L273 TraceCheckUtils]: 15: Hoare triple {977#(bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {977#(bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:02,963 INFO L273 TraceCheckUtils]: 14: Hoare triple {987#(bvslt (bvadd main_~a~0 (_ bv2 32)) (_ bv100000 32))} ~a~0 := ~bvadd32(1bv32, ~a~0); {977#(bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:02,964 INFO L273 TraceCheckUtils]: 13: Hoare triple {987#(bvslt (bvadd main_~a~0 (_ bv2 32)) (_ bv100000 32))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {987#(bvslt (bvadd main_~a~0 (_ bv2 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:02,965 INFO L273 TraceCheckUtils]: 12: Hoare triple {987#(bvslt (bvadd main_~a~0 (_ bv2 32)) (_ bv100000 32))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {987#(bvslt (bvadd main_~a~0 (_ bv2 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:02,971 INFO L273 TraceCheckUtils]: 11: Hoare triple {997#(bvslt (bvadd main_~a~0 (_ bv3 32)) (_ bv100000 32))} ~a~0 := ~bvadd32(1bv32, ~a~0); {987#(bvslt (bvadd main_~a~0 (_ bv2 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:02,972 INFO L273 TraceCheckUtils]: 10: Hoare triple {997#(bvslt (bvadd main_~a~0 (_ bv3 32)) (_ bv100000 32))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {997#(bvslt (bvadd main_~a~0 (_ bv3 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:02,973 INFO L273 TraceCheckUtils]: 9: Hoare triple {997#(bvslt (bvadd main_~a~0 (_ bv3 32)) (_ bv100000 32))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {997#(bvslt (bvadd main_~a~0 (_ bv3 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:02,980 INFO L273 TraceCheckUtils]: 8: Hoare triple {1007#(bvslt (bvadd main_~a~0 (_ bv4 32)) (_ bv100000 32))} ~a~0 := ~bvadd32(1bv32, ~a~0); {997#(bvslt (bvadd main_~a~0 (_ bv3 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:02,987 INFO L273 TraceCheckUtils]: 7: Hoare triple {1007#(bvslt (bvadd main_~a~0 (_ bv4 32)) (_ bv100000 32))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1007#(bvslt (bvadd main_~a~0 (_ bv4 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:02,988 INFO L273 TraceCheckUtils]: 6: Hoare triple {1007#(bvslt (bvadd main_~a~0 (_ bv4 32)) (_ bv100000 32))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1007#(bvslt (bvadd main_~a~0 (_ bv4 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:02,989 INFO L273 TraceCheckUtils]: 5: Hoare triple {789#true} call ~#aa~0.base, ~#aa~0.offset := #Ultimate.alloc(400000bv32);~a~0 := 0bv32;~b~0 := 0bv32;~c~0 := 0bv32;call ~#bb~0.base, ~#bb~0.offset := #Ultimate.alloc(400000bv32);havoc ~cc~0; {1007#(bvslt (bvadd main_~a~0 (_ bv4 32)) (_ bv100000 32))} is VALID [2018-11-23 10:10:02,989 INFO L256 TraceCheckUtils]: 4: Hoare triple {789#true} call #t~ret6 := main(); {789#true} is VALID [2018-11-23 10:10:02,989 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {789#true} {789#true} #75#return; {789#true} is VALID [2018-11-23 10:10:02,990 INFO L273 TraceCheckUtils]: 2: Hoare triple {789#true} assume true; {789#true} is VALID [2018-11-23 10:10:02,990 INFO L273 TraceCheckUtils]: 1: Hoare triple {789#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {789#true} is VALID [2018-11-23 10:10:02,991 INFO L256 TraceCheckUtils]: 0: Hoare triple {789#true} call ULTIMATE.init(); {789#true} is VALID [2018-11-23 10:10:02,995 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-23 10:10:02,998 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:10:02,998 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-11-23 10:10:02,998 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 39 [2018-11-23 10:10:03,000 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:10:03,000 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states. [2018-11-23 10:10:03,117 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 44 edges. 44 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:10:03,117 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-23 10:10:03,117 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-23 10:10:03,118 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-11-23 10:10:03,118 INFO L87 Difference]: Start difference. First operand 44 states and 54 transitions. Second operand 12 states. [2018-11-23 10:10:05,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:10:05,353 INFO L93 Difference]: Finished difference Result 105 states and 144 transitions. [2018-11-23 10:10:05,353 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 10:10:05,353 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 39 [2018-11-23 10:10:05,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:10:05,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-23 10:10:05,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 131 transitions. [2018-11-23 10:10:05,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-23 10:10:05,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 131 transitions. [2018-11-23 10:10:05,363 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states and 131 transitions. [2018-11-23 10:10:05,651 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 131 edges. 131 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:10:05,655 INFO L225 Difference]: With dead ends: 105 [2018-11-23 10:10:05,655 INFO L226 Difference]: Without dead ends: 80 [2018-11-23 10:10:05,656 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 81 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=94, Invalid=146, Unknown=0, NotChecked=0, Total=240 [2018-11-23 10:10:05,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-11-23 10:10:05,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 80. [2018-11-23 10:10:05,711 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:10:05,711 INFO L82 GeneralOperation]: Start isEquivalent. First operand 80 states. Second operand 80 states. [2018-11-23 10:10:05,711 INFO L74 IsIncluded]: Start isIncluded. First operand 80 states. Second operand 80 states. [2018-11-23 10:10:05,711 INFO L87 Difference]: Start difference. First operand 80 states. Second operand 80 states. [2018-11-23 10:10:05,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:10:05,716 INFO L93 Difference]: Finished difference Result 80 states and 102 transitions. [2018-11-23 10:10:05,716 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 102 transitions. [2018-11-23 10:10:05,717 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:10:05,717 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:10:05,717 INFO L74 IsIncluded]: Start isIncluded. First operand 80 states. Second operand 80 states. [2018-11-23 10:10:05,717 INFO L87 Difference]: Start difference. First operand 80 states. Second operand 80 states. [2018-11-23 10:10:05,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:10:05,722 INFO L93 Difference]: Finished difference Result 80 states and 102 transitions. [2018-11-23 10:10:05,723 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 102 transitions. [2018-11-23 10:10:05,724 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:10:05,724 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:10:05,724 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:10:05,724 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:10:05,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-11-23 10:10:05,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 102 transitions. [2018-11-23 10:10:05,729 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 102 transitions. Word has length 39 [2018-11-23 10:10:05,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:10:05,729 INFO L480 AbstractCegarLoop]: Abstraction has 80 states and 102 transitions. [2018-11-23 10:10:05,729 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-23 10:10:05,729 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 102 transitions. [2018-11-23 10:10:05,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2018-11-23 10:10:05,732 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:10:05,732 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:10:05,733 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:10:05,733 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:10:05,733 INFO L82 PathProgramCache]: Analyzing trace with hash -1565123340, now seen corresponding path program 3 times [2018-11-23 10:10:05,734 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:10:05,734 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:10:05,755 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2018-11-23 10:10:05,890 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-11-23 10:10:05,891 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:10:07,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unknown [2018-11-23 10:10:07,951 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:10:08,032 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-11-23 10:10:08,036 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-23 10:10:08,042 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:10:08,042 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:8, output treesize:4 [2018-11-23 10:10:08,241 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 36 [2018-11-23 10:10:08,249 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-11-23 10:10:08,253 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:10:08,273 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:10:08,299 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-11-23 10:10:08,299 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:42, output treesize:38 [2018-11-23 10:10:08,316 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:10:08,317 WARN L384 uantifierElimination]: Input elimination task: ∃ [|v_#memory_int_14|, |main_~#bb~0.base|, |main_~#bb~0.offset|, v_main_~b~0_13]. (let ((.cse0 (select (select |v_#memory_int_14| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))))) (and (bvsge .cse0 (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (= (store |v_#memory_int_14| |main_~#bb~0.base| (store (select |v_#memory_int_14| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13)) .cse0)) |#memory_int|) (bvslt main_~a~0 (_ bv100000 32)))) [2018-11-23 10:10:08,317 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ [|main_~#bb~0.base|, |main_~#bb~0.offset|, v_main_~b~0_13]. (let ((.cse0 (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))))) (and (bvsge .cse0 (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (= .cse0 (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13)))) (bvslt main_~a~0 (_ bv100000 32)))) [2018-11-23 10:10:09,754 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 40 [2018-11-23 10:10:09,776 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 1 [2018-11-23 10:10:09,781 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:10:09,853 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 21 [2018-11-23 10:10:09,862 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 2 xjuncts. [2018-11-23 10:10:09,878 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-23 10:10:09,948 INFO L267 ElimStorePlain]: Start of recursive call 1: 6 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-11-23 10:10:09,949 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 7 variables, input treesize:60, output treesize:34 [2018-11-23 10:10:09,964 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:10:09,965 WARN L384 uantifierElimination]: Input elimination task: ∃ [|#memory_int|, |main_~#bb~0.base|, |main_~#bb~0.offset|, v_main_~b~0_13, |main_~#aa~0.base|, |main_~#aa~0.offset|, v_prenex_1]. (let ((.cse0 (select |#memory_int| |main_~#aa~0.base|))) (let ((.cse1 (select .cse0 (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) v_prenex_1) (_ bv4294967292 32))))) (and (= (select .cse0 (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) |main_#t~mem2|) (bvsge .cse1 (_ bv0 32)) (bvslt (bvadd v_prenex_1 (_ bv4294967295 32)) (_ bv100000 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (not (bvslt v_prenex_1 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) .cse1) (bvslt main_~a~0 (_ bv100000 32))))) [2018-11-23 10:10:09,965 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ [|main_~#aa~0.offset|, v_prenex_1]. (let ((.cse0 (bvslt main_~a~0 (_ bv100000 32)))) (or (and .cse0 (bvsge |main_#t~mem2| (_ bv0 32))) (and (bvslt (bvadd v_prenex_1 (_ bv4294967295 32)) (_ bv100000 32)) (not (bvslt v_prenex_1 (_ bv100000 32))) (not (= (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) v_prenex_1) (_ bv4294967292 32)) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0)))) .cse0))) [2018-11-23 10:10:10,402 INFO L256 TraceCheckUtils]: 0: Hoare triple {1453#true} call ULTIMATE.init(); {1453#true} is VALID [2018-11-23 10:10:10,402 INFO L273 TraceCheckUtils]: 1: Hoare triple {1453#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {1453#true} is VALID [2018-11-23 10:10:10,402 INFO L273 TraceCheckUtils]: 2: Hoare triple {1453#true} assume true; {1453#true} is VALID [2018-11-23 10:10:10,403 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1453#true} {1453#true} #75#return; {1453#true} is VALID [2018-11-23 10:10:10,403 INFO L256 TraceCheckUtils]: 4: Hoare triple {1453#true} call #t~ret6 := main(); {1453#true} is VALID [2018-11-23 10:10:10,428 INFO L273 TraceCheckUtils]: 5: Hoare triple {1453#true} call ~#aa~0.base, ~#aa~0.offset := #Ultimate.alloc(400000bv32);~a~0 := 0bv32;~b~0 := 0bv32;~c~0 := 0bv32;call ~#bb~0.base, ~#bb~0.offset := #Ultimate.alloc(400000bv32);havoc ~cc~0; {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,436 INFO L273 TraceCheckUtils]: 6: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,437 INFO L273 TraceCheckUtils]: 7: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,437 INFO L273 TraceCheckUtils]: 8: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,438 INFO L273 TraceCheckUtils]: 9: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,438 INFO L273 TraceCheckUtils]: 10: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,438 INFO L273 TraceCheckUtils]: 11: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,439 INFO L273 TraceCheckUtils]: 12: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,439 INFO L273 TraceCheckUtils]: 13: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,440 INFO L273 TraceCheckUtils]: 14: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,441 INFO L273 TraceCheckUtils]: 15: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,441 INFO L273 TraceCheckUtils]: 16: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,442 INFO L273 TraceCheckUtils]: 17: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,443 INFO L273 TraceCheckUtils]: 18: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,443 INFO L273 TraceCheckUtils]: 19: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,444 INFO L273 TraceCheckUtils]: 20: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,445 INFO L273 TraceCheckUtils]: 21: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,445 INFO L273 TraceCheckUtils]: 22: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,446 INFO L273 TraceCheckUtils]: 23: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,446 INFO L273 TraceCheckUtils]: 24: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,447 INFO L273 TraceCheckUtils]: 25: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,448 INFO L273 TraceCheckUtils]: 26: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,448 INFO L273 TraceCheckUtils]: 27: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,449 INFO L273 TraceCheckUtils]: 28: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,450 INFO L273 TraceCheckUtils]: 29: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,450 INFO L273 TraceCheckUtils]: 30: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,451 INFO L273 TraceCheckUtils]: 31: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,452 INFO L273 TraceCheckUtils]: 32: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} is VALID [2018-11-23 10:10:10,453 INFO L273 TraceCheckUtils]: 33: Hoare triple {1473#(not (= |main_~#bb~0.base| |main_~#aa~0.base|))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1558#(and (= (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) |main_#t~mem0|) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt main_~a~0 (_ bv100000 32)))} is VALID [2018-11-23 10:10:12,475 INFO L273 TraceCheckUtils]: 34: Hoare triple {1558#(and (= (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) |main_#t~mem0|) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt main_~a~0 (_ bv100000 32)))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1562#(and (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)) (bvslt main_~a~0 (_ bv100000 32)) (exists ((|main_~#bb~0.offset| (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (= (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13)))))))} is UNKNOWN [2018-11-23 10:10:13,642 INFO L273 TraceCheckUtils]: 35: Hoare triple {1562#(and (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)) (bvslt main_~a~0 (_ bv100000 32)) (exists ((|main_~#bb~0.offset| (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (= (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13)))))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1566#(and (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (exists ((|main_~#bb~0.offset| (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)))) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32)))} is VALID [2018-11-23 10:10:13,649 INFO L273 TraceCheckUtils]: 36: Hoare triple {1566#(and (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (exists ((|main_~#bb~0.offset| (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)))) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32)))} assume !~bvslt32(~a~0, 100000bv32); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,650 INFO L273 TraceCheckUtils]: 37: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} ~a~0 := 0bv32; {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,661 INFO L273 TraceCheckUtils]: 38: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,663 INFO L273 TraceCheckUtils]: 39: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,664 INFO L273 TraceCheckUtils]: 40: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,664 INFO L273 TraceCheckUtils]: 41: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,671 INFO L273 TraceCheckUtils]: 42: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,671 INFO L273 TraceCheckUtils]: 43: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,672 INFO L273 TraceCheckUtils]: 44: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,672 INFO L273 TraceCheckUtils]: 45: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,673 INFO L273 TraceCheckUtils]: 46: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,674 INFO L273 TraceCheckUtils]: 47: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,674 INFO L273 TraceCheckUtils]: 48: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,675 INFO L273 TraceCheckUtils]: 49: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,676 INFO L273 TraceCheckUtils]: 50: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,678 INFO L273 TraceCheckUtils]: 51: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,680 INFO L273 TraceCheckUtils]: 52: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,681 INFO L273 TraceCheckUtils]: 53: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,691 INFO L273 TraceCheckUtils]: 54: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,692 INFO L273 TraceCheckUtils]: 55: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,693 INFO L273 TraceCheckUtils]: 56: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,710 INFO L273 TraceCheckUtils]: 57: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,724 INFO L273 TraceCheckUtils]: 58: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,740 INFO L273 TraceCheckUtils]: 59: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,754 INFO L273 TraceCheckUtils]: 60: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,763 INFO L273 TraceCheckUtils]: 61: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,778 INFO L273 TraceCheckUtils]: 62: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,787 INFO L273 TraceCheckUtils]: 63: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:13,800 INFO L273 TraceCheckUtils]: 64: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} is VALID [2018-11-23 10:10:15,838 INFO L273 TraceCheckUtils]: 65: Hoare triple {1570#(exists ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~a~0 (_ BitVec 32)) (v_main_~b~0_13 (_ BitVec 32)) (|main_~#bb~0.base| (_ BitVec 32))) (and (not (bvslt main_~a~0 (_ bv100000 32))) (= (select (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) v_main_~b~0_13))) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32)))) (bvsge (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0) (_ bv4294967292 32))) (_ bv0 32)) (not (= |main_~#bb~0.base| |main_~#aa~0.base|)) (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1658#(or (and (bvslt main_~a~0 (_ bv100000 32)) (exists ((v_prenex_1 (_ BitVec 32))) (and (bvslt (bvadd v_prenex_1 (_ bv4294967295 32)) (_ bv100000 32)) (not (= (bvadd (bvmul (_ bv4 32) v_prenex_1) (_ bv4294967292 32)) (bvmul (_ bv4 32) main_~a~0))) (not (bvslt v_prenex_1 (_ bv100000 32)))))) (and (bvslt main_~a~0 (_ bv100000 32)) (bvsge |main_#t~mem2| (_ bv0 32))))} is UNKNOWN [2018-11-23 10:10:15,839 INFO L273 TraceCheckUtils]: 66: Hoare triple {1658#(or (and (bvslt main_~a~0 (_ bv100000 32)) (exists ((v_prenex_1 (_ BitVec 32))) (and (bvslt (bvadd v_prenex_1 (_ bv4294967295 32)) (_ bv100000 32)) (not (= (bvadd (bvmul (_ bv4 32) v_prenex_1) (_ bv4294967292 32)) (bvmul (_ bv4 32) main_~a~0))) (not (bvslt v_prenex_1 (_ bv100000 32)))))) (and (bvslt main_~a~0 (_ bv100000 32)) (bvsge |main_#t~mem2| (_ bv0 32))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1662#(and (bvslt main_~a~0 (_ bv100000 32)) (exists ((v_prenex_1 (_ BitVec 32))) (and (bvslt (bvadd v_prenex_1 (_ bv4294967295 32)) (_ bv100000 32)) (not (= (bvadd (bvmul (_ bv4 32) v_prenex_1) (_ bv4294967292 32)) (bvmul (_ bv4 32) main_~a~0))) (not (bvslt v_prenex_1 (_ bv100000 32))))))} is VALID [2018-11-23 10:10:15,851 INFO L273 TraceCheckUtils]: 67: Hoare triple {1662#(and (bvslt main_~a~0 (_ bv100000 32)) (exists ((v_prenex_1 (_ BitVec 32))) (and (bvslt (bvadd v_prenex_1 (_ bv4294967295 32)) (_ bv100000 32)) (not (= (bvadd (bvmul (_ bv4 32) v_prenex_1) (_ bv4294967292 32)) (bvmul (_ bv4 32) main_~a~0))) (not (bvslt v_prenex_1 (_ bv100000 32))))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1666#(and (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32)) (exists ((v_prenex_1 (_ BitVec 32))) (and (bvslt (bvadd v_prenex_1 (_ bv4294967295 32)) (_ bv100000 32)) (not (bvslt v_prenex_1 (_ bv100000 32))) (not (= (bvmul (_ bv4 32) v_prenex_1) (bvmul (_ bv4 32) main_~a~0))))))} is VALID [2018-11-23 10:10:15,857 INFO L273 TraceCheckUtils]: 68: Hoare triple {1666#(and (bvslt (bvadd main_~a~0 (_ bv4294967295 32)) (_ bv100000 32)) (exists ((v_prenex_1 (_ BitVec 32))) (and (bvslt (bvadd v_prenex_1 (_ bv4294967295 32)) (_ bv100000 32)) (not (bvslt v_prenex_1 (_ bv100000 32))) (not (= (bvmul (_ bv4 32) v_prenex_1) (bvmul (_ bv4 32) main_~a~0))))))} assume !~bvslt32(~a~0, 100000bv32); {1454#false} is VALID [2018-11-23 10:10:15,857 INFO L273 TraceCheckUtils]: 69: Hoare triple {1454#false} havoc ~x~0;~x~0 := 0bv32; {1454#false} is VALID [2018-11-23 10:10:15,858 INFO L273 TraceCheckUtils]: 70: Hoare triple {1454#false} assume !!~bvslt32(~x~0, ~b~0);call #t~mem5 := read~intINTTYPE4(~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {1454#false} is VALID [2018-11-23 10:10:15,858 INFO L256 TraceCheckUtils]: 71: Hoare triple {1454#false} call __VERIFIER_assert((if ~bvsge32(#t~mem5, 0bv32) then 1bv32 else 0bv32)); {1454#false} is VALID [2018-11-23 10:10:15,858 INFO L273 TraceCheckUtils]: 72: Hoare triple {1454#false} ~cond := #in~cond; {1454#false} is VALID [2018-11-23 10:10:15,858 INFO L273 TraceCheckUtils]: 73: Hoare triple {1454#false} assume 0bv32 == ~cond; {1454#false} is VALID [2018-11-23 10:10:15,858 INFO L273 TraceCheckUtils]: 74: Hoare triple {1454#false} assume !false; {1454#false} is VALID [2018-11-23 10:10:15,898 INFO L134 CoverageAnalysis]: Checked inductivity of 290 backedges. 9 proven. 47 refuted. 0 times theorem prover too weak. 234 trivial. 0 not checked. [2018-11-23 10:10:15,898 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:11:36,403 WARN L180 SmtUtils]: Spent 58.47 s on a formula simplification. DAG size of input: 42 DAG size of output: 39 [2018-11-23 10:11:38,427 INFO L303 Elim1Store]: Index analysis took 2017 ms [2018-11-23 10:11:38,428 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2018-11-23 10:11:42,468 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (= (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0)) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) v_prenex_2))) [2018-11-23 10:11:42,471 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:11:42,473 INFO L303 Elim1Store]: Index analysis took 4040 ms [2018-11-23 10:11:42,474 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 21 [2018-11-23 10:11:42,476 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:11:42,510 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:11:44,531 INFO L303 Elim1Store]: Index analysis took 2011 ms [2018-11-23 10:11:44,532 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2018-11-23 10:11:48,583 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (= (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0)) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) v_prenex_2))) [2018-11-23 10:11:48,587 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:11:48,588 INFO L303 Elim1Store]: Index analysis took 4053 ms [2018-11-23 10:11:48,589 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 21 [2018-11-23 10:11:48,591 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 10:11:48,594 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:11:48,594 INFO L267 ElimStorePlain]: Start of recursive call 1: 5 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:11:48,595 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 6 variables, input treesize:63, output treesize:1 [2018-11-23 10:11:50,615 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:11:50,615 WARN L384 uantifierElimination]: Input elimination task: ∀ [|#memory_int|, |main_~#aa~0.offset|, main_~a~0, |main_~#bb~0.offset|, main_~b~0, v_prenex_2]. (let ((.cse0 (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (bvslt (bvadd v_prenex_2 (_ bv1 32)) (_ bv100000 32)) (not (bvslt v_prenex_2 (_ bv100000 32))) (not (bvslt (select (select (store |#memory_int| |main_~#bb~0.base| (store (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) main_~b~0)) .cse0)) |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) v_prenex_2))) (_ bv0 32))) (not (bvsge .cse0 (_ bv0 32))))) [2018-11-23 10:11:50,615 WARN L385 uantifierElimination]: ElimStorePlain result: ∀ []. true [2018-11-23 10:11:50,644 INFO L273 TraceCheckUtils]: 74: Hoare triple {1454#false} assume !false; {1454#false} is VALID [2018-11-23 10:11:50,644 INFO L273 TraceCheckUtils]: 73: Hoare triple {1454#false} assume 0bv32 == ~cond; {1454#false} is VALID [2018-11-23 10:11:50,644 INFO L273 TraceCheckUtils]: 72: Hoare triple {1454#false} ~cond := #in~cond; {1454#false} is VALID [2018-11-23 10:11:50,644 INFO L256 TraceCheckUtils]: 71: Hoare triple {1454#false} call __VERIFIER_assert((if ~bvsge32(#t~mem5, 0bv32) then 1bv32 else 0bv32)); {1454#false} is VALID [2018-11-23 10:11:50,644 INFO L273 TraceCheckUtils]: 70: Hoare triple {1454#false} assume !!~bvslt32(~x~0, ~b~0);call #t~mem5 := read~intINTTYPE4(~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~x~0)), 4bv32); {1454#false} is VALID [2018-11-23 10:11:50,645 INFO L273 TraceCheckUtils]: 69: Hoare triple {1454#false} havoc ~x~0;~x~0 := 0bv32; {1454#false} is VALID [2018-11-23 10:11:50,645 INFO L273 TraceCheckUtils]: 68: Hoare triple {1706#(bvslt main_~a~0 (_ bv100000 32))} assume !~bvslt32(~a~0, 100000bv32); {1454#false} is VALID [2018-11-23 10:11:50,646 INFO L273 TraceCheckUtils]: 67: Hoare triple {1710#(bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1706#(bvslt main_~a~0 (_ bv100000 32))} is VALID [2018-11-23 10:11:50,647 INFO L273 TraceCheckUtils]: 66: Hoare triple {1714#(or (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt |main_#t~mem2| (_ bv0 32))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1710#(bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32))} is VALID [2018-11-23 10:11:50,649 INFO L273 TraceCheckUtils]: 65: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1714#(or (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt |main_#t~mem2| (_ bv0 32))))} is VALID [2018-11-23 10:11:50,650 INFO L273 TraceCheckUtils]: 64: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,650 INFO L273 TraceCheckUtils]: 63: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,651 INFO L273 TraceCheckUtils]: 62: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,651 INFO L273 TraceCheckUtils]: 61: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,651 INFO L273 TraceCheckUtils]: 60: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,652 INFO L273 TraceCheckUtils]: 59: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,652 INFO L273 TraceCheckUtils]: 58: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,653 INFO L273 TraceCheckUtils]: 57: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,653 INFO L273 TraceCheckUtils]: 56: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,654 INFO L273 TraceCheckUtils]: 55: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,655 INFO L273 TraceCheckUtils]: 54: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,655 INFO L273 TraceCheckUtils]: 53: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,656 INFO L273 TraceCheckUtils]: 52: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,656 INFO L273 TraceCheckUtils]: 51: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,657 INFO L273 TraceCheckUtils]: 50: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,658 INFO L273 TraceCheckUtils]: 49: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,658 INFO L273 TraceCheckUtils]: 48: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,659 INFO L273 TraceCheckUtils]: 47: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,661 INFO L273 TraceCheckUtils]: 46: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,664 INFO L273 TraceCheckUtils]: 45: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,668 INFO L273 TraceCheckUtils]: 44: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,669 INFO L273 TraceCheckUtils]: 43: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,670 INFO L273 TraceCheckUtils]: 42: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,674 INFO L273 TraceCheckUtils]: 41: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,675 INFO L273 TraceCheckUtils]: 40: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,675 INFO L273 TraceCheckUtils]: 39: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume ~bvslt32(#t~mem2, 0bv32);havoc #t~mem2;call #t~mem3 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);~cc~0 := ~cc~0[~c~0 := #t~mem3];havoc #t~mem3;~c~0 := ~bvadd32(1bv32, ~c~0); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,676 INFO L273 TraceCheckUtils]: 38: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem2 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,676 INFO L273 TraceCheckUtils]: 37: Hoare triple {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} ~a~0 := 0bv32; {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,679 INFO L273 TraceCheckUtils]: 36: Hoare triple {1806#(or (bvslt main_~a~0 (_ bv100000 32)) (forall ((v_prenex_2 (_ BitVec 32))) (or (bvslt (bvadd v_prenex_2 (_ bv1 32)) (_ bv100000 32)) (not (bvslt v_prenex_2 (_ bv100000 32))) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) v_prenex_2))) (_ bv0 32))))))} assume !~bvslt32(~a~0, 100000bv32); {1718#(forall ((main_~a~0 (_ BitVec 32))) (or (not (bvslt main_~a~0 (_ bv100000 32))) (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))) (_ bv0 32)))))} is VALID [2018-11-23 10:11:50,680 INFO L273 TraceCheckUtils]: 35: Hoare triple {1810#(or (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (forall ((v_prenex_2 (_ BitVec 32))) (or (bvslt (bvadd v_prenex_2 (_ bv1 32)) (_ bv100000 32)) (not (bvslt v_prenex_2 (_ bv100000 32))) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) v_prenex_2))) (_ bv0 32))))))} ~a~0 := ~bvadd32(1bv32, ~a~0); {1806#(or (bvslt main_~a~0 (_ bv100000 32)) (forall ((v_prenex_2 (_ BitVec 32))) (or (bvslt (bvadd v_prenex_2 (_ bv1 32)) (_ bv100000 32)) (not (bvslt v_prenex_2 (_ bv100000 32))) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) v_prenex_2))) (_ bv0 32))))))} is VALID [2018-11-23 10:11:52,697 INFO L273 TraceCheckUtils]: 34: Hoare triple {1814#(or (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvsge |main_#t~mem0| (_ bv0 32))) (forall ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~b~0 (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (or (bvslt (bvadd v_prenex_2 (_ bv1 32)) (_ bv100000 32)) (not (bvslt v_prenex_2 (_ bv100000 32))) (not (bvslt (select (select (store |#memory_int| |main_~#bb~0.base| (store (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) main_~b~0)) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))))) |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) v_prenex_2))) (_ bv0 32))))))} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1810#(or (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (forall ((v_prenex_2 (_ BitVec 32))) (or (bvslt (bvadd v_prenex_2 (_ bv1 32)) (_ bv100000 32)) (not (bvslt v_prenex_2 (_ bv100000 32))) (not (bvslt (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) v_prenex_2))) (_ bv0 32))))))} is UNKNOWN [2018-11-23 10:11:54,725 INFO L273 TraceCheckUtils]: 33: Hoare triple {1453#true} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1814#(or (bvslt (bvadd main_~a~0 (_ bv1 32)) (_ bv100000 32)) (not (bvsge |main_#t~mem0| (_ bv0 32))) (forall ((|main_~#bb~0.offset| (_ BitVec 32)) (main_~b~0 (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (or (bvslt (bvadd v_prenex_2 (_ bv1 32)) (_ bv100000 32)) (not (bvslt v_prenex_2 (_ bv100000 32))) (not (bvslt (select (select (store |#memory_int| |main_~#bb~0.base| (store (select |#memory_int| |main_~#bb~0.base|) (bvadd |main_~#bb~0.offset| (bvmul (_ bv4 32) main_~b~0)) (select (select |#memory_int| |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) main_~a~0))))) |main_~#aa~0.base|) (bvadd |main_~#aa~0.offset| (bvmul (_ bv4 32) v_prenex_2))) (_ bv0 32))))))} is UNKNOWN [2018-11-23 10:11:54,725 INFO L273 TraceCheckUtils]: 32: Hoare triple {1453#true} ~a~0 := ~bvadd32(1bv32, ~a~0); {1453#true} is VALID [2018-11-23 10:11:54,726 INFO L273 TraceCheckUtils]: 31: Hoare triple {1453#true} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1453#true} is VALID [2018-11-23 10:11:54,726 INFO L273 TraceCheckUtils]: 30: Hoare triple {1453#true} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1453#true} is VALID [2018-11-23 10:11:54,726 INFO L273 TraceCheckUtils]: 29: Hoare triple {1453#true} ~a~0 := ~bvadd32(1bv32, ~a~0); {1453#true} is VALID [2018-11-23 10:11:54,726 INFO L273 TraceCheckUtils]: 28: Hoare triple {1453#true} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1453#true} is VALID [2018-11-23 10:11:54,726 INFO L273 TraceCheckUtils]: 27: Hoare triple {1453#true} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1453#true} is VALID [2018-11-23 10:11:54,726 INFO L273 TraceCheckUtils]: 26: Hoare triple {1453#true} ~a~0 := ~bvadd32(1bv32, ~a~0); {1453#true} is VALID [2018-11-23 10:11:54,727 INFO L273 TraceCheckUtils]: 25: Hoare triple {1453#true} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1453#true} is VALID [2018-11-23 10:11:54,727 INFO L273 TraceCheckUtils]: 24: Hoare triple {1453#true} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1453#true} is VALID [2018-11-23 10:11:54,727 INFO L273 TraceCheckUtils]: 23: Hoare triple {1453#true} ~a~0 := ~bvadd32(1bv32, ~a~0); {1453#true} is VALID [2018-11-23 10:11:54,727 INFO L273 TraceCheckUtils]: 22: Hoare triple {1453#true} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1453#true} is VALID [2018-11-23 10:11:54,727 INFO L273 TraceCheckUtils]: 21: Hoare triple {1453#true} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1453#true} is VALID [2018-11-23 10:11:54,727 INFO L273 TraceCheckUtils]: 20: Hoare triple {1453#true} ~a~0 := ~bvadd32(1bv32, ~a~0); {1453#true} is VALID [2018-11-23 10:11:54,727 INFO L273 TraceCheckUtils]: 19: Hoare triple {1453#true} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1453#true} is VALID [2018-11-23 10:11:54,728 INFO L273 TraceCheckUtils]: 18: Hoare triple {1453#true} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1453#true} is VALID [2018-11-23 10:11:54,728 INFO L273 TraceCheckUtils]: 17: Hoare triple {1453#true} ~a~0 := ~bvadd32(1bv32, ~a~0); {1453#true} is VALID [2018-11-23 10:11:54,728 INFO L273 TraceCheckUtils]: 16: Hoare triple {1453#true} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1453#true} is VALID [2018-11-23 10:11:54,728 INFO L273 TraceCheckUtils]: 15: Hoare triple {1453#true} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1453#true} is VALID [2018-11-23 10:11:54,728 INFO L273 TraceCheckUtils]: 14: Hoare triple {1453#true} ~a~0 := ~bvadd32(1bv32, ~a~0); {1453#true} is VALID [2018-11-23 10:11:54,728 INFO L273 TraceCheckUtils]: 13: Hoare triple {1453#true} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1453#true} is VALID [2018-11-23 10:11:54,729 INFO L273 TraceCheckUtils]: 12: Hoare triple {1453#true} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1453#true} is VALID [2018-11-23 10:11:54,729 INFO L273 TraceCheckUtils]: 11: Hoare triple {1453#true} ~a~0 := ~bvadd32(1bv32, ~a~0); {1453#true} is VALID [2018-11-23 10:11:54,729 INFO L273 TraceCheckUtils]: 10: Hoare triple {1453#true} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1453#true} is VALID [2018-11-23 10:11:54,729 INFO L273 TraceCheckUtils]: 9: Hoare triple {1453#true} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1453#true} is VALID [2018-11-23 10:11:54,729 INFO L273 TraceCheckUtils]: 8: Hoare triple {1453#true} ~a~0 := ~bvadd32(1bv32, ~a~0); {1453#true} is VALID [2018-11-23 10:11:54,730 INFO L273 TraceCheckUtils]: 7: Hoare triple {1453#true} assume ~bvsge32(#t~mem0, 0bv32);havoc #t~mem0;call #t~mem1 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32);call write~intINTTYPE4(#t~mem1, ~#bb~0.base, ~bvadd32(~#bb~0.offset, ~bvmul32(4bv32, ~b~0)), 4bv32);havoc #t~mem1;~b~0 := ~bvadd32(1bv32, ~b~0); {1453#true} is VALID [2018-11-23 10:11:54,730 INFO L273 TraceCheckUtils]: 6: Hoare triple {1453#true} assume !!~bvslt32(~a~0, 100000bv32);call #t~mem0 := read~intINTTYPE4(~#aa~0.base, ~bvadd32(~#aa~0.offset, ~bvmul32(4bv32, ~a~0)), 4bv32); {1453#true} is VALID [2018-11-23 10:11:54,730 INFO L273 TraceCheckUtils]: 5: Hoare triple {1453#true} call ~#aa~0.base, ~#aa~0.offset := #Ultimate.alloc(400000bv32);~a~0 := 0bv32;~b~0 := 0bv32;~c~0 := 0bv32;call ~#bb~0.base, ~#bb~0.offset := #Ultimate.alloc(400000bv32);havoc ~cc~0; {1453#true} is VALID [2018-11-23 10:11:54,730 INFO L256 TraceCheckUtils]: 4: Hoare triple {1453#true} call #t~ret6 := main(); {1453#true} is VALID [2018-11-23 10:11:54,731 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1453#true} {1453#true} #75#return; {1453#true} is VALID [2018-11-23 10:11:54,731 INFO L273 TraceCheckUtils]: 2: Hoare triple {1453#true} assume true; {1453#true} is VALID [2018-11-23 10:11:54,731 INFO L273 TraceCheckUtils]: 1: Hoare triple {1453#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {1453#true} is VALID [2018-11-23 10:11:54,731 INFO L256 TraceCheckUtils]: 0: Hoare triple {1453#true} call ULTIMATE.init(); {1453#true} is VALID [2018-11-23 10:11:54,755 INFO L134 CoverageAnalysis]: Checked inductivity of 290 backedges. 28 proven. 28 refuted. 0 times theorem prover too weak. 234 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (6)] Exception during sending of exit command (exit): Broken pipe [2018-11-23 10:11:54,759 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:11:54,759 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 17 [2018-11-23 10:11:54,761 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 75 [2018-11-23 10:11:54,766 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:11:54,766 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 17 states. [2018-11-23 10:12:09,538 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 43 edges. 36 inductive. 0 not inductive. 7 times theorem prover too weak to decide inductivity. [2018-11-23 10:12:09,538 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-23 10:12:09,538 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-23 10:12:09,539 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=211, Unknown=7, NotChecked=0, Total=272 [2018-11-23 10:12:09,539 INFO L87 Difference]: Start difference. First operand 80 states and 102 transitions. Second operand 17 states. [2018-11-23 10:12:10,066 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 29 DAG size of output: 28 [2018-11-23 10:12:10,473 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 36 DAG size of output: 35 [2018-11-23 10:12:11,163 WARN L180 SmtUtils]: Spent 239.00 ms on a formula simplification. DAG size of input: 45 DAG size of output: 44 [2018-11-23 10:12:29,142 WARN L180 SmtUtils]: Spent 16.40 s on a formula simplification. DAG size of input: 68 DAG size of output: 67 [2018-11-23 10:12:45,586 WARN L180 SmtUtils]: Spent 16.30 s on a formula simplification. DAG size of input: 57 DAG size of output: 56 [2018-11-23 10:13:02,704 WARN L180 SmtUtils]: Spent 12.62 s on a formula simplification. DAG size of input: 70 DAG size of output: 54 [2018-11-23 10:13:09,512 WARN L180 SmtUtils]: Spent 6.15 s on a formula simplification that was a NOOP. DAG size: 44 [2018-11-23 10:13:18,293 WARN L180 SmtUtils]: Spent 8.18 s on a formula simplification that was a NOOP. DAG size: 58 [2018-11-23 10:13:26,529 WARN L180 SmtUtils]: Spent 8.11 s on a formula simplification that was a NOOP. DAG size: 44 [2018-11-23 10:13:45,047 WARN L180 SmtUtils]: Spent 14.27 s on a formula simplification. DAG size of input: 57 DAG size of output: 42