java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerCInline_WitnessPrinter.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf -i ../../../trunk/examples/svcomp/ldv-regression/test24_false-unreach-call.c -------------------------------------------------------------------------------- This is Ultimate 0.1.23-61f4311 [2018-11-23 11:07:04,083 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 11:07:04,085 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 11:07:04,098 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 11:07:04,098 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 11:07:04,099 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 11:07:04,101 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 11:07:04,103 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 11:07:04,105 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 11:07:04,105 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 11:07:04,106 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 11:07:04,107 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 11:07:04,108 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 11:07:04,109 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 11:07:04,110 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 11:07:04,111 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 11:07:04,112 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 11:07:04,114 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 11:07:04,116 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 11:07:04,118 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 11:07:04,119 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 11:07:04,120 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 11:07:04,123 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 11:07:04,123 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 11:07:04,123 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 11:07:04,125 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 11:07:04,126 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 11:07:04,127 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 11:07:04,127 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 11:07:04,129 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 11:07:04,129 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 11:07:04,130 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 11:07:04,130 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 11:07:04,131 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 11:07:04,132 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 11:07:04,133 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 11:07:04,133 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-23 11:07:04,149 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 11:07:04,150 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 11:07:04,150 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 11:07:04,151 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 11:07:04,151 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 11:07:04,152 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 11:07:04,152 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 11:07:04,152 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 11:07:04,152 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 11:07:04,152 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 11:07:04,153 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 11:07:04,153 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 11:07:04,153 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 11:07:04,153 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 11:07:04,153 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-23 11:07:04,153 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-23 11:07:04,154 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 11:07:04,154 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 11:07:04,154 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 11:07:04,154 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 11:07:04,155 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 11:07:04,155 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 11:07:04,155 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 11:07:04,155 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 11:07:04,155 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 11:07:04,156 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 11:07:04,156 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 11:07:04,156 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 11:07:04,156 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-23 11:07:04,156 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 11:07:04,157 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-23 11:07:04,157 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-23 11:07:04,157 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 11:07:04,204 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 11:07:04,224 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 11:07:04,228 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 11:07:04,229 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 11:07:04,230 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 11:07:04,230 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-regression/test24_false-unreach-call.c [2018-11-23 11:07:04,298 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8b90c6ca8/fbb00e8b7b094ae3a9c7f9c6a67d5290/FLAGfbcbec4c2 [2018-11-23 11:07:04,821 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 11:07:04,822 INFO L161 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/ldv-regression/test24_false-unreach-call.c [2018-11-23 11:07:04,830 INFO L355 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8b90c6ca8/fbb00e8b7b094ae3a9c7f9c6a67d5290/FLAGfbcbec4c2 [2018-11-23 11:07:05,123 INFO L363 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8b90c6ca8/fbb00e8b7b094ae3a9c7f9c6a67d5290 [2018-11-23 11:07:05,133 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 11:07:05,134 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 11:07:05,136 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 11:07:05,136 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 11:07:05,140 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 11:07:05,142 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 11:07:05" (1/1) ... [2018-11-23 11:07:05,145 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@43eddf43 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 11:07:05, skipping insertion in model container [2018-11-23 11:07:05,145 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 11:07:05" (1/1) ... [2018-11-23 11:07:05,156 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 11:07:05,186 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 11:07:05,428 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 11:07:05,443 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 11:07:05,475 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 11:07:05,501 INFO L195 MainTranslator]: Completed translation [2018-11-23 11:07:05,501 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 11:07:05 WrapperNode [2018-11-23 11:07:05,502 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 11:07:05,503 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 11:07:05,503 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 11:07:05,503 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 11:07:05,514 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 11:07:05" (1/1) ... [2018-11-23 11:07:05,528 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 11:07:05" (1/1) ... [2018-11-23 11:07:05,538 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 11:07:05,539 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 11:07:05,539 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 11:07:05,539 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 11:07:05,552 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 11:07:05" (1/1) ... [2018-11-23 11:07:05,552 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 11:07:05" (1/1) ... [2018-11-23 11:07:05,555 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 11:07:05" (1/1) ... [2018-11-23 11:07:05,556 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 11:07:05" (1/1) ... [2018-11-23 11:07:05,583 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 11:07:05" (1/1) ... [2018-11-23 11:07:05,596 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 11:07:05" (1/1) ... [2018-11-23 11:07:05,599 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 11:07:05" (1/1) ... [2018-11-23 11:07:05,606 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 11:07:05,607 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 11:07:05,607 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 11:07:05,607 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 11:07:05,610 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 11:07:05" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 11:07:05,751 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 11:07:05,751 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 11:07:05,751 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 11:07:05,752 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-23 11:07:05,752 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 11:07:05,752 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 11:07:05,752 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 11:07:05,752 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 11:07:05,753 INFO L130 BoogieDeclarations]: Found specification of procedure check [2018-11-23 11:07:05,753 INFO L138 BoogieDeclarations]: Found implementation of procedure check [2018-11-23 11:07:05,753 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 11:07:05,753 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-23 11:07:06,326 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 11:07:06,326 INFO L280 CfgBuilder]: Removed 2 assue(true) statements. [2018-11-23 11:07:06,326 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 11:07:06 BoogieIcfgContainer [2018-11-23 11:07:06,327 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 11:07:06,327 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 11:07:06,327 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 11:07:06,331 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 11:07:06,331 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 11:07:05" (1/3) ... [2018-11-23 11:07:06,332 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@67a22f7b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 11:07:06, skipping insertion in model container [2018-11-23 11:07:06,333 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 11:07:05" (2/3) ... [2018-11-23 11:07:06,333 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@67a22f7b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 11:07:06, skipping insertion in model container [2018-11-23 11:07:06,333 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 11:07:06" (3/3) ... [2018-11-23 11:07:06,335 INFO L112 eAbstractionObserver]: Analyzing ICFG test24_false-unreach-call.c [2018-11-23 11:07:06,347 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 11:07:06,359 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 11:07:06,383 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 11:07:06,427 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 11:07:06,428 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 11:07:06,428 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 11:07:06,428 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 11:07:06,430 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 11:07:06,430 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 11:07:06,430 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 11:07:06,431 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 11:07:06,431 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 11:07:06,455 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states. [2018-11-23 11:07:06,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-11-23 11:07:06,462 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 11:07:06,463 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 11:07:06,465 INFO L423 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 11:07:06,471 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 11:07:06,472 INFO L82 PathProgramCache]: Analyzing trace with hash -1543897818, now seen corresponding path program 1 times [2018-11-23 11:07:06,476 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 11:07:06,477 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 11:07:06,503 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 11:07:06,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 11:07:06,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 11:07:06,586 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 11:07:06,905 INFO L256 TraceCheckUtils]: 0: Hoare triple {27#true} call ULTIMATE.init(); {27#true} is VALID [2018-11-23 11:07:06,910 INFO L273 TraceCheckUtils]: 1: Hoare triple {27#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {27#true} is VALID [2018-11-23 11:07:06,911 INFO L273 TraceCheckUtils]: 2: Hoare triple {27#true} assume true; {27#true} is VALID [2018-11-23 11:07:06,912 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {27#true} {27#true} #52#return; {27#true} is VALID [2018-11-23 11:07:06,912 INFO L256 TraceCheckUtils]: 4: Hoare triple {27#true} call #t~ret9 := main(); {27#true} is VALID [2018-11-23 11:07:06,913 INFO L273 TraceCheckUtils]: 5: Hoare triple {27#true} call ~#ad1~0.base, ~#ad1~0.offset := #Ultimate.alloc(160bv32);havoc ~ad2~0.base, ~ad2~0.offset;havoc ~i~0;havoc ~j~0;havoc ~pa~0.base, ~pa~0.offset;~j~0 := 0bv32; {27#true} is VALID [2018-11-23 11:07:06,926 INFO L273 TraceCheckUtils]: 6: Hoare triple {27#true} assume !true; {28#false} is VALID [2018-11-23 11:07:06,927 INFO L273 TraceCheckUtils]: 7: Hoare triple {28#false} ~i~0 := #t~nondet4;havoc #t~nondet4; {28#false} is VALID [2018-11-23 11:07:06,927 INFO L273 TraceCheckUtils]: 8: Hoare triple {28#false} assume ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32);~ad2~0.base, ~ad2~0.offset := ~#ad1~0.base, ~#ad1~0.offset;call write~intINTTYPE4(~i~0, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~pa~0.base, ~pa~0.offset := ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0));call #t~mem5 := read~intINTTYPE4(~ad2~0.base, ~bvadd32(~ad2~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(10bv32, #t~mem5);havoc #t~mem5; {28#false} is VALID [2018-11-23 11:07:06,927 INFO L273 TraceCheckUtils]: 9: Hoare triple {28#false} assume !true; {28#false} is VALID [2018-11-23 11:07:06,928 INFO L256 TraceCheckUtils]: 10: Hoare triple {28#false} call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); {28#false} is VALID [2018-11-23 11:07:06,928 INFO L273 TraceCheckUtils]: 11: Hoare triple {28#false} ~ad1.base, ~ad1.offset := #in~ad1.base, #in~ad1.offset;~b := #in~b;call #t~mem0 := read~intINTTYPE4(~ad1.base, ~bvadd32(~ad1.offset, ~bvmul32(8bv32, ~b)), 4bv32);#res := (if #t~mem0 == ~b then 1bv32 else 0bv32);havoc #t~mem0; {28#false} is VALID [2018-11-23 11:07:06,928 INFO L273 TraceCheckUtils]: 12: Hoare triple {28#false} assume true; {28#false} is VALID [2018-11-23 11:07:06,929 INFO L268 TraceCheckUtils]: 13: Hoare quadruple {28#false} {28#false} #56#return; {28#false} is VALID [2018-11-23 11:07:06,929 INFO L273 TraceCheckUtils]: 14: Hoare triple {28#false} assume 0bv32 == #t~ret8;havoc #t~ret8; {28#false} is VALID [2018-11-23 11:07:06,929 INFO L273 TraceCheckUtils]: 15: Hoare triple {28#false} assume !false; {28#false} is VALID [2018-11-23 11:07:06,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 11:07:06,933 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (2)] Exception during sending of exit command (exit): Broken pipe [2018-11-23 11:07:06,940 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 11:07:06,940 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 11:07:06,946 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 16 [2018-11-23 11:07:06,950 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 11:07:06,956 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states. [2018-11-23 11:07:07,098 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 11:07:07,098 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-23 11:07:07,106 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-23 11:07:07,106 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-23 11:07:07,109 INFO L87 Difference]: Start difference. First operand 24 states. Second operand 2 states. [2018-11-23 11:07:07,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:07,333 INFO L93 Difference]: Finished difference Result 40 states and 48 transitions. [2018-11-23 11:07:07,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-23 11:07:07,334 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 16 [2018-11-23 11:07:07,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 11:07:07,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-23 11:07:07,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 48 transitions. [2018-11-23 11:07:07,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-23 11:07:07,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 48 transitions. [2018-11-23 11:07:07,359 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states and 48 transitions. [2018-11-23 11:07:07,515 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 48 edges. 48 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 11:07:07,527 INFO L225 Difference]: With dead ends: 40 [2018-11-23 11:07:07,528 INFO L226 Difference]: Without dead ends: 19 [2018-11-23 11:07:07,531 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-23 11:07:07,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-11-23 11:07:07,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2018-11-23 11:07:07,627 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 11:07:07,627 INFO L82 GeneralOperation]: Start isEquivalent. First operand 19 states. Second operand 19 states. [2018-11-23 11:07:07,628 INFO L74 IsIncluded]: Start isIncluded. First operand 19 states. Second operand 19 states. [2018-11-23 11:07:07,628 INFO L87 Difference]: Start difference. First operand 19 states. Second operand 19 states. [2018-11-23 11:07:07,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:07,632 INFO L93 Difference]: Finished difference Result 19 states and 20 transitions. [2018-11-23 11:07:07,632 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 20 transitions. [2018-11-23 11:07:07,633 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 11:07:07,633 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 11:07:07,633 INFO L74 IsIncluded]: Start isIncluded. First operand 19 states. Second operand 19 states. [2018-11-23 11:07:07,633 INFO L87 Difference]: Start difference. First operand 19 states. Second operand 19 states. [2018-11-23 11:07:07,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:07,637 INFO L93 Difference]: Finished difference Result 19 states and 20 transitions. [2018-11-23 11:07:07,638 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 20 transitions. [2018-11-23 11:07:07,638 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 11:07:07,638 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 11:07:07,639 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 11:07:07,639 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 11:07:07,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2018-11-23 11:07:07,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 20 transitions. [2018-11-23 11:07:07,643 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 20 transitions. Word has length 16 [2018-11-23 11:07:07,644 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 11:07:07,644 INFO L480 AbstractCegarLoop]: Abstraction has 19 states and 20 transitions. [2018-11-23 11:07:07,644 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-23 11:07:07,644 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 20 transitions. [2018-11-23 11:07:07,645 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-23 11:07:07,645 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 11:07:07,645 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 11:07:07,646 INFO L423 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 11:07:07,646 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 11:07:07,646 INFO L82 PathProgramCache]: Analyzing trace with hash 1718744263, now seen corresponding path program 1 times [2018-11-23 11:07:07,647 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 11:07:07,647 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 11:07:07,669 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 11:07:07,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 11:07:07,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 11:07:07,725 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 11:07:07,786 INFO L256 TraceCheckUtils]: 0: Hoare triple {195#true} call ULTIMATE.init(); {195#true} is VALID [2018-11-23 11:07:07,787 INFO L273 TraceCheckUtils]: 1: Hoare triple {195#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {195#true} is VALID [2018-11-23 11:07:07,787 INFO L273 TraceCheckUtils]: 2: Hoare triple {195#true} assume true; {195#true} is VALID [2018-11-23 11:07:07,787 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {195#true} {195#true} #52#return; {195#true} is VALID [2018-11-23 11:07:07,787 INFO L256 TraceCheckUtils]: 4: Hoare triple {195#true} call #t~ret9 := main(); {195#true} is VALID [2018-11-23 11:07:07,789 INFO L273 TraceCheckUtils]: 5: Hoare triple {195#true} call ~#ad1~0.base, ~#ad1~0.offset := #Ultimate.alloc(160bv32);havoc ~ad2~0.base, ~ad2~0.offset;havoc ~i~0;havoc ~j~0;havoc ~pa~0.base, ~pa~0.offset;~j~0 := 0bv32; {215#(= main_~j~0 (_ bv0 32))} is VALID [2018-11-23 11:07:07,790 INFO L273 TraceCheckUtils]: 6: Hoare triple {215#(= main_~j~0 (_ bv0 32))} assume !~bvslt32(~j~0, 20bv32); {196#false} is VALID [2018-11-23 11:07:07,790 INFO L273 TraceCheckUtils]: 7: Hoare triple {196#false} ~i~0 := #t~nondet4;havoc #t~nondet4; {196#false} is VALID [2018-11-23 11:07:07,791 INFO L273 TraceCheckUtils]: 8: Hoare triple {196#false} assume ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32);~ad2~0.base, ~ad2~0.offset := ~#ad1~0.base, ~#ad1~0.offset;call write~intINTTYPE4(~i~0, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~pa~0.base, ~pa~0.offset := ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0));call #t~mem5 := read~intINTTYPE4(~ad2~0.base, ~bvadd32(~ad2~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(10bv32, #t~mem5);havoc #t~mem5; {196#false} is VALID [2018-11-23 11:07:07,791 INFO L273 TraceCheckUtils]: 9: Hoare triple {196#false} call #t~mem6 := read~intINTTYPE4(~pa~0.base, ~pa~0.offset, 4bv32); {196#false} is VALID [2018-11-23 11:07:07,792 INFO L273 TraceCheckUtils]: 10: Hoare triple {196#false} assume !~bvslt32(~i~0, #t~mem6);havoc #t~mem6; {196#false} is VALID [2018-11-23 11:07:07,792 INFO L256 TraceCheckUtils]: 11: Hoare triple {196#false} call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); {196#false} is VALID [2018-11-23 11:07:07,793 INFO L273 TraceCheckUtils]: 12: Hoare triple {196#false} ~ad1.base, ~ad1.offset := #in~ad1.base, #in~ad1.offset;~b := #in~b;call #t~mem0 := read~intINTTYPE4(~ad1.base, ~bvadd32(~ad1.offset, ~bvmul32(8bv32, ~b)), 4bv32);#res := (if #t~mem0 == ~b then 1bv32 else 0bv32);havoc #t~mem0; {196#false} is VALID [2018-11-23 11:07:07,793 INFO L273 TraceCheckUtils]: 13: Hoare triple {196#false} assume true; {196#false} is VALID [2018-11-23 11:07:07,793 INFO L268 TraceCheckUtils]: 14: Hoare quadruple {196#false} {196#false} #56#return; {196#false} is VALID [2018-11-23 11:07:07,793 INFO L273 TraceCheckUtils]: 15: Hoare triple {196#false} assume 0bv32 == #t~ret8;havoc #t~ret8; {196#false} is VALID [2018-11-23 11:07:07,794 INFO L273 TraceCheckUtils]: 16: Hoare triple {196#false} assume !false; {196#false} is VALID [2018-11-23 11:07:07,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 11:07:07,796 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 11:07:07,803 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 11:07:07,804 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 11:07:07,805 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 17 [2018-11-23 11:07:07,806 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 11:07:07,806 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-23 11:07:07,850 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 11:07:07,850 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 11:07:07,851 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 11:07:07,851 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 11:07:07,851 INFO L87 Difference]: Start difference. First operand 19 states and 20 transitions. Second operand 3 states. [2018-11-23 11:07:08,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:08,149 INFO L93 Difference]: Finished difference Result 32 states and 34 transitions. [2018-11-23 11:07:08,149 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 11:07:08,150 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 17 [2018-11-23 11:07:08,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 11:07:08,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 11:07:08,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 34 transitions. [2018-11-23 11:07:08,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 11:07:08,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 34 transitions. [2018-11-23 11:07:08,160 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 34 transitions. [2018-11-23 11:07:08,397 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 34 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 11:07:08,399 INFO L225 Difference]: With dead ends: 32 [2018-11-23 11:07:08,399 INFO L226 Difference]: Without dead ends: 21 [2018-11-23 11:07:08,400 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 11:07:08,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2018-11-23 11:07:08,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 20. [2018-11-23 11:07:08,418 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 11:07:08,419 INFO L82 GeneralOperation]: Start isEquivalent. First operand 21 states. Second operand 20 states. [2018-11-23 11:07:08,419 INFO L74 IsIncluded]: Start isIncluded. First operand 21 states. Second operand 20 states. [2018-11-23 11:07:08,419 INFO L87 Difference]: Start difference. First operand 21 states. Second operand 20 states. [2018-11-23 11:07:08,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:08,421 INFO L93 Difference]: Finished difference Result 21 states and 22 transitions. [2018-11-23 11:07:08,422 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 22 transitions. [2018-11-23 11:07:08,422 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 11:07:08,422 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 11:07:08,422 INFO L74 IsIncluded]: Start isIncluded. First operand 20 states. Second operand 21 states. [2018-11-23 11:07:08,423 INFO L87 Difference]: Start difference. First operand 20 states. Second operand 21 states. [2018-11-23 11:07:08,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:08,425 INFO L93 Difference]: Finished difference Result 21 states and 22 transitions. [2018-11-23 11:07:08,425 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 22 transitions. [2018-11-23 11:07:08,426 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 11:07:08,426 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 11:07:08,426 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 11:07:08,426 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 11:07:08,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-11-23 11:07:08,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 21 transitions. [2018-11-23 11:07:08,428 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 21 transitions. Word has length 17 [2018-11-23 11:07:08,429 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 11:07:08,429 INFO L480 AbstractCegarLoop]: Abstraction has 20 states and 21 transitions. [2018-11-23 11:07:08,429 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 11:07:08,429 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 21 transitions. [2018-11-23 11:07:08,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-11-23 11:07:08,430 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 11:07:08,430 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 11:07:08,430 INFO L423 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 11:07:08,431 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 11:07:08,431 INFO L82 PathProgramCache]: Analyzing trace with hash 1681398309, now seen corresponding path program 1 times [2018-11-23 11:07:08,432 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 11:07:08,432 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 11:07:08,452 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 11:07:08,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 11:07:08,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 11:07:08,511 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 11:07:08,710 INFO L256 TraceCheckUtils]: 0: Hoare triple {366#true} call ULTIMATE.init(); {366#true} is VALID [2018-11-23 11:07:08,710 INFO L273 TraceCheckUtils]: 1: Hoare triple {366#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {366#true} is VALID [2018-11-23 11:07:08,710 INFO L273 TraceCheckUtils]: 2: Hoare triple {366#true} assume true; {366#true} is VALID [2018-11-23 11:07:08,711 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {366#true} {366#true} #52#return; {366#true} is VALID [2018-11-23 11:07:08,711 INFO L256 TraceCheckUtils]: 4: Hoare triple {366#true} call #t~ret9 := main(); {366#true} is VALID [2018-11-23 11:07:08,712 INFO L273 TraceCheckUtils]: 5: Hoare triple {366#true} call ~#ad1~0.base, ~#ad1~0.offset := #Ultimate.alloc(160bv32);havoc ~ad2~0.base, ~ad2~0.offset;havoc ~i~0;havoc ~j~0;havoc ~pa~0.base, ~pa~0.offset;~j~0 := 0bv32; {386#(= main_~j~0 (_ bv0 32))} is VALID [2018-11-23 11:07:08,713 INFO L273 TraceCheckUtils]: 6: Hoare triple {386#(= main_~j~0 (_ bv0 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {386#(= main_~j~0 (_ bv0 32))} is VALID [2018-11-23 11:07:08,714 INFO L273 TraceCheckUtils]: 7: Hoare triple {386#(= main_~j~0 (_ bv0 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {393#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:08,715 INFO L273 TraceCheckUtils]: 8: Hoare triple {393#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !~bvslt32(~j~0, 20bv32); {367#false} is VALID [2018-11-23 11:07:08,716 INFO L273 TraceCheckUtils]: 9: Hoare triple {367#false} ~i~0 := #t~nondet4;havoc #t~nondet4; {367#false} is VALID [2018-11-23 11:07:08,716 INFO L273 TraceCheckUtils]: 10: Hoare triple {367#false} assume ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32);~ad2~0.base, ~ad2~0.offset := ~#ad1~0.base, ~#ad1~0.offset;call write~intINTTYPE4(~i~0, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~pa~0.base, ~pa~0.offset := ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0));call #t~mem5 := read~intINTTYPE4(~ad2~0.base, ~bvadd32(~ad2~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(10bv32, #t~mem5);havoc #t~mem5; {367#false} is VALID [2018-11-23 11:07:08,717 INFO L273 TraceCheckUtils]: 11: Hoare triple {367#false} call #t~mem6 := read~intINTTYPE4(~pa~0.base, ~pa~0.offset, 4bv32); {367#false} is VALID [2018-11-23 11:07:08,717 INFO L273 TraceCheckUtils]: 12: Hoare triple {367#false} assume !~bvslt32(~i~0, #t~mem6);havoc #t~mem6; {367#false} is VALID [2018-11-23 11:07:08,718 INFO L256 TraceCheckUtils]: 13: Hoare triple {367#false} call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); {367#false} is VALID [2018-11-23 11:07:08,718 INFO L273 TraceCheckUtils]: 14: Hoare triple {367#false} ~ad1.base, ~ad1.offset := #in~ad1.base, #in~ad1.offset;~b := #in~b;call #t~mem0 := read~intINTTYPE4(~ad1.base, ~bvadd32(~ad1.offset, ~bvmul32(8bv32, ~b)), 4bv32);#res := (if #t~mem0 == ~b then 1bv32 else 0bv32);havoc #t~mem0; {367#false} is VALID [2018-11-23 11:07:08,719 INFO L273 TraceCheckUtils]: 15: Hoare triple {367#false} assume true; {367#false} is VALID [2018-11-23 11:07:08,719 INFO L268 TraceCheckUtils]: 16: Hoare quadruple {367#false} {367#false} #56#return; {367#false} is VALID [2018-11-23 11:07:08,720 INFO L273 TraceCheckUtils]: 17: Hoare triple {367#false} assume 0bv32 == #t~ret8;havoc #t~ret8; {367#false} is VALID [2018-11-23 11:07:08,720 INFO L273 TraceCheckUtils]: 18: Hoare triple {367#false} assume !false; {367#false} is VALID [2018-11-23 11:07:08,721 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 11:07:08,721 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 11:07:08,962 INFO L273 TraceCheckUtils]: 18: Hoare triple {367#false} assume !false; {367#false} is VALID [2018-11-23 11:07:08,962 INFO L273 TraceCheckUtils]: 17: Hoare triple {367#false} assume 0bv32 == #t~ret8;havoc #t~ret8; {367#false} is VALID [2018-11-23 11:07:08,962 INFO L268 TraceCheckUtils]: 16: Hoare quadruple {366#true} {367#false} #56#return; {367#false} is VALID [2018-11-23 11:07:08,963 INFO L273 TraceCheckUtils]: 15: Hoare triple {366#true} assume true; {366#true} is VALID [2018-11-23 11:07:08,963 INFO L273 TraceCheckUtils]: 14: Hoare triple {366#true} ~ad1.base, ~ad1.offset := #in~ad1.base, #in~ad1.offset;~b := #in~b;call #t~mem0 := read~intINTTYPE4(~ad1.base, ~bvadd32(~ad1.offset, ~bvmul32(8bv32, ~b)), 4bv32);#res := (if #t~mem0 == ~b then 1bv32 else 0bv32);havoc #t~mem0; {366#true} is VALID [2018-11-23 11:07:08,963 INFO L256 TraceCheckUtils]: 13: Hoare triple {367#false} call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); {366#true} is VALID [2018-11-23 11:07:08,964 INFO L273 TraceCheckUtils]: 12: Hoare triple {367#false} assume !~bvslt32(~i~0, #t~mem6);havoc #t~mem6; {367#false} is VALID [2018-11-23 11:07:08,964 INFO L273 TraceCheckUtils]: 11: Hoare triple {367#false} call #t~mem6 := read~intINTTYPE4(~pa~0.base, ~pa~0.offset, 4bv32); {367#false} is VALID [2018-11-23 11:07:08,964 INFO L273 TraceCheckUtils]: 10: Hoare triple {367#false} assume ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32);~ad2~0.base, ~ad2~0.offset := ~#ad1~0.base, ~#ad1~0.offset;call write~intINTTYPE4(~i~0, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~pa~0.base, ~pa~0.offset := ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0));call #t~mem5 := read~intINTTYPE4(~ad2~0.base, ~bvadd32(~ad2~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(10bv32, #t~mem5);havoc #t~mem5; {367#false} is VALID [2018-11-23 11:07:08,964 INFO L273 TraceCheckUtils]: 9: Hoare triple {367#false} ~i~0 := #t~nondet4;havoc #t~nondet4; {367#false} is VALID [2018-11-23 11:07:08,966 INFO L273 TraceCheckUtils]: 8: Hoare triple {457#(bvslt main_~j~0 (_ bv20 32))} assume !~bvslt32(~j~0, 20bv32); {367#false} is VALID [2018-11-23 11:07:08,968 INFO L273 TraceCheckUtils]: 7: Hoare triple {461#(bvslt (bvadd main_~j~0 (_ bv1 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {457#(bvslt main_~j~0 (_ bv20 32))} is VALID [2018-11-23 11:07:08,971 INFO L273 TraceCheckUtils]: 6: Hoare triple {461#(bvslt (bvadd main_~j~0 (_ bv1 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {461#(bvslt (bvadd main_~j~0 (_ bv1 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:08,972 INFO L273 TraceCheckUtils]: 5: Hoare triple {366#true} call ~#ad1~0.base, ~#ad1~0.offset := #Ultimate.alloc(160bv32);havoc ~ad2~0.base, ~ad2~0.offset;havoc ~i~0;havoc ~j~0;havoc ~pa~0.base, ~pa~0.offset;~j~0 := 0bv32; {461#(bvslt (bvadd main_~j~0 (_ bv1 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:08,973 INFO L256 TraceCheckUtils]: 4: Hoare triple {366#true} call #t~ret9 := main(); {366#true} is VALID [2018-11-23 11:07:08,973 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {366#true} {366#true} #52#return; {366#true} is VALID [2018-11-23 11:07:08,973 INFO L273 TraceCheckUtils]: 2: Hoare triple {366#true} assume true; {366#true} is VALID [2018-11-23 11:07:08,973 INFO L273 TraceCheckUtils]: 1: Hoare triple {366#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {366#true} is VALID [2018-11-23 11:07:08,974 INFO L256 TraceCheckUtils]: 0: Hoare triple {366#true} call ULTIMATE.init(); {366#true} is VALID [2018-11-23 11:07:08,975 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 11:07:08,979 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 11:07:08,979 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 6 [2018-11-23 11:07:08,979 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2018-11-23 11:07:08,980 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 11:07:08,980 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states. [2018-11-23 11:07:09,057 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 27 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 11:07:09,057 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 11:07:09,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 11:07:09,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-23 11:07:09,058 INFO L87 Difference]: Start difference. First operand 20 states and 21 transitions. Second operand 6 states. [2018-11-23 11:07:09,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:09,435 INFO L93 Difference]: Finished difference Result 37 states and 41 transitions. [2018-11-23 11:07:09,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 11:07:09,436 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2018-11-23 11:07:09,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 11:07:09,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-23 11:07:09,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 41 transitions. [2018-11-23 11:07:09,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-23 11:07:09,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 41 transitions. [2018-11-23 11:07:09,448 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 41 transitions. [2018-11-23 11:07:09,591 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 41 edges. 41 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 11:07:09,592 INFO L225 Difference]: With dead ends: 37 [2018-11-23 11:07:09,592 INFO L226 Difference]: Without dead ends: 26 [2018-11-23 11:07:09,593 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2018-11-23 11:07:09,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2018-11-23 11:07:09,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2018-11-23 11:07:09,610 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 11:07:09,610 INFO L82 GeneralOperation]: Start isEquivalent. First operand 26 states. Second operand 26 states. [2018-11-23 11:07:09,610 INFO L74 IsIncluded]: Start isIncluded. First operand 26 states. Second operand 26 states. [2018-11-23 11:07:09,610 INFO L87 Difference]: Start difference. First operand 26 states. Second operand 26 states. [2018-11-23 11:07:09,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:09,613 INFO L93 Difference]: Finished difference Result 26 states and 27 transitions. [2018-11-23 11:07:09,613 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 27 transitions. [2018-11-23 11:07:09,614 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 11:07:09,614 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 11:07:09,614 INFO L74 IsIncluded]: Start isIncluded. First operand 26 states. Second operand 26 states. [2018-11-23 11:07:09,614 INFO L87 Difference]: Start difference. First operand 26 states. Second operand 26 states. [2018-11-23 11:07:09,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:09,617 INFO L93 Difference]: Finished difference Result 26 states and 27 transitions. [2018-11-23 11:07:09,617 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 27 transitions. [2018-11-23 11:07:09,618 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 11:07:09,618 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 11:07:09,618 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 11:07:09,618 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 11:07:09,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-11-23 11:07:09,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 27 transitions. [2018-11-23 11:07:09,620 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 27 transitions. Word has length 19 [2018-11-23 11:07:09,621 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 11:07:09,621 INFO L480 AbstractCegarLoop]: Abstraction has 26 states and 27 transitions. [2018-11-23 11:07:09,621 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 11:07:09,621 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 27 transitions. [2018-11-23 11:07:09,622 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-23 11:07:09,622 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 11:07:09,622 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 11:07:09,623 INFO L423 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 11:07:09,623 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 11:07:09,623 INFO L82 PathProgramCache]: Analyzing trace with hash -2034053825, now seen corresponding path program 2 times [2018-11-23 11:07:09,624 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 11:07:09,624 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 11:07:09,648 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 11:07:09,721 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 11:07:09,721 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 11:07:09,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 11:07:09,741 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 11:07:09,919 INFO L256 TraceCheckUtils]: 0: Hoare triple {632#true} call ULTIMATE.init(); {632#true} is VALID [2018-11-23 11:07:09,920 INFO L273 TraceCheckUtils]: 1: Hoare triple {632#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {632#true} is VALID [2018-11-23 11:07:09,920 INFO L273 TraceCheckUtils]: 2: Hoare triple {632#true} assume true; {632#true} is VALID [2018-11-23 11:07:09,921 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {632#true} {632#true} #52#return; {632#true} is VALID [2018-11-23 11:07:09,921 INFO L256 TraceCheckUtils]: 4: Hoare triple {632#true} call #t~ret9 := main(); {632#true} is VALID [2018-11-23 11:07:09,923 INFO L273 TraceCheckUtils]: 5: Hoare triple {632#true} call ~#ad1~0.base, ~#ad1~0.offset := #Ultimate.alloc(160bv32);havoc ~ad2~0.base, ~ad2~0.offset;havoc ~i~0;havoc ~j~0;havoc ~pa~0.base, ~pa~0.offset;~j~0 := 0bv32; {652#(= main_~j~0 (_ bv0 32))} is VALID [2018-11-23 11:07:09,923 INFO L273 TraceCheckUtils]: 6: Hoare triple {652#(= main_~j~0 (_ bv0 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {652#(= main_~j~0 (_ bv0 32))} is VALID [2018-11-23 11:07:09,925 INFO L273 TraceCheckUtils]: 7: Hoare triple {652#(= main_~j~0 (_ bv0 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {659#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:09,925 INFO L273 TraceCheckUtils]: 8: Hoare triple {659#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {659#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:09,927 INFO L273 TraceCheckUtils]: 9: Hoare triple {659#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {666#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:09,927 INFO L273 TraceCheckUtils]: 10: Hoare triple {666#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {666#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:09,929 INFO L273 TraceCheckUtils]: 11: Hoare triple {666#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {673#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:09,931 INFO L273 TraceCheckUtils]: 12: Hoare triple {673#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {673#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:09,933 INFO L273 TraceCheckUtils]: 13: Hoare triple {673#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {680#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:09,933 INFO L273 TraceCheckUtils]: 14: Hoare triple {680#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume !~bvslt32(~j~0, 20bv32); {633#false} is VALID [2018-11-23 11:07:09,934 INFO L273 TraceCheckUtils]: 15: Hoare triple {633#false} ~i~0 := #t~nondet4;havoc #t~nondet4; {633#false} is VALID [2018-11-23 11:07:09,934 INFO L273 TraceCheckUtils]: 16: Hoare triple {633#false} assume ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32);~ad2~0.base, ~ad2~0.offset := ~#ad1~0.base, ~#ad1~0.offset;call write~intINTTYPE4(~i~0, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~pa~0.base, ~pa~0.offset := ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0));call #t~mem5 := read~intINTTYPE4(~ad2~0.base, ~bvadd32(~ad2~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(10bv32, #t~mem5);havoc #t~mem5; {633#false} is VALID [2018-11-23 11:07:09,934 INFO L273 TraceCheckUtils]: 17: Hoare triple {633#false} call #t~mem6 := read~intINTTYPE4(~pa~0.base, ~pa~0.offset, 4bv32); {633#false} is VALID [2018-11-23 11:07:09,935 INFO L273 TraceCheckUtils]: 18: Hoare triple {633#false} assume !~bvslt32(~i~0, #t~mem6);havoc #t~mem6; {633#false} is VALID [2018-11-23 11:07:09,935 INFO L256 TraceCheckUtils]: 19: Hoare triple {633#false} call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); {633#false} is VALID [2018-11-23 11:07:09,935 INFO L273 TraceCheckUtils]: 20: Hoare triple {633#false} ~ad1.base, ~ad1.offset := #in~ad1.base, #in~ad1.offset;~b := #in~b;call #t~mem0 := read~intINTTYPE4(~ad1.base, ~bvadd32(~ad1.offset, ~bvmul32(8bv32, ~b)), 4bv32);#res := (if #t~mem0 == ~b then 1bv32 else 0bv32);havoc #t~mem0; {633#false} is VALID [2018-11-23 11:07:09,936 INFO L273 TraceCheckUtils]: 21: Hoare triple {633#false} assume true; {633#false} is VALID [2018-11-23 11:07:09,936 INFO L268 TraceCheckUtils]: 22: Hoare quadruple {633#false} {633#false} #56#return; {633#false} is VALID [2018-11-23 11:07:09,936 INFO L273 TraceCheckUtils]: 23: Hoare triple {633#false} assume 0bv32 == #t~ret8;havoc #t~ret8; {633#false} is VALID [2018-11-23 11:07:09,937 INFO L273 TraceCheckUtils]: 24: Hoare triple {633#false} assume !false; {633#false} is VALID [2018-11-23 11:07:09,938 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 11:07:09,938 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 11:07:10,275 INFO L273 TraceCheckUtils]: 24: Hoare triple {633#false} assume !false; {633#false} is VALID [2018-11-23 11:07:10,276 INFO L273 TraceCheckUtils]: 23: Hoare triple {633#false} assume 0bv32 == #t~ret8;havoc #t~ret8; {633#false} is VALID [2018-11-23 11:07:10,276 INFO L268 TraceCheckUtils]: 22: Hoare quadruple {632#true} {633#false} #56#return; {633#false} is VALID [2018-11-23 11:07:10,276 INFO L273 TraceCheckUtils]: 21: Hoare triple {632#true} assume true; {632#true} is VALID [2018-11-23 11:07:10,277 INFO L273 TraceCheckUtils]: 20: Hoare triple {632#true} ~ad1.base, ~ad1.offset := #in~ad1.base, #in~ad1.offset;~b := #in~b;call #t~mem0 := read~intINTTYPE4(~ad1.base, ~bvadd32(~ad1.offset, ~bvmul32(8bv32, ~b)), 4bv32);#res := (if #t~mem0 == ~b then 1bv32 else 0bv32);havoc #t~mem0; {632#true} is VALID [2018-11-23 11:07:10,277 INFO L256 TraceCheckUtils]: 19: Hoare triple {633#false} call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); {632#true} is VALID [2018-11-23 11:07:10,277 INFO L273 TraceCheckUtils]: 18: Hoare triple {633#false} assume !~bvslt32(~i~0, #t~mem6);havoc #t~mem6; {633#false} is VALID [2018-11-23 11:07:10,277 INFO L273 TraceCheckUtils]: 17: Hoare triple {633#false} call #t~mem6 := read~intINTTYPE4(~pa~0.base, ~pa~0.offset, 4bv32); {633#false} is VALID [2018-11-23 11:07:10,278 INFO L273 TraceCheckUtils]: 16: Hoare triple {633#false} assume ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32);~ad2~0.base, ~ad2~0.offset := ~#ad1~0.base, ~#ad1~0.offset;call write~intINTTYPE4(~i~0, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~pa~0.base, ~pa~0.offset := ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0));call #t~mem5 := read~intINTTYPE4(~ad2~0.base, ~bvadd32(~ad2~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(10bv32, #t~mem5);havoc #t~mem5; {633#false} is VALID [2018-11-23 11:07:10,278 INFO L273 TraceCheckUtils]: 15: Hoare triple {633#false} ~i~0 := #t~nondet4;havoc #t~nondet4; {633#false} is VALID [2018-11-23 11:07:10,282 INFO L273 TraceCheckUtils]: 14: Hoare triple {744#(bvslt main_~j~0 (_ bv20 32))} assume !~bvslt32(~j~0, 20bv32); {633#false} is VALID [2018-11-23 11:07:10,283 INFO L273 TraceCheckUtils]: 13: Hoare triple {748#(bvslt (bvadd main_~j~0 (_ bv1 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {744#(bvslt main_~j~0 (_ bv20 32))} is VALID [2018-11-23 11:07:10,284 INFO L273 TraceCheckUtils]: 12: Hoare triple {748#(bvslt (bvadd main_~j~0 (_ bv1 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {748#(bvslt (bvadd main_~j~0 (_ bv1 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:10,287 INFO L273 TraceCheckUtils]: 11: Hoare triple {755#(bvslt (bvadd main_~j~0 (_ bv2 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {748#(bvslt (bvadd main_~j~0 (_ bv1 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:10,288 INFO L273 TraceCheckUtils]: 10: Hoare triple {755#(bvslt (bvadd main_~j~0 (_ bv2 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {755#(bvslt (bvadd main_~j~0 (_ bv2 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:10,292 INFO L273 TraceCheckUtils]: 9: Hoare triple {762#(bvslt (bvadd main_~j~0 (_ bv3 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {755#(bvslt (bvadd main_~j~0 (_ bv2 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:10,293 INFO L273 TraceCheckUtils]: 8: Hoare triple {762#(bvslt (bvadd main_~j~0 (_ bv3 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {762#(bvslt (bvadd main_~j~0 (_ bv3 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:10,297 INFO L273 TraceCheckUtils]: 7: Hoare triple {769#(bvslt (bvadd main_~j~0 (_ bv4 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {762#(bvslt (bvadd main_~j~0 (_ bv3 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:10,297 INFO L273 TraceCheckUtils]: 6: Hoare triple {769#(bvslt (bvadd main_~j~0 (_ bv4 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {769#(bvslt (bvadd main_~j~0 (_ bv4 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:10,298 INFO L273 TraceCheckUtils]: 5: Hoare triple {632#true} call ~#ad1~0.base, ~#ad1~0.offset := #Ultimate.alloc(160bv32);havoc ~ad2~0.base, ~ad2~0.offset;havoc ~i~0;havoc ~j~0;havoc ~pa~0.base, ~pa~0.offset;~j~0 := 0bv32; {769#(bvslt (bvadd main_~j~0 (_ bv4 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:10,298 INFO L256 TraceCheckUtils]: 4: Hoare triple {632#true} call #t~ret9 := main(); {632#true} is VALID [2018-11-23 11:07:10,299 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {632#true} {632#true} #52#return; {632#true} is VALID [2018-11-23 11:07:10,299 INFO L273 TraceCheckUtils]: 2: Hoare triple {632#true} assume true; {632#true} is VALID [2018-11-23 11:07:10,299 INFO L273 TraceCheckUtils]: 1: Hoare triple {632#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {632#true} is VALID [2018-11-23 11:07:10,299 INFO L256 TraceCheckUtils]: 0: Hoare triple {632#true} call ULTIMATE.init(); {632#true} is VALID [2018-11-23 11:07:10,301 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 11:07:10,311 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 11:07:10,311 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-11-23 11:07:10,312 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 25 [2018-11-23 11:07:10,313 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 11:07:10,313 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states. [2018-11-23 11:07:10,569 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 39 edges. 39 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 11:07:10,570 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-23 11:07:10,570 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-23 11:07:10,570 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-11-23 11:07:10,571 INFO L87 Difference]: Start difference. First operand 26 states and 27 transitions. Second operand 12 states. [2018-11-23 11:07:11,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:11,471 INFO L93 Difference]: Finished difference Result 49 states and 56 transitions. [2018-11-23 11:07:11,472 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 11:07:11,472 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 25 [2018-11-23 11:07:11,472 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 11:07:11,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-23 11:07:11,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 56 transitions. [2018-11-23 11:07:11,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-23 11:07:11,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 56 transitions. [2018-11-23 11:07:11,478 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states and 56 transitions. [2018-11-23 11:07:11,651 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 56 edges. 56 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 11:07:11,653 INFO L225 Difference]: With dead ends: 49 [2018-11-23 11:07:11,653 INFO L226 Difference]: Without dead ends: 38 [2018-11-23 11:07:11,654 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=94, Invalid=146, Unknown=0, NotChecked=0, Total=240 [2018-11-23 11:07:11,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2018-11-23 11:07:11,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 38. [2018-11-23 11:07:11,673 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 11:07:11,673 INFO L82 GeneralOperation]: Start isEquivalent. First operand 38 states. Second operand 38 states. [2018-11-23 11:07:11,673 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand 38 states. [2018-11-23 11:07:11,674 INFO L87 Difference]: Start difference. First operand 38 states. Second operand 38 states. [2018-11-23 11:07:11,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:11,677 INFO L93 Difference]: Finished difference Result 38 states and 39 transitions. [2018-11-23 11:07:11,678 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 39 transitions. [2018-11-23 11:07:11,678 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 11:07:11,678 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 11:07:11,679 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand 38 states. [2018-11-23 11:07:11,679 INFO L87 Difference]: Start difference. First operand 38 states. Second operand 38 states. [2018-11-23 11:07:11,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:11,682 INFO L93 Difference]: Finished difference Result 38 states and 39 transitions. [2018-11-23 11:07:11,682 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 39 transitions. [2018-11-23 11:07:11,682 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 11:07:11,683 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 11:07:11,683 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 11:07:11,683 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 11:07:11,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-11-23 11:07:11,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 39 transitions. [2018-11-23 11:07:11,686 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 39 transitions. Word has length 25 [2018-11-23 11:07:11,686 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 11:07:11,686 INFO L480 AbstractCegarLoop]: Abstraction has 38 states and 39 transitions. [2018-11-23 11:07:11,686 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-23 11:07:11,686 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 39 transitions. [2018-11-23 11:07:11,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-11-23 11:07:11,688 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 11:07:11,688 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 11:07:11,688 INFO L423 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 11:07:11,688 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 11:07:11,688 INFO L82 PathProgramCache]: Analyzing trace with hash -285073165, now seen corresponding path program 3 times [2018-11-23 11:07:11,689 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 11:07:11,689 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 11:07:11,711 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2018-11-23 11:07:12,849 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-11-23 11:07:12,849 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 11:07:12,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 11:07:12,879 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 11:07:13,086 INFO L256 TraceCheckUtils]: 0: Hoare triple {1006#true} call ULTIMATE.init(); {1006#true} is VALID [2018-11-23 11:07:13,087 INFO L273 TraceCheckUtils]: 1: Hoare triple {1006#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {1006#true} is VALID [2018-11-23 11:07:13,087 INFO L273 TraceCheckUtils]: 2: Hoare triple {1006#true} assume true; {1006#true} is VALID [2018-11-23 11:07:13,088 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1006#true} {1006#true} #52#return; {1006#true} is VALID [2018-11-23 11:07:13,088 INFO L256 TraceCheckUtils]: 4: Hoare triple {1006#true} call #t~ret9 := main(); {1006#true} is VALID [2018-11-23 11:07:13,089 INFO L273 TraceCheckUtils]: 5: Hoare triple {1006#true} call ~#ad1~0.base, ~#ad1~0.offset := #Ultimate.alloc(160bv32);havoc ~ad2~0.base, ~ad2~0.offset;havoc ~i~0;havoc ~j~0;havoc ~pa~0.base, ~pa~0.offset;~j~0 := 0bv32; {1026#(= main_~j~0 (_ bv0 32))} is VALID [2018-11-23 11:07:13,090 INFO L273 TraceCheckUtils]: 6: Hoare triple {1026#(= main_~j~0 (_ bv0 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1026#(= main_~j~0 (_ bv0 32))} is VALID [2018-11-23 11:07:13,093 INFO L273 TraceCheckUtils]: 7: Hoare triple {1026#(= main_~j~0 (_ bv0 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1033#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,093 INFO L273 TraceCheckUtils]: 8: Hoare triple {1033#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1033#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,094 INFO L273 TraceCheckUtils]: 9: Hoare triple {1033#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1040#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,094 INFO L273 TraceCheckUtils]: 10: Hoare triple {1040#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1040#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,095 INFO L273 TraceCheckUtils]: 11: Hoare triple {1040#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1047#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,095 INFO L273 TraceCheckUtils]: 12: Hoare triple {1047#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1047#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,096 INFO L273 TraceCheckUtils]: 13: Hoare triple {1047#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1054#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,096 INFO L273 TraceCheckUtils]: 14: Hoare triple {1054#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1054#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,097 INFO L273 TraceCheckUtils]: 15: Hoare triple {1054#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1061#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,097 INFO L273 TraceCheckUtils]: 16: Hoare triple {1061#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1061#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,099 INFO L273 TraceCheckUtils]: 17: Hoare triple {1061#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1068#(= (bvadd main_~j~0 (_ bv4294967290 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,099 INFO L273 TraceCheckUtils]: 18: Hoare triple {1068#(= (bvadd main_~j~0 (_ bv4294967290 32)) (_ bv0 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1068#(= (bvadd main_~j~0 (_ bv4294967290 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,100 INFO L273 TraceCheckUtils]: 19: Hoare triple {1068#(= (bvadd main_~j~0 (_ bv4294967290 32)) (_ bv0 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1075#(= (_ bv7 32) main_~j~0)} is VALID [2018-11-23 11:07:13,101 INFO L273 TraceCheckUtils]: 20: Hoare triple {1075#(= (_ bv7 32) main_~j~0)} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1075#(= (_ bv7 32) main_~j~0)} is VALID [2018-11-23 11:07:13,102 INFO L273 TraceCheckUtils]: 21: Hoare triple {1075#(= (_ bv7 32) main_~j~0)} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1082#(= (bvadd main_~j~0 (_ bv4294967288 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,103 INFO L273 TraceCheckUtils]: 22: Hoare triple {1082#(= (bvadd main_~j~0 (_ bv4294967288 32)) (_ bv0 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1082#(= (bvadd main_~j~0 (_ bv4294967288 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,104 INFO L273 TraceCheckUtils]: 23: Hoare triple {1082#(= (bvadd main_~j~0 (_ bv4294967288 32)) (_ bv0 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1089#(= (_ bv9 32) main_~j~0)} is VALID [2018-11-23 11:07:13,106 INFO L273 TraceCheckUtils]: 24: Hoare triple {1089#(= (_ bv9 32) main_~j~0)} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1089#(= (_ bv9 32) main_~j~0)} is VALID [2018-11-23 11:07:13,108 INFO L273 TraceCheckUtils]: 25: Hoare triple {1089#(= (_ bv9 32) main_~j~0)} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1096#(= (bvadd main_~j~0 (_ bv4294967286 32)) (_ bv0 32))} is VALID [2018-11-23 11:07:13,109 INFO L273 TraceCheckUtils]: 26: Hoare triple {1096#(= (bvadd main_~j~0 (_ bv4294967286 32)) (_ bv0 32))} assume !~bvslt32(~j~0, 20bv32); {1007#false} is VALID [2018-11-23 11:07:13,109 INFO L273 TraceCheckUtils]: 27: Hoare triple {1007#false} ~i~0 := #t~nondet4;havoc #t~nondet4; {1007#false} is VALID [2018-11-23 11:07:13,109 INFO L273 TraceCheckUtils]: 28: Hoare triple {1007#false} assume ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32);~ad2~0.base, ~ad2~0.offset := ~#ad1~0.base, ~#ad1~0.offset;call write~intINTTYPE4(~i~0, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~pa~0.base, ~pa~0.offset := ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0));call #t~mem5 := read~intINTTYPE4(~ad2~0.base, ~bvadd32(~ad2~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(10bv32, #t~mem5);havoc #t~mem5; {1007#false} is VALID [2018-11-23 11:07:13,110 INFO L273 TraceCheckUtils]: 29: Hoare triple {1007#false} call #t~mem6 := read~intINTTYPE4(~pa~0.base, ~pa~0.offset, 4bv32); {1007#false} is VALID [2018-11-23 11:07:13,110 INFO L273 TraceCheckUtils]: 30: Hoare triple {1007#false} assume !~bvslt32(~i~0, #t~mem6);havoc #t~mem6; {1007#false} is VALID [2018-11-23 11:07:13,110 INFO L256 TraceCheckUtils]: 31: Hoare triple {1007#false} call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); {1007#false} is VALID [2018-11-23 11:07:13,111 INFO L273 TraceCheckUtils]: 32: Hoare triple {1007#false} ~ad1.base, ~ad1.offset := #in~ad1.base, #in~ad1.offset;~b := #in~b;call #t~mem0 := read~intINTTYPE4(~ad1.base, ~bvadd32(~ad1.offset, ~bvmul32(8bv32, ~b)), 4bv32);#res := (if #t~mem0 == ~b then 1bv32 else 0bv32);havoc #t~mem0; {1007#false} is VALID [2018-11-23 11:07:13,111 INFO L273 TraceCheckUtils]: 33: Hoare triple {1007#false} assume true; {1007#false} is VALID [2018-11-23 11:07:13,112 INFO L268 TraceCheckUtils]: 34: Hoare quadruple {1007#false} {1007#false} #56#return; {1007#false} is VALID [2018-11-23 11:07:13,112 INFO L273 TraceCheckUtils]: 35: Hoare triple {1007#false} assume 0bv32 == #t~ret8;havoc #t~ret8; {1007#false} is VALID [2018-11-23 11:07:13,112 INFO L273 TraceCheckUtils]: 36: Hoare triple {1007#false} assume !false; {1007#false} is VALID [2018-11-23 11:07:13,116 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 11:07:13,116 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 11:07:13,810 INFO L273 TraceCheckUtils]: 36: Hoare triple {1007#false} assume !false; {1007#false} is VALID [2018-11-23 11:07:13,810 INFO L273 TraceCheckUtils]: 35: Hoare triple {1007#false} assume 0bv32 == #t~ret8;havoc #t~ret8; {1007#false} is VALID [2018-11-23 11:07:13,810 INFO L268 TraceCheckUtils]: 34: Hoare quadruple {1006#true} {1007#false} #56#return; {1007#false} is VALID [2018-11-23 11:07:13,811 INFO L273 TraceCheckUtils]: 33: Hoare triple {1006#true} assume true; {1006#true} is VALID [2018-11-23 11:07:13,811 INFO L273 TraceCheckUtils]: 32: Hoare triple {1006#true} ~ad1.base, ~ad1.offset := #in~ad1.base, #in~ad1.offset;~b := #in~b;call #t~mem0 := read~intINTTYPE4(~ad1.base, ~bvadd32(~ad1.offset, ~bvmul32(8bv32, ~b)), 4bv32);#res := (if #t~mem0 == ~b then 1bv32 else 0bv32);havoc #t~mem0; {1006#true} is VALID [2018-11-23 11:07:13,811 INFO L256 TraceCheckUtils]: 31: Hoare triple {1007#false} call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); {1006#true} is VALID [2018-11-23 11:07:13,812 INFO L273 TraceCheckUtils]: 30: Hoare triple {1007#false} assume !~bvslt32(~i~0, #t~mem6);havoc #t~mem6; {1007#false} is VALID [2018-11-23 11:07:13,812 INFO L273 TraceCheckUtils]: 29: Hoare triple {1007#false} call #t~mem6 := read~intINTTYPE4(~pa~0.base, ~pa~0.offset, 4bv32); {1007#false} is VALID [2018-11-23 11:07:13,812 INFO L273 TraceCheckUtils]: 28: Hoare triple {1007#false} assume ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32);~ad2~0.base, ~ad2~0.offset := ~#ad1~0.base, ~#ad1~0.offset;call write~intINTTYPE4(~i~0, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~pa~0.base, ~pa~0.offset := ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0));call #t~mem5 := read~intINTTYPE4(~ad2~0.base, ~bvadd32(~ad2~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(10bv32, #t~mem5);havoc #t~mem5; {1007#false} is VALID [2018-11-23 11:07:13,813 INFO L273 TraceCheckUtils]: 27: Hoare triple {1007#false} ~i~0 := #t~nondet4;havoc #t~nondet4; {1007#false} is VALID [2018-11-23 11:07:13,813 INFO L273 TraceCheckUtils]: 26: Hoare triple {1160#(bvslt main_~j~0 (_ bv20 32))} assume !~bvslt32(~j~0, 20bv32); {1007#false} is VALID [2018-11-23 11:07:13,814 INFO L273 TraceCheckUtils]: 25: Hoare triple {1164#(bvslt (bvadd main_~j~0 (_ bv1 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1160#(bvslt main_~j~0 (_ bv20 32))} is VALID [2018-11-23 11:07:13,814 INFO L273 TraceCheckUtils]: 24: Hoare triple {1164#(bvslt (bvadd main_~j~0 (_ bv1 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1164#(bvslt (bvadd main_~j~0 (_ bv1 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,818 INFO L273 TraceCheckUtils]: 23: Hoare triple {1171#(bvslt (bvadd main_~j~0 (_ bv2 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1164#(bvslt (bvadd main_~j~0 (_ bv1 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,818 INFO L273 TraceCheckUtils]: 22: Hoare triple {1171#(bvslt (bvadd main_~j~0 (_ bv2 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1171#(bvslt (bvadd main_~j~0 (_ bv2 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,822 INFO L273 TraceCheckUtils]: 21: Hoare triple {1178#(bvslt (bvadd main_~j~0 (_ bv3 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1171#(bvslt (bvadd main_~j~0 (_ bv2 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,823 INFO L273 TraceCheckUtils]: 20: Hoare triple {1178#(bvslt (bvadd main_~j~0 (_ bv3 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1178#(bvslt (bvadd main_~j~0 (_ bv3 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,828 INFO L273 TraceCheckUtils]: 19: Hoare triple {1185#(bvslt (bvadd main_~j~0 (_ bv4 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1178#(bvslt (bvadd main_~j~0 (_ bv3 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,828 INFO L273 TraceCheckUtils]: 18: Hoare triple {1185#(bvslt (bvadd main_~j~0 (_ bv4 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1185#(bvslt (bvadd main_~j~0 (_ bv4 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,832 INFO L273 TraceCheckUtils]: 17: Hoare triple {1192#(bvslt (bvadd main_~j~0 (_ bv5 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1185#(bvslt (bvadd main_~j~0 (_ bv4 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,833 INFO L273 TraceCheckUtils]: 16: Hoare triple {1192#(bvslt (bvadd main_~j~0 (_ bv5 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1192#(bvslt (bvadd main_~j~0 (_ bv5 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,837 INFO L273 TraceCheckUtils]: 15: Hoare triple {1199#(bvslt (bvadd main_~j~0 (_ bv6 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1192#(bvslt (bvadd main_~j~0 (_ bv5 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,838 INFO L273 TraceCheckUtils]: 14: Hoare triple {1199#(bvslt (bvadd main_~j~0 (_ bv6 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1199#(bvslt (bvadd main_~j~0 (_ bv6 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,841 INFO L273 TraceCheckUtils]: 13: Hoare triple {1206#(bvslt (bvadd main_~j~0 (_ bv7 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1199#(bvslt (bvadd main_~j~0 (_ bv6 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,842 INFO L273 TraceCheckUtils]: 12: Hoare triple {1206#(bvslt (bvadd main_~j~0 (_ bv7 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1206#(bvslt (bvadd main_~j~0 (_ bv7 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,846 INFO L273 TraceCheckUtils]: 11: Hoare triple {1213#(bvslt (bvadd main_~j~0 (_ bv8 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1206#(bvslt (bvadd main_~j~0 (_ bv7 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,847 INFO L273 TraceCheckUtils]: 10: Hoare triple {1213#(bvslt (bvadd main_~j~0 (_ bv8 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1213#(bvslt (bvadd main_~j~0 (_ bv8 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,850 INFO L273 TraceCheckUtils]: 9: Hoare triple {1220#(bvslt (bvadd main_~j~0 (_ bv9 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1213#(bvslt (bvadd main_~j~0 (_ bv8 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,851 INFO L273 TraceCheckUtils]: 8: Hoare triple {1220#(bvslt (bvadd main_~j~0 (_ bv9 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1220#(bvslt (bvadd main_~j~0 (_ bv9 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,854 INFO L273 TraceCheckUtils]: 7: Hoare triple {1227#(bvslt (bvadd main_~j~0 (_ bv10 32)) (_ bv20 32))} #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; {1220#(bvslt (bvadd main_~j~0 (_ bv9 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,855 INFO L273 TraceCheckUtils]: 6: Hoare triple {1227#(bvslt (bvadd main_~j~0 (_ bv10 32)) (_ bv20 32))} assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; {1227#(bvslt (bvadd main_~j~0 (_ bv10 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,856 INFO L273 TraceCheckUtils]: 5: Hoare triple {1006#true} call ~#ad1~0.base, ~#ad1~0.offset := #Ultimate.alloc(160bv32);havoc ~ad2~0.base, ~ad2~0.offset;havoc ~i~0;havoc ~j~0;havoc ~pa~0.base, ~pa~0.offset;~j~0 := 0bv32; {1227#(bvslt (bvadd main_~j~0 (_ bv10 32)) (_ bv20 32))} is VALID [2018-11-23 11:07:13,856 INFO L256 TraceCheckUtils]: 4: Hoare triple {1006#true} call #t~ret9 := main(); {1006#true} is VALID [2018-11-23 11:07:13,856 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1006#true} {1006#true} #52#return; {1006#true} is VALID [2018-11-23 11:07:13,857 INFO L273 TraceCheckUtils]: 2: Hoare triple {1006#true} assume true; {1006#true} is VALID [2018-11-23 11:07:13,857 INFO L273 TraceCheckUtils]: 1: Hoare triple {1006#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; {1006#true} is VALID [2018-11-23 11:07:13,857 INFO L256 TraceCheckUtils]: 0: Hoare triple {1006#true} call ULTIMATE.init(); {1006#true} is VALID [2018-11-23 11:07:13,860 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 11:07:13,862 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 11:07:13,862 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 24 [2018-11-23 11:07:13,863 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 37 [2018-11-23 11:07:13,864 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 11:07:13,864 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 24 states. [2018-11-23 11:07:14,016 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 63 edges. 63 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 11:07:14,017 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-23 11:07:14,017 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-23 11:07:14,018 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=387, Unknown=0, NotChecked=0, Total=552 [2018-11-23 11:07:14,018 INFO L87 Difference]: Start difference. First operand 38 states and 39 transitions. Second operand 24 states. [2018-11-23 11:07:17,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:17,401 INFO L93 Difference]: Finished difference Result 69 states and 80 transitions. [2018-11-23 11:07:17,401 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-23 11:07:17,401 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 37 [2018-11-23 11:07:17,402 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 11:07:17,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-11-23 11:07:17,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 80 transitions. [2018-11-23 11:07:17,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-11-23 11:07:17,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 80 transitions. [2018-11-23 11:07:17,409 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 22 states and 80 transitions. [2018-11-23 11:07:17,670 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 80 edges. 80 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 11:07:17,673 INFO L225 Difference]: With dead ends: 69 [2018-11-23 11:07:17,673 INFO L226 Difference]: Without dead ends: 58 [2018-11-23 11:07:17,674 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 81 GetRequests, 51 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=341, Invalid=651, Unknown=0, NotChecked=0, Total=992 [2018-11-23 11:07:17,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-11-23 11:07:17,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 58. [2018-11-23 11:07:17,747 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 11:07:17,747 INFO L82 GeneralOperation]: Start isEquivalent. First operand 58 states. Second operand 58 states. [2018-11-23 11:07:17,747 INFO L74 IsIncluded]: Start isIncluded. First operand 58 states. Second operand 58 states. [2018-11-23 11:07:17,748 INFO L87 Difference]: Start difference. First operand 58 states. Second operand 58 states. [2018-11-23 11:07:17,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:17,752 INFO L93 Difference]: Finished difference Result 58 states and 59 transitions. [2018-11-23 11:07:17,753 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 59 transitions. [2018-11-23 11:07:17,754 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 11:07:17,754 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 11:07:17,755 INFO L74 IsIncluded]: Start isIncluded. First operand 58 states. Second operand 58 states. [2018-11-23 11:07:17,755 INFO L87 Difference]: Start difference. First operand 58 states. Second operand 58 states. [2018-11-23 11:07:17,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 11:07:17,762 INFO L93 Difference]: Finished difference Result 58 states and 59 transitions. [2018-11-23 11:07:17,763 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 59 transitions. [2018-11-23 11:07:17,763 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 11:07:17,764 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 11:07:17,764 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 11:07:17,764 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 11:07:17,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-11-23 11:07:17,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 59 transitions. [2018-11-23 11:07:17,773 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 59 transitions. Word has length 37 [2018-11-23 11:07:17,789 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 11:07:17,790 INFO L480 AbstractCegarLoop]: Abstraction has 58 states and 59 transitions. [2018-11-23 11:07:17,790 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-23 11:07:17,790 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 59 transitions. [2018-11-23 11:07:17,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-23 11:07:17,794 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 11:07:17,794 INFO L402 BasicCegarLoop]: trace histogram [20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 11:07:17,795 INFO L423 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 11:07:17,796 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 11:07:17,797 INFO L82 PathProgramCache]: Analyzing trace with hash 68058911, now seen corresponding path program 4 times [2018-11-23 11:07:17,797 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 11:07:17,797 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 11:07:17,824 INFO L101 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 11:07:29,771 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 11:07:29,771 INFO L250 tOrderPrioritization]: Conjunction of SSA is sat [2018-11-23 11:07:35,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 11:07:36,916 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] CALL call ULTIMATE.init(); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |old(#NULL.base)|=(_ bv0 32), |old(#NULL.offset)|=(_ bv0 32)] [?] #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |old(#NULL.base)|=(_ bv0 32), |old(#NULL.offset)|=(_ bv0 32)] [?] assume true; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |old(#NULL.base)|=(_ bv0 32), |old(#NULL.offset)|=(_ bv0 32)] [?] RET #52#return; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32)] [?] CALL call #t~ret9 := main(); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32)] [?] call ~#ad1~0.base, ~#ad1~0.offset := #Ultimate.alloc(160bv32);havoc ~ad2~0.base, ~ad2~0.offset;havoc ~i~0;havoc ~j~0;havoc ~pa~0.base, ~pa~0.offset;~j~0 := 0bv32; VAL [main_~j~0=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv1 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv1 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv2 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv2 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv3 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv3 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv4 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv4 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv5 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv5 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv6 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv6 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv7 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv7 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv8 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv8 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv9 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv9 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv10 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv10 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv11 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv11 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv12 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv12 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv13 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv13 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv14 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv14 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv15 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv15 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv16 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv16 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv17 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv17 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv18 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv18 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv19 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv19 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv20 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !~bvslt32(~j~0, 20bv32); VAL [main_~j~0=(_ bv20 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] ~i~0 := #t~nondet4;havoc #t~nondet4; VAL [main_~i~0=(_ bv9 32), main_~j~0=(_ bv20 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32);~ad2~0.base, ~ad2~0.offset := ~#ad1~0.base, ~#ad1~0.offset;call write~intINTTYPE4(~i~0, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~pa~0.base, ~pa~0.offset := ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0));call #t~mem5 := read~intINTTYPE4(~ad2~0.base, ~bvadd32(~ad2~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(10bv32, #t~mem5);havoc #t~mem5; VAL [main_~ad2~0.base=(_ bv1 32), main_~ad2~0.offset=(_ bv0 32), main_~i~0=(_ bv19 32), main_~j~0=(_ bv20 32), main_~pa~0.base=(_ bv1 32), main_~pa~0.offset=(_ bv72 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] call #t~mem6 := read~intINTTYPE4(~pa~0.base, ~pa~0.offset, 4bv32); VAL [main_~ad2~0.base=(_ bv1 32), main_~ad2~0.offset=(_ bv0 32), main_~i~0=(_ bv19 32), main_~j~0=(_ bv20 32), main_~pa~0.base=(_ bv1 32), main_~pa~0.offset=(_ bv72 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_#t~mem6|=(_ bv9 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !~bvslt32(~i~0, #t~mem6);havoc #t~mem6; VAL [main_~ad2~0.base=(_ bv1 32), main_~ad2~0.offset=(_ bv0 32), main_~i~0=(_ bv19 32), main_~j~0=(_ bv20 32), main_~pa~0.base=(_ bv1 32), main_~pa~0.offset=(_ bv72 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] CALL call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |check_#in~ad1.base|=(_ bv1 32), |check_#in~ad1.offset|=(_ bv0 32), |check_#in~b|=(_ bv19 32)] [?] ~ad1.base, ~ad1.offset := #in~ad1.base, #in~ad1.offset;~b := #in~b;call #t~mem0 := read~intINTTYPE4(~ad1.base, ~bvadd32(~ad1.offset, ~bvmul32(8bv32, ~b)), 4bv32);#res := (if #t~mem0 == ~b then 1bv32 else 0bv32);havoc #t~mem0; VAL [check_~ad1.base=(_ bv1 32), check_~ad1.offset=(_ bv0 32), check_~b=(_ bv19 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |check_#in~ad1.base|=(_ bv1 32), |check_#in~ad1.offset|=(_ bv0 32), |check_#in~b|=(_ bv19 32), |check_#res|=(_ bv0 32)] [?] assume true; VAL [check_~ad1.base=(_ bv1 32), check_~ad1.offset=(_ bv0 32), check_~b=(_ bv19 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |check_#in~ad1.base|=(_ bv1 32), |check_#in~ad1.offset|=(_ bv0 32), |check_#in~b|=(_ bv19 32), |check_#res|=(_ bv0 32)] [?] RET #56#return; VAL [main_~ad2~0.base=(_ bv1 32), main_~ad2~0.offset=(_ bv0 32), main_~i~0=(_ bv19 32), main_~j~0=(_ bv20 32), main_~pa~0.base=(_ bv1 32), main_~pa~0.offset=(_ bv72 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_#t~ret8|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume 0bv32 == #t~ret8;havoc #t~ret8; VAL [main_~ad2~0.base=(_ bv1 32), main_~ad2~0.offset=(_ bv0 32), main_~i~0=(_ bv19 32), main_~j~0=(_ bv20 32), main_~pa~0.base=(_ bv1 32), main_~pa~0.offset=(_ bv72 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !false; VAL [main_~ad2~0.base=(_ bv1 32), main_~ad2~0.offset=(_ bv0 32), main_~i~0=(_ bv19 32), main_~j~0=(_ bv20 32), main_~pa~0.base=(_ bv1 32), main_~pa~0.offset=(_ bv72 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] CALL call ULTIMATE.init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32] [?] #NULL.base, #NULL.offset := 0bv32, 0bv32; [?] #valid := #valid[0bv32 := 0bv1]; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32] [?] ensures true; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32] [?] CALL call #t~ret9 := main(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32] [L15] call ~#ad1~0.base, ~#ad1~0.offset := #Ultimate.alloc(160bv32); [L15] havoc ~ad2~0.base, ~ad2~0.offset; [L16] havoc ~i~0; [L16] havoc ~j~0; [L16] havoc ~pa~0.base, ~pa~0.offset; [L17] ~j~0 := 0bv32; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=0bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=0bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=1bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=1bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=2bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=2bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=3bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=3bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=4bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=4bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=5bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=5bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=6bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=6bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=7bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=7bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=8bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=8bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=9bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=9bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=10bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=10bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=11bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=11bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=12bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=12bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=13bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=13bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=14bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=14bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=15bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=15bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=16bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=16bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=17bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=17bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=18bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=18bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=19bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=19bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=20bv32] [L17-L20] assume !~bvslt32(~j~0, 20bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=20bv32] [L21] ~i~0 := #t~nondet4; [L21] havoc #t~nondet4; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~i~0=9bv32, ~j~0=20bv32] [L22-L33] assume ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32); [L23] ~ad2~0.base, ~ad2~0.offset := ~#ad1~0.base, ~#ad1~0.offset; [L24] call write~intINTTYPE4(~i~0, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32); [L25] ~pa~0.base, ~pa~0.offset := ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)); [L26] call #t~mem5 := read~intINTTYPE4(~ad2~0.base, ~bvadd32(~ad2~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32); [L26] ~i~0 := ~bvadd32(10bv32, #t~mem5); [L26] havoc #t~mem5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L27] call #t~mem6 := read~intINTTYPE4(~pa~0.base, ~pa~0.offset, 4bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~mem6=9bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L27-L29] assume !~bvslt32(~i~0, #t~mem6); [L27] havoc #t~mem6; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L30] CALL call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); VAL [#in~ad1.base=1bv32, #in~ad1.offset=0bv32, #in~b=19bv32, #NULL.base=0bv32, #NULL.offset=0bv32] [L8-L11] ~ad1.base, ~ad1.offset := #in~ad1.base, #in~ad1.offset; [L8-L11] ~b := #in~b; [L10] call #t~mem0 := read~intINTTYPE4(~ad1.base, ~bvadd32(~ad1.offset, ~bvmul32(8bv32, ~b)), 4bv32); [L10] #res := (if #t~mem0 == ~b then 1bv32 else 0bv32); [L10] havoc #t~mem0; VAL [#in~ad1.base=1bv32, #in~ad1.offset=0bv32, #in~b=19bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, ~ad1.base=1bv32, ~ad1.offset=0bv32, ~b=19bv32] [L8-L11] ensures true; VAL [#in~ad1.base=1bv32, #in~ad1.offset=0bv32, #in~b=19bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, ~ad1.base=1bv32, ~ad1.offset=0bv32, ~b=19bv32] [L30] RET call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~ret8=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L30-L32] assume 0bv32 == #t~ret8; [L30] havoc #t~ret8; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L37] assert false; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] CALL call ULTIMATE.init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32] [?] #NULL.base, #NULL.offset := 0bv32, 0bv32; [?] #valid := #valid[0bv32 := 0bv1]; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32] [?] ensures true; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32] [?] CALL call #t~ret9 := main(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32] [L15] call ~#ad1~0.base, ~#ad1~0.offset := #Ultimate.alloc(160bv32); [L15] havoc ~ad2~0.base, ~ad2~0.offset; [L16] havoc ~i~0; [L16] havoc ~j~0; [L16] havoc ~pa~0.base, ~pa~0.offset; [L17] ~j~0 := 0bv32; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=0bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=0bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=1bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=1bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=2bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=2bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=3bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=3bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=4bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=4bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=5bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=5bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=6bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=6bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=7bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=7bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=8bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=8bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=9bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=9bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=10bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=10bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=11bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=11bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=12bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=12bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=13bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=13bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=14bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=14bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=15bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=15bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=16bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=16bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=17bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=17bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=18bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=18bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=19bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=19bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=20bv32] [L17-L20] assume !~bvslt32(~j~0, 20bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=20bv32] [L21] ~i~0 := #t~nondet4; [L21] havoc #t~nondet4; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~i~0=9bv32, ~j~0=20bv32] [L22-L33] assume ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32); [L23] ~ad2~0.base, ~ad2~0.offset := ~#ad1~0.base, ~#ad1~0.offset; [L24] call write~intINTTYPE4(~i~0, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32); [L25] ~pa~0.base, ~pa~0.offset := ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)); [L26] call #t~mem5 := read~intINTTYPE4(~ad2~0.base, ~bvadd32(~ad2~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32); [L26] ~i~0 := ~bvadd32(10bv32, #t~mem5); [L26] havoc #t~mem5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L27] call #t~mem6 := read~intINTTYPE4(~pa~0.base, ~pa~0.offset, 4bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~mem6=9bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L27-L29] assume !~bvslt32(~i~0, #t~mem6); [L27] havoc #t~mem6; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L30] CALL call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); VAL [#in~ad1.base=1bv32, #in~ad1.offset=0bv32, #in~b=19bv32, #NULL.base=0bv32, #NULL.offset=0bv32] [L8-L11] ~ad1.base, ~ad1.offset := #in~ad1.base, #in~ad1.offset; [L8-L11] ~b := #in~b; [L10] call #t~mem0 := read~intINTTYPE4(~ad1.base, ~bvadd32(~ad1.offset, ~bvmul32(8bv32, ~b)), 4bv32); [L10] #res := (if #t~mem0 == ~b then 1bv32 else 0bv32); [L10] havoc #t~mem0; VAL [#in~ad1.base=1bv32, #in~ad1.offset=0bv32, #in~b=19bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, ~ad1.base=1bv32, ~ad1.offset=0bv32, ~b=19bv32] [L8-L11] ensures true; VAL [#in~ad1.base=1bv32, #in~ad1.offset=0bv32, #in~b=19bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, ~ad1.base=1bv32, ~ad1.offset=0bv32, ~b=19bv32] [L30] RET call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~ret8=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L30-L32] assume 0bv32 == #t~ret8; [L30] havoc #t~ret8; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L37] assert false; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] #NULL := { base: 0bv32, offset: 0bv32 }; [?] #valid[0bv32] := 0bv1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [?] CALL call #t~ret9 := main(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [L15] FCALL call ~#ad1~0 := #Ultimate.alloc(160bv32); [L15] havoc ~ad2~0; [L16] havoc ~i~0; [L16] havoc ~j~0; [L16] havoc ~pa~0; [L17] ~j~0 := 0bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L17-L20] COND TRUE !~bvslt32(~j~0, 20bv32) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L21] ~i~0 := #t~nondet4; [L21] havoc #t~nondet4; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~i~0=9bv32, ~j~0=20bv32] [L22] COND TRUE ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32) [L23] ~ad2~0 := ~#ad1~0; [L24] FCALL call write~intINTTYPE4(~i~0, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L25] ~pa~0 := { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }; [L26] FCALL call #t~mem5 := read~intINTTYPE4({ base: ~ad2~0!base, offset: ~bvadd32(~ad2~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L26] ~i~0 := ~bvadd32(10bv32, #t~mem5); [L26] havoc #t~mem5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27] FCALL call #t~mem6 := read~intINTTYPE4(~pa~0, 4bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~mem6=9bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27-L29] COND TRUE !~bvslt32(~i~0, #t~mem6) [L27] havoc #t~mem6; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] CALL call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32] [L8-L11] ~ad1 := #in~ad1; [L8-L11] ~b := #in~b; [L10] FCALL call #t~mem0 := read~intINTTYPE4({ base: ~ad1!base, offset: ~bvadd32(~ad1!offset, ~bvmul32(8bv32, ~b)) }, 4bv32); [L10] #res := (if #t~mem0 == ~b then 1bv32 else 0bv32); [L10] havoc #t~mem0; VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, ~ad1!base=1bv32, ~ad1!offset=0bv32, ~b=19bv32] [L30] RET call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret8=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] COND TRUE 0bv32 == #t~ret8 [L30] havoc #t~ret8; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L37] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] #NULL := { base: 0bv32, offset: 0bv32 }; [?] #valid[0bv32] := 0bv1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [?] CALL call #t~ret9 := main(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [L15] FCALL call ~#ad1~0 := #Ultimate.alloc(160bv32); [L15] havoc ~ad2~0; [L16] havoc ~i~0; [L16] havoc ~j~0; [L16] havoc ~pa~0; [L17] ~j~0 := 0bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L17-L20] COND TRUE !~bvslt32(~j~0, 20bv32) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L21] ~i~0 := #t~nondet4; [L21] havoc #t~nondet4; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~i~0=9bv32, ~j~0=20bv32] [L22] COND TRUE ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32) [L23] ~ad2~0 := ~#ad1~0; [L24] FCALL call write~intINTTYPE4(~i~0, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L25] ~pa~0 := { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }; [L26] FCALL call #t~mem5 := read~intINTTYPE4({ base: ~ad2~0!base, offset: ~bvadd32(~ad2~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L26] ~i~0 := ~bvadd32(10bv32, #t~mem5); [L26] havoc #t~mem5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27] FCALL call #t~mem6 := read~intINTTYPE4(~pa~0, 4bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~mem6=9bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27-L29] COND TRUE !~bvslt32(~i~0, #t~mem6) [L27] havoc #t~mem6; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] CALL call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32] [L8-L11] ~ad1 := #in~ad1; [L8-L11] ~b := #in~b; [L10] FCALL call #t~mem0 := read~intINTTYPE4({ base: ~ad1!base, offset: ~bvadd32(~ad1!offset, ~bvmul32(8bv32, ~b)) }, 4bv32); [L10] #res := (if #t~mem0 == ~b then 1bv32 else 0bv32); [L10] havoc #t~mem0; VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, ~ad1!base=1bv32, ~ad1!offset=0bv32, ~b=19bv32] [L30] RET call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret8=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] COND TRUE 0bv32 == #t~ret8 [L30] havoc #t~ret8; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L37] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] #NULL := { base: 0bv32, offset: 0bv32 }; [?] #valid[0bv32] := 0bv1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [?] CALL call #t~ret9 := main(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [L15] FCALL call ~#ad1~0 := #Ultimate.alloc(160bv32); [L15] havoc ~ad2~0; [L16] havoc ~i~0; [L16] havoc ~j~0; [L16] havoc ~pa~0; [L17] ~j~0 := 0bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L17-L20] COND TRUE !~bvslt32(~j~0, 20bv32) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L21] ~i~0 := #t~nondet4; [L21] havoc #t~nondet4; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~i~0=9bv32, ~j~0=20bv32] [L22] COND TRUE ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32) [L23] ~ad2~0 := ~#ad1~0; [L24] FCALL call write~intINTTYPE4(~i~0, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L25] ~pa~0 := { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }; [L26] FCALL call #t~mem5 := read~intINTTYPE4({ base: ~ad2~0!base, offset: ~bvadd32(~ad2~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L26] ~i~0 := ~bvadd32(10bv32, #t~mem5); [L26] havoc #t~mem5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27] FCALL call #t~mem6 := read~intINTTYPE4(~pa~0, 4bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~mem6=9bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27-L29] COND TRUE !~bvslt32(~i~0, #t~mem6) [L27] havoc #t~mem6; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] CALL call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32] [L8-L11] ~ad1 := #in~ad1; [L8-L11] ~b := #in~b; [L10] FCALL call #t~mem0 := read~intINTTYPE4({ base: ~ad1!base, offset: ~bvadd32(~ad1!offset, ~bvmul32(8bv32, ~b)) }, 4bv32); [L10] #res := (if #t~mem0 == ~b then 1bv32 else 0bv32); [L10] havoc #t~mem0; VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, ~ad1!base=1bv32, ~ad1!offset=0bv32, ~b=19bv32] [L30] RET call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret8=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] COND TRUE 0bv32 == #t~ret8 [L30] havoc #t~ret8; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L37] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] #NULL := { base: 0bv32, offset: 0bv32 }; [?] #valid[0bv32] := 0bv1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [?] CALL call #t~ret9 := main(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [L15] FCALL call ~#ad1~0 := #Ultimate.alloc(160bv32); [L15] havoc ~ad2~0; [L16] havoc ~i~0; [L16] havoc ~j~0; [L16] havoc ~pa~0; [L17] ~j~0 := 0bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L17-L20] COND TRUE !~bvslt32(~j~0, 20bv32) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L21] ~i~0 := #t~nondet4; [L21] havoc #t~nondet4; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~i~0=9bv32, ~j~0=20bv32] [L22] COND TRUE ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32) [L23] ~ad2~0 := ~#ad1~0; [L24] FCALL call write~intINTTYPE4(~i~0, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L25] ~pa~0 := { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }; [L26] FCALL call #t~mem5 := read~intINTTYPE4({ base: ~ad2~0!base, offset: ~bvadd32(~ad2~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L26] ~i~0 := ~bvadd32(10bv32, #t~mem5); [L26] havoc #t~mem5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27] FCALL call #t~mem6 := read~intINTTYPE4(~pa~0, 4bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~mem6=9bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27-L29] COND TRUE !~bvslt32(~i~0, #t~mem6) [L27] havoc #t~mem6; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] CALL call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32] [L8-L11] ~ad1 := #in~ad1; [L8-L11] ~b := #in~b; [L10] FCALL call #t~mem0 := read~intINTTYPE4({ base: ~ad1!base, offset: ~bvadd32(~ad1!offset, ~bvmul32(8bv32, ~b)) }, 4bv32); [L10] #res := (if #t~mem0 == ~b then 1bv32 else 0bv32); [L10] havoc #t~mem0; VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, ~ad1!base=1bv32, ~ad1!offset=0bv32, ~b=19bv32] [L30] RET call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret8=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] COND TRUE 0bv32 == #t~ret8 [L30] havoc #t~ret8; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L37] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L15] struct dummy ad1[20], *ad2; [L16] int i, j, *pa; [L17] j=0 VAL [ad1={1:0}, j=0] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=1] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=2] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=3] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=4] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=5] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=6] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=7] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=8] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=9] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=10] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=11] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=12] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=13] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=14] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=15] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=16] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=17] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=18] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=19] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=20] [L17] COND FALSE !(j<20) VAL [ad1={1:0}, j=20] [L21] i = __VERIFIER_nondet_int() [L22] COND TRUE i >= 0 && i < 10 [L23] ad2 = ad1 [L24] ad1[i].a = i [L25] pa = &ad1[i].a [L26] EXPR ad2[i].a [L26] i = ad2[i].a + 10 [L27] EXPR \read(*pa) VAL [\read(*pa)=9, ad1={1:0}, ad2={1:0}, i=19, j=20, pa={1:72}] [L27] COND FALSE !(i < *pa) [L30] CALL, EXPR check(ad1, i) VAL [\old(b)=19, ad1={1:0}] [L10] EXPR ad1[b].a [L10] return ad1[b].a == b; [L30] RET, EXPR check(ad1, i) VAL [ad1={1:0}, ad2={1:0}, check(ad1, i)=0, i=19, j=20, pa={1:72}] [L30] COND TRUE !check(ad1, i) [L37] __VERIFIER_error() VAL [ad1={1:0}, ad2={1:0}, i=19, j=20, pa={1:72}] ----- [2018-11-23 11:07:37,042 WARN L170 areAnnotationChecker]: ULTIMATE.initENTRY has no Hoare annotation [2018-11-23 11:07:37,042 WARN L170 areAnnotationChecker]: ULTIMATE.startENTRY has no Hoare annotation [2018-11-23 11:07:37,042 WARN L170 areAnnotationChecker]: ULTIMATE.startENTRY has no Hoare annotation [2018-11-23 11:07:37,042 WARN L170 areAnnotationChecker]: mainENTRY has no Hoare annotation [2018-11-23 11:07:37,042 WARN L170 areAnnotationChecker]: checkENTRY has no Hoare annotation [2018-11-23 11:07:37,042 WARN L170 areAnnotationChecker]: ULTIMATE.initFINAL has no Hoare annotation [2018-11-23 11:07:37,043 WARN L170 areAnnotationChecker]: L-1 has no Hoare annotation [2018-11-23 11:07:37,044 WARN L170 areAnnotationChecker]: L-1 has no Hoare annotation [2018-11-23 11:07:37,044 WARN L170 areAnnotationChecker]: L17-3 has no Hoare annotation [2018-11-23 11:07:37,044 WARN L170 areAnnotationChecker]: L17-3 has no Hoare annotation [2018-11-23 11:07:37,044 WARN L170 areAnnotationChecker]: L17-3 has no Hoare annotation [2018-11-23 11:07:37,044 WARN L170 areAnnotationChecker]: checkFINAL has no Hoare annotation [2018-11-23 11:07:37,045 WARN L170 areAnnotationChecker]: ULTIMATE.initEXIT has no Hoare annotation [2018-11-23 11:07:37,045 WARN L170 areAnnotationChecker]: ULTIMATE.startFINAL has no Hoare annotation [2018-11-23 11:07:37,045 WARN L170 areAnnotationChecker]: L17-4 has no Hoare annotation [2018-11-23 11:07:37,045 WARN L170 areAnnotationChecker]: L17-2 has no Hoare annotation [2018-11-23 11:07:37,045 WARN L170 areAnnotationChecker]: checkEXIT has no Hoare annotation [2018-11-23 11:07:37,045 WARN L170 areAnnotationChecker]: L22 has no Hoare annotation [2018-11-23 11:07:37,045 WARN L170 areAnnotationChecker]: L22 has no Hoare annotation [2018-11-23 11:07:37,045 WARN L170 areAnnotationChecker]: L30 has no Hoare annotation [2018-11-23 11:07:37,045 WARN L170 areAnnotationChecker]: L30 has no Hoare annotation [2018-11-23 11:07:37,046 WARN L170 areAnnotationChecker]: L27-3 has no Hoare annotation [2018-11-23 11:07:37,048 WARN L170 areAnnotationChecker]: L27-3 has no Hoare annotation [2018-11-23 11:07:37,048 WARN L170 areAnnotationChecker]: L22-2 has no Hoare annotation [2018-11-23 11:07:37,048 WARN L170 areAnnotationChecker]: L31 has no Hoare annotation [2018-11-23 11:07:37,048 WARN L170 areAnnotationChecker]: L31 has no Hoare annotation [2018-11-23 11:07:37,048 WARN L170 areAnnotationChecker]: L27-4 has no Hoare annotation [2018-11-23 11:07:37,048 WARN L170 areAnnotationChecker]: L27-4 has no Hoare annotation [2018-11-23 11:07:37,048 WARN L170 areAnnotationChecker]: L27-1 has no Hoare annotation [2018-11-23 11:07:37,049 WARN L170 areAnnotationChecker]: L27-1 has no Hoare annotation [2018-11-23 11:07:37,049 WARN L170 areAnnotationChecker]: mainFINAL has no Hoare annotation [2018-11-23 11:07:37,049 WARN L170 areAnnotationChecker]: mainEXIT has no Hoare annotation [2018-11-23 11:07:37,049 INFO L163 areAnnotationChecker]: CFG has 0 edges. 0 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. 0 times interpolants missing. [2018-11-23 11:07:37,052 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 11:07:37 BoogieIcfgContainer [2018-11-23 11:07:37,052 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 11:07:37,052 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 11:07:37,057 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 11:07:37,060 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 11:07:37,061 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 11:07:06" (3/4) ... [2018-11-23 11:07:37,063 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] CALL call ULTIMATE.init(); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |old(#NULL.base)|=(_ bv0 32), |old(#NULL.offset)|=(_ bv0 32)] [?] #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1]; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |old(#NULL.base)|=(_ bv0 32), |old(#NULL.offset)|=(_ bv0 32)] [?] assume true; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |old(#NULL.base)|=(_ bv0 32), |old(#NULL.offset)|=(_ bv0 32)] [?] RET #52#return; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32)] [?] CALL call #t~ret9 := main(); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32)] [?] call ~#ad1~0.base, ~#ad1~0.offset := #Ultimate.alloc(160bv32);havoc ~ad2~0.base, ~ad2~0.offset;havoc ~i~0;havoc ~j~0;havoc ~pa~0.base, ~pa~0.offset;~j~0 := 0bv32; VAL [main_~j~0=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv1 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv1 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv2 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv2 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv3 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv3 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv4 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv4 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv5 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv5 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv6 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv6 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv7 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv7 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv8 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv8 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv9 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv9 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv10 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv10 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv11 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv11 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv12 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv12 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv13 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv13 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv14 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv14 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv15 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv15 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv16 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv16 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv17 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv17 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv18 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv18 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv19 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !!~bvslt32(~j~0, 20bv32);call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32);havoc #t~nondet2;call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32);havoc #t~nondet3; VAL [main_~j~0=(_ bv19 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] #t~post1 := ~j~0;~j~0 := ~bvadd32(1bv32, #t~post1);havoc #t~post1; VAL [main_~j~0=(_ bv20 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !~bvslt32(~j~0, 20bv32); VAL [main_~j~0=(_ bv20 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] ~i~0 := #t~nondet4;havoc #t~nondet4; VAL [main_~i~0=(_ bv9 32), main_~j~0=(_ bv20 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32);~ad2~0.base, ~ad2~0.offset := ~#ad1~0.base, ~#ad1~0.offset;call write~intINTTYPE4(~i~0, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~pa~0.base, ~pa~0.offset := ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0));call #t~mem5 := read~intINTTYPE4(~ad2~0.base, ~bvadd32(~ad2~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32);~i~0 := ~bvadd32(10bv32, #t~mem5);havoc #t~mem5; VAL [main_~ad2~0.base=(_ bv1 32), main_~ad2~0.offset=(_ bv0 32), main_~i~0=(_ bv19 32), main_~j~0=(_ bv20 32), main_~pa~0.base=(_ bv1 32), main_~pa~0.offset=(_ bv72 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] call #t~mem6 := read~intINTTYPE4(~pa~0.base, ~pa~0.offset, 4bv32); VAL [main_~ad2~0.base=(_ bv1 32), main_~ad2~0.offset=(_ bv0 32), main_~i~0=(_ bv19 32), main_~j~0=(_ bv20 32), main_~pa~0.base=(_ bv1 32), main_~pa~0.offset=(_ bv72 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_#t~mem6|=(_ bv9 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !~bvslt32(~i~0, #t~mem6);havoc #t~mem6; VAL [main_~ad2~0.base=(_ bv1 32), main_~ad2~0.offset=(_ bv0 32), main_~i~0=(_ bv19 32), main_~j~0=(_ bv20 32), main_~pa~0.base=(_ bv1 32), main_~pa~0.offset=(_ bv72 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] CALL call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |check_#in~ad1.base|=(_ bv1 32), |check_#in~ad1.offset|=(_ bv0 32), |check_#in~b|=(_ bv19 32)] [?] ~ad1.base, ~ad1.offset := #in~ad1.base, #in~ad1.offset;~b := #in~b;call #t~mem0 := read~intINTTYPE4(~ad1.base, ~bvadd32(~ad1.offset, ~bvmul32(8bv32, ~b)), 4bv32);#res := (if #t~mem0 == ~b then 1bv32 else 0bv32);havoc #t~mem0; VAL [check_~ad1.base=(_ bv1 32), check_~ad1.offset=(_ bv0 32), check_~b=(_ bv19 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |check_#in~ad1.base|=(_ bv1 32), |check_#in~ad1.offset|=(_ bv0 32), |check_#in~b|=(_ bv19 32), |check_#res|=(_ bv0 32)] [?] assume true; VAL [check_~ad1.base=(_ bv1 32), check_~ad1.offset=(_ bv0 32), check_~b=(_ bv19 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |check_#in~ad1.base|=(_ bv1 32), |check_#in~ad1.offset|=(_ bv0 32), |check_#in~b|=(_ bv19 32), |check_#res|=(_ bv0 32)] [?] RET #56#return; VAL [main_~ad2~0.base=(_ bv1 32), main_~ad2~0.offset=(_ bv0 32), main_~i~0=(_ bv19 32), main_~j~0=(_ bv20 32), main_~pa~0.base=(_ bv1 32), main_~pa~0.offset=(_ bv72 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_#t~ret8|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume 0bv32 == #t~ret8;havoc #t~ret8; VAL [main_~ad2~0.base=(_ bv1 32), main_~ad2~0.offset=(_ bv0 32), main_~i~0=(_ bv19 32), main_~j~0=(_ bv20 32), main_~pa~0.base=(_ bv1 32), main_~pa~0.offset=(_ bv72 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] assume !false; VAL [main_~ad2~0.base=(_ bv1 32), main_~ad2~0.offset=(_ bv0 32), main_~i~0=(_ bv19 32), main_~j~0=(_ bv20 32), main_~pa~0.base=(_ bv1 32), main_~pa~0.offset=(_ bv72 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |main_~#ad1~0.base|=(_ bv1 32), |main_~#ad1~0.offset|=(_ bv0 32)] [?] CALL call ULTIMATE.init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32] [?] #NULL.base, #NULL.offset := 0bv32, 0bv32; [?] #valid := #valid[0bv32 := 0bv1]; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32] [?] ensures true; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32] [?] CALL call #t~ret9 := main(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32] [L15] call ~#ad1~0.base, ~#ad1~0.offset := #Ultimate.alloc(160bv32); [L15] havoc ~ad2~0.base, ~ad2~0.offset; [L16] havoc ~i~0; [L16] havoc ~j~0; [L16] havoc ~pa~0.base, ~pa~0.offset; [L17] ~j~0 := 0bv32; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=0bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=0bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=1bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=1bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=2bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=2bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=3bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=3bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=4bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=4bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=5bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=5bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=6bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=6bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=7bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=7bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=8bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=8bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=9bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=9bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=10bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=10bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=11bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=11bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=12bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=12bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=13bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=13bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=14bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=14bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=15bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=15bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=16bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=16bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=17bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=17bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=18bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=18bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=19bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=19bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=20bv32] [L17-L20] assume !~bvslt32(~j~0, 20bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=20bv32] [L21] ~i~0 := #t~nondet4; [L21] havoc #t~nondet4; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~i~0=9bv32, ~j~0=20bv32] [L22-L33] assume ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32); [L23] ~ad2~0.base, ~ad2~0.offset := ~#ad1~0.base, ~#ad1~0.offset; [L24] call write~intINTTYPE4(~i~0, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32); [L25] ~pa~0.base, ~pa~0.offset := ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)); [L26] call #t~mem5 := read~intINTTYPE4(~ad2~0.base, ~bvadd32(~ad2~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32); [L26] ~i~0 := ~bvadd32(10bv32, #t~mem5); [L26] havoc #t~mem5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L27] call #t~mem6 := read~intINTTYPE4(~pa~0.base, ~pa~0.offset, 4bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~mem6=9bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L27-L29] assume !~bvslt32(~i~0, #t~mem6); [L27] havoc #t~mem6; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L30] CALL call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); VAL [#in~ad1.base=1bv32, #in~ad1.offset=0bv32, #in~b=19bv32, #NULL.base=0bv32, #NULL.offset=0bv32] [L8-L11] ~ad1.base, ~ad1.offset := #in~ad1.base, #in~ad1.offset; [L8-L11] ~b := #in~b; [L10] call #t~mem0 := read~intINTTYPE4(~ad1.base, ~bvadd32(~ad1.offset, ~bvmul32(8bv32, ~b)), 4bv32); [L10] #res := (if #t~mem0 == ~b then 1bv32 else 0bv32); [L10] havoc #t~mem0; VAL [#in~ad1.base=1bv32, #in~ad1.offset=0bv32, #in~b=19bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, ~ad1.base=1bv32, ~ad1.offset=0bv32, ~b=19bv32] [L8-L11] ensures true; VAL [#in~ad1.base=1bv32, #in~ad1.offset=0bv32, #in~b=19bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, ~ad1.base=1bv32, ~ad1.offset=0bv32, ~b=19bv32] [L30] RET call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~ret8=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L30-L32] assume 0bv32 == #t~ret8; [L30] havoc #t~ret8; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L37] assert false; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] CALL call ULTIMATE.init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32] [?] #NULL.base, #NULL.offset := 0bv32, 0bv32; [?] #valid := #valid[0bv32 := 0bv1]; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32] [?] ensures true; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32] [?] CALL call #t~ret9 := main(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32] [L15] call ~#ad1~0.base, ~#ad1~0.offset := #Ultimate.alloc(160bv32); [L15] havoc ~ad2~0.base, ~ad2~0.offset; [L16] havoc ~i~0; [L16] havoc ~j~0; [L16] havoc ~pa~0.base, ~pa~0.offset; [L17] ~j~0 := 0bv32; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=0bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=0bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=1bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=1bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=2bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=2bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=3bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=3bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=4bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=4bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=5bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=5bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=6bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=6bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=7bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=7bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=8bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=8bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=9bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=9bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=10bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=10bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=11bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=11bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=12bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=12bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=13bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=13bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=14bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=14bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=15bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=15bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=16bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=16bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=17bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=17bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=18bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=18bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=19bv32] [L17-L20] assume !!~bvslt32(~j~0, 20bv32); [L18] call write~intINTTYPE4(#t~nondet2, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0)), 4bv32); [L18] havoc #t~nondet2; [L19] call write~intINTTYPE4(#t~nondet3, ~#ad1~0.base, ~bvadd32(4bv32, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~j~0))), 4bv32); [L19] havoc #t~nondet3; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=19bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=20bv32] [L17-L20] assume !~bvslt32(~j~0, 20bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~j~0=20bv32] [L21] ~i~0 := #t~nondet4; [L21] havoc #t~nondet4; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~i~0=9bv32, ~j~0=20bv32] [L22-L33] assume ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32); [L23] ~ad2~0.base, ~ad2~0.offset := ~#ad1~0.base, ~#ad1~0.offset; [L24] call write~intINTTYPE4(~i~0, ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32); [L25] ~pa~0.base, ~pa~0.offset := ~#ad1~0.base, ~bvadd32(~#ad1~0.offset, ~bvmul32(8bv32, ~i~0)); [L26] call #t~mem5 := read~intINTTYPE4(~ad2~0.base, ~bvadd32(~ad2~0.offset, ~bvmul32(8bv32, ~i~0)), 4bv32); [L26] ~i~0 := ~bvadd32(10bv32, #t~mem5); [L26] havoc #t~mem5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L27] call #t~mem6 := read~intINTTYPE4(~pa~0.base, ~pa~0.offset, 4bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~mem6=9bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L27-L29] assume !~bvslt32(~i~0, #t~mem6); [L27] havoc #t~mem6; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L30] CALL call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); VAL [#in~ad1.base=1bv32, #in~ad1.offset=0bv32, #in~b=19bv32, #NULL.base=0bv32, #NULL.offset=0bv32] [L8-L11] ~ad1.base, ~ad1.offset := #in~ad1.base, #in~ad1.offset; [L8-L11] ~b := #in~b; [L10] call #t~mem0 := read~intINTTYPE4(~ad1.base, ~bvadd32(~ad1.offset, ~bvmul32(8bv32, ~b)), 4bv32); [L10] #res := (if #t~mem0 == ~b then 1bv32 else 0bv32); [L10] havoc #t~mem0; VAL [#in~ad1.base=1bv32, #in~ad1.offset=0bv32, #in~b=19bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, ~ad1.base=1bv32, ~ad1.offset=0bv32, ~b=19bv32] [L8-L11] ensures true; VAL [#in~ad1.base=1bv32, #in~ad1.offset=0bv32, #in~b=19bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, ~ad1.base=1bv32, ~ad1.offset=0bv32, ~b=19bv32] [L30] RET call #t~ret8 := check(~#ad1~0.base, ~#ad1~0.offset, ~i~0); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~ret8=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L30-L32] assume 0bv32 == #t~ret8; [L30] havoc #t~ret8; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [L37] assert false; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, ~#ad1~0.base=1bv32, ~#ad1~0.offset=0bv32, ~ad2~0.base=1bv32, ~ad2~0.offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0.base=1bv32, ~pa~0.offset=72bv32] [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] #NULL := { base: 0bv32, offset: 0bv32 }; [?] #valid[0bv32] := 0bv1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [?] CALL call #t~ret9 := main(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [L15] FCALL call ~#ad1~0 := #Ultimate.alloc(160bv32); [L15] havoc ~ad2~0; [L16] havoc ~i~0; [L16] havoc ~j~0; [L16] havoc ~pa~0; [L17] ~j~0 := 0bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L17-L20] COND TRUE !~bvslt32(~j~0, 20bv32) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L21] ~i~0 := #t~nondet4; [L21] havoc #t~nondet4; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~i~0=9bv32, ~j~0=20bv32] [L22] COND TRUE ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32) [L23] ~ad2~0 := ~#ad1~0; [L24] FCALL call write~intINTTYPE4(~i~0, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L25] ~pa~0 := { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }; [L26] FCALL call #t~mem5 := read~intINTTYPE4({ base: ~ad2~0!base, offset: ~bvadd32(~ad2~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L26] ~i~0 := ~bvadd32(10bv32, #t~mem5); [L26] havoc #t~mem5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27] FCALL call #t~mem6 := read~intINTTYPE4(~pa~0, 4bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~mem6=9bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27-L29] COND TRUE !~bvslt32(~i~0, #t~mem6) [L27] havoc #t~mem6; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] CALL call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32] [L8-L11] ~ad1 := #in~ad1; [L8-L11] ~b := #in~b; [L10] FCALL call #t~mem0 := read~intINTTYPE4({ base: ~ad1!base, offset: ~bvadd32(~ad1!offset, ~bvmul32(8bv32, ~b)) }, 4bv32); [L10] #res := (if #t~mem0 == ~b then 1bv32 else 0bv32); [L10] havoc #t~mem0; VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, ~ad1!base=1bv32, ~ad1!offset=0bv32, ~b=19bv32] [L30] RET call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret8=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] COND TRUE 0bv32 == #t~ret8 [L30] havoc #t~ret8; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L37] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] #NULL := { base: 0bv32, offset: 0bv32 }; [?] #valid[0bv32] := 0bv1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [?] CALL call #t~ret9 := main(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [L15] FCALL call ~#ad1~0 := #Ultimate.alloc(160bv32); [L15] havoc ~ad2~0; [L16] havoc ~i~0; [L16] havoc ~j~0; [L16] havoc ~pa~0; [L17] ~j~0 := 0bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L17-L20] COND TRUE !~bvslt32(~j~0, 20bv32) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L21] ~i~0 := #t~nondet4; [L21] havoc #t~nondet4; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~i~0=9bv32, ~j~0=20bv32] [L22] COND TRUE ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32) [L23] ~ad2~0 := ~#ad1~0; [L24] FCALL call write~intINTTYPE4(~i~0, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L25] ~pa~0 := { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }; [L26] FCALL call #t~mem5 := read~intINTTYPE4({ base: ~ad2~0!base, offset: ~bvadd32(~ad2~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L26] ~i~0 := ~bvadd32(10bv32, #t~mem5); [L26] havoc #t~mem5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27] FCALL call #t~mem6 := read~intINTTYPE4(~pa~0, 4bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~mem6=9bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27-L29] COND TRUE !~bvslt32(~i~0, #t~mem6) [L27] havoc #t~mem6; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] CALL call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32] [L8-L11] ~ad1 := #in~ad1; [L8-L11] ~b := #in~b; [L10] FCALL call #t~mem0 := read~intINTTYPE4({ base: ~ad1!base, offset: ~bvadd32(~ad1!offset, ~bvmul32(8bv32, ~b)) }, 4bv32); [L10] #res := (if #t~mem0 == ~b then 1bv32 else 0bv32); [L10] havoc #t~mem0; VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, ~ad1!base=1bv32, ~ad1!offset=0bv32, ~b=19bv32] [L30] RET call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret8=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] COND TRUE 0bv32 == #t~ret8 [L30] havoc #t~ret8; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L37] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] #NULL := { base: 0bv32, offset: 0bv32 }; [?] #valid[0bv32] := 0bv1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [?] CALL call #t~ret9 := main(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [L15] FCALL call ~#ad1~0 := #Ultimate.alloc(160bv32); [L15] havoc ~ad2~0; [L16] havoc ~i~0; [L16] havoc ~j~0; [L16] havoc ~pa~0; [L17] ~j~0 := 0bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L17-L20] COND TRUE !~bvslt32(~j~0, 20bv32) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L21] ~i~0 := #t~nondet4; [L21] havoc #t~nondet4; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~i~0=9bv32, ~j~0=20bv32] [L22] COND TRUE ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32) [L23] ~ad2~0 := ~#ad1~0; [L24] FCALL call write~intINTTYPE4(~i~0, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L25] ~pa~0 := { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }; [L26] FCALL call #t~mem5 := read~intINTTYPE4({ base: ~ad2~0!base, offset: ~bvadd32(~ad2~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L26] ~i~0 := ~bvadd32(10bv32, #t~mem5); [L26] havoc #t~mem5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27] FCALL call #t~mem6 := read~intINTTYPE4(~pa~0, 4bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~mem6=9bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27-L29] COND TRUE !~bvslt32(~i~0, #t~mem6) [L27] havoc #t~mem6; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] CALL call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32] [L8-L11] ~ad1 := #in~ad1; [L8-L11] ~b := #in~b; [L10] FCALL call #t~mem0 := read~intINTTYPE4({ base: ~ad1!base, offset: ~bvadd32(~ad1!offset, ~bvmul32(8bv32, ~b)) }, 4bv32); [L10] #res := (if #t~mem0 == ~b then 1bv32 else 0bv32); [L10] havoc #t~mem0; VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, ~ad1!base=1bv32, ~ad1!offset=0bv32, ~b=19bv32] [L30] RET call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret8=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] COND TRUE 0bv32 == #t~ret8 [L30] havoc #t~ret8; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L37] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] #NULL := { base: 0bv32, offset: 0bv32 }; [?] #valid[0bv32] := 0bv1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [?] CALL call #t~ret9 := main(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32] [L15] FCALL call ~#ad1~0 := #Ultimate.alloc(160bv32); [L15] havoc ~ad2~0; [L16] havoc ~i~0; [L16] havoc ~j~0; [L16] havoc ~pa~0; [L17] ~j~0 := 0bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=0bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=1bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=2bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=3bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=4bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=5bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=6bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=7bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=8bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=9bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=10bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=11bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=12bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=13bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=14bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=15bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=16bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=17bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=18bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17-L20] COND FALSE !(!~bvslt32(~j~0, 20bv32)) [L18] FCALL call write~intINTTYPE4(#t~nondet2, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0)) }, 4bv32); [L18] havoc #t~nondet2; [L19] FCALL call write~intINTTYPE4(#t~nondet3, { base: ~#ad1~0!base, offset: ~bvadd32(4bv32, ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~j~0))) }, 4bv32); [L19] havoc #t~nondet3; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=19bv32] [L17] #t~post1 := ~j~0; [L17] ~j~0 := ~bvadd32(1bv32, #t~post1); [L17] havoc #t~post1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L17-L20] COND TRUE !~bvslt32(~j~0, 20bv32) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~j~0=20bv32] [L21] ~i~0 := #t~nondet4; [L21] havoc #t~nondet4; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~i~0=9bv32, ~j~0=20bv32] [L22] COND TRUE ~bvsge32(~i~0, 0bv32) && ~bvslt32(~i~0, 10bv32) [L23] ~ad2~0 := ~#ad1~0; [L24] FCALL call write~intINTTYPE4(~i~0, { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L25] ~pa~0 := { base: ~#ad1~0!base, offset: ~bvadd32(~#ad1~0!offset, ~bvmul32(8bv32, ~i~0)) }; [L26] FCALL call #t~mem5 := read~intINTTYPE4({ base: ~ad2~0!base, offset: ~bvadd32(~ad2~0!offset, ~bvmul32(8bv32, ~i~0)) }, 4bv32); [L26] ~i~0 := ~bvadd32(10bv32, #t~mem5); [L26] havoc #t~mem5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27] FCALL call #t~mem6 := read~intINTTYPE4(~pa~0, 4bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~mem6=9bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L27-L29] COND TRUE !~bvslt32(~i~0, #t~mem6) [L27] havoc #t~mem6; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] CALL call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32] [L8-L11] ~ad1 := #in~ad1; [L8-L11] ~b := #in~b; [L10] FCALL call #t~mem0 := read~intINTTYPE4({ base: ~ad1!base, offset: ~bvadd32(~ad1!offset, ~bvmul32(8bv32, ~b)) }, 4bv32); [L10] #res := (if #t~mem0 == ~b then 1bv32 else 0bv32); [L10] havoc #t~mem0; VAL [#in~ad1!base=1bv32, #in~ad1!offset=0bv32, #in~b=19bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, ~ad1!base=1bv32, ~ad1!offset=0bv32, ~b=19bv32] [L30] RET call #t~ret8 := check(~#ad1~0, ~i~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret8=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L30] COND TRUE 0bv32 == #t~ret8 [L30] havoc #t~ret8; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L37] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, ~#ad1~0!base=1bv32, ~#ad1~0!offset=0bv32, ~ad2~0!base=1bv32, ~ad2~0!offset=0bv32, ~i~0=19bv32, ~j~0=20bv32, ~pa~0!base=1bv32, ~pa~0!offset=72bv32] [L15] struct dummy ad1[20], *ad2; [L16] int i, j, *pa; [L17] j=0 VAL [ad1={1:0}, j=0] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=1] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=2] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=3] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=4] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=5] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=6] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=7] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=8] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=9] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=10] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=11] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=12] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=13] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=14] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=15] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=16] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=17] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=18] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=19] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=20] [L17] COND FALSE !(j<20) VAL [ad1={1:0}, j=20] [L21] i = __VERIFIER_nondet_int() [L22] COND TRUE i >= 0 && i < 10 [L23] ad2 = ad1 [L24] ad1[i].a = i [L25] pa = &ad1[i].a [L26] EXPR ad2[i].a [L26] i = ad2[i].a + 10 [L27] EXPR \read(*pa) VAL [\read(*pa)=9, ad1={1:0}, ad2={1:0}, i=19, j=20, pa={1:72}] [L27] COND FALSE !(i < *pa) [L30] CALL, EXPR check(ad1, i) VAL [\old(b)=19, ad1={1:0}] [L10] EXPR ad1[b].a [L10] return ad1[b].a == b; [L30] RET, EXPR check(ad1, i) VAL [ad1={1:0}, ad2={1:0}, check(ad1, i)=0, i=19, j=20, pa={1:72}] [L30] COND TRUE !check(ad1, i) [L37] __VERIFIER_error() VAL [ad1={1:0}, ad2={1:0}, i=19, j=20, pa={1:72}] ----- [2018-11-23 11:07:37,207 INFO L145 WitnessManager]: Wrote witness to /storage/repos/svcomp/c/ldv-regression/test24_false-unreach-call.c-witness.graphml [2018-11-23 11:07:37,207 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 11:07:37,209 INFO L168 Benchmark]: Toolchain (without parser) took 32075.84 ms. Allocated memory was 1.5 GB in the beginning and 2.4 GB in the end (delta: 850.4 MB). Free memory was 1.4 GB in the beginning and 2.3 GB in the end (delta: -866.5 MB). There was no memory consumed. Max. memory is 7.1 GB. [2018-11-23 11:07:37,211 INFO L168 Benchmark]: CDTParser took 1.19 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-11-23 11:07:37,211 INFO L168 Benchmark]: CACSL2BoogieTranslator took 366.29 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-11-23 11:07:37,212 INFO L168 Benchmark]: Boogie Procedure Inliner took 35.75 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-11-23 11:07:37,213 INFO L168 Benchmark]: Boogie Preprocessor took 67.80 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-11-23 11:07:37,213 INFO L168 Benchmark]: RCFGBuilder took 719.87 ms. Allocated memory was 1.5 GB in the beginning and 2.2 GB in the end (delta: 699.4 MB). Free memory was 1.4 GB in the beginning and 2.1 GB in the end (delta: -722.7 MB). Peak memory consumption was 15.2 MB. Max. memory is 7.1 GB. [2018-11-23 11:07:37,213 INFO L168 Benchmark]: TraceAbstraction took 30724.73 ms. Allocated memory was 2.2 GB in the beginning and 2.4 GB in the end (delta: 151.0 MB). Free memory was 2.1 GB in the beginning and 2.3 GB in the end (delta: -169.7 MB). There was no memory consumed. Max. memory is 7.1 GB. [2018-11-23 11:07:37,214 INFO L168 Benchmark]: Witness Printer took 154.82 ms. Allocated memory is still 2.4 GB. Free memory was 2.3 GB in the beginning and 2.3 GB in the end (delta: 15.4 MB). Peak memory consumption was 15.4 MB. Max. memory is 7.1 GB. [2018-11-23 11:07:37,216 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - GenericResult: Assertions are enabled Assertions are enabled - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 1.19 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 366.29 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 35.75 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 67.80 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 719.87 ms. Allocated memory was 1.5 GB in the beginning and 2.2 GB in the end (delta: 699.4 MB). Free memory was 1.4 GB in the beginning and 2.1 GB in the end (delta: -722.7 MB). Peak memory consumption was 15.2 MB. Max. memory is 7.1 GB. * TraceAbstraction took 30724.73 ms. Allocated memory was 2.2 GB in the beginning and 2.4 GB in the end (delta: 151.0 MB). Free memory was 2.1 GB in the beginning and 2.3 GB in the end (delta: -169.7 MB). There was no memory consumed. Max. memory is 7.1 GB. * Witness Printer took 154.82 ms. Allocated memory is still 2.4 GB. Free memory was 2.3 GB in the beginning and 2.3 GB in the end (delta: 15.4 MB). Peak memory consumption was 15.4 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 37]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] struct dummy ad1[20], *ad2; [L16] int i, j, *pa; [L17] j=0 VAL [ad1={1:0}, j=0] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=1] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=2] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=3] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=4] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=5] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=6] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=7] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=8] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=9] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=10] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=11] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=12] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=13] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=14] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=15] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=16] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=17] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=18] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=19] [L17] COND TRUE j<20 [L18] ad1[j].a = __VERIFIER_nondet_int() [L19] ad1[j].b = __VERIFIER_nondet_int() [L17] j++ VAL [ad1={1:0}, j=20] [L17] COND FALSE !(j<20) VAL [ad1={1:0}, j=20] [L21] i = __VERIFIER_nondet_int() [L22] COND TRUE i >= 0 && i < 10 [L23] ad2 = ad1 [L24] ad1[i].a = i [L25] pa = &ad1[i].a [L26] EXPR ad2[i].a [L26] i = ad2[i].a + 10 [L27] EXPR \read(*pa) VAL [\read(*pa)=9, ad1={1:0}, ad2={1:0}, i=19, j=20, pa={1:72}] [L27] COND FALSE !(i < *pa) [L30] CALL, EXPR check(ad1, i) VAL [\old(b)=19, ad1={1:0}] [L10] EXPR ad1[b].a [L10] return ad1[b].a == b; [L30] RET, EXPR check(ad1, i) VAL [ad1={1:0}, ad2={1:0}, check(ad1, i)=0, i=19, j=20, pa={1:72}] [L30] COND TRUE !check(ad1, i) [L37] __VERIFIER_error() VAL [ad1={1:0}, ad2={1:0}, i=19, j=20, pa={1:72}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 24 locations, 1 error locations. UNSAFE Result, 30.6s OverallTime, 6 OverallIterations, 20 TraceHistogramMax, 6.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 98 SDtfs, 35 SDslu, 368 SDs, 0 SdLazy, 358 SolverSat, 34 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 203 GetRequests, 153 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 2.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=58occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 5 MinimizatonAttempts, 1 StatesRemovedByMinimization, 1 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 13.1s SatisfiabilityAnalysisTime, 2.5s InterpolantComputationTime, 171 NumberOfCodeBlocks, 171 NumberOfCodeBlocksAsserted, 18 NumberOfCheckSat, 187 ConstructedInterpolants, 0 QuantifiedInterpolants, 12357 SizeOfPredicates, 4 NumberOfNonLiveVariables, 304 ConjunctsInSsa, 24 ConjunctsInUnsatCore, 8 InterpolantComputations, 2 PerfectInterpolantSequences, 0/234 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...