java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerCInline_WitnessPrinter.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf -i ../../../trunk/examples/svcomp/locks/test_locks_15_false-unreach-call_true-valid-memsafety_false-termination.c -------------------------------------------------------------------------------- This is Ultimate 0.1.23-61f4311 [2018-11-23 10:53:33,752 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 10:53:33,754 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 10:53:33,772 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 10:53:33,772 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 10:53:33,774 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 10:53:33,776 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 10:53:33,778 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 10:53:33,783 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 10:53:33,784 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 10:53:33,788 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 10:53:33,788 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 10:53:33,789 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 10:53:33,790 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 10:53:33,791 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 10:53:33,792 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 10:53:33,795 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 10:53:33,802 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 10:53:33,804 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 10:53:33,808 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 10:53:33,809 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 10:53:33,810 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 10:53:33,813 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 10:53:33,813 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 10:53:33,813 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 10:53:33,814 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 10:53:33,815 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 10:53:33,816 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 10:53:33,816 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 10:53:33,817 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 10:53:33,818 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 10:53:33,818 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... 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[2018-11-23 10:53:33,822 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-23 10:53:33,849 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 10:53:33,850 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 10:53:33,851 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 10:53:33,851 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 10:53:33,851 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 10:53:33,852 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 10:53:33,852 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 10:53:33,852 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 10:53:33,852 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 10:53:33,853 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 10:53:33,853 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 10:53:33,853 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 10:53:33,853 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 10:53:33,853 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 10:53:33,853 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-23 10:53:33,854 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-23 10:53:33,854 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 10:53:33,854 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 10:53:33,854 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 10:53:33,854 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 10:53:33,855 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 10:53:33,855 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 10:53:33,855 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 10:53:33,855 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 10:53:33,855 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:53:33,856 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 10:53:33,856 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 10:53:33,856 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 10:53:33,856 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-23 10:53:33,857 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 10:53:33,857 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-23 10:53:33,857 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-23 10:53:33,857 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 10:53:33,914 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 10:53:33,932 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 10:53:33,937 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 10:53:33,938 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 10:53:33,939 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 10:53:33,940 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/locks/test_locks_15_false-unreach-call_true-valid-memsafety_false-termination.c [2018-11-23 10:53:34,010 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2739ba539/efe84fbfc2a64154bd2da97db4310dde/FLAGb0ba6c68b [2018-11-23 10:53:34,444 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 10:53:34,445 INFO L161 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/locks/test_locks_15_false-unreach-call_true-valid-memsafety_false-termination.c [2018-11-23 10:53:34,453 INFO L355 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2739ba539/efe84fbfc2a64154bd2da97db4310dde/FLAGb0ba6c68b [2018-11-23 10:53:34,796 INFO L363 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2739ba539/efe84fbfc2a64154bd2da97db4310dde [2018-11-23 10:53:34,807 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 10:53:34,808 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 10:53:34,809 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 10:53:34,809 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 10:53:34,813 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 10:53:34,815 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:53:34" (1/1) ... [2018-11-23 10:53:34,818 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1035785c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:53:34, skipping insertion in model container [2018-11-23 10:53:34,818 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:53:34" (1/1) ... [2018-11-23 10:53:34,827 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 10:53:34,855 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 10:53:35,084 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:53:35,090 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 10:53:35,128 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:53:35,143 INFO L195 MainTranslator]: Completed translation [2018-11-23 10:53:35,143 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:53:35 WrapperNode [2018-11-23 10:53:35,144 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 10:53:35,144 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 10:53:35,144 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 10:53:35,145 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 10:53:35,152 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:53:35" (1/1) ... [2018-11-23 10:53:35,160 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:53:35" (1/1) ... [2018-11-23 10:53:35,167 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 10:53:35,167 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 10:53:35,168 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 10:53:35,168 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 10:53:35,178 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:53:35" (1/1) ... [2018-11-23 10:53:35,179 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:53:35" (1/1) ... [2018-11-23 10:53:35,181 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:53:35" (1/1) ... [2018-11-23 10:53:35,181 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:53:35" (1/1) ... [2018-11-23 10:53:35,194 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:53:35" (1/1) ... [2018-11-23 10:53:35,208 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:53:35" (1/1) ... [2018-11-23 10:53:35,210 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:53:35" (1/1) ... [2018-11-23 10:53:35,216 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 10:53:35,217 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 10:53:35,217 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 10:53:35,217 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 10:53:35,222 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:53:35" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:53:35,365 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 10:53:35,365 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 10:53:35,365 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 10:53:35,365 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 10:53:35,366 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 10:53:35,366 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 10:53:36,452 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 10:53:36,452 INFO L280 CfgBuilder]: Removed 1 assue(true) statements. [2018-11-23 10:53:36,453 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:53:36 BoogieIcfgContainer [2018-11-23 10:53:36,453 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 10:53:36,454 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 10:53:36,454 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 10:53:36,458 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 10:53:36,458 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 10:53:34" (1/3) ... [2018-11-23 10:53:36,459 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3986035e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:53:36, skipping insertion in model container [2018-11-23 10:53:36,459 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:53:35" (2/3) ... [2018-11-23 10:53:36,460 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3986035e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:53:36, skipping insertion in model container [2018-11-23 10:53:36,460 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:53:36" (3/3) ... [2018-11-23 10:53:36,461 INFO L112 eAbstractionObserver]: Analyzing ICFG test_locks_15_false-unreach-call_true-valid-memsafety_false-termination.c [2018-11-23 10:53:36,471 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 10:53:36,480 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 10:53:36,498 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 10:53:36,528 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 10:53:36,529 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 10:53:36,529 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 10:53:36,529 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 10:53:36,529 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 10:53:36,530 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 10:53:36,530 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 10:53:36,530 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 10:53:36,530 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 10:53:36,550 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states. [2018-11-23 10:53:36,556 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-23 10:53:36,557 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:53:36,558 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:53:36,560 INFO L423 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:53:36,566 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:53:36,566 INFO L82 PathProgramCache]: Analyzing trace with hash -563352914, now seen corresponding path program 1 times [2018-11-23 10:53:36,571 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:53:36,571 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:53:36,589 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:53:36,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:53:36,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:53:36,685 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:53:36,927 INFO L256 TraceCheckUtils]: 0: Hoare triple {62#true} call ULTIMATE.init(); {62#true} is VALID [2018-11-23 10:53:36,931 INFO L273 TraceCheckUtils]: 1: Hoare triple {62#true} assume true; {62#true} is VALID [2018-11-23 10:53:36,932 INFO L268 TraceCheckUtils]: 2: Hoare quadruple {62#true} {62#true} #282#return; {62#true} is VALID [2018-11-23 10:53:36,932 INFO L256 TraceCheckUtils]: 3: Hoare triple {62#true} call #t~ret16 := main(); {62#true} is VALID [2018-11-23 10:53:36,932 INFO L273 TraceCheckUtils]: 4: Hoare triple {62#true} ~p1~0 := #t~nondet0;havoc #t~nondet0;havoc ~lk1~0;~p2~0 := #t~nondet1;havoc #t~nondet1;havoc ~lk2~0;~p3~0 := #t~nondet2;havoc #t~nondet2;havoc ~lk3~0;~p4~0 := #t~nondet3;havoc #t~nondet3;havoc ~lk4~0;~p5~0 := #t~nondet4;havoc #t~nondet4;havoc ~lk5~0;~p6~0 := #t~nondet5;havoc #t~nondet5;havoc ~lk6~0;~p7~0 := #t~nondet6;havoc #t~nondet6;havoc ~lk7~0;~p8~0 := #t~nondet7;havoc #t~nondet7;havoc ~lk8~0;~p9~0 := #t~nondet8;havoc #t~nondet8;havoc ~lk9~0;~p10~0 := #t~nondet9;havoc #t~nondet9;havoc ~lk10~0;~p11~0 := #t~nondet10;havoc #t~nondet10;havoc ~lk11~0;~p12~0 := #t~nondet11;havoc #t~nondet11;havoc ~lk12~0;~p13~0 := #t~nondet12;havoc #t~nondet12;havoc ~lk13~0;~p14~0 := #t~nondet13;havoc #t~nondet13;havoc ~lk14~0;~p15~0 := #t~nondet14;havoc #t~nondet14;havoc ~lk15~0;havoc ~cond~0; {62#true} is VALID [2018-11-23 10:53:36,933 INFO L273 TraceCheckUtils]: 5: Hoare triple {62#true} assume !false;~cond~0 := #t~nondet15;havoc #t~nondet15; {62#true} is VALID [2018-11-23 10:53:36,933 INFO L273 TraceCheckUtils]: 6: Hoare triple {62#true} assume !(0bv32 == ~cond~0);~lk1~0 := 0bv32;~lk2~0 := 0bv32;~lk3~0 := 0bv32;~lk4~0 := 0bv32;~lk5~0 := 0bv32;~lk6~0 := 0bv32;~lk7~0 := 0bv32;~lk8~0 := 0bv32;~lk9~0 := 0bv32;~lk10~0 := 0bv32;~lk11~0 := 0bv32;~lk12~0 := 0bv32;~lk13~0 := 0bv32;~lk14~0 := 0bv32;~lk15~0 := 0bv32; {62#true} is VALID [2018-11-23 10:53:36,935 INFO L273 TraceCheckUtils]: 7: Hoare triple {62#true} assume 0bv32 != ~p1~0;~lk1~0 := 1bv32; {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:36,938 INFO L273 TraceCheckUtils]: 8: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume 0bv32 != ~p2~0;~lk2~0 := 1bv32; {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:36,939 INFO L273 TraceCheckUtils]: 9: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume 0bv32 != ~p3~0;~lk3~0 := 1bv32; {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:36,942 INFO L273 TraceCheckUtils]: 10: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume 0bv32 != ~p4~0;~lk4~0 := 1bv32; {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:36,942 INFO L273 TraceCheckUtils]: 11: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume 0bv32 != ~p5~0;~lk5~0 := 1bv32; {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:36,943 INFO L273 TraceCheckUtils]: 12: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume 0bv32 != ~p6~0;~lk6~0 := 1bv32; {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:36,945 INFO L273 TraceCheckUtils]: 13: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume 0bv32 != ~p7~0;~lk7~0 := 1bv32; {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:36,946 INFO L273 TraceCheckUtils]: 14: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume !(0bv32 != ~p8~0); {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:36,954 INFO L273 TraceCheckUtils]: 15: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume 0bv32 != ~p9~0;~lk9~0 := 1bv32; {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:36,964 INFO L273 TraceCheckUtils]: 16: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume 0bv32 != ~p10~0;~lk10~0 := 1bv32; {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:36,982 INFO L273 TraceCheckUtils]: 17: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume 0bv32 != ~p11~0;~lk11~0 := 1bv32; {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:36,997 INFO L273 TraceCheckUtils]: 18: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume 0bv32 != ~p12~0;~lk12~0 := 1bv32; {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:37,011 INFO L273 TraceCheckUtils]: 19: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume 0bv32 != ~p13~0;~lk13~0 := 1bv32; {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:37,020 INFO L273 TraceCheckUtils]: 20: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume 0bv32 != ~p14~0;~lk14~0 := 1bv32; {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:37,031 INFO L273 TraceCheckUtils]: 21: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume 0bv32 != ~p15~0;~lk15~0 := 1bv32; {88#(not (= (_ bv0 32) main_~p1~0))} is VALID [2018-11-23 10:53:37,042 INFO L273 TraceCheckUtils]: 22: Hoare triple {88#(not (= (_ bv0 32) main_~p1~0))} assume !(0bv32 != ~p1~0); {63#false} is VALID [2018-11-23 10:53:37,043 INFO L273 TraceCheckUtils]: 23: Hoare triple {63#false} assume !(0bv32 != ~p2~0); {63#false} is VALID [2018-11-23 10:53:37,043 INFO L273 TraceCheckUtils]: 24: Hoare triple {63#false} assume !false; {63#false} is VALID [2018-11-23 10:53:37,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:53:37,058 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:53:37,068 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:53:37,068 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 10:53:37,077 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-11-23 10:53:37,080 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:53:37,091 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-23 10:53:37,176 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 25 edges. 25 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:53:37,176 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 10:53:37,184 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 10:53:37,185 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:53:37,187 INFO L87 Difference]: Start difference. First operand 59 states. Second operand 3 states. [2018-11-23 10:53:38,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:53:38,215 INFO L93 Difference]: Finished difference Result 164 states and 305 transitions. [2018-11-23 10:53:38,216 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 10:53:38,216 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-11-23 10:53:38,216 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:53:38,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:53:38,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 305 transitions. [2018-11-23 10:53:38,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:53:38,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 305 transitions. [2018-11-23 10:53:38,246 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 305 transitions. [2018-11-23 10:53:39,035 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 305 edges. 305 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:53:39,051 INFO L225 Difference]: With dead ends: 164 [2018-11-23 10:53:39,052 INFO L226 Difference]: Without dead ends: 102 [2018-11-23 10:53:39,056 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:53:39,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-11-23 10:53:39,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 100. [2018-11-23 10:53:39,151 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:53:39,151 INFO L82 GeneralOperation]: Start isEquivalent. First operand 102 states. Second operand 100 states. [2018-11-23 10:53:39,152 INFO L74 IsIncluded]: Start isIncluded. First operand 102 states. Second operand 100 states. [2018-11-23 10:53:39,152 INFO L87 Difference]: Start difference. First operand 102 states. Second operand 100 states. [2018-11-23 10:53:39,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:53:39,163 INFO L93 Difference]: Finished difference Result 102 states and 187 transitions. [2018-11-23 10:53:39,163 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 187 transitions. [2018-11-23 10:53:39,165 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:53:39,165 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:53:39,165 INFO L74 IsIncluded]: Start isIncluded. First operand 100 states. Second operand 102 states. [2018-11-23 10:53:39,165 INFO L87 Difference]: Start difference. First operand 100 states. Second operand 102 states. [2018-11-23 10:53:39,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:53:39,175 INFO L93 Difference]: Finished difference Result 102 states and 187 transitions. [2018-11-23 10:53:39,175 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 187 transitions. [2018-11-23 10:53:39,177 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:53:39,177 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:53:39,177 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:53:39,178 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:53:39,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100 states. [2018-11-23 10:53:39,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 186 transitions. [2018-11-23 10:53:39,186 INFO L78 Accepts]: Start accepts. Automaton has 100 states and 186 transitions. Word has length 25 [2018-11-23 10:53:39,187 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:53:39,187 INFO L480 AbstractCegarLoop]: Abstraction has 100 states and 186 transitions. [2018-11-23 10:53:39,187 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 10:53:39,187 INFO L276 IsEmpty]: Start isEmpty. Operand 100 states and 186 transitions. [2018-11-23 10:53:39,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-23 10:53:39,189 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:53:39,189 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:53:39,189 INFO L423 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:53:39,190 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:53:39,190 INFO L82 PathProgramCache]: Analyzing trace with hash -563360106, now seen corresponding path program 1 times [2018-11-23 10:53:39,190 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:53:39,191 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:53:39,216 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:53:39,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:53:39,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:53:39,274 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:53:39,391 INFO L256 TraceCheckUtils]: 0: Hoare triple {627#true} call ULTIMATE.init(); {627#true} is VALID [2018-11-23 10:53:39,391 INFO L273 TraceCheckUtils]: 1: Hoare triple {627#true} assume true; {627#true} is VALID [2018-11-23 10:53:39,391 INFO L268 TraceCheckUtils]: 2: Hoare quadruple {627#true} {627#true} #282#return; {627#true} is VALID [2018-11-23 10:53:39,392 INFO L256 TraceCheckUtils]: 3: Hoare triple {627#true} call #t~ret16 := main(); {627#true} is VALID [2018-11-23 10:53:39,392 INFO L273 TraceCheckUtils]: 4: Hoare triple {627#true} ~p1~0 := #t~nondet0;havoc #t~nondet0;havoc ~lk1~0;~p2~0 := #t~nondet1;havoc #t~nondet1;havoc ~lk2~0;~p3~0 := #t~nondet2;havoc #t~nondet2;havoc ~lk3~0;~p4~0 := #t~nondet3;havoc #t~nondet3;havoc ~lk4~0;~p5~0 := #t~nondet4;havoc #t~nondet4;havoc ~lk5~0;~p6~0 := #t~nondet5;havoc #t~nondet5;havoc ~lk6~0;~p7~0 := #t~nondet6;havoc #t~nondet6;havoc ~lk7~0;~p8~0 := #t~nondet7;havoc #t~nondet7;havoc ~lk8~0;~p9~0 := #t~nondet8;havoc #t~nondet8;havoc ~lk9~0;~p10~0 := #t~nondet9;havoc #t~nondet9;havoc ~lk10~0;~p11~0 := #t~nondet10;havoc #t~nondet10;havoc ~lk11~0;~p12~0 := #t~nondet11;havoc #t~nondet11;havoc ~lk12~0;~p13~0 := #t~nondet12;havoc #t~nondet12;havoc ~lk13~0;~p14~0 := #t~nondet13;havoc #t~nondet13;havoc ~lk14~0;~p15~0 := #t~nondet14;havoc #t~nondet14;havoc ~lk15~0;havoc ~cond~0; {627#true} is VALID [2018-11-23 10:53:39,392 INFO L273 TraceCheckUtils]: 5: Hoare triple {627#true} assume !false;~cond~0 := #t~nondet15;havoc #t~nondet15; {627#true} is VALID [2018-11-23 10:53:39,393 INFO L273 TraceCheckUtils]: 6: Hoare triple {627#true} assume !(0bv32 == ~cond~0);~lk1~0 := 0bv32;~lk2~0 := 0bv32;~lk3~0 := 0bv32;~lk4~0 := 0bv32;~lk5~0 := 0bv32;~lk6~0 := 0bv32;~lk7~0 := 0bv32;~lk8~0 := 0bv32;~lk9~0 := 0bv32;~lk10~0 := 0bv32;~lk11~0 := 0bv32;~lk12~0 := 0bv32;~lk13~0 := 0bv32;~lk14~0 := 0bv32;~lk15~0 := 0bv32; {627#true} is VALID [2018-11-23 10:53:39,394 INFO L273 TraceCheckUtils]: 7: Hoare triple {627#true} assume 0bv32 != ~p1~0;~lk1~0 := 1bv32; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,394 INFO L273 TraceCheckUtils]: 8: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 != ~p2~0;~lk2~0 := 1bv32; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,397 INFO L273 TraceCheckUtils]: 9: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 != ~p3~0;~lk3~0 := 1bv32; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,397 INFO L273 TraceCheckUtils]: 10: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 != ~p4~0;~lk4~0 := 1bv32; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,400 INFO L273 TraceCheckUtils]: 11: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 != ~p5~0;~lk5~0 := 1bv32; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,400 INFO L273 TraceCheckUtils]: 12: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 != ~p6~0;~lk6~0 := 1bv32; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,401 INFO L273 TraceCheckUtils]: 13: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 != ~p7~0;~lk7~0 := 1bv32; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,401 INFO L273 TraceCheckUtils]: 14: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume !(0bv32 != ~p8~0); {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,403 INFO L273 TraceCheckUtils]: 15: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 != ~p9~0;~lk9~0 := 1bv32; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,403 INFO L273 TraceCheckUtils]: 16: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 != ~p10~0;~lk10~0 := 1bv32; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,404 INFO L273 TraceCheckUtils]: 17: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 != ~p11~0;~lk11~0 := 1bv32; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,405 INFO L273 TraceCheckUtils]: 18: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 != ~p12~0;~lk12~0 := 1bv32; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,405 INFO L273 TraceCheckUtils]: 19: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 != ~p13~0;~lk13~0 := 1bv32; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,406 INFO L273 TraceCheckUtils]: 20: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 != ~p14~0;~lk14~0 := 1bv32; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,407 INFO L273 TraceCheckUtils]: 21: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 != ~p15~0;~lk15~0 := 1bv32; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,411 INFO L273 TraceCheckUtils]: 22: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 != ~p1~0; {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:53:39,411 INFO L273 TraceCheckUtils]: 23: Hoare triple {653#(= (bvadd main_~lk1~0 (_ bv4294967295 32)) (_ bv0 32))} assume 1bv32 != ~lk1~0; {628#false} is VALID [2018-11-23 10:53:39,412 INFO L273 TraceCheckUtils]: 24: Hoare triple {628#false} assume !false; {628#false} is VALID [2018-11-23 10:53:39,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:53:39,414 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:53:39,415 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:53:39,416 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 10:53:39,417 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-11-23 10:53:39,417 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:53:39,417 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-23 10:53:39,463 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 25 edges. 25 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:53:39,463 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 10:53:39,463 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 10:53:39,464 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:53:39,464 INFO L87 Difference]: Start difference. First operand 100 states and 186 transitions. Second operand 3 states. [2018-11-23 10:53:39,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:53:39,785 INFO L93 Difference]: Finished difference Result 103 states and 189 transitions. [2018-11-23 10:53:39,786 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 10:53:39,786 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-11-23 10:53:39,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:53:39,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:53:39,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 130 transitions. [2018-11-23 10:53:39,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:53:39,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 130 transitions. [2018-11-23 10:53:39,793 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 130 transitions. [2018-11-23 10:53:40,009 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 130 edges. 130 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:53:40,013 INFO L225 Difference]: With dead ends: 103 [2018-11-23 10:53:40,013 INFO L226 Difference]: Without dead ends: 101 [2018-11-23 10:53:40,014 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:53:40,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2018-11-23 10:53:40,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 101. [2018-11-23 10:53:40,033 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:53:40,033 INFO L82 GeneralOperation]: Start isEquivalent. First operand 101 states. Second operand 101 states. [2018-11-23 10:53:40,034 INFO L74 IsIncluded]: Start isIncluded. First operand 101 states. Second operand 101 states. [2018-11-23 10:53:40,034 INFO L87 Difference]: Start difference. First operand 101 states. Second operand 101 states. [2018-11-23 10:53:40,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:53:40,040 INFO L93 Difference]: Finished difference Result 101 states and 187 transitions. [2018-11-23 10:53:40,040 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 187 transitions. [2018-11-23 10:53:40,042 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:53:40,042 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:53:40,042 INFO L74 IsIncluded]: Start isIncluded. First operand 101 states. Second operand 101 states. [2018-11-23 10:53:40,042 INFO L87 Difference]: Start difference. First operand 101 states. Second operand 101 states. [2018-11-23 10:53:40,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:53:40,057 INFO L93 Difference]: Finished difference Result 101 states and 187 transitions. [2018-11-23 10:53:40,057 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 187 transitions. [2018-11-23 10:53:40,060 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:53:40,060 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:53:40,061 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:53:40,061 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:53:40,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2018-11-23 10:53:40,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 187 transitions. [2018-11-23 10:53:40,071 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 187 transitions. Word has length 25 [2018-11-23 10:53:40,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:53:40,071 INFO L480 AbstractCegarLoop]: Abstraction has 101 states and 187 transitions. [2018-11-23 10:53:40,071 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 10:53:40,071 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 187 transitions. [2018-11-23 10:53:40,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-23 10:53:40,072 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:53:40,073 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:53:40,073 INFO L423 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:53:40,073 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:53:40,073 INFO L82 PathProgramCache]: Analyzing trace with hash 1737469676, now seen corresponding path program 1 times [2018-11-23 10:53:40,078 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:53:40,078 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:53:40,104 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:53:40,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:53:40,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:53:40,144 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:53:40,209 INFO L256 TraceCheckUtils]: 0: Hoare triple {1125#true} call ULTIMATE.init(); {1125#true} is VALID [2018-11-23 10:53:40,210 INFO L273 TraceCheckUtils]: 1: Hoare triple {1125#true} assume true; {1125#true} is VALID [2018-11-23 10:53:40,210 INFO L268 TraceCheckUtils]: 2: Hoare quadruple {1125#true} {1125#true} #282#return; {1125#true} is VALID [2018-11-23 10:53:40,211 INFO L256 TraceCheckUtils]: 3: Hoare triple {1125#true} call #t~ret16 := main(); {1125#true} is VALID [2018-11-23 10:53:40,211 INFO L273 TraceCheckUtils]: 4: Hoare triple {1125#true} ~p1~0 := #t~nondet0;havoc #t~nondet0;havoc ~lk1~0;~p2~0 := #t~nondet1;havoc #t~nondet1;havoc ~lk2~0;~p3~0 := #t~nondet2;havoc #t~nondet2;havoc ~lk3~0;~p4~0 := #t~nondet3;havoc #t~nondet3;havoc ~lk4~0;~p5~0 := #t~nondet4;havoc #t~nondet4;havoc ~lk5~0;~p6~0 := #t~nondet5;havoc #t~nondet5;havoc ~lk6~0;~p7~0 := #t~nondet6;havoc #t~nondet6;havoc ~lk7~0;~p8~0 := #t~nondet7;havoc #t~nondet7;havoc ~lk8~0;~p9~0 := #t~nondet8;havoc #t~nondet8;havoc ~lk9~0;~p10~0 := #t~nondet9;havoc #t~nondet9;havoc ~lk10~0;~p11~0 := #t~nondet10;havoc #t~nondet10;havoc ~lk11~0;~p12~0 := #t~nondet11;havoc #t~nondet11;havoc ~lk12~0;~p13~0 := #t~nondet12;havoc #t~nondet12;havoc ~lk13~0;~p14~0 := #t~nondet13;havoc #t~nondet13;havoc ~lk14~0;~p15~0 := #t~nondet14;havoc #t~nondet14;havoc ~lk15~0;havoc ~cond~0; {1125#true} is VALID [2018-11-23 10:53:40,212 INFO L273 TraceCheckUtils]: 5: Hoare triple {1125#true} assume !false;~cond~0 := #t~nondet15;havoc #t~nondet15; {1125#true} is VALID [2018-11-23 10:53:40,212 INFO L273 TraceCheckUtils]: 6: Hoare triple {1125#true} assume !(0bv32 == ~cond~0);~lk1~0 := 0bv32;~lk2~0 := 0bv32;~lk3~0 := 0bv32;~lk4~0 := 0bv32;~lk5~0 := 0bv32;~lk6~0 := 0bv32;~lk7~0 := 0bv32;~lk8~0 := 0bv32;~lk9~0 := 0bv32;~lk10~0 := 0bv32;~lk11~0 := 0bv32;~lk12~0 := 0bv32;~lk13~0 := 0bv32;~lk14~0 := 0bv32;~lk15~0 := 0bv32; {1125#true} is VALID [2018-11-23 10:53:40,212 INFO L273 TraceCheckUtils]: 7: Hoare triple {1125#true} assume !(0bv32 != ~p1~0); {1125#true} is VALID [2018-11-23 10:53:40,214 INFO L273 TraceCheckUtils]: 8: Hoare triple {1125#true} assume 0bv32 != ~p2~0;~lk2~0 := 1bv32; {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,215 INFO L273 TraceCheckUtils]: 9: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume 0bv32 != ~p3~0;~lk3~0 := 1bv32; {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,216 INFO L273 TraceCheckUtils]: 10: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume 0bv32 != ~p4~0;~lk4~0 := 1bv32; {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,216 INFO L273 TraceCheckUtils]: 11: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume 0bv32 != ~p5~0;~lk5~0 := 1bv32; {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,219 INFO L273 TraceCheckUtils]: 12: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume 0bv32 != ~p6~0;~lk6~0 := 1bv32; {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,220 INFO L273 TraceCheckUtils]: 13: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume 0bv32 != ~p7~0;~lk7~0 := 1bv32; {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,220 INFO L273 TraceCheckUtils]: 14: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume !(0bv32 != ~p8~0); {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,222 INFO L273 TraceCheckUtils]: 15: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume 0bv32 != ~p9~0;~lk9~0 := 1bv32; {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,222 INFO L273 TraceCheckUtils]: 16: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume 0bv32 != ~p10~0;~lk10~0 := 1bv32; {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,224 INFO L273 TraceCheckUtils]: 17: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume 0bv32 != ~p11~0;~lk11~0 := 1bv32; {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,224 INFO L273 TraceCheckUtils]: 18: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume 0bv32 != ~p12~0;~lk12~0 := 1bv32; {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,227 INFO L273 TraceCheckUtils]: 19: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume 0bv32 != ~p13~0;~lk13~0 := 1bv32; {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,227 INFO L273 TraceCheckUtils]: 20: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume 0bv32 != ~p14~0;~lk14~0 := 1bv32; {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,247 INFO L273 TraceCheckUtils]: 21: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume 0bv32 != ~p15~0;~lk15~0 := 1bv32; {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,262 INFO L273 TraceCheckUtils]: 22: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume !(0bv32 != ~p1~0); {1154#(not (= (_ bv0 32) main_~p2~0))} is VALID [2018-11-23 10:53:40,271 INFO L273 TraceCheckUtils]: 23: Hoare triple {1154#(not (= (_ bv0 32) main_~p2~0))} assume !(0bv32 != ~p2~0); {1126#false} is VALID [2018-11-23 10:53:40,272 INFO L273 TraceCheckUtils]: 24: Hoare triple {1126#false} assume !false; {1126#false} is VALID [2018-11-23 10:53:40,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:53:40,274 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:53:40,279 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:53:40,280 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 10:53:40,280 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-11-23 10:53:40,280 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:53:40,281 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-23 10:53:40,344 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 25 edges. 25 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:53:40,344 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 10:53:40,344 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 10:53:40,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:53:40,345 INFO L87 Difference]: Start difference. First operand 101 states and 187 transitions. Second operand 3 states. [2018-11-23 10:53:40,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:53:40,568 INFO L93 Difference]: Finished difference Result 236 states and 440 transitions. [2018-11-23 10:53:40,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 10:53:40,568 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-11-23 10:53:40,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:53:40,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:53:40,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 230 transitions. [2018-11-23 10:53:40,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:53:40,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 230 transitions. [2018-11-23 10:53:40,577 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 230 transitions. [2018-11-23 10:53:40,929 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 230 edges. 230 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:53:40,935 INFO L225 Difference]: With dead ends: 236 [2018-11-23 10:53:40,935 INFO L226 Difference]: Without dead ends: 140 [2018-11-23 10:53:40,936 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:53:40,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-11-23 10:53:40,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 138. [2018-11-23 10:53:40,962 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:53:40,962 INFO L82 GeneralOperation]: Start isEquivalent. First operand 140 states. Second operand 138 states. [2018-11-23 10:53:40,962 INFO L74 IsIncluded]: Start isIncluded. First operand 140 states. Second operand 138 states. [2018-11-23 10:53:40,963 INFO L87 Difference]: Start difference. First operand 140 states. Second operand 138 states. [2018-11-23 10:53:40,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:53:40,972 INFO L93 Difference]: Finished difference Result 140 states and 254 transitions. [2018-11-23 10:53:40,972 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 254 transitions. [2018-11-23 10:53:40,973 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:53:40,974 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:53:40,976 INFO L74 IsIncluded]: Start isIncluded. First operand 138 states. Second operand 140 states. [2018-11-23 10:53:40,976 INFO L87 Difference]: Start difference. First operand 138 states. Second operand 140 states. [2018-11-23 10:53:40,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:53:40,989 INFO L93 Difference]: Finished difference Result 140 states and 254 transitions. [2018-11-23 10:53:40,989 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 254 transitions. [2018-11-23 10:53:40,990 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:53:40,990 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:53:40,990 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:53:40,991 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:53:40,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-11-23 10:53:40,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 253 transitions. [2018-11-23 10:53:40,998 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 253 transitions. Word has length 25 [2018-11-23 10:53:40,999 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:53:40,999 INFO L480 AbstractCegarLoop]: Abstraction has 138 states and 253 transitions. [2018-11-23 10:53:40,999 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 10:53:40,999 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 253 transitions. [2018-11-23 10:53:41,000 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-23 10:53:41,000 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:53:41,001 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:53:41,001 INFO L423 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:53:41,001 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:53:41,002 INFO L82 PathProgramCache]: Analyzing trace with hash 1737462484, now seen corresponding path program 1 times [2018-11-23 10:53:41,002 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:53:41,002 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:53:41,029 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:53:41,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:53:41,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:53:41,074 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:53:41,143 INFO L256 TraceCheckUtils]: 0: Hoare triple {1876#true} call ULTIMATE.init(); {1876#true} is VALID [2018-11-23 10:53:41,144 INFO L273 TraceCheckUtils]: 1: Hoare triple {1876#true} assume true; {1876#true} is VALID [2018-11-23 10:53:41,144 INFO L268 TraceCheckUtils]: 2: Hoare quadruple {1876#true} {1876#true} #282#return; {1876#true} is VALID [2018-11-23 10:53:41,144 INFO L256 TraceCheckUtils]: 3: Hoare triple {1876#true} call #t~ret16 := main(); {1876#true} is VALID [2018-11-23 10:53:41,145 INFO L273 TraceCheckUtils]: 4: Hoare triple {1876#true} ~p1~0 := #t~nondet0;havoc #t~nondet0;havoc ~lk1~0;~p2~0 := #t~nondet1;havoc #t~nondet1;havoc ~lk2~0;~p3~0 := #t~nondet2;havoc #t~nondet2;havoc ~lk3~0;~p4~0 := #t~nondet3;havoc #t~nondet3;havoc ~lk4~0;~p5~0 := #t~nondet4;havoc #t~nondet4;havoc ~lk5~0;~p6~0 := #t~nondet5;havoc #t~nondet5;havoc ~lk6~0;~p7~0 := #t~nondet6;havoc #t~nondet6;havoc ~lk7~0;~p8~0 := #t~nondet7;havoc #t~nondet7;havoc ~lk8~0;~p9~0 := #t~nondet8;havoc #t~nondet8;havoc ~lk9~0;~p10~0 := #t~nondet9;havoc #t~nondet9;havoc ~lk10~0;~p11~0 := #t~nondet10;havoc #t~nondet10;havoc ~lk11~0;~p12~0 := #t~nondet11;havoc #t~nondet11;havoc ~lk12~0;~p13~0 := #t~nondet12;havoc #t~nondet12;havoc ~lk13~0;~p14~0 := #t~nondet13;havoc #t~nondet13;havoc ~lk14~0;~p15~0 := #t~nondet14;havoc #t~nondet14;havoc ~lk15~0;havoc ~cond~0; {1876#true} is VALID [2018-11-23 10:53:41,145 INFO L273 TraceCheckUtils]: 5: Hoare triple {1876#true} assume !false;~cond~0 := #t~nondet15;havoc #t~nondet15; {1876#true} is VALID [2018-11-23 10:53:41,145 INFO L273 TraceCheckUtils]: 6: Hoare triple {1876#true} assume !(0bv32 == ~cond~0);~lk1~0 := 0bv32;~lk2~0 := 0bv32;~lk3~0 := 0bv32;~lk4~0 := 0bv32;~lk5~0 := 0bv32;~lk6~0 := 0bv32;~lk7~0 := 0bv32;~lk8~0 := 0bv32;~lk9~0 := 0bv32;~lk10~0 := 0bv32;~lk11~0 := 0bv32;~lk12~0 := 0bv32;~lk13~0 := 0bv32;~lk14~0 := 0bv32;~lk15~0 := 0bv32; {1876#true} is VALID [2018-11-23 10:53:41,146 INFO L273 TraceCheckUtils]: 7: Hoare triple {1876#true} assume !(0bv32 != ~p1~0); {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,148 INFO L273 TraceCheckUtils]: 8: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume 0bv32 != ~p2~0;~lk2~0 := 1bv32; {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,148 INFO L273 TraceCheckUtils]: 9: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume 0bv32 != ~p3~0;~lk3~0 := 1bv32; {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,150 INFO L273 TraceCheckUtils]: 10: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume 0bv32 != ~p4~0;~lk4~0 := 1bv32; {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,150 INFO L273 TraceCheckUtils]: 11: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume 0bv32 != ~p5~0;~lk5~0 := 1bv32; {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,152 INFO L273 TraceCheckUtils]: 12: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume 0bv32 != ~p6~0;~lk6~0 := 1bv32; {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,153 INFO L273 TraceCheckUtils]: 13: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume 0bv32 != ~p7~0;~lk7~0 := 1bv32; {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,153 INFO L273 TraceCheckUtils]: 14: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume !(0bv32 != ~p8~0); {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,155 INFO L273 TraceCheckUtils]: 15: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume 0bv32 != ~p9~0;~lk9~0 := 1bv32; {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,155 INFO L273 TraceCheckUtils]: 16: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume 0bv32 != ~p10~0;~lk10~0 := 1bv32; {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,158 INFO L273 TraceCheckUtils]: 17: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume 0bv32 != ~p11~0;~lk11~0 := 1bv32; {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,161 INFO L273 TraceCheckUtils]: 18: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume 0bv32 != ~p12~0;~lk12~0 := 1bv32; {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,162 INFO L273 TraceCheckUtils]: 19: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume 0bv32 != ~p13~0;~lk13~0 := 1bv32; {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,163 INFO L273 TraceCheckUtils]: 20: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume 0bv32 != ~p14~0;~lk14~0 := 1bv32; {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,163 INFO L273 TraceCheckUtils]: 21: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume 0bv32 != ~p15~0;~lk15~0 := 1bv32; {1902#(= (_ bv0 32) main_~p1~0)} is VALID [2018-11-23 10:53:41,164 INFO L273 TraceCheckUtils]: 22: Hoare triple {1902#(= (_ bv0 32) main_~p1~0)} assume 0bv32 != ~p1~0; {1877#false} is VALID [2018-11-23 10:53:41,165 INFO L273 TraceCheckUtils]: 23: Hoare triple {1877#false} assume 1bv32 != ~lk1~0; {1877#false} is VALID [2018-11-23 10:53:41,165 INFO L273 TraceCheckUtils]: 24: Hoare triple {1877#false} assume !false; {1877#false} is VALID [2018-11-23 10:53:41,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:53:41,167 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:53:41,173 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:53:41,173 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 10:53:41,174 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-11-23 10:53:41,174 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:53:41,174 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-23 10:53:41,213 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 25 edges. 25 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:53:41,213 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 10:53:41,214 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 10:53:41,214 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:53:41,214 INFO L87 Difference]: Start difference. First operand 138 states and 253 transitions. Second operand 3 states. [2018-11-23 10:53:41,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:53:41,473 INFO L93 Difference]: Finished difference Result 190 states and 344 transitions. [2018-11-23 10:53:41,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 10:53:41,473 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-11-23 10:53:41,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:53:41,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:53:41,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 277 transitions. [2018-11-23 10:53:41,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:53:41,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 277 transitions. [2018-11-23 10:53:41,483 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 277 transitions. [2018-11-23 10:53:41,860 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 277 edges. 277 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:53:41,864 INFO L225 Difference]: With dead ends: 190 [2018-11-23 10:53:41,864 INFO L226 Difference]: Without dead ends: 138 [2018-11-23 10:53:41,865 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:53:41,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-11-23 10:53:41,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 136. [2018-11-23 10:53:41,902 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:53:41,902 INFO L82 GeneralOperation]: Start isEquivalent. First operand 138 states. Second operand 136 states. [2018-11-23 10:53:41,902 INFO L74 IsIncluded]: Start isIncluded. First operand 138 states. Second operand 136 states. [2018-11-23 10:53:41,902 INFO L87 Difference]: Start difference. First operand 138 states. Second operand 136 states. [2018-11-23 10:53:41,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:53:41,908 INFO L93 Difference]: Finished difference Result 138 states and 247 transitions. [2018-11-23 10:53:41,908 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 247 transitions. [2018-11-23 10:53:41,910 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:53:41,910 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:53:41,910 INFO L74 IsIncluded]: Start isIncluded. First operand 136 states. Second operand 138 states. [2018-11-23 10:53:41,910 INFO L87 Difference]: Start difference. First operand 136 states. Second operand 138 states. [2018-11-23 10:53:41,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:53:41,917 INFO L93 Difference]: Finished difference Result 138 states and 247 transitions. [2018-11-23 10:53:41,917 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 247 transitions. [2018-11-23 10:53:41,917 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:53:41,918 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:53:41,924 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:53:41,924 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:53:41,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-11-23 10:53:41,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 246 transitions. [2018-11-23 10:53:41,929 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 246 transitions. Word has length 25 [2018-11-23 10:53:41,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:53:41,930 INFO L480 AbstractCegarLoop]: Abstraction has 136 states and 246 transitions. [2018-11-23 10:53:41,930 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 10:53:41,930 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 246 transitions. [2018-11-23 10:53:41,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-23 10:53:41,931 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:53:41,931 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:53:41,932 INFO L423 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:53:41,932 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:53:41,932 INFO L82 PathProgramCache]: Analyzing trace with hash 149121774, now seen corresponding path program 1 times [2018-11-23 10:53:41,932 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:53:41,933 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:53:41,964 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:53:41,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 10:53:42,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 10:53:42,063 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-11-23 10:53:42,063 WARN L521 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] CALL call ULTIMATE.init(); [?] assume true; [?] RET #282#return; [?] CALL call #t~ret16 := main(); [?] ~p1~0 := #t~nondet0;havoc #t~nondet0;havoc ~lk1~0;~p2~0 := #t~nondet1;havoc #t~nondet1;havoc ~lk2~0;~p3~0 := #t~nondet2;havoc #t~nondet2;havoc ~lk3~0;~p4~0 := #t~nondet3;havoc #t~nondet3;havoc ~lk4~0;~p5~0 := #t~nondet4;havoc #t~nondet4;havoc ~lk5~0;~p6~0 := #t~nondet5;havoc #t~nondet5;havoc ~lk6~0;~p7~0 := #t~nondet6;havoc #t~nondet6;havoc ~lk7~0;~p8~0 := #t~nondet7;havoc #t~nondet7;havoc ~lk8~0;~p9~0 := #t~nondet8;havoc #t~nondet8;havoc ~lk9~0;~p10~0 := #t~nondet9;havoc #t~nondet9;havoc ~lk10~0;~p11~0 := #t~nondet10;havoc #t~nondet10;havoc ~lk11~0;~p12~0 := #t~nondet11;havoc #t~nondet11;havoc ~lk12~0;~p13~0 := #t~nondet12;havoc #t~nondet12;havoc ~lk13~0;~p14~0 := #t~nondet13;havoc #t~nondet13;havoc ~lk14~0;~p15~0 := #t~nondet14;havoc #t~nondet14;havoc ~lk15~0;havoc ~cond~0; VAL [main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !false;~cond~0 := #t~nondet15;havoc #t~nondet15; VAL [main_~cond~0=(_ bv14 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !(0bv32 == ~cond~0);~lk1~0 := 0bv32;~lk2~0 := 0bv32;~lk3~0 := 0bv32;~lk4~0 := 0bv32;~lk5~0 := 0bv32;~lk6~0 := 0bv32;~lk7~0 := 0bv32;~lk8~0 := 0bv32;~lk9~0 := 0bv32;~lk10~0 := 0bv32;~lk11~0 := 0bv32;~lk12~0 := 0bv32;~lk13~0 := 0bv32;~lk14~0 := 0bv32;~lk15~0 := 0bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv0 32), main_~lk4~0=(_ bv0 32), main_~lk5~0=(_ bv0 32), main_~lk6~0=(_ bv0 32), main_~lk7~0=(_ bv0 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !(0bv32 != ~p1~0); VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv0 32), main_~lk4~0=(_ bv0 32), main_~lk5~0=(_ bv0 32), main_~lk6~0=(_ bv0 32), main_~lk7~0=(_ bv0 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !(0bv32 != ~p2~0); VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv0 32), main_~lk4~0=(_ bv0 32), main_~lk5~0=(_ bv0 32), main_~lk6~0=(_ bv0 32), main_~lk7~0=(_ bv0 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p3~0;~lk3~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv0 32), main_~lk5~0=(_ bv0 32), main_~lk6~0=(_ bv0 32), main_~lk7~0=(_ bv0 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p4~0;~lk4~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv0 32), main_~lk6~0=(_ bv0 32), main_~lk7~0=(_ bv0 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p5~0;~lk5~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv0 32), main_~lk7~0=(_ bv0 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p6~0;~lk6~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv0 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p7~0;~lk7~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !(0bv32 != ~p8~0); VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p9~0;~lk9~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p10~0;~lk10~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p11~0;~lk11~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p12~0;~lk12~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv1 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p13~0;~lk13~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv1 32), main_~lk13~0=(_ bv1 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p14~0;~lk14~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv1 32), main_~lk13~0=(_ bv1 32), main_~lk14~0=(_ bv1 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p15~0;~lk15~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv1 32), main_~lk13~0=(_ bv1 32), main_~lk14~0=(_ bv1 32), main_~lk15~0=(_ bv1 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !(0bv32 != ~p1~0); VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv1 32), main_~lk13~0=(_ bv1 32), main_~lk14~0=(_ bv1 32), main_~lk15~0=(_ bv1 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !(0bv32 != ~p2~0); VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv1 32), main_~lk13~0=(_ bv1 32), main_~lk14~0=(_ bv1 32), main_~lk15~0=(_ bv1 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !false; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv1 32), main_~lk13~0=(_ bv1 32), main_~lk14~0=(_ bv1 32), main_~lk15~0=(_ bv1 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] CALL call ULTIMATE.init(); [?] ensures true; [?] RET call ULTIMATE.init(); [?] CALL call #t~ret16 := main(); [L6] ~p1~0 := #t~nondet0; [L6] havoc #t~nondet0; [L7] havoc ~lk1~0; [L9] ~p2~0 := #t~nondet1; [L9] havoc #t~nondet1; [L10] havoc ~lk2~0; [L12] ~p3~0 := #t~nondet2; [L12] havoc #t~nondet2; [L13] havoc ~lk3~0; [L15] ~p4~0 := #t~nondet3; [L15] havoc #t~nondet3; [L16] havoc ~lk4~0; [L18] ~p5~0 := #t~nondet4; [L18] havoc #t~nondet4; [L19] havoc ~lk5~0; [L21] ~p6~0 := #t~nondet5; [L21] havoc #t~nondet5; [L22] havoc ~lk6~0; [L24] ~p7~0 := #t~nondet6; [L24] havoc #t~nondet6; [L25] havoc ~lk7~0; [L27] ~p8~0 := #t~nondet7; [L27] havoc #t~nondet7; [L28] havoc ~lk8~0; [L30] ~p9~0 := #t~nondet8; [L30] havoc #t~nondet8; [L31] havoc ~lk9~0; [L33] ~p10~0 := #t~nondet9; [L33] havoc #t~nondet9; [L34] havoc ~lk10~0; [L36] ~p11~0 := #t~nondet10; [L36] havoc #t~nondet10; [L37] havoc ~lk11~0; [L39] ~p12~0 := #t~nondet11; [L39] havoc #t~nondet11; [L40] havoc ~lk12~0; [L42] ~p13~0 := #t~nondet12; [L42] havoc #t~nondet12; [L43] havoc ~lk13~0; [L45] ~p14~0 := #t~nondet13; [L45] havoc #t~nondet13; [L46] havoc ~lk14~0; [L48] ~p15~0 := #t~nondet14; [L48] havoc #t~nondet14; [L49] havoc ~lk15~0; [L52] havoc ~cond~0; VAL [~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L54-L228] assume !false; [L55] ~cond~0 := #t~nondet15; [L55] havoc #t~nondet15; VAL [~cond~0=14bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L56-L58] assume !(0bv32 == ~cond~0); [L59] ~lk1~0 := 0bv32; [L61] ~lk2~0 := 0bv32; [L63] ~lk3~0 := 0bv32; [L65] ~lk4~0 := 0bv32; [L67] ~lk5~0 := 0bv32; [L69] ~lk6~0 := 0bv32; [L71] ~lk7~0 := 0bv32; [L73] ~lk8~0 := 0bv32; [L75] ~lk9~0 := 0bv32; [L77] ~lk10~0 := 0bv32; [L79] ~lk11~0 := 0bv32; [L81] ~lk12~0 := 0bv32; [L83] ~lk13~0 := 0bv32; [L85] ~lk14~0 := 0bv32; [L87] ~lk15~0 := 0bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L91-L93] assume !(0bv32 != ~p1~0); VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L95-L97] assume !(0bv32 != ~p2~0); VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L99-L101] assume 0bv32 != ~p3~0; [L100] ~lk3~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L103-L105] assume 0bv32 != ~p4~0; [L104] ~lk4~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L107-L109] assume 0bv32 != ~p5~0; [L108] ~lk5~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L111-L113] assume 0bv32 != ~p6~0; [L112] ~lk6~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L115-L117] assume 0bv32 != ~p7~0; [L116] ~lk7~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L119-L121] assume !(0bv32 != ~p8~0); VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L123-L125] assume 0bv32 != ~p9~0; [L124] ~lk9~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L127-L129] assume 0bv32 != ~p10~0; [L128] ~lk10~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L131-L133] assume 0bv32 != ~p11~0; [L132] ~lk11~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L135-L137] assume 0bv32 != ~p12~0; [L136] ~lk12~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L139-L141] assume 0bv32 != ~p13~0; [L140] ~lk13~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L143-L145] assume 0bv32 != ~p14~0; [L144] ~lk14~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L147-L149] assume 0bv32 != ~p15~0; [L148] ~lk15~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L153-L156] assume !(0bv32 != ~p1~0); VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L158-L161] assume !(0bv32 != ~p2~0); VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L231] assert false; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] CALL call ULTIMATE.init(); [?] ensures true; [?] RET call ULTIMATE.init(); [?] CALL call #t~ret16 := main(); [L6] ~p1~0 := #t~nondet0; [L6] havoc #t~nondet0; [L7] havoc ~lk1~0; [L9] ~p2~0 := #t~nondet1; [L9] havoc #t~nondet1; [L10] havoc ~lk2~0; [L12] ~p3~0 := #t~nondet2; [L12] havoc #t~nondet2; [L13] havoc ~lk3~0; [L15] ~p4~0 := #t~nondet3; [L15] havoc #t~nondet3; [L16] havoc ~lk4~0; [L18] ~p5~0 := #t~nondet4; [L18] havoc #t~nondet4; [L19] havoc ~lk5~0; [L21] ~p6~0 := #t~nondet5; [L21] havoc #t~nondet5; [L22] havoc ~lk6~0; [L24] ~p7~0 := #t~nondet6; [L24] havoc #t~nondet6; [L25] havoc ~lk7~0; [L27] ~p8~0 := #t~nondet7; [L27] havoc #t~nondet7; [L28] havoc ~lk8~0; [L30] ~p9~0 := #t~nondet8; [L30] havoc #t~nondet8; [L31] havoc ~lk9~0; [L33] ~p10~0 := #t~nondet9; [L33] havoc #t~nondet9; [L34] havoc ~lk10~0; [L36] ~p11~0 := #t~nondet10; [L36] havoc #t~nondet10; [L37] havoc ~lk11~0; [L39] ~p12~0 := #t~nondet11; [L39] havoc #t~nondet11; [L40] havoc ~lk12~0; [L42] ~p13~0 := #t~nondet12; [L42] havoc #t~nondet12; [L43] havoc ~lk13~0; [L45] ~p14~0 := #t~nondet13; [L45] havoc #t~nondet13; [L46] havoc ~lk14~0; [L48] ~p15~0 := #t~nondet14; [L48] havoc #t~nondet14; [L49] havoc ~lk15~0; [L52] havoc ~cond~0; VAL [~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L54-L228] assume !false; [L55] ~cond~0 := #t~nondet15; [L55] havoc #t~nondet15; VAL [~cond~0=14bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L56-L58] assume !(0bv32 == ~cond~0); [L59] ~lk1~0 := 0bv32; [L61] ~lk2~0 := 0bv32; [L63] ~lk3~0 := 0bv32; [L65] ~lk4~0 := 0bv32; [L67] ~lk5~0 := 0bv32; [L69] ~lk6~0 := 0bv32; [L71] ~lk7~0 := 0bv32; [L73] ~lk8~0 := 0bv32; [L75] ~lk9~0 := 0bv32; [L77] ~lk10~0 := 0bv32; [L79] ~lk11~0 := 0bv32; [L81] ~lk12~0 := 0bv32; [L83] ~lk13~0 := 0bv32; [L85] ~lk14~0 := 0bv32; [L87] ~lk15~0 := 0bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L91-L93] assume !(0bv32 != ~p1~0); VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L95-L97] assume !(0bv32 != ~p2~0); VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L99-L101] assume 0bv32 != ~p3~0; [L100] ~lk3~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L103-L105] assume 0bv32 != ~p4~0; [L104] ~lk4~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L107-L109] assume 0bv32 != ~p5~0; [L108] ~lk5~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L111-L113] assume 0bv32 != ~p6~0; [L112] ~lk6~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L115-L117] assume 0bv32 != ~p7~0; [L116] ~lk7~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L119-L121] assume !(0bv32 != ~p8~0); VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L123-L125] assume 0bv32 != ~p9~0; [L124] ~lk9~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L127-L129] assume 0bv32 != ~p10~0; [L128] ~lk10~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L131-L133] assume 0bv32 != ~p11~0; [L132] ~lk11~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L135-L137] assume 0bv32 != ~p12~0; [L136] ~lk12~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L139-L141] assume 0bv32 != ~p13~0; [L140] ~lk13~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L143-L145] assume 0bv32 != ~p14~0; [L144] ~lk14~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L147-L149] assume 0bv32 != ~p15~0; [L148] ~lk15~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L153-L156] assume !(0bv32 != ~p1~0); VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L158-L161] assume !(0bv32 != ~p2~0); VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L231] assert false; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret16 := main(); [L6] ~p1~0 := #t~nondet0; [L6] havoc #t~nondet0; [L7] havoc ~lk1~0; [L9] ~p2~0 := #t~nondet1; [L9] havoc #t~nondet1; [L10] havoc ~lk2~0; [L12] ~p3~0 := #t~nondet2; [L12] havoc #t~nondet2; [L13] havoc ~lk3~0; [L15] ~p4~0 := #t~nondet3; [L15] havoc #t~nondet3; [L16] havoc ~lk4~0; [L18] ~p5~0 := #t~nondet4; [L18] havoc #t~nondet4; [L19] havoc ~lk5~0; [L21] ~p6~0 := #t~nondet5; [L21] havoc #t~nondet5; [L22] havoc ~lk6~0; [L24] ~p7~0 := #t~nondet6; [L24] havoc #t~nondet6; [L25] havoc ~lk7~0; [L27] ~p8~0 := #t~nondet7; [L27] havoc #t~nondet7; [L28] havoc ~lk8~0; [L30] ~p9~0 := #t~nondet8; [L30] havoc #t~nondet8; [L31] havoc ~lk9~0; [L33] ~p10~0 := #t~nondet9; [L33] havoc #t~nondet9; [L34] havoc ~lk10~0; [L36] ~p11~0 := #t~nondet10; [L36] havoc #t~nondet10; [L37] havoc ~lk11~0; [L39] ~p12~0 := #t~nondet11; [L39] havoc #t~nondet11; [L40] havoc ~lk12~0; [L42] ~p13~0 := #t~nondet12; [L42] havoc #t~nondet12; [L43] havoc ~lk13~0; [L45] ~p14~0 := #t~nondet13; [L45] havoc #t~nondet13; [L46] havoc ~lk14~0; [L48] ~p15~0 := #t~nondet14; [L48] havoc #t~nondet14; [L49] havoc ~lk15~0; [L52] havoc ~cond~0; VAL [~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L54-L228] COND FALSE !(false) [L55] ~cond~0 := #t~nondet15; [L55] havoc #t~nondet15; VAL [~cond~0=14bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L56] COND FALSE !(0bv32 == ~cond~0) [L59] ~lk1~0 := 0bv32; [L61] ~lk2~0 := 0bv32; [L63] ~lk3~0 := 0bv32; [L65] ~lk4~0 := 0bv32; [L67] ~lk5~0 := 0bv32; [L69] ~lk6~0 := 0bv32; [L71] ~lk7~0 := 0bv32; [L73] ~lk8~0 := 0bv32; [L75] ~lk9~0 := 0bv32; [L77] ~lk10~0 := 0bv32; [L79] ~lk11~0 := 0bv32; [L81] ~lk12~0 := 0bv32; [L83] ~lk13~0 := 0bv32; [L85] ~lk14~0 := 0bv32; [L87] ~lk15~0 := 0bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L91] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L95] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L99] COND TRUE 0bv32 != ~p3~0 [L100] ~lk3~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L103] COND TRUE 0bv32 != ~p4~0 [L104] ~lk4~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L107] COND TRUE 0bv32 != ~p5~0 [L108] ~lk5~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L111] COND TRUE 0bv32 != ~p6~0 [L112] ~lk6~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L115] COND TRUE 0bv32 != ~p7~0 [L116] ~lk7~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L119] COND FALSE !(0bv32 != ~p8~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L123] COND TRUE 0bv32 != ~p9~0 [L124] ~lk9~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L127] COND TRUE 0bv32 != ~p10~0 [L128] ~lk10~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L131] COND TRUE 0bv32 != ~p11~0 [L132] ~lk11~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L135] COND TRUE 0bv32 != ~p12~0 [L136] ~lk12~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L139] COND TRUE 0bv32 != ~p13~0 [L140] ~lk13~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L143] COND TRUE 0bv32 != ~p14~0 [L144] ~lk14~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L147] COND TRUE 0bv32 != ~p15~0 [L148] ~lk15~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L153] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L158] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L231] assert false; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret16 := main(); [L6] ~p1~0 := #t~nondet0; [L6] havoc #t~nondet0; [L7] havoc ~lk1~0; [L9] ~p2~0 := #t~nondet1; [L9] havoc #t~nondet1; [L10] havoc ~lk2~0; [L12] ~p3~0 := #t~nondet2; [L12] havoc #t~nondet2; [L13] havoc ~lk3~0; [L15] ~p4~0 := #t~nondet3; [L15] havoc #t~nondet3; [L16] havoc ~lk4~0; [L18] ~p5~0 := #t~nondet4; [L18] havoc #t~nondet4; [L19] havoc ~lk5~0; [L21] ~p6~0 := #t~nondet5; [L21] havoc #t~nondet5; [L22] havoc ~lk6~0; [L24] ~p7~0 := #t~nondet6; [L24] havoc #t~nondet6; [L25] havoc ~lk7~0; [L27] ~p8~0 := #t~nondet7; [L27] havoc #t~nondet7; [L28] havoc ~lk8~0; [L30] ~p9~0 := #t~nondet8; [L30] havoc #t~nondet8; [L31] havoc ~lk9~0; [L33] ~p10~0 := #t~nondet9; [L33] havoc #t~nondet9; [L34] havoc ~lk10~0; [L36] ~p11~0 := #t~nondet10; [L36] havoc #t~nondet10; [L37] havoc ~lk11~0; [L39] ~p12~0 := #t~nondet11; [L39] havoc #t~nondet11; [L40] havoc ~lk12~0; [L42] ~p13~0 := #t~nondet12; [L42] havoc #t~nondet12; [L43] havoc ~lk13~0; [L45] ~p14~0 := #t~nondet13; [L45] havoc #t~nondet13; [L46] havoc ~lk14~0; [L48] ~p15~0 := #t~nondet14; [L48] havoc #t~nondet14; [L49] havoc ~lk15~0; [L52] havoc ~cond~0; VAL [~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L54-L228] COND FALSE !(false) [L55] ~cond~0 := #t~nondet15; [L55] havoc #t~nondet15; VAL [~cond~0=14bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L56] COND FALSE !(0bv32 == ~cond~0) [L59] ~lk1~0 := 0bv32; [L61] ~lk2~0 := 0bv32; [L63] ~lk3~0 := 0bv32; [L65] ~lk4~0 := 0bv32; [L67] ~lk5~0 := 0bv32; [L69] ~lk6~0 := 0bv32; [L71] ~lk7~0 := 0bv32; [L73] ~lk8~0 := 0bv32; [L75] ~lk9~0 := 0bv32; [L77] ~lk10~0 := 0bv32; [L79] ~lk11~0 := 0bv32; [L81] ~lk12~0 := 0bv32; [L83] ~lk13~0 := 0bv32; [L85] ~lk14~0 := 0bv32; [L87] ~lk15~0 := 0bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L91] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L95] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L99] COND TRUE 0bv32 != ~p3~0 [L100] ~lk3~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L103] COND TRUE 0bv32 != ~p4~0 [L104] ~lk4~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L107] COND TRUE 0bv32 != ~p5~0 [L108] ~lk5~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L111] COND TRUE 0bv32 != ~p6~0 [L112] ~lk6~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L115] COND TRUE 0bv32 != ~p7~0 [L116] ~lk7~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L119] COND FALSE !(0bv32 != ~p8~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L123] COND TRUE 0bv32 != ~p9~0 [L124] ~lk9~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L127] COND TRUE 0bv32 != ~p10~0 [L128] ~lk10~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L131] COND TRUE 0bv32 != ~p11~0 [L132] ~lk11~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L135] COND TRUE 0bv32 != ~p12~0 [L136] ~lk12~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L139] COND TRUE 0bv32 != ~p13~0 [L140] ~lk13~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L143] COND TRUE 0bv32 != ~p14~0 [L144] ~lk14~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L147] COND TRUE 0bv32 != ~p15~0 [L148] ~lk15~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L153] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L158] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L231] assert false; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret16 := main(); [L6] ~p1~0 := #t~nondet0; [L6] havoc #t~nondet0; [L7] havoc ~lk1~0; [L9] ~p2~0 := #t~nondet1; [L9] havoc #t~nondet1; [L10] havoc ~lk2~0; [L12] ~p3~0 := #t~nondet2; [L12] havoc #t~nondet2; [L13] havoc ~lk3~0; [L15] ~p4~0 := #t~nondet3; [L15] havoc #t~nondet3; [L16] havoc ~lk4~0; [L18] ~p5~0 := #t~nondet4; [L18] havoc #t~nondet4; [L19] havoc ~lk5~0; [L21] ~p6~0 := #t~nondet5; [L21] havoc #t~nondet5; [L22] havoc ~lk6~0; [L24] ~p7~0 := #t~nondet6; [L24] havoc #t~nondet6; [L25] havoc ~lk7~0; [L27] ~p8~0 := #t~nondet7; [L27] havoc #t~nondet7; [L28] havoc ~lk8~0; [L30] ~p9~0 := #t~nondet8; [L30] havoc #t~nondet8; [L31] havoc ~lk9~0; [L33] ~p10~0 := #t~nondet9; [L33] havoc #t~nondet9; [L34] havoc ~lk10~0; [L36] ~p11~0 := #t~nondet10; [L36] havoc #t~nondet10; [L37] havoc ~lk11~0; [L39] ~p12~0 := #t~nondet11; [L39] havoc #t~nondet11; [L40] havoc ~lk12~0; [L42] ~p13~0 := #t~nondet12; [L42] havoc #t~nondet12; [L43] havoc ~lk13~0; [L45] ~p14~0 := #t~nondet13; [L45] havoc #t~nondet13; [L46] havoc ~lk14~0; [L48] ~p15~0 := #t~nondet14; [L48] havoc #t~nondet14; [L49] havoc ~lk15~0; [L52] havoc ~cond~0; VAL [~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L54-L228] COND FALSE !(false) [L55] ~cond~0 := #t~nondet15; [L55] havoc #t~nondet15; VAL [~cond~0=14bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L56] COND FALSE !(0bv32 == ~cond~0) [L59] ~lk1~0 := 0bv32; [L61] ~lk2~0 := 0bv32; [L63] ~lk3~0 := 0bv32; [L65] ~lk4~0 := 0bv32; [L67] ~lk5~0 := 0bv32; [L69] ~lk6~0 := 0bv32; [L71] ~lk7~0 := 0bv32; [L73] ~lk8~0 := 0bv32; [L75] ~lk9~0 := 0bv32; [L77] ~lk10~0 := 0bv32; [L79] ~lk11~0 := 0bv32; [L81] ~lk12~0 := 0bv32; [L83] ~lk13~0 := 0bv32; [L85] ~lk14~0 := 0bv32; [L87] ~lk15~0 := 0bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L91] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L95] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L99] COND TRUE 0bv32 != ~p3~0 [L100] ~lk3~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L103] COND TRUE 0bv32 != ~p4~0 [L104] ~lk4~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L107] COND TRUE 0bv32 != ~p5~0 [L108] ~lk5~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L111] COND TRUE 0bv32 != ~p6~0 [L112] ~lk6~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L115] COND TRUE 0bv32 != ~p7~0 [L116] ~lk7~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L119] COND FALSE !(0bv32 != ~p8~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L123] COND TRUE 0bv32 != ~p9~0 [L124] ~lk9~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L127] COND TRUE 0bv32 != ~p10~0 [L128] ~lk10~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L131] COND TRUE 0bv32 != ~p11~0 [L132] ~lk11~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L135] COND TRUE 0bv32 != ~p12~0 [L136] ~lk12~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L139] COND TRUE 0bv32 != ~p13~0 [L140] ~lk13~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L143] COND TRUE 0bv32 != ~p14~0 [L144] ~lk14~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L147] COND TRUE 0bv32 != ~p15~0 [L148] ~lk15~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L153] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L158] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L231] assert false; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret16 := main(); [L6] ~p1~0 := #t~nondet0; [L6] havoc #t~nondet0; [L7] havoc ~lk1~0; [L9] ~p2~0 := #t~nondet1; [L9] havoc #t~nondet1; [L10] havoc ~lk2~0; [L12] ~p3~0 := #t~nondet2; [L12] havoc #t~nondet2; [L13] havoc ~lk3~0; [L15] ~p4~0 := #t~nondet3; [L15] havoc #t~nondet3; [L16] havoc ~lk4~0; [L18] ~p5~0 := #t~nondet4; [L18] havoc #t~nondet4; [L19] havoc ~lk5~0; [L21] ~p6~0 := #t~nondet5; [L21] havoc #t~nondet5; [L22] havoc ~lk6~0; [L24] ~p7~0 := #t~nondet6; [L24] havoc #t~nondet6; [L25] havoc ~lk7~0; [L27] ~p8~0 := #t~nondet7; [L27] havoc #t~nondet7; [L28] havoc ~lk8~0; [L30] ~p9~0 := #t~nondet8; [L30] havoc #t~nondet8; [L31] havoc ~lk9~0; [L33] ~p10~0 := #t~nondet9; [L33] havoc #t~nondet9; [L34] havoc ~lk10~0; [L36] ~p11~0 := #t~nondet10; [L36] havoc #t~nondet10; [L37] havoc ~lk11~0; [L39] ~p12~0 := #t~nondet11; [L39] havoc #t~nondet11; [L40] havoc ~lk12~0; [L42] ~p13~0 := #t~nondet12; [L42] havoc #t~nondet12; [L43] havoc ~lk13~0; [L45] ~p14~0 := #t~nondet13; [L45] havoc #t~nondet13; [L46] havoc ~lk14~0; [L48] ~p15~0 := #t~nondet14; [L48] havoc #t~nondet14; [L49] havoc ~lk15~0; [L52] havoc ~cond~0; VAL [~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L54-L228] COND FALSE !(false) [L55] ~cond~0 := #t~nondet15; [L55] havoc #t~nondet15; VAL [~cond~0=14bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L56] COND FALSE !(0bv32 == ~cond~0) [L59] ~lk1~0 := 0bv32; [L61] ~lk2~0 := 0bv32; [L63] ~lk3~0 := 0bv32; [L65] ~lk4~0 := 0bv32; [L67] ~lk5~0 := 0bv32; [L69] ~lk6~0 := 0bv32; [L71] ~lk7~0 := 0bv32; [L73] ~lk8~0 := 0bv32; [L75] ~lk9~0 := 0bv32; [L77] ~lk10~0 := 0bv32; [L79] ~lk11~0 := 0bv32; [L81] ~lk12~0 := 0bv32; [L83] ~lk13~0 := 0bv32; [L85] ~lk14~0 := 0bv32; [L87] ~lk15~0 := 0bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L91] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L95] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L99] COND TRUE 0bv32 != ~p3~0 [L100] ~lk3~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L103] COND TRUE 0bv32 != ~p4~0 [L104] ~lk4~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L107] COND TRUE 0bv32 != ~p5~0 [L108] ~lk5~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L111] COND TRUE 0bv32 != ~p6~0 [L112] ~lk6~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L115] COND TRUE 0bv32 != ~p7~0 [L116] ~lk7~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L119] COND FALSE !(0bv32 != ~p8~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L123] COND TRUE 0bv32 != ~p9~0 [L124] ~lk9~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L127] COND TRUE 0bv32 != ~p10~0 [L128] ~lk10~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L131] COND TRUE 0bv32 != ~p11~0 [L132] ~lk11~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L135] COND TRUE 0bv32 != ~p12~0 [L136] ~lk12~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L139] COND TRUE 0bv32 != ~p13~0 [L140] ~lk13~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L143] COND TRUE 0bv32 != ~p14~0 [L144] ~lk14~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L147] COND TRUE 0bv32 != ~p15~0 [L148] ~lk15~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L153] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L158] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L231] assert false; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L6] int p1 = __VERIFIER_nondet_int(); [L7] int lk1; [L9] int p2 = __VERIFIER_nondet_int(); [L10] int lk2; [L12] int p3 = __VERIFIER_nondet_int(); [L13] int lk3; [L15] int p4 = __VERIFIER_nondet_int(); [L16] int lk4; [L18] int p5 = __VERIFIER_nondet_int(); [L19] int lk5; [L21] int p6 = __VERIFIER_nondet_int(); [L22] int lk6; [L24] int p7 = __VERIFIER_nondet_int(); [L25] int lk7; [L27] int p8 = __VERIFIER_nondet_int(); [L28] int lk8; [L30] int p9 = __VERIFIER_nondet_int(); [L31] int lk9; [L33] int p10 = __VERIFIER_nondet_int(); [L34] int lk10; [L36] int p11 = __VERIFIER_nondet_int(); [L37] int lk11; [L39] int p12 = __VERIFIER_nondet_int(); [L40] int lk12; [L42] int p13 = __VERIFIER_nondet_int(); [L43] int lk13; [L45] int p14 = __VERIFIER_nondet_int(); [L46] int lk14; [L48] int p15 = __VERIFIER_nondet_int(); [L49] int lk15; [L52] int cond; VAL [p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L54] COND TRUE 1 [L55] cond = __VERIFIER_nondet_int() [L56] COND FALSE !(cond == 0) [L59] lk1 = 0 [L61] lk2 = 0 [L63] lk3 = 0 [L65] lk4 = 0 [L67] lk5 = 0 [L69] lk6 = 0 [L71] lk7 = 0 [L73] lk8 = 0 [L75] lk9 = 0 [L77] lk10 = 0 [L79] lk11 = 0 [L81] lk12 = 0 [L83] lk13 = 0 [L85] lk14 = 0 [L87] lk15 = 0 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=0, lk4=0, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L91] COND FALSE !(p1 != 0) VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=0, lk4=0, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L95] COND FALSE !(p2 != 0) VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=0, lk4=0, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L99] COND TRUE p3 != 0 [L100] lk3 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=0, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L103] COND TRUE p4 != 0 [L104] lk4 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L107] COND TRUE p5 != 0 [L108] lk5 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L111] COND TRUE p6 != 0 [L112] lk6 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L115] COND TRUE p7 != 0 [L116] lk7 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L119] COND FALSE !(p8 != 0) VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L123] COND TRUE p9 != 0 [L124] lk9 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L127] COND TRUE p10 != 0 [L128] lk10 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L131] COND TRUE p11 != 0 [L132] lk11 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L135] COND TRUE p12 != 0 [L136] lk12 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L139] COND TRUE p13 != 0 [L140] lk13 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L143] COND TRUE p14 != 0 [L144] lk14 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L147] COND TRUE p15 != 0 [L148] lk15 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=1, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L153] COND FALSE !(p1 != 0) VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=1, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L158] COND FALSE !(p2 != 0) VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=1, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L231] __VERIFIER_error() VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=1, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] ----- [2018-11-23 10:53:42,294 WARN L170 areAnnotationChecker]: ULTIMATE.initFINAL has no Hoare annotation [2018-11-23 10:53:42,294 WARN L170 areAnnotationChecker]: ULTIMATE.startENTRY has no Hoare annotation [2018-11-23 10:53:42,294 WARN L170 areAnnotationChecker]: ULTIMATE.startENTRY has no Hoare annotation [2018-11-23 10:53:42,294 WARN L170 areAnnotationChecker]: mainENTRY has no Hoare annotation [2018-11-23 10:53:42,294 WARN L170 areAnnotationChecker]: ULTIMATE.initEXIT has no Hoare annotation [2018-11-23 10:53:42,294 WARN L170 areAnnotationChecker]: L-1 has no Hoare annotation [2018-11-23 10:53:42,295 WARN L170 areAnnotationChecker]: L-1 has no Hoare annotation [2018-11-23 10:53:42,295 WARN L170 areAnnotationChecker]: L223-1 has no Hoare annotation [2018-11-23 10:53:42,295 WARN L170 areAnnotationChecker]: L223-1 has no Hoare annotation [2018-11-23 10:53:42,295 WARN L170 areAnnotationChecker]: L223-1 has no Hoare annotation [2018-11-23 10:53:42,295 WARN L170 areAnnotationChecker]: ULTIMATE.startFINAL has no Hoare annotation [2018-11-23 10:53:42,295 WARN L170 areAnnotationChecker]: L229 has no Hoare annotation [2018-11-23 10:53:42,295 WARN L170 areAnnotationChecker]: L56 has no Hoare annotation [2018-11-23 10:53:42,295 WARN L170 areAnnotationChecker]: L56 has no Hoare annotation [2018-11-23 10:53:42,296 WARN L170 areAnnotationChecker]: mainFINAL has no Hoare annotation [2018-11-23 10:53:42,296 WARN L170 areAnnotationChecker]: L91 has no Hoare annotation [2018-11-23 10:53:42,296 WARN L170 areAnnotationChecker]: L91 has no Hoare annotation [2018-11-23 10:53:42,296 WARN L170 areAnnotationChecker]: mainEXIT has no Hoare annotation [2018-11-23 10:53:42,296 WARN L170 areAnnotationChecker]: L91-2 has no Hoare annotation [2018-11-23 10:53:42,296 WARN L170 areAnnotationChecker]: L91-2 has no Hoare annotation [2018-11-23 10:53:42,296 WARN L170 areAnnotationChecker]: L95-1 has no Hoare annotation [2018-11-23 10:53:42,297 WARN L170 areAnnotationChecker]: L95-1 has no Hoare annotation [2018-11-23 10:53:42,297 WARN L170 areAnnotationChecker]: L99-1 has no Hoare annotation [2018-11-23 10:53:42,297 WARN L170 areAnnotationChecker]: L99-1 has no Hoare annotation [2018-11-23 10:53:42,297 WARN L170 areAnnotationChecker]: L103-1 has no Hoare annotation [2018-11-23 10:53:42,297 WARN L170 areAnnotationChecker]: L103-1 has no Hoare annotation [2018-11-23 10:53:42,297 WARN L170 areAnnotationChecker]: L107-1 has no Hoare annotation [2018-11-23 10:53:42,298 WARN L170 areAnnotationChecker]: L107-1 has no Hoare annotation [2018-11-23 10:53:42,298 WARN L170 areAnnotationChecker]: L111-1 has no Hoare annotation [2018-11-23 10:53:42,298 WARN L170 areAnnotationChecker]: L111-1 has no Hoare annotation [2018-11-23 10:53:42,298 WARN L170 areAnnotationChecker]: L115-1 has no Hoare annotation [2018-11-23 10:53:42,298 WARN L170 areAnnotationChecker]: L115-1 has no Hoare annotation [2018-11-23 10:53:42,298 WARN L170 areAnnotationChecker]: L119-1 has no Hoare annotation [2018-11-23 10:53:42,298 WARN L170 areAnnotationChecker]: L119-1 has no Hoare annotation [2018-11-23 10:53:42,299 WARN L170 areAnnotationChecker]: L123-1 has no Hoare annotation [2018-11-23 10:53:42,299 WARN L170 areAnnotationChecker]: L123-1 has no Hoare annotation [2018-11-23 10:53:42,299 WARN L170 areAnnotationChecker]: L127-1 has no Hoare annotation [2018-11-23 10:53:42,299 WARN L170 areAnnotationChecker]: L127-1 has no Hoare annotation [2018-11-23 10:53:42,299 WARN L170 areAnnotationChecker]: L131-1 has no Hoare annotation [2018-11-23 10:53:42,299 WARN L170 areAnnotationChecker]: L131-1 has no Hoare annotation [2018-11-23 10:53:42,299 WARN L170 areAnnotationChecker]: L135-1 has no Hoare annotation [2018-11-23 10:53:42,300 WARN L170 areAnnotationChecker]: L135-1 has no Hoare annotation [2018-11-23 10:53:42,300 WARN L170 areAnnotationChecker]: L139-1 has no Hoare annotation [2018-11-23 10:53:42,300 WARN L170 areAnnotationChecker]: L139-1 has no Hoare annotation [2018-11-23 10:53:42,300 WARN L170 areAnnotationChecker]: L143-1 has no Hoare annotation [2018-11-23 10:53:42,300 WARN L170 areAnnotationChecker]: L143-1 has no Hoare annotation [2018-11-23 10:53:42,300 WARN L170 areAnnotationChecker]: L147-1 has no Hoare annotation [2018-11-23 10:53:42,300 WARN L170 areAnnotationChecker]: L147-1 has no Hoare annotation [2018-11-23 10:53:42,301 WARN L170 areAnnotationChecker]: L154 has no Hoare annotation [2018-11-23 10:53:42,301 WARN L170 areAnnotationChecker]: L154 has no Hoare annotation [2018-11-23 10:53:42,301 WARN L170 areAnnotationChecker]: L153-1 has no Hoare annotation [2018-11-23 10:53:42,301 WARN L170 areAnnotationChecker]: L153-1 has no Hoare annotation [2018-11-23 10:53:42,301 WARN L170 areAnnotationChecker]: L224-1 has no Hoare annotation [2018-11-23 10:53:42,301 WARN L170 areAnnotationChecker]: L224-1 has no Hoare annotation [2018-11-23 10:53:42,301 WARN L170 areAnnotationChecker]: L159 has no Hoare annotation [2018-11-23 10:53:42,301 WARN L170 areAnnotationChecker]: L159 has no Hoare annotation [2018-11-23 10:53:42,302 WARN L170 areAnnotationChecker]: L158 has no Hoare annotation [2018-11-23 10:53:42,302 WARN L170 areAnnotationChecker]: L158 has no Hoare annotation [2018-11-23 10:53:42,302 WARN L170 areAnnotationChecker]: L164 has no Hoare annotation [2018-11-23 10:53:42,302 WARN L170 areAnnotationChecker]: L164 has no Hoare annotation [2018-11-23 10:53:42,302 WARN L170 areAnnotationChecker]: L163-1 has no Hoare annotation [2018-11-23 10:53:42,302 WARN L170 areAnnotationChecker]: L163-1 has no Hoare annotation [2018-11-23 10:53:42,302 WARN L170 areAnnotationChecker]: L169 has no Hoare annotation [2018-11-23 10:53:42,303 WARN L170 areAnnotationChecker]: L169 has no Hoare annotation [2018-11-23 10:53:42,303 WARN L170 areAnnotationChecker]: L168-1 has no Hoare annotation [2018-11-23 10:53:42,303 WARN L170 areAnnotationChecker]: L168-1 has no Hoare annotation [2018-11-23 10:53:42,303 WARN L170 areAnnotationChecker]: L174 has no Hoare annotation [2018-11-23 10:53:42,303 WARN L170 areAnnotationChecker]: L174 has no Hoare annotation [2018-11-23 10:53:42,303 WARN L170 areAnnotationChecker]: L173-1 has no Hoare annotation [2018-11-23 10:53:42,303 WARN L170 areAnnotationChecker]: L173-1 has no Hoare annotation [2018-11-23 10:53:42,304 WARN L170 areAnnotationChecker]: L179 has no Hoare annotation [2018-11-23 10:53:42,304 WARN L170 areAnnotationChecker]: L179 has no Hoare annotation [2018-11-23 10:53:42,304 WARN L170 areAnnotationChecker]: L178-1 has no Hoare annotation [2018-11-23 10:53:42,304 WARN L170 areAnnotationChecker]: L178-1 has no Hoare annotation [2018-11-23 10:53:42,304 WARN L170 areAnnotationChecker]: L184 has no Hoare annotation [2018-11-23 10:53:42,304 WARN L170 areAnnotationChecker]: L184 has no Hoare annotation [2018-11-23 10:53:42,304 WARN L170 areAnnotationChecker]: L183-1 has no Hoare annotation [2018-11-23 10:53:42,305 WARN L170 areAnnotationChecker]: L183-1 has no Hoare annotation [2018-11-23 10:53:42,305 WARN L170 areAnnotationChecker]: L189 has no Hoare annotation [2018-11-23 10:53:42,305 WARN L170 areAnnotationChecker]: L189 has no Hoare annotation [2018-11-23 10:53:42,305 WARN L170 areAnnotationChecker]: L188-1 has no Hoare annotation [2018-11-23 10:53:42,305 WARN L170 areAnnotationChecker]: L188-1 has no Hoare annotation [2018-11-23 10:53:42,305 WARN L170 areAnnotationChecker]: L194 has no Hoare annotation [2018-11-23 10:53:42,305 WARN L170 areAnnotationChecker]: L194 has no Hoare annotation [2018-11-23 10:53:42,306 WARN L170 areAnnotationChecker]: L193-1 has no Hoare annotation [2018-11-23 10:53:42,306 WARN L170 areAnnotationChecker]: L193-1 has no Hoare annotation [2018-11-23 10:53:42,306 WARN L170 areAnnotationChecker]: L199 has no Hoare annotation [2018-11-23 10:53:42,306 WARN L170 areAnnotationChecker]: L199 has no Hoare annotation [2018-11-23 10:53:42,306 WARN L170 areAnnotationChecker]: L198-1 has no Hoare annotation [2018-11-23 10:53:42,306 WARN L170 areAnnotationChecker]: L198-1 has no Hoare annotation [2018-11-23 10:53:42,306 WARN L170 areAnnotationChecker]: L204 has no Hoare annotation [2018-11-23 10:53:42,307 WARN L170 areAnnotationChecker]: L204 has no Hoare annotation [2018-11-23 10:53:42,307 WARN L170 areAnnotationChecker]: L203-1 has no Hoare annotation [2018-11-23 10:53:42,307 WARN L170 areAnnotationChecker]: L203-1 has no Hoare annotation [2018-11-23 10:53:42,307 WARN L170 areAnnotationChecker]: L209 has no Hoare annotation [2018-11-23 10:53:42,307 WARN L170 areAnnotationChecker]: L209 has no Hoare annotation [2018-11-23 10:53:42,307 WARN L170 areAnnotationChecker]: L208-1 has no Hoare annotation [2018-11-23 10:53:42,307 WARN L170 areAnnotationChecker]: L208-1 has no Hoare annotation [2018-11-23 10:53:42,308 WARN L170 areAnnotationChecker]: L214 has no Hoare annotation [2018-11-23 10:53:42,308 WARN L170 areAnnotationChecker]: L214 has no Hoare annotation [2018-11-23 10:53:42,308 WARN L170 areAnnotationChecker]: L213-1 has no Hoare annotation [2018-11-23 10:53:42,308 WARN L170 areAnnotationChecker]: L213-1 has no Hoare annotation [2018-11-23 10:53:42,308 WARN L170 areAnnotationChecker]: L219 has no Hoare annotation [2018-11-23 10:53:42,308 WARN L170 areAnnotationChecker]: L219 has no Hoare annotation [2018-11-23 10:53:42,308 WARN L170 areAnnotationChecker]: L218 has no Hoare annotation [2018-11-23 10:53:42,309 WARN L170 areAnnotationChecker]: L218 has no Hoare annotation [2018-11-23 10:53:42,309 WARN L170 areAnnotationChecker]: L224 has no Hoare annotation [2018-11-23 10:53:42,309 WARN L170 areAnnotationChecker]: L224 has no Hoare annotation [2018-11-23 10:53:42,309 INFO L163 areAnnotationChecker]: CFG has 0 edges. 0 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. 0 times interpolants missing. [2018-11-23 10:53:42,312 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 10:53:42 BoogieIcfgContainer [2018-11-23 10:53:42,312 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 10:53:42,313 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 10:53:42,313 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 10:53:42,313 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 10:53:42,314 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:53:36" (3/4) ... [2018-11-23 10:53:42,317 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] CALL call ULTIMATE.init(); [?] assume true; [?] RET #282#return; [?] CALL call #t~ret16 := main(); [?] ~p1~0 := #t~nondet0;havoc #t~nondet0;havoc ~lk1~0;~p2~0 := #t~nondet1;havoc #t~nondet1;havoc ~lk2~0;~p3~0 := #t~nondet2;havoc #t~nondet2;havoc ~lk3~0;~p4~0 := #t~nondet3;havoc #t~nondet3;havoc ~lk4~0;~p5~0 := #t~nondet4;havoc #t~nondet4;havoc ~lk5~0;~p6~0 := #t~nondet5;havoc #t~nondet5;havoc ~lk6~0;~p7~0 := #t~nondet6;havoc #t~nondet6;havoc ~lk7~0;~p8~0 := #t~nondet7;havoc #t~nondet7;havoc ~lk8~0;~p9~0 := #t~nondet8;havoc #t~nondet8;havoc ~lk9~0;~p10~0 := #t~nondet9;havoc #t~nondet9;havoc ~lk10~0;~p11~0 := #t~nondet10;havoc #t~nondet10;havoc ~lk11~0;~p12~0 := #t~nondet11;havoc #t~nondet11;havoc ~lk12~0;~p13~0 := #t~nondet12;havoc #t~nondet12;havoc ~lk13~0;~p14~0 := #t~nondet13;havoc #t~nondet13;havoc ~lk14~0;~p15~0 := #t~nondet14;havoc #t~nondet14;havoc ~lk15~0;havoc ~cond~0; VAL [main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !false;~cond~0 := #t~nondet15;havoc #t~nondet15; VAL [main_~cond~0=(_ bv14 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !(0bv32 == ~cond~0);~lk1~0 := 0bv32;~lk2~0 := 0bv32;~lk3~0 := 0bv32;~lk4~0 := 0bv32;~lk5~0 := 0bv32;~lk6~0 := 0bv32;~lk7~0 := 0bv32;~lk8~0 := 0bv32;~lk9~0 := 0bv32;~lk10~0 := 0bv32;~lk11~0 := 0bv32;~lk12~0 := 0bv32;~lk13~0 := 0bv32;~lk14~0 := 0bv32;~lk15~0 := 0bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv0 32), main_~lk4~0=(_ bv0 32), main_~lk5~0=(_ bv0 32), main_~lk6~0=(_ bv0 32), main_~lk7~0=(_ bv0 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !(0bv32 != ~p1~0); VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv0 32), main_~lk4~0=(_ bv0 32), main_~lk5~0=(_ bv0 32), main_~lk6~0=(_ bv0 32), main_~lk7~0=(_ bv0 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !(0bv32 != ~p2~0); VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv0 32), main_~lk4~0=(_ bv0 32), main_~lk5~0=(_ bv0 32), main_~lk6~0=(_ bv0 32), main_~lk7~0=(_ bv0 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p3~0;~lk3~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv0 32), main_~lk5~0=(_ bv0 32), main_~lk6~0=(_ bv0 32), main_~lk7~0=(_ bv0 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p4~0;~lk4~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv0 32), main_~lk6~0=(_ bv0 32), main_~lk7~0=(_ bv0 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p5~0;~lk5~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv0 32), main_~lk7~0=(_ bv0 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p6~0;~lk6~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv0 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p7~0;~lk7~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !(0bv32 != ~p8~0); VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv0 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p9~0;~lk9~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv0 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p10~0;~lk10~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv0 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p11~0;~lk11~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv0 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p12~0;~lk12~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv1 32), main_~lk13~0=(_ bv0 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p13~0;~lk13~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv1 32), main_~lk13~0=(_ bv1 32), main_~lk14~0=(_ bv0 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p14~0;~lk14~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv1 32), main_~lk13~0=(_ bv1 32), main_~lk14~0=(_ bv1 32), main_~lk15~0=(_ bv0 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume 0bv32 != ~p15~0;~lk15~0 := 1bv32; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv1 32), main_~lk13~0=(_ bv1 32), main_~lk14~0=(_ bv1 32), main_~lk15~0=(_ bv1 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !(0bv32 != ~p1~0); VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv1 32), main_~lk13~0=(_ bv1 32), main_~lk14~0=(_ bv1 32), main_~lk15~0=(_ bv1 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !(0bv32 != ~p2~0); VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv1 32), main_~lk13~0=(_ bv1 32), main_~lk14~0=(_ bv1 32), main_~lk15~0=(_ bv1 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] assume !false; VAL [main_~cond~0=(_ bv14 32), main_~lk10~0=(_ bv1 32), main_~lk11~0=(_ bv1 32), main_~lk12~0=(_ bv1 32), main_~lk13~0=(_ bv1 32), main_~lk14~0=(_ bv1 32), main_~lk15~0=(_ bv1 32), main_~lk1~0=(_ bv0 32), main_~lk2~0=(_ bv0 32), main_~lk3~0=(_ bv1 32), main_~lk4~0=(_ bv1 32), main_~lk5~0=(_ bv1 32), main_~lk6~0=(_ bv1 32), main_~lk7~0=(_ bv1 32), main_~lk8~0=(_ bv0 32), main_~lk9~0=(_ bv1 32), main_~p10~0=(_ bv7 32), main_~p11~0=(_ bv2 32), main_~p12~0=(_ bv4 32), main_~p13~0=(_ bv3 32), main_~p14~0=(_ bv8 32), main_~p15~0=(_ bv10 32), main_~p1~0=(_ bv0 32), main_~p2~0=(_ bv0 32), main_~p3~0=(_ bv9 32), main_~p4~0=(_ bv11 32), main_~p5~0=(_ bv13 32), main_~p6~0=(_ bv6 32), main_~p7~0=(_ bv12 32), main_~p8~0=(_ bv0 32), main_~p9~0=(_ bv5 32)] [?] CALL call ULTIMATE.init(); [?] ensures true; [?] RET call ULTIMATE.init(); [?] CALL call #t~ret16 := main(); [L6] ~p1~0 := #t~nondet0; [L6] havoc #t~nondet0; [L7] havoc ~lk1~0; [L9] ~p2~0 := #t~nondet1; [L9] havoc #t~nondet1; [L10] havoc ~lk2~0; [L12] ~p3~0 := #t~nondet2; [L12] havoc #t~nondet2; [L13] havoc ~lk3~0; [L15] ~p4~0 := #t~nondet3; [L15] havoc #t~nondet3; [L16] havoc ~lk4~0; [L18] ~p5~0 := #t~nondet4; [L18] havoc #t~nondet4; [L19] havoc ~lk5~0; [L21] ~p6~0 := #t~nondet5; [L21] havoc #t~nondet5; [L22] havoc ~lk6~0; [L24] ~p7~0 := #t~nondet6; [L24] havoc #t~nondet6; [L25] havoc ~lk7~0; [L27] ~p8~0 := #t~nondet7; [L27] havoc #t~nondet7; [L28] havoc ~lk8~0; [L30] ~p9~0 := #t~nondet8; [L30] havoc #t~nondet8; [L31] havoc ~lk9~0; [L33] ~p10~0 := #t~nondet9; [L33] havoc #t~nondet9; [L34] havoc ~lk10~0; [L36] ~p11~0 := #t~nondet10; [L36] havoc #t~nondet10; [L37] havoc ~lk11~0; [L39] ~p12~0 := #t~nondet11; [L39] havoc #t~nondet11; [L40] havoc ~lk12~0; [L42] ~p13~0 := #t~nondet12; [L42] havoc #t~nondet12; [L43] havoc ~lk13~0; [L45] ~p14~0 := #t~nondet13; [L45] havoc #t~nondet13; [L46] havoc ~lk14~0; [L48] ~p15~0 := #t~nondet14; [L48] havoc #t~nondet14; [L49] havoc ~lk15~0; [L52] havoc ~cond~0; VAL [~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L54-L228] assume !false; [L55] ~cond~0 := #t~nondet15; [L55] havoc #t~nondet15; VAL [~cond~0=14bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L56-L58] assume !(0bv32 == ~cond~0); [L59] ~lk1~0 := 0bv32; [L61] ~lk2~0 := 0bv32; [L63] ~lk3~0 := 0bv32; [L65] ~lk4~0 := 0bv32; [L67] ~lk5~0 := 0bv32; [L69] ~lk6~0 := 0bv32; [L71] ~lk7~0 := 0bv32; [L73] ~lk8~0 := 0bv32; [L75] ~lk9~0 := 0bv32; [L77] ~lk10~0 := 0bv32; [L79] ~lk11~0 := 0bv32; [L81] ~lk12~0 := 0bv32; [L83] ~lk13~0 := 0bv32; [L85] ~lk14~0 := 0bv32; [L87] ~lk15~0 := 0bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L91-L93] assume !(0bv32 != ~p1~0); VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L95-L97] assume !(0bv32 != ~p2~0); VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L99-L101] assume 0bv32 != ~p3~0; [L100] ~lk3~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L103-L105] assume 0bv32 != ~p4~0; [L104] ~lk4~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L107-L109] assume 0bv32 != ~p5~0; [L108] ~lk5~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L111-L113] assume 0bv32 != ~p6~0; [L112] ~lk6~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L115-L117] assume 0bv32 != ~p7~0; [L116] ~lk7~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L119-L121] assume !(0bv32 != ~p8~0); VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L123-L125] assume 0bv32 != ~p9~0; [L124] ~lk9~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L127-L129] assume 0bv32 != ~p10~0; [L128] ~lk10~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L131-L133] assume 0bv32 != ~p11~0; [L132] ~lk11~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L135-L137] assume 0bv32 != ~p12~0; [L136] ~lk12~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L139-L141] assume 0bv32 != ~p13~0; [L140] ~lk13~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L143-L145] assume 0bv32 != ~p14~0; [L144] ~lk14~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L147-L149] assume 0bv32 != ~p15~0; [L148] ~lk15~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L153-L156] assume !(0bv32 != ~p1~0); VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L158-L161] assume !(0bv32 != ~p2~0); VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L231] assert false; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] CALL call ULTIMATE.init(); [?] ensures true; [?] RET call ULTIMATE.init(); [?] CALL call #t~ret16 := main(); [L6] ~p1~0 := #t~nondet0; [L6] havoc #t~nondet0; [L7] havoc ~lk1~0; [L9] ~p2~0 := #t~nondet1; [L9] havoc #t~nondet1; [L10] havoc ~lk2~0; [L12] ~p3~0 := #t~nondet2; [L12] havoc #t~nondet2; [L13] havoc ~lk3~0; [L15] ~p4~0 := #t~nondet3; [L15] havoc #t~nondet3; [L16] havoc ~lk4~0; [L18] ~p5~0 := #t~nondet4; [L18] havoc #t~nondet4; [L19] havoc ~lk5~0; [L21] ~p6~0 := #t~nondet5; [L21] havoc #t~nondet5; [L22] havoc ~lk6~0; [L24] ~p7~0 := #t~nondet6; [L24] havoc #t~nondet6; [L25] havoc ~lk7~0; [L27] ~p8~0 := #t~nondet7; [L27] havoc #t~nondet7; [L28] havoc ~lk8~0; [L30] ~p9~0 := #t~nondet8; [L30] havoc #t~nondet8; [L31] havoc ~lk9~0; [L33] ~p10~0 := #t~nondet9; [L33] havoc #t~nondet9; [L34] havoc ~lk10~0; [L36] ~p11~0 := #t~nondet10; [L36] havoc #t~nondet10; [L37] havoc ~lk11~0; [L39] ~p12~0 := #t~nondet11; [L39] havoc #t~nondet11; [L40] havoc ~lk12~0; [L42] ~p13~0 := #t~nondet12; [L42] havoc #t~nondet12; [L43] havoc ~lk13~0; [L45] ~p14~0 := #t~nondet13; [L45] havoc #t~nondet13; [L46] havoc ~lk14~0; [L48] ~p15~0 := #t~nondet14; [L48] havoc #t~nondet14; [L49] havoc ~lk15~0; [L52] havoc ~cond~0; VAL [~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L54-L228] assume !false; [L55] ~cond~0 := #t~nondet15; [L55] havoc #t~nondet15; VAL [~cond~0=14bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L56-L58] assume !(0bv32 == ~cond~0); [L59] ~lk1~0 := 0bv32; [L61] ~lk2~0 := 0bv32; [L63] ~lk3~0 := 0bv32; [L65] ~lk4~0 := 0bv32; [L67] ~lk5~0 := 0bv32; [L69] ~lk6~0 := 0bv32; [L71] ~lk7~0 := 0bv32; [L73] ~lk8~0 := 0bv32; [L75] ~lk9~0 := 0bv32; [L77] ~lk10~0 := 0bv32; [L79] ~lk11~0 := 0bv32; [L81] ~lk12~0 := 0bv32; [L83] ~lk13~0 := 0bv32; [L85] ~lk14~0 := 0bv32; [L87] ~lk15~0 := 0bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L91-L93] assume !(0bv32 != ~p1~0); VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L95-L97] assume !(0bv32 != ~p2~0); VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L99-L101] assume 0bv32 != ~p3~0; [L100] ~lk3~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L103-L105] assume 0bv32 != ~p4~0; [L104] ~lk4~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L107-L109] assume 0bv32 != ~p5~0; [L108] ~lk5~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L111-L113] assume 0bv32 != ~p6~0; [L112] ~lk6~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L115-L117] assume 0bv32 != ~p7~0; [L116] ~lk7~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L119-L121] assume !(0bv32 != ~p8~0); VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L123-L125] assume 0bv32 != ~p9~0; [L124] ~lk9~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L127-L129] assume 0bv32 != ~p10~0; [L128] ~lk10~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L131-L133] assume 0bv32 != ~p11~0; [L132] ~lk11~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L135-L137] assume 0bv32 != ~p12~0; [L136] ~lk12~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L139-L141] assume 0bv32 != ~p13~0; [L140] ~lk13~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L143-L145] assume 0bv32 != ~p14~0; [L144] ~lk14~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L147-L149] assume 0bv32 != ~p15~0; [L148] ~lk15~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L153-L156] assume !(0bv32 != ~p1~0); VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L158-L161] assume !(0bv32 != ~p2~0); VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L231] assert false; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret16 := main(); [L6] ~p1~0 := #t~nondet0; [L6] havoc #t~nondet0; [L7] havoc ~lk1~0; [L9] ~p2~0 := #t~nondet1; [L9] havoc #t~nondet1; [L10] havoc ~lk2~0; [L12] ~p3~0 := #t~nondet2; [L12] havoc #t~nondet2; [L13] havoc ~lk3~0; [L15] ~p4~0 := #t~nondet3; [L15] havoc #t~nondet3; [L16] havoc ~lk4~0; [L18] ~p5~0 := #t~nondet4; [L18] havoc #t~nondet4; [L19] havoc ~lk5~0; [L21] ~p6~0 := #t~nondet5; [L21] havoc #t~nondet5; [L22] havoc ~lk6~0; [L24] ~p7~0 := #t~nondet6; [L24] havoc #t~nondet6; [L25] havoc ~lk7~0; [L27] ~p8~0 := #t~nondet7; [L27] havoc #t~nondet7; [L28] havoc ~lk8~0; [L30] ~p9~0 := #t~nondet8; [L30] havoc #t~nondet8; [L31] havoc ~lk9~0; [L33] ~p10~0 := #t~nondet9; [L33] havoc #t~nondet9; [L34] havoc ~lk10~0; [L36] ~p11~0 := #t~nondet10; [L36] havoc #t~nondet10; [L37] havoc ~lk11~0; [L39] ~p12~0 := #t~nondet11; [L39] havoc #t~nondet11; [L40] havoc ~lk12~0; [L42] ~p13~0 := #t~nondet12; [L42] havoc #t~nondet12; [L43] havoc ~lk13~0; [L45] ~p14~0 := #t~nondet13; [L45] havoc #t~nondet13; [L46] havoc ~lk14~0; [L48] ~p15~0 := #t~nondet14; [L48] havoc #t~nondet14; [L49] havoc ~lk15~0; [L52] havoc ~cond~0; VAL [~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L54-L228] COND FALSE !(false) [L55] ~cond~0 := #t~nondet15; [L55] havoc #t~nondet15; VAL [~cond~0=14bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L56] COND FALSE !(0bv32 == ~cond~0) [L59] ~lk1~0 := 0bv32; [L61] ~lk2~0 := 0bv32; [L63] ~lk3~0 := 0bv32; [L65] ~lk4~0 := 0bv32; [L67] ~lk5~0 := 0bv32; [L69] ~lk6~0 := 0bv32; [L71] ~lk7~0 := 0bv32; [L73] ~lk8~0 := 0bv32; [L75] ~lk9~0 := 0bv32; [L77] ~lk10~0 := 0bv32; [L79] ~lk11~0 := 0bv32; [L81] ~lk12~0 := 0bv32; [L83] ~lk13~0 := 0bv32; [L85] ~lk14~0 := 0bv32; [L87] ~lk15~0 := 0bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L91] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L95] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L99] COND TRUE 0bv32 != ~p3~0 [L100] ~lk3~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L103] COND TRUE 0bv32 != ~p4~0 [L104] ~lk4~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L107] COND TRUE 0bv32 != ~p5~0 [L108] ~lk5~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L111] COND TRUE 0bv32 != ~p6~0 [L112] ~lk6~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L115] COND TRUE 0bv32 != ~p7~0 [L116] ~lk7~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L119] COND FALSE !(0bv32 != ~p8~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L123] COND TRUE 0bv32 != ~p9~0 [L124] ~lk9~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L127] COND TRUE 0bv32 != ~p10~0 [L128] ~lk10~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L131] COND TRUE 0bv32 != ~p11~0 [L132] ~lk11~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L135] COND TRUE 0bv32 != ~p12~0 [L136] ~lk12~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L139] COND TRUE 0bv32 != ~p13~0 [L140] ~lk13~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L143] COND TRUE 0bv32 != ~p14~0 [L144] ~lk14~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L147] COND TRUE 0bv32 != ~p15~0 [L148] ~lk15~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L153] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L158] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L231] assert false; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret16 := main(); [L6] ~p1~0 := #t~nondet0; [L6] havoc #t~nondet0; [L7] havoc ~lk1~0; [L9] ~p2~0 := #t~nondet1; [L9] havoc #t~nondet1; [L10] havoc ~lk2~0; [L12] ~p3~0 := #t~nondet2; [L12] havoc #t~nondet2; [L13] havoc ~lk3~0; [L15] ~p4~0 := #t~nondet3; [L15] havoc #t~nondet3; [L16] havoc ~lk4~0; [L18] ~p5~0 := #t~nondet4; [L18] havoc #t~nondet4; [L19] havoc ~lk5~0; [L21] ~p6~0 := #t~nondet5; [L21] havoc #t~nondet5; [L22] havoc ~lk6~0; [L24] ~p7~0 := #t~nondet6; [L24] havoc #t~nondet6; [L25] havoc ~lk7~0; [L27] ~p8~0 := #t~nondet7; [L27] havoc #t~nondet7; [L28] havoc ~lk8~0; [L30] ~p9~0 := #t~nondet8; [L30] havoc #t~nondet8; [L31] havoc ~lk9~0; [L33] ~p10~0 := #t~nondet9; [L33] havoc #t~nondet9; [L34] havoc ~lk10~0; [L36] ~p11~0 := #t~nondet10; [L36] havoc #t~nondet10; [L37] havoc ~lk11~0; [L39] ~p12~0 := #t~nondet11; [L39] havoc #t~nondet11; [L40] havoc ~lk12~0; [L42] ~p13~0 := #t~nondet12; [L42] havoc #t~nondet12; [L43] havoc ~lk13~0; [L45] ~p14~0 := #t~nondet13; [L45] havoc #t~nondet13; [L46] havoc ~lk14~0; [L48] ~p15~0 := #t~nondet14; [L48] havoc #t~nondet14; [L49] havoc ~lk15~0; [L52] havoc ~cond~0; VAL [~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L54-L228] COND FALSE !(false) [L55] ~cond~0 := #t~nondet15; [L55] havoc #t~nondet15; VAL [~cond~0=14bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L56] COND FALSE !(0bv32 == ~cond~0) [L59] ~lk1~0 := 0bv32; [L61] ~lk2~0 := 0bv32; [L63] ~lk3~0 := 0bv32; [L65] ~lk4~0 := 0bv32; [L67] ~lk5~0 := 0bv32; [L69] ~lk6~0 := 0bv32; [L71] ~lk7~0 := 0bv32; [L73] ~lk8~0 := 0bv32; [L75] ~lk9~0 := 0bv32; [L77] ~lk10~0 := 0bv32; [L79] ~lk11~0 := 0bv32; [L81] ~lk12~0 := 0bv32; [L83] ~lk13~0 := 0bv32; [L85] ~lk14~0 := 0bv32; [L87] ~lk15~0 := 0bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L91] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L95] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L99] COND TRUE 0bv32 != ~p3~0 [L100] ~lk3~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L103] COND TRUE 0bv32 != ~p4~0 [L104] ~lk4~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L107] COND TRUE 0bv32 != ~p5~0 [L108] ~lk5~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L111] COND TRUE 0bv32 != ~p6~0 [L112] ~lk6~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L115] COND TRUE 0bv32 != ~p7~0 [L116] ~lk7~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L119] COND FALSE !(0bv32 != ~p8~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L123] COND TRUE 0bv32 != ~p9~0 [L124] ~lk9~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L127] COND TRUE 0bv32 != ~p10~0 [L128] ~lk10~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L131] COND TRUE 0bv32 != ~p11~0 [L132] ~lk11~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L135] COND TRUE 0bv32 != ~p12~0 [L136] ~lk12~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L139] COND TRUE 0bv32 != ~p13~0 [L140] ~lk13~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L143] COND TRUE 0bv32 != ~p14~0 [L144] ~lk14~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L147] COND TRUE 0bv32 != ~p15~0 [L148] ~lk15~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L153] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L158] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L231] assert false; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret16 := main(); [L6] ~p1~0 := #t~nondet0; [L6] havoc #t~nondet0; [L7] havoc ~lk1~0; [L9] ~p2~0 := #t~nondet1; [L9] havoc #t~nondet1; [L10] havoc ~lk2~0; [L12] ~p3~0 := #t~nondet2; [L12] havoc #t~nondet2; [L13] havoc ~lk3~0; [L15] ~p4~0 := #t~nondet3; [L15] havoc #t~nondet3; [L16] havoc ~lk4~0; [L18] ~p5~0 := #t~nondet4; [L18] havoc #t~nondet4; [L19] havoc ~lk5~0; [L21] ~p6~0 := #t~nondet5; [L21] havoc #t~nondet5; [L22] havoc ~lk6~0; [L24] ~p7~0 := #t~nondet6; [L24] havoc #t~nondet6; [L25] havoc ~lk7~0; [L27] ~p8~0 := #t~nondet7; [L27] havoc #t~nondet7; [L28] havoc ~lk8~0; [L30] ~p9~0 := #t~nondet8; [L30] havoc #t~nondet8; [L31] havoc ~lk9~0; [L33] ~p10~0 := #t~nondet9; [L33] havoc #t~nondet9; [L34] havoc ~lk10~0; [L36] ~p11~0 := #t~nondet10; [L36] havoc #t~nondet10; [L37] havoc ~lk11~0; [L39] ~p12~0 := #t~nondet11; [L39] havoc #t~nondet11; [L40] havoc ~lk12~0; [L42] ~p13~0 := #t~nondet12; [L42] havoc #t~nondet12; [L43] havoc ~lk13~0; [L45] ~p14~0 := #t~nondet13; [L45] havoc #t~nondet13; [L46] havoc ~lk14~0; [L48] ~p15~0 := #t~nondet14; [L48] havoc #t~nondet14; [L49] havoc ~lk15~0; [L52] havoc ~cond~0; VAL [~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L54-L228] COND FALSE !(false) [L55] ~cond~0 := #t~nondet15; [L55] havoc #t~nondet15; VAL [~cond~0=14bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L56] COND FALSE !(0bv32 == ~cond~0) [L59] ~lk1~0 := 0bv32; [L61] ~lk2~0 := 0bv32; [L63] ~lk3~0 := 0bv32; [L65] ~lk4~0 := 0bv32; [L67] ~lk5~0 := 0bv32; [L69] ~lk6~0 := 0bv32; [L71] ~lk7~0 := 0bv32; [L73] ~lk8~0 := 0bv32; [L75] ~lk9~0 := 0bv32; [L77] ~lk10~0 := 0bv32; [L79] ~lk11~0 := 0bv32; [L81] ~lk12~0 := 0bv32; [L83] ~lk13~0 := 0bv32; [L85] ~lk14~0 := 0bv32; [L87] ~lk15~0 := 0bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L91] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L95] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L99] COND TRUE 0bv32 != ~p3~0 [L100] ~lk3~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L103] COND TRUE 0bv32 != ~p4~0 [L104] ~lk4~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L107] COND TRUE 0bv32 != ~p5~0 [L108] ~lk5~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L111] COND TRUE 0bv32 != ~p6~0 [L112] ~lk6~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L115] COND TRUE 0bv32 != ~p7~0 [L116] ~lk7~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L119] COND FALSE !(0bv32 != ~p8~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L123] COND TRUE 0bv32 != ~p9~0 [L124] ~lk9~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L127] COND TRUE 0bv32 != ~p10~0 [L128] ~lk10~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L131] COND TRUE 0bv32 != ~p11~0 [L132] ~lk11~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L135] COND TRUE 0bv32 != ~p12~0 [L136] ~lk12~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L139] COND TRUE 0bv32 != ~p13~0 [L140] ~lk13~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L143] COND TRUE 0bv32 != ~p14~0 [L144] ~lk14~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L147] COND TRUE 0bv32 != ~p15~0 [L148] ~lk15~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L153] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L158] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L231] assert false; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret16 := main(); [L6] ~p1~0 := #t~nondet0; [L6] havoc #t~nondet0; [L7] havoc ~lk1~0; [L9] ~p2~0 := #t~nondet1; [L9] havoc #t~nondet1; [L10] havoc ~lk2~0; [L12] ~p3~0 := #t~nondet2; [L12] havoc #t~nondet2; [L13] havoc ~lk3~0; [L15] ~p4~0 := #t~nondet3; [L15] havoc #t~nondet3; [L16] havoc ~lk4~0; [L18] ~p5~0 := #t~nondet4; [L18] havoc #t~nondet4; [L19] havoc ~lk5~0; [L21] ~p6~0 := #t~nondet5; [L21] havoc #t~nondet5; [L22] havoc ~lk6~0; [L24] ~p7~0 := #t~nondet6; [L24] havoc #t~nondet6; [L25] havoc ~lk7~0; [L27] ~p8~0 := #t~nondet7; [L27] havoc #t~nondet7; [L28] havoc ~lk8~0; [L30] ~p9~0 := #t~nondet8; [L30] havoc #t~nondet8; [L31] havoc ~lk9~0; [L33] ~p10~0 := #t~nondet9; [L33] havoc #t~nondet9; [L34] havoc ~lk10~0; [L36] ~p11~0 := #t~nondet10; [L36] havoc #t~nondet10; [L37] havoc ~lk11~0; [L39] ~p12~0 := #t~nondet11; [L39] havoc #t~nondet11; [L40] havoc ~lk12~0; [L42] ~p13~0 := #t~nondet12; [L42] havoc #t~nondet12; [L43] havoc ~lk13~0; [L45] ~p14~0 := #t~nondet13; [L45] havoc #t~nondet13; [L46] havoc ~lk14~0; [L48] ~p15~0 := #t~nondet14; [L48] havoc #t~nondet14; [L49] havoc ~lk15~0; [L52] havoc ~cond~0; VAL [~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L54-L228] COND FALSE !(false) [L55] ~cond~0 := #t~nondet15; [L55] havoc #t~nondet15; VAL [~cond~0=14bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L56] COND FALSE !(0bv32 == ~cond~0) [L59] ~lk1~0 := 0bv32; [L61] ~lk2~0 := 0bv32; [L63] ~lk3~0 := 0bv32; [L65] ~lk4~0 := 0bv32; [L67] ~lk5~0 := 0bv32; [L69] ~lk6~0 := 0bv32; [L71] ~lk7~0 := 0bv32; [L73] ~lk8~0 := 0bv32; [L75] ~lk9~0 := 0bv32; [L77] ~lk10~0 := 0bv32; [L79] ~lk11~0 := 0bv32; [L81] ~lk12~0 := 0bv32; [L83] ~lk13~0 := 0bv32; [L85] ~lk14~0 := 0bv32; [L87] ~lk15~0 := 0bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L91] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L95] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=0bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L99] COND TRUE 0bv32 != ~p3~0 [L100] ~lk3~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=0bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L103] COND TRUE 0bv32 != ~p4~0 [L104] ~lk4~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=0bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L107] COND TRUE 0bv32 != ~p5~0 [L108] ~lk5~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=0bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L111] COND TRUE 0bv32 != ~p6~0 [L112] ~lk6~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=0bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L115] COND TRUE 0bv32 != ~p7~0 [L116] ~lk7~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L119] COND FALSE !(0bv32 != ~p8~0) VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=0bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L123] COND TRUE 0bv32 != ~p9~0 [L124] ~lk9~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=0bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L127] COND TRUE 0bv32 != ~p10~0 [L128] ~lk10~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=0bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L131] COND TRUE 0bv32 != ~p11~0 [L132] ~lk11~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=0bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L135] COND TRUE 0bv32 != ~p12~0 [L136] ~lk12~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=0bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L139] COND TRUE 0bv32 != ~p13~0 [L140] ~lk13~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=0bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L143] COND TRUE 0bv32 != ~p14~0 [L144] ~lk14~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=0bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L147] COND TRUE 0bv32 != ~p15~0 [L148] ~lk15~0 := 1bv32; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L153] COND FALSE !(0bv32 != ~p1~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L158] COND FALSE !(0bv32 != ~p2~0) VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L231] assert false; VAL [~cond~0=14bv32, ~lk10~0=1bv32, ~lk11~0=1bv32, ~lk12~0=1bv32, ~lk13~0=1bv32, ~lk14~0=1bv32, ~lk15~0=1bv32, ~lk1~0=0bv32, ~lk2~0=0bv32, ~lk3~0=1bv32, ~lk4~0=1bv32, ~lk5~0=1bv32, ~lk6~0=1bv32, ~lk7~0=1bv32, ~lk8~0=0bv32, ~lk9~0=1bv32, ~p10~0=7bv32, ~p11~0=2bv32, ~p12~0=4bv32, ~p13~0=3bv32, ~p14~0=8bv32, ~p15~0=10bv32, ~p1~0=0bv32, ~p2~0=0bv32, ~p3~0=9bv32, ~p4~0=11bv32, ~p5~0=13bv32, ~p6~0=6bv32, ~p7~0=12bv32, ~p8~0=0bv32, ~p9~0=5bv32] [L6] int p1 = __VERIFIER_nondet_int(); [L7] int lk1; [L9] int p2 = __VERIFIER_nondet_int(); [L10] int lk2; [L12] int p3 = __VERIFIER_nondet_int(); [L13] int lk3; [L15] int p4 = __VERIFIER_nondet_int(); [L16] int lk4; [L18] int p5 = __VERIFIER_nondet_int(); [L19] int lk5; [L21] int p6 = __VERIFIER_nondet_int(); [L22] int lk6; [L24] int p7 = __VERIFIER_nondet_int(); [L25] int lk7; [L27] int p8 = __VERIFIER_nondet_int(); [L28] int lk8; [L30] int p9 = __VERIFIER_nondet_int(); [L31] int lk9; [L33] int p10 = __VERIFIER_nondet_int(); [L34] int lk10; [L36] int p11 = __VERIFIER_nondet_int(); [L37] int lk11; [L39] int p12 = __VERIFIER_nondet_int(); [L40] int lk12; [L42] int p13 = __VERIFIER_nondet_int(); [L43] int lk13; [L45] int p14 = __VERIFIER_nondet_int(); [L46] int lk14; [L48] int p15 = __VERIFIER_nondet_int(); [L49] int lk15; [L52] int cond; VAL [p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L54] COND TRUE 1 [L55] cond = __VERIFIER_nondet_int() [L56] COND FALSE !(cond == 0) [L59] lk1 = 0 [L61] lk2 = 0 [L63] lk3 = 0 [L65] lk4 = 0 [L67] lk5 = 0 [L69] lk6 = 0 [L71] lk7 = 0 [L73] lk8 = 0 [L75] lk9 = 0 [L77] lk10 = 0 [L79] lk11 = 0 [L81] lk12 = 0 [L83] lk13 = 0 [L85] lk14 = 0 [L87] lk15 = 0 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=0, lk4=0, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L91] COND FALSE !(p1 != 0) VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=0, lk4=0, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L95] COND FALSE !(p2 != 0) VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=0, lk4=0, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L99] COND TRUE p3 != 0 [L100] lk3 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=0, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L103] COND TRUE p4 != 0 [L104] lk4 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L107] COND TRUE p5 != 0 [L108] lk5 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L111] COND TRUE p6 != 0 [L112] lk6 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L115] COND TRUE p7 != 0 [L116] lk7 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L119] COND FALSE !(p8 != 0) VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L123] COND TRUE p9 != 0 [L124] lk9 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L127] COND TRUE p10 != 0 [L128] lk10 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L131] COND TRUE p11 != 0 [L132] lk11 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L135] COND TRUE p12 != 0 [L136] lk12 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L139] COND TRUE p13 != 0 [L140] lk13 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L143] COND TRUE p14 != 0 [L144] lk14 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L147] COND TRUE p15 != 0 [L148] lk15 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=1, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L153] COND FALSE !(p1 != 0) VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=1, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L158] COND FALSE !(p2 != 0) VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=1, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L231] __VERIFIER_error() VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=1, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] ----- [2018-11-23 10:53:42,486 INFO L145 WitnessManager]: Wrote witness to /storage/repos/svcomp/c/locks/test_locks_15_false-unreach-call_true-valid-memsafety_false-termination.c-witness.graphml [2018-11-23 10:53:42,486 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 10:53:42,488 INFO L168 Benchmark]: Toolchain (without parser) took 7679.90 ms. Allocated memory was 1.5 GB in the beginning and 2.2 GB in the end (delta: 715.1 MB). Free memory was 1.4 GB in the beginning and 1.6 GB in the end (delta: -211.2 MB). Peak memory consumption was 503.9 MB. Max. memory is 7.1 GB. [2018-11-23 10:53:42,490 INFO L168 Benchmark]: CDTParser took 0.24 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-11-23 10:53:42,490 INFO L168 Benchmark]: CACSL2BoogieTranslator took 334.73 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-11-23 10:53:42,490 INFO L168 Benchmark]: Boogie Procedure Inliner took 22.81 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-11-23 10:53:42,491 INFO L168 Benchmark]: Boogie Preprocessor took 48.74 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-11-23 10:53:42,491 INFO L168 Benchmark]: RCFGBuilder took 1236.84 ms. Allocated memory was 1.5 GB in the beginning and 2.2 GB in the end (delta: 715.1 MB). Free memory was 1.4 GB in the beginning and 2.1 GB in the end (delta: -724.0 MB). Peak memory consumption was 15.2 MB. Max. memory is 7.1 GB. [2018-11-23 10:53:42,492 INFO L168 Benchmark]: TraceAbstraction took 5858.18 ms. Allocated memory is still 2.2 GB. Free memory was 2.1 GB in the beginning and 1.6 GB in the end (delta: 488.8 MB). Peak memory consumption was 488.8 MB. Max. memory is 7.1 GB. [2018-11-23 10:53:42,492 INFO L168 Benchmark]: Witness Printer took 173.41 ms. Allocated memory is still 2.2 GB. Free memory was 1.6 GB in the beginning and 1.6 GB in the end (delta: 13.4 MB). Peak memory consumption was 13.4 MB. Max. memory is 7.1 GB. [2018-11-23 10:53:42,495 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - GenericResult: Assertions are enabled Assertions are enabled - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 334.73 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 22.81 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 48.74 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 1236.84 ms. Allocated memory was 1.5 GB in the beginning and 2.2 GB in the end (delta: 715.1 MB). Free memory was 1.4 GB in the beginning and 2.1 GB in the end (delta: -724.0 MB). Peak memory consumption was 15.2 MB. Max. memory is 7.1 GB. * TraceAbstraction took 5858.18 ms. Allocated memory is still 2.2 GB. Free memory was 2.1 GB in the beginning and 1.6 GB in the end (delta: 488.8 MB). Peak memory consumption was 488.8 MB. Max. memory is 7.1 GB. * Witness Printer took 173.41 ms. Allocated memory is still 2.2 GB. Free memory was 1.6 GB in the beginning and 1.6 GB in the end (delta: 13.4 MB). Peak memory consumption was 13.4 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 231]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L6] int p1 = __VERIFIER_nondet_int(); [L7] int lk1; [L9] int p2 = __VERIFIER_nondet_int(); [L10] int lk2; [L12] int p3 = __VERIFIER_nondet_int(); [L13] int lk3; [L15] int p4 = __VERIFIER_nondet_int(); [L16] int lk4; [L18] int p5 = __VERIFIER_nondet_int(); [L19] int lk5; [L21] int p6 = __VERIFIER_nondet_int(); [L22] int lk6; [L24] int p7 = __VERIFIER_nondet_int(); [L25] int lk7; [L27] int p8 = __VERIFIER_nondet_int(); [L28] int lk8; [L30] int p9 = __VERIFIER_nondet_int(); [L31] int lk9; [L33] int p10 = __VERIFIER_nondet_int(); [L34] int lk10; [L36] int p11 = __VERIFIER_nondet_int(); [L37] int lk11; [L39] int p12 = __VERIFIER_nondet_int(); [L40] int lk12; [L42] int p13 = __VERIFIER_nondet_int(); [L43] int lk13; [L45] int p14 = __VERIFIER_nondet_int(); [L46] int lk14; [L48] int p15 = __VERIFIER_nondet_int(); [L49] int lk15; [L52] int cond; VAL [p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L54] COND TRUE 1 [L55] cond = __VERIFIER_nondet_int() [L56] COND FALSE !(cond == 0) [L59] lk1 = 0 [L61] lk2 = 0 [L63] lk3 = 0 [L65] lk4 = 0 [L67] lk5 = 0 [L69] lk6 = 0 [L71] lk7 = 0 [L73] lk8 = 0 [L75] lk9 = 0 [L77] lk10 = 0 [L79] lk11 = 0 [L81] lk12 = 0 [L83] lk13 = 0 [L85] lk14 = 0 [L87] lk15 = 0 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=0, lk4=0, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L91] COND FALSE !(p1 != 0) VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=0, lk4=0, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L95] COND FALSE !(p2 != 0) VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=0, lk4=0, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L99] COND TRUE p3 != 0 [L100] lk3 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=0, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L103] COND TRUE p4 != 0 [L104] lk4 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=0, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L107] COND TRUE p5 != 0 [L108] lk5 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=0, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L111] COND TRUE p6 != 0 [L112] lk6 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=0, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L115] COND TRUE p7 != 0 [L116] lk7 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L119] COND FALSE !(p8 != 0) VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=0, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L123] COND TRUE p9 != 0 [L124] lk9 = 1 VAL [cond=14, lk1=0, lk10=0, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L127] COND TRUE p10 != 0 [L128] lk10 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=0, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L131] COND TRUE p11 != 0 [L132] lk11 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=0, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L135] COND TRUE p12 != 0 [L136] lk12 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=0, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L139] COND TRUE p13 != 0 [L140] lk13 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=0, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L143] COND TRUE p14 != 0 [L144] lk14 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=0, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L147] COND TRUE p15 != 0 [L148] lk15 = 1 VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=1, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L153] COND FALSE !(p1 != 0) VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=1, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L158] COND FALSE !(p2 != 0) VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=1, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] [L231] __VERIFIER_error() VAL [cond=14, lk1=0, lk10=1, lk11=1, lk12=1, lk13=1, lk14=1, lk15=1, lk2=0, lk3=1, lk4=1, lk5=1, lk6=1, lk7=1, lk8=0, lk9=1, p1=0, p10=7, p11=2, p12=4, p13=3, p14=8, p15=10, p2=0, p3=9, p4=11, p5=13, p6=6, p7=12, p8=0, p9=5] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 59 locations, 1 error locations. UNSAFE Result, 5.7s OverallTime, 5 OverallIterations, 1 TraceHistogramMax, 3.6s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 488 SDtfs, 243 SDslu, 321 SDs, 0 SdLazy, 20 SolverSat, 5 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 96 GetRequests, 92 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=138occurred in iteration=3, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 4 MinimizatonAttempts, 6 StatesRemovedByMinimization, 3 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.0s SatisfiabilityAnalysisTime, 0.8s InterpolantComputationTime, 125 NumberOfCodeBlocks, 125 NumberOfCodeBlocksAsserted, 5 NumberOfCheckSat, 96 ConstructedInterpolants, 0 QuantifiedInterpolants, 6720 SizeOfPredicates, 1 NumberOfNonLiveVariables, 294 ConjunctsInSsa, 8 ConjunctsInUnsatCore, 4 InterpolantComputations, 4 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...