java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test15_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-acfac67 [2018-01-28 22:34:29,600 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-28 22:34:29,610 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-28 22:34:29,625 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-28 22:34:29,625 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-28 22:34:29,626 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-28 22:34:29,627 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-28 22:34:29,628 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-28 22:34:29,630 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-28 22:34:29,631 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-28 22:34:29,632 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-28 22:34:29,632 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-28 22:34:29,633 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-28 22:34:29,634 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-28 22:34:29,635 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-28 22:34:29,637 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-28 22:34:29,639 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-28 22:34:29,641 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-28 22:34:29,643 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-28 22:34:29,644 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-28 22:34:29,646 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-28 22:34:29,646 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-28 22:34:29,646 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-28 22:34:29,647 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-28 22:34:29,648 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-28 22:34:29,649 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-28 22:34:29,650 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-28 22:34:29,650 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-28 22:34:29,651 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-28 22:34:29,651 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-28 22:34:29,651 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-28 22:34:29,652 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf [2018-01-28 22:34:29,659 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-28 22:34:29,660 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-28 22:34:29,660 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-28 22:34:29,661 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-28 22:34:29,661 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-28 22:34:29,661 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-28 22:34:29,661 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-28 22:34:29,661 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-28 22:34:29,662 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-28 22:34:29,662 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-28 22:34:29,662 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-28 22:34:29,662 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-28 22:34:29,662 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-28 22:34:29,662 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-28 22:34:29,663 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-28 22:34:29,663 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-28 22:34:29,663 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-28 22:34:29,663 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-28 22:34:29,663 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-28 22:34:29,663 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-01-28 22:34:29,663 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-28 22:34:29,663 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-28 22:34:29,664 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-28 22:34:29,664 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-28 22:34:29,664 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-28 22:34:29,664 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-28 22:34:29,664 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-28 22:34:29,665 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-28 22:34:29,665 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-28 22:34:29,665 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-28 22:34:29,665 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-28 22:34:29,665 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-28 22:34:29,666 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-28 22:34:29,666 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-28 22:34:29,696 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-28 22:34:29,706 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-28 22:34:29,709 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-28 22:34:29,710 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-28 22:34:29,711 INFO L276 PluginConnector]: CDTParser initialized [2018-01-28 22:34:29,711 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test15_true-valid-memsafety_true-termination.i [2018-01-28 22:34:29,901 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-28 22:34:29,906 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-28 22:34:29,906 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-28 22:34:29,906 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-28 22:34:29,911 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-28 22:34:29,912 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.01 10:34:29" (1/1) ... [2018-01-28 22:34:29,914 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@715ee194 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 10:34:29, skipping insertion in model container [2018-01-28 22:34:29,914 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.01 10:34:29" (1/1) ... [2018-01-28 22:34:29,927 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-28 22:34:29,975 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-28 22:34:30,098 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-28 22:34:30,128 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-28 22:34:30,142 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 10:34:30 WrapperNode [2018-01-28 22:34:30,142 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-28 22:34:30,143 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-28 22:34:30,143 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-28 22:34:30,143 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-28 22:34:30,153 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 10:34:30" (1/1) ... [2018-01-28 22:34:30,153 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 10:34:30" (1/1) ... [2018-01-28 22:34:30,165 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 10:34:30" (1/1) ... [2018-01-28 22:34:30,165 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 10:34:30" (1/1) ... [2018-01-28 22:34:30,174 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 10:34:30" (1/1) ... [2018-01-28 22:34:30,178 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 10:34:30" (1/1) ... [2018-01-28 22:34:30,180 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 10:34:30" (1/1) ... [2018-01-28 22:34:30,184 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-28 22:34:30,184 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-28 22:34:30,185 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-28 22:34:30,185 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-28 22:34:30,186 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 10:34:30" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-28 22:34:30,233 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-28 22:34:30,233 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-28 22:34:30,233 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_nonpositive [2018-01-28 22:34:30,233 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-01-28 22:34:30,233 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-01-28 22:34:30,234 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-01-28 22:34:30,234 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-01-28 22:34:30,234 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_hid_get_drvdata [2018-01-28 22:34:30,234 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_hid_set_drvdata [2018-01-28 22:34:30,234 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_init_arvo_device_struct [2018-01-28 22:34:30,234 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_init_specials [2018-01-28 22:34:30,234 INFO L136 BoogieDeclarations]: Found implementation of procedure lvd_arvo_remove_specials [2018-01-28 22:34:30,234 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_probe [2018-01-28 22:34:30,234 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_remove [2018-01-28 22:34:30,234 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-01-28 22:34:30,235 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-28 22:34:30,235 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-28 22:34:30,235 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-28 22:34:30,235 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-01-28 22:34:30,235 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-01-28 22:34:30,235 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-28 22:34:30,235 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-28 22:34:30,236 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-28 22:34:30,236 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-01-28 22:34:30,236 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-01-28 22:34:30,236 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-01-28 22:34:30,236 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-01-28 22:34:30,237 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-01-28 22:34:30,237 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-28 22:34:30,237 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_nonpositive [2018-01-28 22:34:30,237 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-01-28 22:34:30,237 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-01-28 22:34:30,237 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-01-28 22:34:30,238 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-01-28 22:34:30,238 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_hid_get_drvdata [2018-01-28 22:34:30,238 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_hid_set_drvdata [2018-01-28 22:34:30,238 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_init_arvo_device_struct [2018-01-28 22:34:30,238 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_init_specials [2018-01-28 22:34:30,238 INFO L128 BoogieDeclarations]: Found specification of procedure lvd_arvo_remove_specials [2018-01-28 22:34:30,238 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_probe [2018-01-28 22:34:30,239 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_remove [2018-01-28 22:34:30,239 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-01-28 22:34:30,239 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-28 22:34:30,239 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-28 22:34:30,239 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-28 22:34:30,794 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-28 22:34:30,794 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.01 10:34:30 BoogieIcfgContainer [2018-01-28 22:34:30,794 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-28 22:34:30,795 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-28 22:34:30,795 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-28 22:34:30,798 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-28 22:34:30,798 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.01 10:34:29" (1/3) ... [2018-01-28 22:34:30,798 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@22b4ee1d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.01 10:34:30, skipping insertion in model container [2018-01-28 22:34:30,799 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 10:34:30" (2/3) ... [2018-01-28 22:34:30,799 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@22b4ee1d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.01 10:34:30, skipping insertion in model container [2018-01-28 22:34:30,799 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.01 10:34:30" (3/3) ... [2018-01-28 22:34:30,800 INFO L107 eAbstractionObserver]: Analyzing ICFG memleaks_test15_true-valid-memsafety_true-termination.i [2018-01-28 22:34:30,806 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-28 22:34:30,812 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 45 error locations. [2018-01-28 22:34:30,856 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-28 22:34:30,856 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-28 22:34:30,856 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-28 22:34:30,856 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-28 22:34:30,856 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-28 22:34:30,857 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-28 22:34:30,857 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-28 22:34:30,857 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-28 22:34:30,858 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-28 22:34:30,879 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states. [2018-01-28 22:34:30,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-01-28 22:34:30,885 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:30,886 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:30,887 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:30,890 INFO L82 PathProgramCache]: Analyzing trace with hash -411099236, now seen corresponding path program 1 times [2018-01-28 22:34:30,892 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:30,892 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:30,936 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:30,936 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:30,937 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:30,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:30,994 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:31,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-28 22:34:31,165 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:34:31,165 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-28 22:34:31,167 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-28 22:34:31,176 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-28 22:34:31,177 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-28 22:34:31,179 INFO L87 Difference]: Start difference. First operand 225 states. Second operand 3 states. [2018-01-28 22:34:31,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:31,487 INFO L93 Difference]: Finished difference Result 293 states and 322 transitions. [2018-01-28 22:34:31,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-28 22:34:31,489 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 21 [2018-01-28 22:34:31,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:31,504 INFO L225 Difference]: With dead ends: 293 [2018-01-28 22:34:31,504 INFO L226 Difference]: Without dead ends: 286 [2018-01-28 22:34:31,508 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-28 22:34:31,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286 states. [2018-01-28 22:34:31,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286 to 227. [2018-01-28 22:34:31,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227 states. [2018-01-28 22:34:31,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227 states to 227 states and 243 transitions. [2018-01-28 22:34:31,569 INFO L78 Accepts]: Start accepts. Automaton has 227 states and 243 transitions. Word has length 21 [2018-01-28 22:34:31,570 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:31,570 INFO L432 AbstractCegarLoop]: Abstraction has 227 states and 243 transitions. [2018-01-28 22:34:31,570 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-28 22:34:31,570 INFO L276 IsEmpty]: Start isEmpty. Operand 227 states and 243 transitions. [2018-01-28 22:34:31,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-01-28 22:34:31,572 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:31,572 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:31,572 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:31,573 INFO L82 PathProgramCache]: Analyzing trace with hash -1317459009, now seen corresponding path program 1 times [2018-01-28 22:34:31,573 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:31,573 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:31,574 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:31,574 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:31,574 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:31,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:31,594 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:31,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-28 22:34:31,686 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:34:31,686 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-28 22:34:31,687 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-28 22:34:31,688 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-28 22:34:31,688 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-28 22:34:31,688 INFO L87 Difference]: Start difference. First operand 227 states and 243 transitions. Second operand 6 states. [2018-01-28 22:34:31,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:31,774 INFO L93 Difference]: Finished difference Result 278 states and 303 transitions. [2018-01-28 22:34:31,776 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-28 22:34:31,776 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-01-28 22:34:31,777 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:31,780 INFO L225 Difference]: With dead ends: 278 [2018-01-28 22:34:31,780 INFO L226 Difference]: Without dead ends: 274 [2018-01-28 22:34:31,781 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-01-28 22:34:31,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states. [2018-01-28 22:34:31,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 222. [2018-01-28 22:34:31,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222 states. [2018-01-28 22:34:31,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 235 transitions. [2018-01-28 22:34:31,802 INFO L78 Accepts]: Start accepts. Automaton has 222 states and 235 transitions. Word has length 22 [2018-01-28 22:34:31,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:31,803 INFO L432 AbstractCegarLoop]: Abstraction has 222 states and 235 transitions. [2018-01-28 22:34:31,803 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-28 22:34:31,803 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 235 transitions. [2018-01-28 22:34:31,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-01-28 22:34:31,804 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:31,804 INFO L330 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:31,804 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:31,805 INFO L82 PathProgramCache]: Analyzing trace with hash -1940195697, now seen corresponding path program 1 times [2018-01-28 22:34:31,805 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:31,805 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:31,806 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:31,806 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:31,806 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:31,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:31,820 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:31,880 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-01-28 22:34:31,880 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:34:31,881 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:34:31,909 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:31,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:31,946 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:34:31,987 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-01-28 22:34:32,007 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-28 22:34:32,007 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4] total 8 [2018-01-28 22:34:32,008 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-28 22:34:32,008 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-28 22:34:32,008 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-01-28 22:34:32,008 INFO L87 Difference]: Start difference. First operand 222 states and 235 transitions. Second operand 8 states. [2018-01-28 22:34:32,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:32,053 INFO L93 Difference]: Finished difference Result 438 states and 465 transitions. [2018-01-28 22:34:32,053 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-28 22:34:32,053 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 30 [2018-01-28 22:34:32,054 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:32,055 INFO L225 Difference]: With dead ends: 438 [2018-01-28 22:34:32,056 INFO L226 Difference]: Without dead ends: 224 [2018-01-28 22:34:32,057 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 28 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2018-01-28 22:34:32,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-01-28 22:34:32,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 224. [2018-01-28 22:34:32,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 224 states. [2018-01-28 22:34:32,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 238 transitions. [2018-01-28 22:34:32,074 INFO L78 Accepts]: Start accepts. Automaton has 224 states and 238 transitions. Word has length 30 [2018-01-28 22:34:32,075 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:32,075 INFO L432 AbstractCegarLoop]: Abstraction has 224 states and 238 transitions. [2018-01-28 22:34:32,075 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-28 22:34:32,075 INFO L276 IsEmpty]: Start isEmpty. Operand 224 states and 238 transitions. [2018-01-28 22:34:32,076 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-01-28 22:34:32,076 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:32,076 INFO L330 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:32,076 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:32,077 INFO L82 PathProgramCache]: Analyzing trace with hash 855171532, now seen corresponding path program 1 times [2018-01-28 22:34:32,077 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:32,077 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:32,078 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:32,078 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:32,079 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:32,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:32,095 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:32,169 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 3 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-28 22:34:32,170 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:34:32,170 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:34:32,179 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:32,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:32,204 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:34:32,226 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-28 22:34:32,228 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:32,235 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:34:32,235 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-28 22:34:32,278 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 3 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-28 22:34:32,297 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-28 22:34:32,297 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-01-28 22:34:32,298 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-28 22:34:32,298 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-28 22:34:32,298 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-28 22:34:32,298 INFO L87 Difference]: Start difference. First operand 224 states and 238 transitions. Second operand 7 states. [2018-01-28 22:34:32,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:32,794 INFO L93 Difference]: Finished difference Result 281 states and 303 transitions. [2018-01-28 22:34:32,794 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-28 22:34:32,794 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 31 [2018-01-28 22:34:32,794 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:32,796 INFO L225 Difference]: With dead ends: 281 [2018-01-28 22:34:32,796 INFO L226 Difference]: Without dead ends: 279 [2018-01-28 22:34:32,797 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 29 SyntacticMatches, 3 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-01-28 22:34:32,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 279 states. [2018-01-28 22:34:32,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 279 to 240. [2018-01-28 22:34:32,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 240 states. [2018-01-28 22:34:32,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 240 states to 240 states and 268 transitions. [2018-01-28 22:34:32,811 INFO L78 Accepts]: Start accepts. Automaton has 240 states and 268 transitions. Word has length 31 [2018-01-28 22:34:32,813 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:32,813 INFO L432 AbstractCegarLoop]: Abstraction has 240 states and 268 transitions. [2018-01-28 22:34:32,813 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-28 22:34:32,813 INFO L276 IsEmpty]: Start isEmpty. Operand 240 states and 268 transitions. [2018-01-28 22:34:32,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-01-28 22:34:32,814 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:32,814 INFO L330 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:32,815 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:32,815 INFO L82 PathProgramCache]: Analyzing trace with hash 855171531, now seen corresponding path program 1 times [2018-01-28 22:34:32,815 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:32,815 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:32,816 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:32,816 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:32,816 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:32,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:32,830 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:32,868 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-28 22:34:32,868 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:34:32,869 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:34:32,873 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:32,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:32,889 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:34:32,916 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-28 22:34:32,936 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-28 22:34:32,937 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-01-28 22:34:32,937 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-28 22:34:32,937 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-28 22:34:32,937 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-28 22:34:32,937 INFO L87 Difference]: Start difference. First operand 240 states and 268 transitions. Second operand 6 states. [2018-01-28 22:34:32,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:32,968 INFO L93 Difference]: Finished difference Result 240 states and 268 transitions. [2018-01-28 22:34:32,970 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-28 22:34:32,970 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 31 [2018-01-28 22:34:32,970 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:32,972 INFO L225 Difference]: With dead ends: 240 [2018-01-28 22:34:32,972 INFO L226 Difference]: Without dead ends: 239 [2018-01-28 22:34:32,973 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 29 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-01-28 22:34:32,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2018-01-28 22:34:32,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 239. [2018-01-28 22:34:32,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 239 states. [2018-01-28 22:34:32,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 239 states to 239 states and 266 transitions. [2018-01-28 22:34:32,987 INFO L78 Accepts]: Start accepts. Automaton has 239 states and 266 transitions. Word has length 31 [2018-01-28 22:34:32,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:32,987 INFO L432 AbstractCegarLoop]: Abstraction has 239 states and 266 transitions. [2018-01-28 22:34:32,987 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-28 22:34:32,987 INFO L276 IsEmpty]: Start isEmpty. Operand 239 states and 266 transitions. [2018-01-28 22:34:32,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-28 22:34:32,988 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:32,989 INFO L330 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:32,989 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:32,989 INFO L82 PathProgramCache]: Analyzing trace with hash -391957859, now seen corresponding path program 1 times [2018-01-28 22:34:32,989 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:32,989 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:32,990 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:32,990 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:32,991 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:33,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:33,004 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:33,058 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-01-28 22:34:33,059 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:34:33,059 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-28 22:34:33,059 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-28 22:34:33,059 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-28 22:34:33,059 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-28 22:34:33,060 INFO L87 Difference]: Start difference. First operand 239 states and 266 transitions. Second operand 6 states. [2018-01-28 22:34:33,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:33,175 INFO L93 Difference]: Finished difference Result 286 states and 317 transitions. [2018-01-28 22:34:33,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-28 22:34:33,176 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 32 [2018-01-28 22:34:33,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:33,177 INFO L225 Difference]: With dead ends: 286 [2018-01-28 22:34:33,178 INFO L226 Difference]: Without dead ends: 280 [2018-01-28 22:34:33,178 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-01-28 22:34:33,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 280 states. [2018-01-28 22:34:33,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 280 to 239. [2018-01-28 22:34:33,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 239 states. [2018-01-28 22:34:33,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 239 states to 239 states and 265 transitions. [2018-01-28 22:34:33,193 INFO L78 Accepts]: Start accepts. Automaton has 239 states and 265 transitions. Word has length 32 [2018-01-28 22:34:33,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:33,193 INFO L432 AbstractCegarLoop]: Abstraction has 239 states and 265 transitions. [2018-01-28 22:34:33,193 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-28 22:34:33,193 INFO L276 IsEmpty]: Start isEmpty. Operand 239 states and 265 transitions. [2018-01-28 22:34:33,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-28 22:34:33,194 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:33,195 INFO L330 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:33,195 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:33,195 INFO L82 PathProgramCache]: Analyzing trace with hash -1330801367, now seen corresponding path program 1 times [2018-01-28 22:34:33,195 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:33,195 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:33,196 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:33,196 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:33,196 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:33,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:33,212 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:33,339 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-28 22:34:33,339 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:34:33,339 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:34:33,348 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:33,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:33,367 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:34:33,542 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-28 22:34:33,567 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-28 22:34:33,567 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 8] total 12 [2018-01-28 22:34:33,567 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-28 22:34:33,568 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-28 22:34:33,568 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=122, Unknown=9, NotChecked=0, Total=156 [2018-01-28 22:34:33,568 INFO L87 Difference]: Start difference. First operand 239 states and 265 transitions. Second operand 13 states. [2018-01-28 22:34:34,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:34,623 INFO L93 Difference]: Finished difference Result 282 states and 304 transitions. [2018-01-28 22:34:34,654 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-28 22:34:34,654 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 34 [2018-01-28 22:34:34,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:34,656 INFO L225 Difference]: With dead ends: 282 [2018-01-28 22:34:34,656 INFO L226 Difference]: Without dead ends: 277 [2018-01-28 22:34:34,656 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 32 SyntacticMatches, 3 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=59, Invalid=274, Unknown=9, NotChecked=0, Total=342 [2018-01-28 22:34:34,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277 states. [2018-01-28 22:34:34,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277 to 238. [2018-01-28 22:34:34,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-01-28 22:34:34,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 263 transitions. [2018-01-28 22:34:34,666 INFO L78 Accepts]: Start accepts. Automaton has 238 states and 263 transitions. Word has length 34 [2018-01-28 22:34:34,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:34,666 INFO L432 AbstractCegarLoop]: Abstraction has 238 states and 263 transitions. [2018-01-28 22:34:34,666 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-28 22:34:34,666 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 263 transitions. [2018-01-28 22:34:34,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-01-28 22:34:34,667 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:34,668 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:34,668 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:34,668 INFO L82 PathProgramCache]: Analyzing trace with hash 297311418, now seen corresponding path program 1 times [2018-01-28 22:34:34,668 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:34,668 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:34,669 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:34,670 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:34,670 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:34,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:34,679 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:34,725 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-01-28 22:34:34,725 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:34:34,725 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:34:34,732 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:34,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:34,750 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:34:34,760 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-28 22:34:34,792 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-01-28 22:34:34,792 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [5] total 5 [2018-01-28 22:34:34,793 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-28 22:34:34,793 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-28 22:34:34,793 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-28 22:34:34,793 INFO L87 Difference]: Start difference. First operand 238 states and 263 transitions. Second operand 5 states. [2018-01-28 22:34:34,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:34,842 INFO L93 Difference]: Finished difference Result 445 states and 478 transitions. [2018-01-28 22:34:34,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-28 22:34:34,842 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 39 [2018-01-28 22:34:34,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:34,844 INFO L225 Difference]: With dead ends: 445 [2018-01-28 22:34:34,844 INFO L226 Difference]: Without dead ends: 223 [2018-01-28 22:34:34,845 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 38 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-28 22:34:34,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-01-28 22:34:34,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 223. [2018-01-28 22:34:34,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 223 states. [2018-01-28 22:34:34,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 235 transitions. [2018-01-28 22:34:34,855 INFO L78 Accepts]: Start accepts. Automaton has 223 states and 235 transitions. Word has length 39 [2018-01-28 22:34:34,855 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:34,855 INFO L432 AbstractCegarLoop]: Abstraction has 223 states and 235 transitions. [2018-01-28 22:34:34,855 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-28 22:34:34,855 INFO L276 IsEmpty]: Start isEmpty. Operand 223 states and 235 transitions. [2018-01-28 22:34:34,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-01-28 22:34:34,856 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:34,856 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:34,856 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:34,857 INFO L82 PathProgramCache]: Analyzing trace with hash -336491381, now seen corresponding path program 2 times [2018-01-28 22:34:34,857 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:34,857 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:34,858 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:34,858 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:34,858 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:34,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:34,870 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:34,931 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 11 proven. 2 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-01-28 22:34:34,931 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:34:34,931 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:34:34,941 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-28 22:34:34,951 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-28 22:34:34,957 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-28 22:34:34,967 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-28 22:34:34,969 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:34:34,984 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-28 22:34:34,984 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:34,995 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:34:34,995 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-28 22:34:35,011 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 11 proven. 2 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-01-28 22:34:35,031 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-28 22:34:35,031 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-01-28 22:34:35,032 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-28 22:34:35,032 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-28 22:34:35,032 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-28 22:34:35,032 INFO L87 Difference]: Start difference. First operand 223 states and 235 transitions. Second operand 7 states. [2018-01-28 22:34:35,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:35,412 INFO L93 Difference]: Finished difference Result 251 states and 267 transitions. [2018-01-28 22:34:35,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-28 22:34:35,412 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 40 [2018-01-28 22:34:35,412 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:35,414 INFO L225 Difference]: With dead ends: 251 [2018-01-28 22:34:35,414 INFO L226 Difference]: Without dead ends: 246 [2018-01-28 22:34:35,414 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 39 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-01-28 22:34:35,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-01-28 22:34:35,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 243. [2018-01-28 22:34:35,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 243 states. [2018-01-28 22:34:35,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 243 states to 243 states and 262 transitions. [2018-01-28 22:34:35,424 INFO L78 Accepts]: Start accepts. Automaton has 243 states and 262 transitions. Word has length 40 [2018-01-28 22:34:35,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:35,424 INFO L432 AbstractCegarLoop]: Abstraction has 243 states and 262 transitions. [2018-01-28 22:34:35,424 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-28 22:34:35,425 INFO L276 IsEmpty]: Start isEmpty. Operand 243 states and 262 transitions. [2018-01-28 22:34:35,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-01-28 22:34:35,425 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:35,426 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:35,426 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:35,426 INFO L82 PathProgramCache]: Analyzing trace with hash -336491380, now seen corresponding path program 1 times [2018-01-28 22:34:35,426 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:35,426 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:35,427 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:35,427 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-28 22:34:35,427 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:35,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:35,440 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:35,938 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 13 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-01-28 22:34:35,938 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:34:35,938 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:34:35,947 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:35,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:35,971 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:34:35,986 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-28 22:34:35,987 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:36,008 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-28 22:34:36,008 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:36,019 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-01-28 22:34:36,019 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:38, output treesize:36 [2018-01-28 22:34:36,109 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 13 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-01-28 22:34:36,130 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-28 22:34:36,130 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-01-28 22:34:36,130 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-28 22:34:36,130 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-28 22:34:36,131 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2018-01-28 22:34:36,131 INFO L87 Difference]: Start difference. First operand 243 states and 262 transitions. Second operand 13 states. [2018-01-28 22:34:36,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:36,841 INFO L93 Difference]: Finished difference Result 283 states and 309 transitions. [2018-01-28 22:34:36,841 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-28 22:34:36,842 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 40 [2018-01-28 22:34:36,842 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:36,844 INFO L225 Difference]: With dead ends: 283 [2018-01-28 22:34:36,844 INFO L226 Difference]: Without dead ends: 278 [2018-01-28 22:34:36,844 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 36 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=54, Invalid=218, Unknown=0, NotChecked=0, Total=272 [2018-01-28 22:34:36,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278 states. [2018-01-28 22:34:36,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278 to 266. [2018-01-28 22:34:36,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 266 states. [2018-01-28 22:34:36,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 266 states to 266 states and 298 transitions. [2018-01-28 22:34:36,865 INFO L78 Accepts]: Start accepts. Automaton has 266 states and 298 transitions. Word has length 40 [2018-01-28 22:34:36,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:36,865 INFO L432 AbstractCegarLoop]: Abstraction has 266 states and 298 transitions. [2018-01-28 22:34:36,865 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-28 22:34:36,865 INFO L276 IsEmpty]: Start isEmpty. Operand 266 states and 298 transitions. [2018-01-28 22:34:36,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-28 22:34:36,866 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:36,866 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:36,866 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:36,867 INFO L82 PathProgramCache]: Analyzing trace with hash -1214775628, now seen corresponding path program 1 times [2018-01-28 22:34:36,867 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:36,867 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:36,868 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:36,868 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:36,868 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:36,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:36,881 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:37,023 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 16 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-01-28 22:34:37,024 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:34:37,024 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:34:37,035 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:37,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:37,056 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:34:37,060 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-28 22:34:37,061 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:37,062 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:34:37,062 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-28 22:34:37,103 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:37,104 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:37,108 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-01-28 22:34:37,108 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:37,155 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:34:37,156 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-01-28 22:34:37,183 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 16 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-01-28 22:34:37,204 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-28 22:34:37,205 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 10 [2018-01-28 22:34:37,205 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-28 22:34:37,205 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-28 22:34:37,205 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=86, Unknown=1, NotChecked=0, Total=110 [2018-01-28 22:34:37,205 INFO L87 Difference]: Start difference. First operand 266 states and 298 transitions. Second operand 11 states. [2018-01-28 22:34:38,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:38,094 INFO L93 Difference]: Finished difference Result 292 states and 324 transitions. [2018-01-28 22:34:38,095 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-28 22:34:38,095 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 41 [2018-01-28 22:34:38,096 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:38,097 INFO L225 Difference]: With dead ends: 292 [2018-01-28 22:34:38,098 INFO L226 Difference]: Without dead ends: 290 [2018-01-28 22:34:38,098 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 37 SyntacticMatches, 3 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=41, Invalid=140, Unknown=1, NotChecked=0, Total=182 [2018-01-28 22:34:38,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 290 states. [2018-01-28 22:34:38,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 290 to 275. [2018-01-28 22:34:38,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 275 states. [2018-01-28 22:34:38,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 275 states to 275 states and 309 transitions. [2018-01-28 22:34:38,120 INFO L78 Accepts]: Start accepts. Automaton has 275 states and 309 transitions. Word has length 41 [2018-01-28 22:34:38,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:38,120 INFO L432 AbstractCegarLoop]: Abstraction has 275 states and 309 transitions. [2018-01-28 22:34:38,120 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-28 22:34:38,120 INFO L276 IsEmpty]: Start isEmpty. Operand 275 states and 309 transitions. [2018-01-28 22:34:38,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-28 22:34:38,121 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:38,121 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:38,121 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:38,122 INFO L82 PathProgramCache]: Analyzing trace with hash -1214775627, now seen corresponding path program 1 times [2018-01-28 22:34:38,122 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:38,123 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:38,124 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:38,124 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:38,124 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:38,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:38,139 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:38,508 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 16 proven. 7 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-01-28 22:34:38,508 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:34:38,508 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:34:38,513 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:38,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:38,531 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:34:38,546 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2018-01-28 22:34:38,547 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:38,569 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-01-28 22:34:38,570 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:38,585 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-01-28 22:34:38,585 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:38,586 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-01-28 22:34:38,587 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:38,599 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-01-28 22:34:38,599 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:50, output treesize:46 [2018-01-28 22:34:38,758 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:38,758 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:38,759 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2018-01-28 22:34:38,759 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:38,776 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:38,777 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 37 [2018-01-28 22:34:38,777 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:38,797 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:38,797 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:38,798 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 26 [2018-01-28 22:34:38,798 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:38,813 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-01-28 22:34:38,813 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:38,827 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-01-28 22:34:38,828 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 8 variables, input treesize:67, output treesize:49 [2018-01-28 22:34:38,872 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 16 proven. 7 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-01-28 22:34:38,892 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-28 22:34:38,892 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 17 [2018-01-28 22:34:38,892 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-28 22:34:38,893 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-28 22:34:38,893 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=261, Unknown=1, NotChecked=0, Total=306 [2018-01-28 22:34:38,893 INFO L87 Difference]: Start difference. First operand 275 states and 309 transitions. Second operand 18 states. [2018-01-28 22:34:39,137 WARN L146 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 68 DAG size of output 65 [2018-01-28 22:34:52,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:52,119 INFO L93 Difference]: Finished difference Result 292 states and 331 transitions. [2018-01-28 22:34:52,119 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-28 22:34:52,119 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 41 [2018-01-28 22:34:52,119 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:52,121 INFO L225 Difference]: With dead ends: 292 [2018-01-28 22:34:52,121 INFO L226 Difference]: Without dead ends: 287 [2018-01-28 22:34:52,122 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 35 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 68 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=84, Invalid=421, Unknown=1, NotChecked=0, Total=506 [2018-01-28 22:34:52,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states. [2018-01-28 22:34:52,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 236. [2018-01-28 22:34:52,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236 states. [2018-01-28 22:34:52,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236 states to 236 states and 252 transitions. [2018-01-28 22:34:52,140 INFO L78 Accepts]: Start accepts. Automaton has 236 states and 252 transitions. Word has length 41 [2018-01-28 22:34:52,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:52,140 INFO L432 AbstractCegarLoop]: Abstraction has 236 states and 252 transitions. [2018-01-28 22:34:52,140 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-28 22:34:52,140 INFO L276 IsEmpty]: Start isEmpty. Operand 236 states and 252 transitions. [2018-01-28 22:34:52,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-01-28 22:34:52,141 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:52,141 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:52,141 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:52,142 INFO L82 PathProgramCache]: Analyzing trace with hash -1995664814, now seen corresponding path program 1 times [2018-01-28 22:34:52,142 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:52,142 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:52,143 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:52,143 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:52,143 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:52,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:52,153 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:52,379 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 8 proven. 7 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-28 22:34:52,380 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:34:52,380 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:34:52,390 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:52,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:52,414 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:34:52,422 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-28 22:34:52,423 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:52,424 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:34:52,425 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-28 22:34:52,471 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:52,471 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:52,472 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-01-28 22:34:52,473 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:52,478 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:34:52,479 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:15 [2018-01-28 22:34:52,564 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:52,564 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 15 [2018-01-28 22:34:52,565 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:52,569 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:34:52,569 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:25, output treesize:15 [2018-01-28 22:34:52,588 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 11 proven. 4 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-28 22:34:52,611 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-28 22:34:52,611 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 16 [2018-01-28 22:34:52,611 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-28 22:34:52,612 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-28 22:34:52,612 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=232, Unknown=0, NotChecked=0, Total=272 [2018-01-28 22:34:52,612 INFO L87 Difference]: Start difference. First operand 236 states and 252 transitions. Second operand 17 states. [2018-01-28 22:34:53,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:53,547 INFO L93 Difference]: Finished difference Result 257 states and 277 transitions. [2018-01-28 22:34:53,548 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-28 22:34:53,548 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 46 [2018-01-28 22:34:53,548 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:53,549 INFO L225 Difference]: With dead ends: 257 [2018-01-28 22:34:53,549 INFO L226 Difference]: Without dead ends: 255 [2018-01-28 22:34:53,549 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 66 GetRequests, 39 SyntacticMatches, 5 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=84, Invalid=468, Unknown=0, NotChecked=0, Total=552 [2018-01-28 22:34:53,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 255 states. [2018-01-28 22:34:53,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 255 to 236. [2018-01-28 22:34:53,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236 states. [2018-01-28 22:34:53,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236 states to 236 states and 252 transitions. [2018-01-28 22:34:53,564 INFO L78 Accepts]: Start accepts. Automaton has 236 states and 252 transitions. Word has length 46 [2018-01-28 22:34:53,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:53,564 INFO L432 AbstractCegarLoop]: Abstraction has 236 states and 252 transitions. [2018-01-28 22:34:53,564 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-28 22:34:53,564 INFO L276 IsEmpty]: Start isEmpty. Operand 236 states and 252 transitions. [2018-01-28 22:34:53,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-01-28 22:34:53,565 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:53,565 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:53,565 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:53,565 INFO L82 PathProgramCache]: Analyzing trace with hash -1733237887, now seen corresponding path program 1 times [2018-01-28 22:34:53,565 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:53,565 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:53,566 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:53,566 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:53,566 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:53,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:53,573 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:53,693 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-28 22:34:53,694 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:34:53,694 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-28 22:34:53,694 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-28 22:34:53,694 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-28 22:34:53,694 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-28 22:34:53,694 INFO L87 Difference]: Start difference. First operand 236 states and 252 transitions. Second operand 6 states. [2018-01-28 22:34:53,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:53,814 INFO L93 Difference]: Finished difference Result 446 states and 475 transitions. [2018-01-28 22:34:53,814 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-28 22:34:53,814 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 47 [2018-01-28 22:34:53,815 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:53,816 INFO L225 Difference]: With dead ends: 446 [2018-01-28 22:34:53,816 INFO L226 Difference]: Without dead ends: 245 [2018-01-28 22:34:53,817 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-01-28 22:34:53,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245 states. [2018-01-28 22:34:53,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245 to 240. [2018-01-28 22:34:53,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 240 states. [2018-01-28 22:34:53,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 240 states to 240 states and 256 transitions. [2018-01-28 22:34:53,838 INFO L78 Accepts]: Start accepts. Automaton has 240 states and 256 transitions. Word has length 47 [2018-01-28 22:34:53,839 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:53,839 INFO L432 AbstractCegarLoop]: Abstraction has 240 states and 256 transitions. [2018-01-28 22:34:53,839 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-28 22:34:53,839 INFO L276 IsEmpty]: Start isEmpty. Operand 240 states and 256 transitions. [2018-01-28 22:34:53,840 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-01-28 22:34:53,840 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:53,840 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:53,840 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:53,840 INFO L82 PathProgramCache]: Analyzing trace with hash 1867931960, now seen corresponding path program 1 times [2018-01-28 22:34:53,840 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:53,840 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:53,841 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:53,841 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:53,842 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:53,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:53,852 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:53,940 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-01-28 22:34:53,940 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:34:53,941 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-28 22:34:53,941 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-28 22:34:53,941 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-28 22:34:53,941 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-28 22:34:53,941 INFO L87 Difference]: Start difference. First operand 240 states and 256 transitions. Second operand 7 states. [2018-01-28 22:34:54,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:54,147 INFO L93 Difference]: Finished difference Result 242 states and 258 transitions. [2018-01-28 22:34:54,147 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-28 22:34:54,147 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 48 [2018-01-28 22:34:54,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:54,148 INFO L225 Difference]: With dead ends: 242 [2018-01-28 22:34:54,149 INFO L226 Difference]: Without dead ends: 241 [2018-01-28 22:34:54,149 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-01-28 22:34:54,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 241 states. [2018-01-28 22:34:54,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 241 to 239. [2018-01-28 22:34:54,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 239 states. [2018-01-28 22:34:54,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 239 states to 239 states and 255 transitions. [2018-01-28 22:34:54,164 INFO L78 Accepts]: Start accepts. Automaton has 239 states and 255 transitions. Word has length 48 [2018-01-28 22:34:54,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:54,165 INFO L432 AbstractCegarLoop]: Abstraction has 239 states and 255 transitions. [2018-01-28 22:34:54,165 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-28 22:34:54,165 INFO L276 IsEmpty]: Start isEmpty. Operand 239 states and 255 transitions. [2018-01-28 22:34:54,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-01-28 22:34:54,166 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:54,166 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:54,166 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:54,166 INFO L82 PathProgramCache]: Analyzing trace with hash 1867931961, now seen corresponding path program 1 times [2018-01-28 22:34:54,166 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:54,166 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:54,167 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:54,167 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:54,167 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:54,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:54,177 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:54,343 WARN L146 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 19 DAG size of output 17 [2018-01-28 22:34:54,659 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-28 22:34:54,659 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:34:54,660 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-01-28 22:34:54,660 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-28 22:34:54,660 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-28 22:34:54,660 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-01-28 22:34:54,660 INFO L87 Difference]: Start difference. First operand 239 states and 255 transitions. Second operand 8 states. [2018-01-28 22:34:54,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:54,933 INFO L93 Difference]: Finished difference Result 244 states and 260 transitions. [2018-01-28 22:34:54,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-28 22:34:54,933 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 48 [2018-01-28 22:34:54,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:54,935 INFO L225 Difference]: With dead ends: 244 [2018-01-28 22:34:54,935 INFO L226 Difference]: Without dead ends: 243 [2018-01-28 22:34:54,935 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=31, Invalid=101, Unknown=0, NotChecked=0, Total=132 [2018-01-28 22:34:54,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 243 states. [2018-01-28 22:34:54,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 243 to 238. [2018-01-28 22:34:54,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-01-28 22:34:54,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 254 transitions. [2018-01-28 22:34:54,954 INFO L78 Accepts]: Start accepts. Automaton has 238 states and 254 transitions. Word has length 48 [2018-01-28 22:34:54,954 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:54,954 INFO L432 AbstractCegarLoop]: Abstraction has 238 states and 254 transitions. [2018-01-28 22:34:54,954 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-28 22:34:54,955 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 254 transitions. [2018-01-28 22:34:54,955 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-01-28 22:34:54,955 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:54,955 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:54,955 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:54,956 INFO L82 PathProgramCache]: Analyzing trace with hash -1913073949, now seen corresponding path program 1 times [2018-01-28 22:34:54,956 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:54,956 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:54,957 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:54,957 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:54,957 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:54,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:54,969 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:55,374 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-28 22:34:55,375 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:34:55,375 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:34:55,389 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:55,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:55,411 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:34:55,877 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-28 22:34:55,898 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-28 22:34:55,898 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 12] total 19 [2018-01-28 22:34:55,898 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-28 22:34:55,899 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-28 22:34:55,899 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=329, Unknown=8, NotChecked=0, Total=380 [2018-01-28 22:34:55,899 INFO L87 Difference]: Start difference. First operand 238 states and 254 transitions. Second operand 20 states. [2018-01-28 22:34:56,167 WARN L146 SmtUtils]: Spent 133ms on a formula simplification. DAG size of input: 29 DAG size of output 15 [2018-01-28 22:34:57,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:57,660 INFO L93 Difference]: Finished difference Result 255 states and 271 transitions. [2018-01-28 22:34:57,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-28 22:34:57,677 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 49 [2018-01-28 22:34:57,678 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:57,679 INFO L225 Difference]: With dead ends: 255 [2018-01-28 22:34:57,679 INFO L226 Difference]: Without dead ends: 240 [2018-01-28 22:34:57,679 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 44 SyntacticMatches, 6 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=108, Invalid=754, Unknown=8, NotChecked=0, Total=870 [2018-01-28 22:34:57,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240 states. [2018-01-28 22:34:57,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240 to 230. [2018-01-28 22:34:57,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-01-28 22:34:57,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 245 transitions. [2018-01-28 22:34:57,698 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 245 transitions. Word has length 49 [2018-01-28 22:34:57,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:57,698 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 245 transitions. [2018-01-28 22:34:57,698 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-28 22:34:57,698 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 245 transitions. [2018-01-28 22:34:57,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-01-28 22:34:57,699 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:57,699 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:57,699 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:57,700 INFO L82 PathProgramCache]: Analyzing trace with hash 1362475738, now seen corresponding path program 1 times [2018-01-28 22:34:57,700 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:57,700 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:57,701 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:57,701 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:57,701 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:57,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:57,712 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:57,829 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-01-28 22:34:57,829 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:34:57,829 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-01-28 22:34:57,829 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-28 22:34:57,830 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-28 22:34:57,830 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-28 22:34:57,830 INFO L87 Difference]: Start difference. First operand 230 states and 245 transitions. Second operand 7 states. [2018-01-28 22:34:57,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:34:57,971 INFO L93 Difference]: Finished difference Result 234 states and 248 transitions. [2018-01-28 22:34:57,972 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-28 22:34:57,972 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 50 [2018-01-28 22:34:57,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:34:57,973 INFO L225 Difference]: With dead ends: 234 [2018-01-28 22:34:57,973 INFO L226 Difference]: Without dead ends: 227 [2018-01-28 22:34:57,973 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-01-28 22:34:57,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227 states. [2018-01-28 22:34:57,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227 to 227. [2018-01-28 22:34:57,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227 states. [2018-01-28 22:34:57,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227 states to 227 states and 241 transitions. [2018-01-28 22:34:57,991 INFO L78 Accepts]: Start accepts. Automaton has 227 states and 241 transitions. Word has length 50 [2018-01-28 22:34:57,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:34:57,992 INFO L432 AbstractCegarLoop]: Abstraction has 227 states and 241 transitions. [2018-01-28 22:34:57,992 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-28 22:34:57,992 INFO L276 IsEmpty]: Start isEmpty. Operand 227 states and 241 transitions. [2018-01-28 22:34:57,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-01-28 22:34:57,993 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:34:57,993 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:34:57,993 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:34:57,993 INFO L82 PathProgramCache]: Analyzing trace with hash 1964816830, now seen corresponding path program 1 times [2018-01-28 22:34:57,993 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:34:57,993 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:34:57,994 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:57,995 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:57,995 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:34:58,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:58,015 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:34:58,359 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 17 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-01-28 22:34:58,359 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:34:58,359 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:34:58,364 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:34:58,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:34:58,388 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:34:58,403 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-01-28 22:34:58,404 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:58,420 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2018-01-28 22:34:58,421 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:58,434 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-01-28 22:34:58,435 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:58,436 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-01-28 22:34:58,436 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:58,448 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-01-28 22:34:58,448 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:50, output treesize:46 [2018-01-28 22:34:58,615 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:58,616 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:58,616 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 44 [2018-01-28 22:34:58,617 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:58,640 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:58,642 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 41 [2018-01-28 22:34:58,642 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:58,667 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:58,667 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 47 [2018-01-28 22:34:58,668 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:58,692 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:58,692 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:58,693 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 41 [2018-01-28 22:34:58,693 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:58,716 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 4 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-28 22:34:58,716 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 6 variables, input treesize:79, output treesize:69 [2018-01-28 22:34:58,923 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:58,924 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:58,924 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:58,925 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:58,926 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 50 [2018-01-28 22:34:58,926 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:58,999 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,000 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,002 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,003 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 5 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 67 [2018-01-28 22:34:59,003 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:59,098 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,099 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,100 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,100 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,101 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 48 [2018-01-28 22:34:59,101 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:59,167 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,168 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,169 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,170 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 5 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 63 [2018-01-28 22:34:59,171 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:59,241 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,242 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,242 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,243 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 48 [2018-01-28 22:34:59,243 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:59,309 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,310 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,311 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 5 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 67 [2018-01-28 22:34:59,311 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:59,376 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,377 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,378 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:34:59,378 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 46 [2018-01-28 22:34:59,379 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:59,438 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-01-28 22:34:59,438 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-01-28 22:34:59,493 INFO L267 ElimStorePlain]: Start of recursive call 1: 8 dim-0 vars, 8 dim-1 vars, End of recursive call: 8 dim-0 vars, and 4 xjuncts. [2018-01-28 22:34:59,493 INFO L202 ElimStorePlain]: Needed 9 recursive calls to eliminate 16 variables, input treesize:213, output treesize:165 [2018-01-28 22:35:01,593 WARN L143 SmtUtils]: Spent 2055ms on a formula simplification that was a NOOP. DAG size: 75 [2018-01-28 22:35:01,604 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 49 [2018-01-28 22:35:01,606 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-01-28 22:35:01,606 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:35:01,618 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:35:01,696 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 55 [2018-01-28 22:35:01,698 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-01-28 22:35:01,698 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-28 22:35:01,713 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:35:01,785 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 49 [2018-01-28 22:35:01,787 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-01-28 22:35:01,787 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-01-28 22:35:01,797 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:35:01,860 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 51 [2018-01-28 22:35:01,862 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-01-28 22:35:01,862 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-01-28 22:35:01,873 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:35:01,934 INFO L267 ElimStorePlain]: Start of recursive call 1: 12 dim-0 vars, 4 dim-2 vars, End of recursive call: 8 dim-0 vars, and 4 xjuncts. [2018-01-28 22:35:01,935 INFO L202 ElimStorePlain]: Needed 9 recursive calls to eliminate 16 variables, input treesize:217, output treesize:213 [2018-01-28 22:35:02,095 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 43 [2018-01-28 22:35:02,133 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2018-01-28 22:35:02,133 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:35:02,159 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:35:02,219 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 49 [2018-01-28 22:35:02,221 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 14 [2018-01-28 22:35:02,221 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:35:02,231 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:35:02,287 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 47 [2018-01-28 22:35:02,289 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 12 [2018-01-28 22:35:02,290 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:35:02,299 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:35:02,353 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 57 [2018-01-28 22:35:02,356 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2018-01-28 22:35:02,357 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:35:02,369 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:35:02,426 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 4 dim-2 vars, End of recursive call: 16 dim-0 vars, and 4 xjuncts. [2018-01-28 22:35:02,427 INFO L202 ElimStorePlain]: Needed 9 recursive calls to eliminate 20 variables, input treesize:213, output treesize:165 [2018-01-28 22:35:24,957 WARN L146 SmtUtils]: Spent 18456ms on a formula simplification. DAG size of input: 91 DAG size of output 71 [2018-01-28 22:35:24,991 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 17 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-01-28 22:35:25,011 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-28 22:35:25,011 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 16] total 26 [2018-01-28 22:35:25,011 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-28 22:35:25,011 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-28 22:35:25,012 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=611, Unknown=4, NotChecked=0, Total=702 [2018-01-28 22:35:25,012 INFO L87 Difference]: Start difference. First operand 227 states and 241 transitions. Second operand 27 states. [2018-01-28 22:35:43,713 WARN L146 SmtUtils]: Spent 2104ms on a formula simplification. DAG size of input: 53 DAG size of output 53 [2018-01-28 22:35:46,034 WARN L146 SmtUtils]: Spent 181ms on a formula simplification. DAG size of input: 85 DAG size of output 59 [2018-01-28 22:35:46,518 WARN L146 SmtUtils]: Spent 418ms on a formula simplification. DAG size of input: 114 DAG size of output 104 [2018-01-28 22:35:48,739 WARN L146 SmtUtils]: Spent 2175ms on a formula simplification. DAG size of input: 90 DAG size of output 88 [2018-01-28 22:36:06,116 WARN L146 SmtUtils]: Spent 15249ms on a formula simplification. DAG size of input: 88 DAG size of output 86 [2018-01-28 22:36:21,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:21,361 INFO L93 Difference]: Finished difference Result 261 states and 279 transitions. [2018-01-28 22:36:21,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-28 22:36:21,361 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 51 [2018-01-28 22:36:21,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:21,362 INFO L225 Difference]: With dead ends: 261 [2018-01-28 22:36:21,362 INFO L226 Difference]: Without dead ends: 260 [2018-01-28 22:36:21,363 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 40 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 301 ImplicationChecksByTransitivity, 53.9s TimeCoverageRelationStatistics Valid=191, Invalid=1207, Unknown=8, NotChecked=0, Total=1406 [2018-01-28 22:36:21,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 260 states. [2018-01-28 22:36:21,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 260 to 226. [2018-01-28 22:36:21,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-01-28 22:36:21,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 240 transitions. [2018-01-28 22:36:21,377 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 240 transitions. Word has length 51 [2018-01-28 22:36:21,377 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:21,377 INFO L432 AbstractCegarLoop]: Abstraction has 226 states and 240 transitions. [2018-01-28 22:36:21,377 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-28 22:36:21,377 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 240 transitions. [2018-01-28 22:36:21,378 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-01-28 22:36:21,378 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:21,378 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:21,378 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:21,378 INFO L82 PathProgramCache]: Analyzing trace with hash -1729210922, now seen corresponding path program 1 times [2018-01-28 22:36:21,379 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:21,379 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:21,379 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:21,379 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:21,380 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:21,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:21,389 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:21,445 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-28 22:36:21,445 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:36:21,445 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-28 22:36:21,445 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-28 22:36:21,446 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-28 22:36:21,446 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-28 22:36:21,446 INFO L87 Difference]: Start difference. First operand 226 states and 240 transitions. Second operand 7 states. [2018-01-28 22:36:21,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:21,638 INFO L93 Difference]: Finished difference Result 236 states and 251 transitions. [2018-01-28 22:36:21,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-28 22:36:21,638 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 59 [2018-01-28 22:36:21,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:21,639 INFO L225 Difference]: With dead ends: 236 [2018-01-28 22:36:21,639 INFO L226 Difference]: Without dead ends: 235 [2018-01-28 22:36:21,639 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-01-28 22:36:21,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235 states. [2018-01-28 22:36:21,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235 to 225. [2018-01-28 22:36:21,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 225 states. [2018-01-28 22:36:21,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 239 transitions. [2018-01-28 22:36:21,653 INFO L78 Accepts]: Start accepts. Automaton has 225 states and 239 transitions. Word has length 59 [2018-01-28 22:36:21,653 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:21,653 INFO L432 AbstractCegarLoop]: Abstraction has 225 states and 239 transitions. [2018-01-28 22:36:21,653 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-28 22:36:21,653 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 239 transitions. [2018-01-28 22:36:21,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-01-28 22:36:21,654 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:21,654 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:21,654 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:21,654 INFO L82 PathProgramCache]: Analyzing trace with hash -1729210921, now seen corresponding path program 1 times [2018-01-28 22:36:21,655 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:21,655 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:21,655 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:21,655 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:21,655 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:21,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:21,665 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:21,828 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-01-28 22:36:21,828 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:36:21,829 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:36:21,838 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:21,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:21,867 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:36:21,943 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-28 22:36:21,973 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-01-28 22:36:21,973 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [10] total 15 [2018-01-28 22:36:21,973 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-28 22:36:21,974 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-28 22:36:21,974 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=205, Unknown=0, NotChecked=0, Total=240 [2018-01-28 22:36:21,974 INFO L87 Difference]: Start difference. First operand 225 states and 239 transitions. Second operand 16 states. [2018-01-28 22:36:22,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:22,273 INFO L93 Difference]: Finished difference Result 235 states and 250 transitions. [2018-01-28 22:36:22,273 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-28 22:36:22,273 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 59 [2018-01-28 22:36:22,274 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:22,275 INFO L225 Difference]: With dead ends: 235 [2018-01-28 22:36:22,275 INFO L226 Difference]: Without dead ends: 234 [2018-01-28 22:36:22,275 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 54 SyntacticMatches, 1 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=55, Invalid=325, Unknown=0, NotChecked=0, Total=380 [2018-01-28 22:36:22,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states. [2018-01-28 22:36:22,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 224. [2018-01-28 22:36:22,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 224 states. [2018-01-28 22:36:22,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 238 transitions. [2018-01-28 22:36:22,302 INFO L78 Accepts]: Start accepts. Automaton has 224 states and 238 transitions. Word has length 59 [2018-01-28 22:36:22,302 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:22,302 INFO L432 AbstractCegarLoop]: Abstraction has 224 states and 238 transitions. [2018-01-28 22:36:22,302 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-28 22:36:22,303 INFO L276 IsEmpty]: Start isEmpty. Operand 224 states and 238 transitions. [2018-01-28 22:36:22,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-01-28 22:36:22,303 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:22,303 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:22,304 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:22,304 INFO L82 PathProgramCache]: Analyzing trace with hash 734378521, now seen corresponding path program 1 times [2018-01-28 22:36:22,304 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:22,304 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:22,305 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:22,305 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:22,305 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:22,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:22,330 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:22,886 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 13 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-01-28 22:36:22,886 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:36:22,886 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:36:22,891 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:22,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:22,918 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:36:22,945 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-01-28 22:36:22,946 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-01-28 22:36:22,946 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:22,948 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:22,955 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-01-28 22:36:22,957 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-01-28 22:36:22,957 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:22,958 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:22,963 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:22,964 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:41, output treesize:27 [2018-01-28 22:36:23,087 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 23 [2018-01-28 22:36:23,088 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2018-01-28 22:36:23,089 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:23,090 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:23,094 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2018-01-28 22:36:23,096 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 9 [2018-01-28 22:36:23,096 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:23,098 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:23,101 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:23,101 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:45, output treesize:9 [2018-01-28 22:36:23,170 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-28 22:36:23,189 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-01-28 22:36:23,189 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [23] total 32 [2018-01-28 22:36:23,190 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-28 22:36:23,190 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-28 22:36:23,190 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=973, Unknown=0, NotChecked=0, Total=1056 [2018-01-28 22:36:23,191 INFO L87 Difference]: Start difference. First operand 224 states and 238 transitions. Second operand 33 states. [2018-01-28 22:36:25,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:25,480 INFO L93 Difference]: Finished difference Result 240 states and 258 transitions. [2018-01-28 22:36:25,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-28 22:36:25,480 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 63 [2018-01-28 22:36:25,480 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:25,482 INFO L225 Difference]: With dead ends: 240 [2018-01-28 22:36:25,482 INFO L226 Difference]: Without dead ends: 239 [2018-01-28 22:36:25,482 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 54 SyntacticMatches, 2 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 449 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=237, Invalid=2313, Unknown=0, NotChecked=0, Total=2550 [2018-01-28 22:36:25,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2018-01-28 22:36:25,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 223. [2018-01-28 22:36:25,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 223 states. [2018-01-28 22:36:25,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 237 transitions. [2018-01-28 22:36:25,497 INFO L78 Accepts]: Start accepts. Automaton has 223 states and 237 transitions. Word has length 63 [2018-01-28 22:36:25,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:25,497 INFO L432 AbstractCegarLoop]: Abstraction has 223 states and 237 transitions. [2018-01-28 22:36:25,497 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-28 22:36:25,497 INFO L276 IsEmpty]: Start isEmpty. Operand 223 states and 237 transitions. [2018-01-28 22:36:25,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-01-28 22:36:25,498 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:25,498 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:25,498 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:25,498 INFO L82 PathProgramCache]: Analyzing trace with hash 734378520, now seen corresponding path program 1 times [2018-01-28 22:36:25,498 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:25,498 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:25,499 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:25,499 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:25,499 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:25,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:25,519 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:25,794 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-01-28 22:36:25,794 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:36:25,794 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:36:25,801 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:25,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:25,832 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:36:25,859 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-01-28 22:36:25,863 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-01-28 22:36:25,864 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:25,866 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:25,877 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:25,877 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:19, output treesize:11 [2018-01-28 22:36:26,046 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 17 [2018-01-28 22:36:26,048 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 5 [2018-01-28 22:36:26,049 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:26,051 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:26,052 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:26,052 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:21, output treesize:5 [2018-01-28 22:36:26,087 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-28 22:36:26,125 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-01-28 22:36:26,125 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [14] total 20 [2018-01-28 22:36:26,126 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-28 22:36:26,126 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-28 22:36:26,126 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=373, Unknown=0, NotChecked=0, Total=420 [2018-01-28 22:36:26,127 INFO L87 Difference]: Start difference. First operand 223 states and 237 transitions. Second operand 21 states. [2018-01-28 22:36:26,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:26,726 INFO L93 Difference]: Finished difference Result 225 states and 239 transitions. [2018-01-28 22:36:26,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-28 22:36:26,726 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 63 [2018-01-28 22:36:26,726 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:26,727 INFO L225 Difference]: With dead ends: 225 [2018-01-28 22:36:26,727 INFO L226 Difference]: Without dead ends: 224 [2018-01-28 22:36:26,728 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 56 SyntacticMatches, 3 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 104 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=116, Invalid=814, Unknown=0, NotChecked=0, Total=930 [2018-01-28 22:36:26,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-01-28 22:36:26,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 222. [2018-01-28 22:36:26,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222 states. [2018-01-28 22:36:26,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 236 transitions. [2018-01-28 22:36:26,752 INFO L78 Accepts]: Start accepts. Automaton has 222 states and 236 transitions. Word has length 63 [2018-01-28 22:36:26,752 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:26,752 INFO L432 AbstractCegarLoop]: Abstraction has 222 states and 236 transitions. [2018-01-28 22:36:26,752 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-28 22:36:26,752 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 236 transitions. [2018-01-28 22:36:26,753 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-01-28 22:36:26,753 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:26,753 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:26,753 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:26,754 INFO L82 PathProgramCache]: Analyzing trace with hash 1290897787, now seen corresponding path program 1 times [2018-01-28 22:36:26,754 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:26,754 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:26,755 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:26,755 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:26,755 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:26,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:26,780 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:27,660 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 10 proven. 6 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-01-28 22:36:27,660 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:36:27,660 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:36:27,666 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:27,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:27,702 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:36:27,705 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-28 22:36:27,705 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:27,714 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:27,714 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-28 22:36:27,915 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:36:27,916 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:36:27,916 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-01-28 22:36:27,917 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:27,920 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:27,921 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:15 [2018-01-28 22:36:27,977 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:36:27,978 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:36:27,979 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:36:27,980 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 34 [2018-01-28 22:36:27,980 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:27,994 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:27,994 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:26, output treesize:28 [2018-01-28 22:36:28,039 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-01-28 22:36:28,041 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-01-28 22:36:28,042 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:28,043 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:28,052 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:28,053 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:41, output treesize:46 [2018-01-28 22:36:28,153 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 63 [2018-01-28 22:36:28,155 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 1 [2018-01-28 22:36:28,156 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:28,160 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:28,167 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:28,168 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:83, output treesize:46 [2018-01-28 22:36:28,174 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-01-28 22:36:28,176 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-01-28 22:36:28,176 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:28,178 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:28,196 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 46 [2018-01-28 22:36:28,198 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-01-28 22:36:28,199 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:28,206 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:28,219 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:28,219 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:74, output treesize:100 [2018-01-28 22:36:28,486 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 75 [2018-01-28 22:36:28,488 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 75 treesize of output 56 [2018-01-28 22:36:28,488 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:28,492 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:28,501 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-28 22:36:28,501 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:118, output treesize:91 [2018-01-28 22:36:28,686 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 61 [2018-01-28 22:36:28,692 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 18 [2018-01-28 22:36:28,692 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:36:28,717 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 14 [2018-01-28 22:36:28,718 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:28,725 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:36:28,733 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-28 22:36:28,733 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:97, output treesize:28 [2018-01-28 22:36:28,792 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-01-28 22:36:28,813 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-01-28 22:36:28,813 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [22] imperfect sequences [23] total 43 [2018-01-28 22:36:28,814 INFO L409 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-01-28 22:36:28,814 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-01-28 22:36:28,815 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=1781, Unknown=0, NotChecked=0, Total=1892 [2018-01-28 22:36:28,815 INFO L87 Difference]: Start difference. First operand 222 states and 236 transitions. Second operand 44 states. [2018-01-28 22:36:31,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:31,837 INFO L93 Difference]: Finished difference Result 241 states and 259 transitions. [2018-01-28 22:36:31,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-28 22:36:31,837 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 64 [2018-01-28 22:36:31,837 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:31,838 INFO L225 Difference]: With dead ends: 241 [2018-01-28 22:36:31,838 INFO L226 Difference]: Without dead ends: 240 [2018-01-28 22:36:31,839 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 110 GetRequests, 45 SyntacticMatches, 3 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 534 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=309, Invalid=3723, Unknown=0, NotChecked=0, Total=4032 [2018-01-28 22:36:31,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240 states. [2018-01-28 22:36:31,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240 to 221. [2018-01-28 22:36:31,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221 states. [2018-01-28 22:36:31,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 235 transitions. [2018-01-28 22:36:31,863 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 235 transitions. Word has length 64 [2018-01-28 22:36:31,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:31,863 INFO L432 AbstractCegarLoop]: Abstraction has 221 states and 235 transitions. [2018-01-28 22:36:31,863 INFO L433 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-01-28 22:36:31,864 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 235 transitions. [2018-01-28 22:36:31,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-01-28 22:36:31,864 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:31,864 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:31,865 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:31,865 INFO L82 PathProgramCache]: Analyzing trace with hash 1290897788, now seen corresponding path program 1 times [2018-01-28 22:36:31,865 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:31,865 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:31,866 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:31,866 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:31,866 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:31,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:31,892 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:32,722 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 13 proven. 6 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-01-28 22:36:32,722 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:36:32,722 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:36:32,727 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:32,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:32,759 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:36:32,761 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-28 22:36:32,761 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:32,762 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:32,762 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-28 22:36:32,905 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:36:32,906 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:36:32,906 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-01-28 22:36:32,907 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:32,911 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:32,911 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:15 [2018-01-28 22:36:32,971 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-01-28 22:36:32,971 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:32,987 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-01-28 22:36:32,987 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,001 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-28 22:36:33,002 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:48, output treesize:46 [2018-01-28 22:36:33,126 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:36:33,127 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:36:33,127 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:36:33,128 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 28 [2018-01-28 22:36:33,128 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,148 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:36:33,148 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:36:33,149 INFO L700 Elim1Store]: detected not equals via solver [2018-01-28 22:36:33,149 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 30 [2018-01-28 22:36:33,150 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,169 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-28 22:36:33,169 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:73, output treesize:59 [2018-01-28 22:36:33,239 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 48 [2018-01-28 22:36:33,242 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-01-28 22:36:33,242 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,252 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,283 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 50 [2018-01-28 22:36:33,286 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-01-28 22:36:33,286 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,295 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,322 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 46 [2018-01-28 22:36:33,324 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-01-28 22:36:33,324 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,333 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,358 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 44 [2018-01-28 22:36:33,360 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-01-28 22:36:33,360 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,369 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,392 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-2 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-28 22:36:33,393 INFO L202 ElimStorePlain]: Needed 9 recursive calls to eliminate 8 variables, input treesize:105, output treesize:107 [2018-01-28 22:36:33,574 WARN L307 Elim1Store]: Array PQE input equivalent to false [2018-01-28 22:36:33,574 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,597 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 121 treesize of output 115 [2018-01-28 22:36:33,600 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 1 [2018-01-28 22:36:33,600 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,608 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,626 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 57 [2018-01-28 22:36:33,628 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 1 [2018-01-28 22:36:33,629 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,633 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,655 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 4 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:36:33,655 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 7 variables, input treesize:299, output treesize:71 [2018-01-28 22:36:33,720 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 45 [2018-01-28 22:36:33,722 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-01-28 22:36:33,723 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,728 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,746 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 67 [2018-01-28 22:36:33,748 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-01-28 22:36:33,748 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,759 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:33,774 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:36:33,774 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:99, output treesize:155 [2018-01-28 22:36:34,406 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 192 treesize of output 149 [2018-01-28 22:36:34,408 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 98 treesize of output 78 [2018-01-28 22:36:34,426 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:36:34,439 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 88 treesize of output 35 [2018-01-28 22:36:34,439 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:34,448 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:36:34,461 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 42 [2018-01-28 22:36:34,462 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 26 [2018-01-28 22:36:34,463 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:36:34,469 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 11 [2018-01-28 22:36:34,469 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-01-28 22:36:34,472 INFO L267 ElimStorePlain]: Start of recursive call 5: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-28 22:36:34,480 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-28 22:36:34,480 INFO L202 ElimStorePlain]: Needed 7 recursive calls to eliminate 5 variables, input treesize:197, output treesize:23 [2018-01-28 22:36:34,556 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 13 proven. 6 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-01-28 22:36:34,576 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-28 22:36:34,576 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 48 [2018-01-28 22:36:34,576 INFO L409 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-01-28 22:36:34,576 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-01-28 22:36:34,577 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=2234, Unknown=0, NotChecked=0, Total=2352 [2018-01-28 22:36:34,577 INFO L87 Difference]: Start difference. First operand 221 states and 235 transitions. Second operand 49 states. [2018-01-28 22:36:35,351 WARN L146 SmtUtils]: Spent 114ms on a formula simplification. DAG size of input: 73 DAG size of output 67 [2018-01-28 22:36:36,688 WARN L146 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 96 DAG size of output 83 [2018-01-28 22:36:36,916 WARN L146 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 102 DAG size of output 89 [2018-01-28 22:36:37,090 WARN L146 SmtUtils]: Spent 105ms on a formula simplification. DAG size of input: 96 DAG size of output 83 [2018-01-28 22:36:37,313 WARN L146 SmtUtils]: Spent 128ms on a formula simplification. DAG size of input: 103 DAG size of output 90 [2018-01-28 22:36:37,573 WARN L146 SmtUtils]: Spent 157ms on a formula simplification. DAG size of input: 112 DAG size of output 104 [2018-01-28 22:36:39,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:39,093 INFO L93 Difference]: Finished difference Result 240 states and 258 transitions. [2018-01-28 22:36:39,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-28 22:36:39,093 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 64 [2018-01-28 22:36:39,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:39,094 INFO L225 Difference]: With dead ends: 240 [2018-01-28 22:36:39,094 INFO L226 Difference]: Without dead ends: 239 [2018-01-28 22:36:39,095 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 42 SyntacticMatches, 2 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 858 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=349, Invalid=4621, Unknown=0, NotChecked=0, Total=4970 [2018-01-28 22:36:39,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2018-01-28 22:36:39,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 220. [2018-01-28 22:36:39,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-01-28 22:36:39,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 234 transitions. [2018-01-28 22:36:39,119 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 234 transitions. Word has length 64 [2018-01-28 22:36:39,119 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:39,120 INFO L432 AbstractCegarLoop]: Abstraction has 220 states and 234 transitions. [2018-01-28 22:36:39,120 INFO L433 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-01-28 22:36:39,120 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 234 transitions. [2018-01-28 22:36:39,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-01-28 22:36:39,121 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:39,121 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:39,121 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:39,121 INFO L82 PathProgramCache]: Analyzing trace with hash -365207090, now seen corresponding path program 1 times [2018-01-28 22:36:39,121 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:39,121 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:39,122 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:39,122 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:39,123 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:39,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:39,137 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:39,247 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-28 22:36:39,248 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:36:39,248 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-28 22:36:39,248 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-28 22:36:39,248 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-28 22:36:39,248 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-28 22:36:39,248 INFO L87 Difference]: Start difference. First operand 220 states and 234 transitions. Second operand 7 states. [2018-01-28 22:36:39,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:39,456 INFO L93 Difference]: Finished difference Result 234 states and 247 transitions. [2018-01-28 22:36:39,600 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-28 22:36:39,600 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 74 [2018-01-28 22:36:39,601 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:39,601 INFO L225 Difference]: With dead ends: 234 [2018-01-28 22:36:39,601 INFO L226 Difference]: Without dead ends: 233 [2018-01-28 22:36:39,602 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-01-28 22:36:39,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2018-01-28 22:36:39,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 230. [2018-01-28 22:36:39,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-01-28 22:36:39,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 244 transitions. [2018-01-28 22:36:39,626 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 244 transitions. Word has length 74 [2018-01-28 22:36:39,627 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:39,627 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 244 transitions. [2018-01-28 22:36:39,627 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-28 22:36:39,627 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 244 transitions. [2018-01-28 22:36:39,628 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-01-28 22:36:39,628 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:39,628 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:39,628 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:39,628 INFO L82 PathProgramCache]: Analyzing trace with hash -365207089, now seen corresponding path program 1 times [2018-01-28 22:36:39,628 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:39,628 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:39,629 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:39,629 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:39,630 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:39,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:39,644 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:39,823 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-01-28 22:36:39,823 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:36:39,823 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:36:39,829 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:39,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:39,866 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:36:40,186 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-01-28 22:36:40,208 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-28 22:36:40,208 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 18 [2018-01-28 22:36:40,208 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-28 22:36:40,208 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-28 22:36:40,208 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=302, Unknown=0, NotChecked=0, Total=342 [2018-01-28 22:36:40,209 INFO L87 Difference]: Start difference. First operand 230 states and 244 transitions. Second operand 19 states. [2018-01-28 22:36:40,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:40,599 INFO L93 Difference]: Finished difference Result 241 states and 255 transitions. [2018-01-28 22:36:40,599 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-28 22:36:40,600 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 74 [2018-01-28 22:36:40,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:40,601 INFO L225 Difference]: With dead ends: 241 [2018-01-28 22:36:40,601 INFO L226 Difference]: Without dead ends: 240 [2018-01-28 22:36:40,601 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 65 SyntacticMatches, 5 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 93 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=85, Invalid=671, Unknown=0, NotChecked=0, Total=756 [2018-01-28 22:36:40,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240 states. [2018-01-28 22:36:40,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240 to 230. [2018-01-28 22:36:40,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-01-28 22:36:40,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 243 transitions. [2018-01-28 22:36:40,626 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 243 transitions. Word has length 74 [2018-01-28 22:36:40,626 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:40,627 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 243 transitions. [2018-01-28 22:36:40,627 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-28 22:36:40,627 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 243 transitions. [2018-01-28 22:36:40,627 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-01-28 22:36:40,627 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:40,628 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:40,628 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:40,628 INFO L82 PathProgramCache]: Analyzing trace with hash 631651345, now seen corresponding path program 1 times [2018-01-28 22:36:40,628 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:40,628 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:40,629 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:40,629 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:40,629 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:40,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:40,644 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:40,725 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-28 22:36:40,726 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:36:40,726 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-01-28 22:36:40,726 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-28 22:36:40,726 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-28 22:36:40,726 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-01-28 22:36:40,727 INFO L87 Difference]: Start difference. First operand 230 states and 243 transitions. Second operand 8 states. [2018-01-28 22:36:40,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:40,995 INFO L93 Difference]: Finished difference Result 232 states and 245 transitions. [2018-01-28 22:36:40,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-28 22:36:40,995 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 85 [2018-01-28 22:36:40,995 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:40,996 INFO L225 Difference]: With dead ends: 232 [2018-01-28 22:36:40,997 INFO L226 Difference]: Without dead ends: 228 [2018-01-28 22:36:40,997 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-01-28 22:36:40,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states. [2018-01-28 22:36:41,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 226. [2018-01-28 22:36:41,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-01-28 22:36:41,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 239 transitions. [2018-01-28 22:36:41,023 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 239 transitions. Word has length 85 [2018-01-28 22:36:41,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:41,023 INFO L432 AbstractCegarLoop]: Abstraction has 226 states and 239 transitions. [2018-01-28 22:36:41,023 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-28 22:36:41,023 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 239 transitions. [2018-01-28 22:36:41,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-01-28 22:36:41,024 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:41,024 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:41,024 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:41,025 INFO L82 PathProgramCache]: Analyzing trace with hash 631651346, now seen corresponding path program 1 times [2018-01-28 22:36:41,025 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:41,025 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:41,026 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:41,026 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:41,026 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:41,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:41,044 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:41,406 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-28 22:36:41,406 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:36:41,407 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-01-28 22:36:41,407 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-28 22:36:41,407 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-28 22:36:41,407 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2018-01-28 22:36:41,407 INFO L87 Difference]: Start difference. First operand 226 states and 239 transitions. Second operand 10 states. [2018-01-28 22:36:41,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:41,810 INFO L93 Difference]: Finished difference Result 228 states and 241 transitions. [2018-01-28 22:36:41,810 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-28 22:36:41,810 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 85 [2018-01-28 22:36:41,811 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:41,812 INFO L225 Difference]: With dead ends: 228 [2018-01-28 22:36:41,812 INFO L226 Difference]: Without dead ends: 224 [2018-01-28 22:36:41,813 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=38, Invalid=144, Unknown=0, NotChecked=0, Total=182 [2018-01-28 22:36:41,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-01-28 22:36:41,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 222. [2018-01-28 22:36:41,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222 states. [2018-01-28 22:36:41,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 235 transitions. [2018-01-28 22:36:41,828 INFO L78 Accepts]: Start accepts. Automaton has 222 states and 235 transitions. Word has length 85 [2018-01-28 22:36:41,828 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:41,829 INFO L432 AbstractCegarLoop]: Abstraction has 222 states and 235 transitions. [2018-01-28 22:36:41,829 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-28 22:36:41,829 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 235 transitions. [2018-01-28 22:36:41,829 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-01-28 22:36:41,829 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:41,830 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:41,830 INFO L371 AbstractCegarLoop]: === Iteration 30 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:41,830 INFO L82 PathProgramCache]: Analyzing trace with hash -1875330636, now seen corresponding path program 1 times [2018-01-28 22:36:41,830 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:41,830 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:41,831 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:41,831 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:41,831 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:41,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:41,841 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:41,905 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-28 22:36:41,905 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:36:41,905 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-28 22:36:41,906 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-28 22:36:41,906 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-28 22:36:41,906 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-28 22:36:41,906 INFO L87 Difference]: Start difference. First operand 222 states and 235 transitions. Second operand 5 states. [2018-01-28 22:36:42,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:42,017 INFO L93 Difference]: Finished difference Result 304 states and 319 transitions. [2018-01-28 22:36:42,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-28 22:36:42,018 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 93 [2018-01-28 22:36:42,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:42,020 INFO L225 Difference]: With dead ends: 304 [2018-01-28 22:36:42,020 INFO L226 Difference]: Without dead ends: 232 [2018-01-28 22:36:42,020 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-28 22:36:42,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232 states. [2018-01-28 22:36:42,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232 to 228. [2018-01-28 22:36:42,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-01-28 22:36:42,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 241 transitions. [2018-01-28 22:36:42,035 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 241 transitions. Word has length 93 [2018-01-28 22:36:42,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:42,036 INFO L432 AbstractCegarLoop]: Abstraction has 228 states and 241 transitions. [2018-01-28 22:36:42,036 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-28 22:36:42,036 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 241 transitions. [2018-01-28 22:36:42,036 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-01-28 22:36:42,036 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:42,037 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:42,037 INFO L371 AbstractCegarLoop]: === Iteration 31 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:42,037 INFO L82 PathProgramCache]: Analyzing trace with hash 1356884695, now seen corresponding path program 1 times [2018-01-28 22:36:42,037 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:42,037 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:42,038 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:42,038 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:42,038 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:42,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:42,047 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:42,069 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-28 22:36:42,069 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:36:42,069 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-28 22:36:42,070 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-28 22:36:42,070 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-28 22:36:42,070 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-28 22:36:42,070 INFO L87 Difference]: Start difference. First operand 228 states and 241 transitions. Second operand 4 states. [2018-01-28 22:36:42,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:42,134 INFO L93 Difference]: Finished difference Result 253 states and 267 transitions. [2018-01-28 22:36:42,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-28 22:36:42,134 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 93 [2018-01-28 22:36:42,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:42,135 INFO L225 Difference]: With dead ends: 253 [2018-01-28 22:36:42,135 INFO L226 Difference]: Without dead ends: 236 [2018-01-28 22:36:42,136 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-28 22:36:42,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-01-28 22:36:42,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 236. [2018-01-28 22:36:42,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236 states. [2018-01-28 22:36:42,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236 states to 236 states and 249 transitions. [2018-01-28 22:36:42,150 INFO L78 Accepts]: Start accepts. Automaton has 236 states and 249 transitions. Word has length 93 [2018-01-28 22:36:42,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:42,150 INFO L432 AbstractCegarLoop]: Abstraction has 236 states and 249 transitions. [2018-01-28 22:36:42,150 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-28 22:36:42,151 INFO L276 IsEmpty]: Start isEmpty. Operand 236 states and 249 transitions. [2018-01-28 22:36:42,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-01-28 22:36:42,151 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:42,151 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:42,151 INFO L371 AbstractCegarLoop]: === Iteration 32 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:42,151 INFO L82 PathProgramCache]: Analyzing trace with hash -516165598, now seen corresponding path program 1 times [2018-01-28 22:36:42,152 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:42,152 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:42,152 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:42,152 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:42,153 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:42,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:42,163 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:42,313 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-28 22:36:42,313 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:36:42,313 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-01-28 22:36:42,313 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-28 22:36:42,314 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-28 22:36:42,314 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-01-28 22:36:42,314 INFO L87 Difference]: Start difference. First operand 236 states and 249 transitions. Second operand 8 states. [2018-01-28 22:36:43,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:43,053 INFO L93 Difference]: Finished difference Result 284 states and 301 transitions. [2018-01-28 22:36:43,053 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-28 22:36:43,053 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 96 [2018-01-28 22:36:43,053 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:43,055 INFO L225 Difference]: With dead ends: 284 [2018-01-28 22:36:43,055 INFO L226 Difference]: Without dead ends: 283 [2018-01-28 22:36:43,055 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=38, Invalid=118, Unknown=0, NotChecked=0, Total=156 [2018-01-28 22:36:43,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 283 states. [2018-01-28 22:36:43,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 283 to 266. [2018-01-28 22:36:43,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 266 states. [2018-01-28 22:36:43,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 266 states to 266 states and 287 transitions. [2018-01-28 22:36:43,078 INFO L78 Accepts]: Start accepts. Automaton has 266 states and 287 transitions. Word has length 96 [2018-01-28 22:36:43,078 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:43,078 INFO L432 AbstractCegarLoop]: Abstraction has 266 states and 287 transitions. [2018-01-28 22:36:43,078 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-28 22:36:43,078 INFO L276 IsEmpty]: Start isEmpty. Operand 266 states and 287 transitions. [2018-01-28 22:36:43,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-01-28 22:36:43,079 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:43,079 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:43,079 INFO L371 AbstractCegarLoop]: === Iteration 33 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:43,079 INFO L82 PathProgramCache]: Analyzing trace with hash -516165597, now seen corresponding path program 1 times [2018-01-28 22:36:43,079 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:43,079 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:43,080 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:43,080 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:43,080 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:43,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:43,091 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:43,413 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-01-28 22:36:43,413 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:36:43,414 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:36:43,419 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:43,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:43,458 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:36:43,651 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-28 22:36:43,684 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-01-28 22:36:43,684 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [17] total 23 [2018-01-28 22:36:43,685 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-28 22:36:43,685 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-28 22:36:43,685 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=499, Unknown=0, NotChecked=0, Total=552 [2018-01-28 22:36:43,685 INFO L87 Difference]: Start difference. First operand 266 states and 287 transitions. Second operand 24 states. [2018-01-28 22:36:44,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:44,692 INFO L93 Difference]: Finished difference Result 296 states and 311 transitions. [2018-01-28 22:36:44,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-28 22:36:44,693 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 96 [2018-01-28 22:36:44,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:44,694 INFO L225 Difference]: With dead ends: 296 [2018-01-28 22:36:44,694 INFO L226 Difference]: Without dead ends: 295 [2018-01-28 22:36:44,694 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 128 GetRequests, 93 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 146 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=121, Invalid=1211, Unknown=0, NotChecked=0, Total=1332 [2018-01-28 22:36:44,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 295 states. [2018-01-28 22:36:44,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 295 to 276. [2018-01-28 22:36:44,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 276 states. [2018-01-28 22:36:44,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 276 states to 276 states and 297 transitions. [2018-01-28 22:36:44,715 INFO L78 Accepts]: Start accepts. Automaton has 276 states and 297 transitions. Word has length 96 [2018-01-28 22:36:44,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:44,716 INFO L432 AbstractCegarLoop]: Abstraction has 276 states and 297 transitions. [2018-01-28 22:36:44,716 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-28 22:36:44,716 INFO L276 IsEmpty]: Start isEmpty. Operand 276 states and 297 transitions. [2018-01-28 22:36:44,716 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-01-28 22:36:44,717 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:44,717 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:44,717 INFO L371 AbstractCegarLoop]: === Iteration 34 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:44,717 INFO L82 PathProgramCache]: Analyzing trace with hash -836007155, now seen corresponding path program 1 times [2018-01-28 22:36:44,717 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:44,717 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:44,718 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:44,718 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:44,718 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:44,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:44,732 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:44,803 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-28 22:36:44,804 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 22:36:44,804 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-28 22:36:44,804 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-28 22:36:44,804 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-28 22:36:44,804 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-28 22:36:44,804 INFO L87 Difference]: Start difference. First operand 276 states and 297 transitions. Second operand 6 states. [2018-01-28 22:36:44,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 22:36:44,851 INFO L93 Difference]: Finished difference Result 347 states and 368 transitions. [2018-01-28 22:36:44,851 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-28 22:36:44,851 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 96 [2018-01-28 22:36:44,852 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 22:36:44,853 INFO L225 Difference]: With dead ends: 347 [2018-01-28 22:36:44,853 INFO L226 Difference]: Without dead ends: 263 [2018-01-28 22:36:44,854 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-01-28 22:36:44,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 263 states. [2018-01-28 22:36:44,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 263 to 263. [2018-01-28 22:36:44,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 263 states. [2018-01-28 22:36:44,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 263 states to 263 states and 281 transitions. [2018-01-28 22:36:44,879 INFO L78 Accepts]: Start accepts. Automaton has 263 states and 281 transitions. Word has length 96 [2018-01-28 22:36:44,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 22:36:44,880 INFO L432 AbstractCegarLoop]: Abstraction has 263 states and 281 transitions. [2018-01-28 22:36:44,880 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-28 22:36:44,880 INFO L276 IsEmpty]: Start isEmpty. Operand 263 states and 281 transitions. [2018-01-28 22:36:44,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-01-28 22:36:44,881 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 22:36:44,881 INFO L330 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 22:36:44,881 INFO L371 AbstractCegarLoop]: === Iteration 35 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-01-28 22:36:44,881 INFO L82 PathProgramCache]: Analyzing trace with hash 1869637385, now seen corresponding path program 1 times [2018-01-28 22:36:44,881 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 22:36:44,881 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 22:36:44,882 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:44,882 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 22:36:44,882 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 22:36:44,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:44,921 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 22:36:45,864 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-01-28 22:36:45,864 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-28 22:36:45,864 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-28 22:36:45,872 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY Received shutdown request... [2018-01-28 22:36:45,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 22:36:45,918 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-28 22:36:45,920 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-01-28 22:36:45,920 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-28 22:36:45,926 WARN L185 ceAbstractionStarter]: Timeout [2018-01-28 22:36:45,926 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.01 10:36:45 BoogieIcfgContainer [2018-01-28 22:36:45,927 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-28 22:36:45,927 INFO L168 Benchmark]: Toolchain (without parser) took 136026.06 ms. Allocated memory was 300.9 MB in the beginning and 648.5 MB in the end (delta: 347.6 MB). Free memory was 260.0 MB in the beginning and 331.2 MB in the end (delta: -71.2 MB). Peak memory consumption was 276.4 MB. Max. memory is 5.3 GB. [2018-01-28 22:36:45,929 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 300.9 MB. Free memory is still 267.0 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-28 22:36:45,929 INFO L168 Benchmark]: CACSL2BoogieTranslator took 236.26 ms. Allocated memory is still 300.9 MB. Free memory was 260.0 MB in the beginning and 244.8 MB in the end (delta: 15.2 MB). Peak memory consumption was 15.2 MB. Max. memory is 5.3 GB. [2018-01-28 22:36:45,929 INFO L168 Benchmark]: Boogie Preprocessor took 41.27 ms. Allocated memory is still 300.9 MB. Free memory was 244.8 MB in the beginning and 242.8 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-28 22:36:45,930 INFO L168 Benchmark]: RCFGBuilder took 609.89 ms. Allocated memory is still 300.9 MB. Free memory was 242.8 MB in the beginning and 196.7 MB in the end (delta: 46.1 MB). Peak memory consumption was 46.1 MB. Max. memory is 5.3 GB. [2018-01-28 22:36:45,930 INFO L168 Benchmark]: TraceAbstraction took 135131.55 ms. Allocated memory was 300.9 MB in the beginning and 648.5 MB in the end (delta: 347.6 MB). Free memory was 195.7 MB in the beginning and 331.2 MB in the end (delta: -135.5 MB). Peak memory consumption was 212.1 MB. Max. memory is 5.3 GB. [2018-01-28 22:36:45,932 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 300.9 MB. Free memory is still 267.0 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 236.26 ms. Allocated memory is still 300.9 MB. Free memory was 260.0 MB in the beginning and 244.8 MB in the end (delta: 15.2 MB). Peak memory consumption was 15.2 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 41.27 ms. Allocated memory is still 300.9 MB. Free memory was 244.8 MB in the beginning and 242.8 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 609.89 ms. Allocated memory is still 300.9 MB. Free memory was 242.8 MB in the beginning and 196.7 MB in the end (delta: 46.1 MB). Peak memory consumption was 46.1 MB. Max. memory is 5.3 GB. * TraceAbstraction took 135131.55 ms. Allocated memory was 300.9 MB in the beginning and 648.5 MB in the end (delta: 347.6 MB). Free memory was 195.7 MB in the beginning and 331.2 MB in the end (delta: -135.5 MB). Peak memory consumption was 212.1 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1463). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1479). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1463). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1479). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1533]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 1533). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1526). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1513). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1513). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1524). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1524). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1514). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1528). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1524). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1526). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1528). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1514). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1524). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1454). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1455). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1456). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1456). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1454). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1455). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1484). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1484). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1490). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1490). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 3, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 1 xjuncts. - StatisticsResult: Ultimate Automizer benchmark data CFG has 17 procedures, 225 locations, 45 error locations. TIMEOUT Result, 135.0s OverallTime, 35 OverallIterations, 3 TraceHistogramMax, 91.6s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 6707 SDtfs, 4030 SDslu, 38712 SDs, 0 SdLazy, 29917 SolverSat, 624 SolverUnsat, 59 SolverUnknown, 0 SolverNotchecked, 52.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1484 GetRequests, 864 SyntacticMatches, 47 SemanticMatches, 573 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2833 ImplicationChecksByTransitivity, 70.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=276occurred in iteration=33, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.6s AutomataMinimizationTime, 34 MinimizatonAttempts, 519 StatesRemovedByMinimization, 28 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.7s SatisfiabilityAnalysisTime, 39.8s InterpolantComputationTime, 2861 NumberOfCodeBlocks, 2861 NumberOfCodeBlocksAsserted, 54 NumberOfCheckSat, 2808 ConstructedInterpolants, 69 QuantifiedInterpolants, 1226412 SizeOfPredicates, 179 NumberOfNonLiveVariables, 3457 ConjunctsInSsa, 580 ConjunctsInUnsatCore, 53 InterpolantComputations, 21 PerfectInterpolantSequences, 831/992 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test15_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-28_22-36-45-942.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test15_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-28_22-36-45-942.csv Completed graceful shutdown