java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/array-memsafety/cstrcat-alloca_true-valid-memsafety_true-termination.i
--------------------------------------------------------------------------------
This is Ultimate 0.1.23-acfac67
[2018-01-28 23:20:21,191 INFO L170 SettingsManager]: Resetting all preferences to default values...
[2018-01-28 23:20:21,193 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values
[2018-01-28 23:20:21,205 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring...
[2018-01-28 23:20:21,205 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values
[2018-01-28 23:20:21,206 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values
[2018-01-28 23:20:21,207 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values
[2018-01-28 23:20:21,209 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values
[2018-01-28 23:20:21,211 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values
[2018-01-28 23:20:21,212 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values
[2018-01-28 23:20:21,212 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring...
[2018-01-28 23:20:21,212 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values
[2018-01-28 23:20:21,213 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values
[2018-01-28 23:20:21,215 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values
[2018-01-28 23:20:21,215 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values
[2018-01-28 23:20:21,218 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values
[2018-01-28 23:20:21,220 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values
[2018-01-28 23:20:21,222 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values
[2018-01-28 23:20:21,223 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values
[2018-01-28 23:20:21,224 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values
[2018-01-28 23:20:21,227 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring...
[2018-01-28 23:20:21,227 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring...
[2018-01-28 23:20:21,227 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values
[2018-01-28 23:20:21,228 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values
[2018-01-28 23:20:21,229 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values
[2018-01-28 23:20:21,230 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring...
[2018-01-28 23:20:21,230 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values
[2018-01-28 23:20:21,231 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring...
[2018-01-28 23:20:21,231 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring...
[2018-01-28 23:20:21,231 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values
[2018-01-28 23:20:21,232 INFO L181 SettingsManager]: Finished resetting all preferences to default values...
[2018-01-28 23:20:21,232 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf
[2018-01-28 23:20:21,242 INFO L110 SettingsManager]: Loading preferences was successful
[2018-01-28 23:20:21,242 INFO L112 SettingsManager]: Preferences different from defaults after loading the file:
[2018-01-28 23:20:21,243 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults:
[2018-01-28 23:20:21,243 INFO L133 SettingsManager]: * to procedures, called more than once=true
[2018-01-28 23:20:21,244 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults:
[2018-01-28 23:20:21,244 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain
[2018-01-28 23:20:21,244 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true
[2018-01-28 23:20:21,245 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults:
[2018-01-28 23:20:21,245 INFO L133 SettingsManager]: * sizeof long=4
[2018-01-28 23:20:21,245 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false
[2018-01-28 23:20:21,245 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true
[2018-01-28 23:20:21,245 INFO L133 SettingsManager]: * sizeof POINTER=4
[2018-01-28 23:20:21,246 INFO L133 SettingsManager]: * Check division by zero=IGNORE
[2018-01-28 23:20:21,246 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true
[2018-01-28 23:20:21,246 INFO L133 SettingsManager]: * Bitprecise bitfields=true
[2018-01-28 23:20:21,246 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true
[2018-01-28 23:20:21,246 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE
[2018-01-28 23:20:21,247 INFO L133 SettingsManager]: * sizeof long double=12
[2018-01-28 23:20:21,247 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults:
[2018-01-28 23:20:21,247 INFO L133 SettingsManager]: * Size of a code block=SingleStatement
[2018-01-28 23:20:21,247 INFO L133 SettingsManager]: * To the following directory=./dump/
[2018-01-28 23:20:21,248 INFO L133 SettingsManager]: * Add additional assume for each assert=false
[2018-01-28 23:20:21,248 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode
[2018-01-28 23:20:21,248 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000
[2018-01-28 23:20:21,248 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults:
[2018-01-28 23:20:21,248 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK
[2018-01-28 23:20:21,249 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP
[2018-01-28 23:20:21,249 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles
[2018-01-28 23:20:21,249 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL
[2018-01-28 23:20:21,249 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode
[2018-01-28 23:20:21,249 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in
[2018-01-28 23:20:21,249 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true
[2018-01-28 23:20:21,250 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults:
[2018-01-28 23:20:21,251 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR
[2018-01-28 23:20:21,287 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp
[2018-01-28 23:20:21,299 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized
[2018-01-28 23:20:21,304 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected.
[2018-01-28 23:20:21,305 INFO L271 PluginConnector]: Initializing CDTParser...
[2018-01-28 23:20:21,306 INFO L276 PluginConnector]: CDTParser initialized
[2018-01-28 23:20:21,306 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/cstrcat-alloca_true-valid-memsafety_true-termination.i
[2018-01-28 23:20:21,456 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] #######################
[2018-01-28 23:20:21,461 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements.
[2018-01-28 23:20:21,461 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator----------------------------
[2018-01-28 23:20:21,461 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator...
[2018-01-28 23:20:21,466 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized
[2018-01-28 23:20:21,467 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.01 11:20:21" (1/1) ...
[2018-01-28 23:20:21,469 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@67990aa8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:20:21, skipping insertion in model container
[2018-01-28 23:20:21,469 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.01 11:20:21" (1/1) ...
[2018-01-28 23:20:21,487 INFO L153 Dispatcher]: Using SV-COMP mode
[2018-01-28 23:20:21,526 INFO L153 Dispatcher]: Using SV-COMP mode
[2018-01-28 23:20:21,642 INFO L450 PostProcessor]: Settings: Checked method=main
[2018-01-28 23:20:21,659 INFO L450 PostProcessor]: Settings: Checked method=main
[2018-01-28 23:20:21,664 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:20:21 WrapperNode
[2018-01-28 23:20:21,665 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator----------------------------
[2018-01-28 23:20:21,665 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor----------------------------
[2018-01-28 23:20:21,665 INFO L271 PluginConnector]: Initializing Boogie Preprocessor...
[2018-01-28 23:20:21,665 INFO L276 PluginConnector]: Boogie Preprocessor initialized
[2018-01-28 23:20:21,682 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:20:21" (1/1) ...
[2018-01-28 23:20:21,682 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:20:21" (1/1) ...
[2018-01-28 23:20:21,694 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:20:21" (1/1) ...
[2018-01-28 23:20:21,695 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:20:21" (1/1) ...
[2018-01-28 23:20:21,699 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:20:21" (1/1) ...
[2018-01-28 23:20:21,703 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:20:21" (1/1) ...
[2018-01-28 23:20:21,705 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:20:21" (1/1) ...
[2018-01-28 23:20:21,707 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor----------------------------
[2018-01-28 23:20:21,707 INFO L113 PluginConnector]: ------------------------RCFGBuilder----------------------------
[2018-01-28 23:20:21,708 INFO L271 PluginConnector]: Initializing RCFGBuilder...
[2018-01-28 23:20:21,708 INFO L276 PluginConnector]: RCFGBuilder initialized
[2018-01-28 23:20:21,709 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:20:21" (1/1) ...
No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3
Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null)
Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000
[2018-01-28 23:20:21,770 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init
[2018-01-28 23:20:21,770 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start
[2018-01-28 23:20:21,770 INFO L136 BoogieDeclarations]: Found implementation of procedure cstrcat
[2018-01-28 23:20:21,771 INFO L136 BoogieDeclarations]: Found implementation of procedure main
[2018-01-28 23:20:21,771 INFO L128 BoogieDeclarations]: Found specification of procedure write~int
[2018-01-28 23:20:21,771 INFO L128 BoogieDeclarations]: Found specification of procedure read~int
[2018-01-28 23:20:21,771 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free
[2018-01-28 23:20:21,771 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc
[2018-01-28 23:20:21,771 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc
[2018-01-28 23:20:21,772 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int
[2018-01-28 23:20:21,772 INFO L128 BoogieDeclarations]: Found specification of procedure cstrcat
[2018-01-28 23:20:21,772 INFO L128 BoogieDeclarations]: Found specification of procedure main
[2018-01-28 23:20:21,772 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init
[2018-01-28 23:20:21,772 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start
[2018-01-28 23:20:22,034 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start)
[2018-01-28 23:20:22,035 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.01 11:20:22 BoogieIcfgContainer
[2018-01-28 23:20:22,035 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder----------------------------
[2018-01-28 23:20:22,035 INFO L113 PluginConnector]: ------------------------IcfgTransformer----------------------------
[2018-01-28 23:20:22,035 INFO L271 PluginConnector]: Initializing IcfgTransformer...
[2018-01-28 23:20:22,036 INFO L276 PluginConnector]: IcfgTransformer initialized
[2018-01-28 23:20:22,039 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.01 11:20:22" (1/1) ...
[2018-01-28 23:20:22,046 INFO L103 apSepIcfgTransformer]: HeapSepIcfgTransformer: Starting heap partitioning
[2018-01-28 23:20:22,046 INFO L104 apSepIcfgTransformer]: To be partitioned heap arrays found [#memory_int]
[2018-01-28 23:20:22,046 INFO L150 apSepIcfgTransformer]: starting freeze-var-style preprocessing
[2018-01-28 23:20:22,112 INFO L218 apSepIcfgTransformer]: finished preprocessing for the equality analysis
[2018-01-28 23:20:22,159 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2)
[2018-01-28 23:21:46,258 INFO L311 AbstractInterpreter]: Visited 89 different actions 1132 times. Merged at 57 different actions 717 times. Widened at 1 different actions 15 times. Found 58 fixpoints after 8 different actions. Largest state had 39 variables.
[2018-01-28 23:21:46,260 INFO L226 apSepIcfgTransformer]: finished equality analysis
[2018-01-28 23:21:46,270 INFO L244 HeapSepPreAnalysis]: Number of read from array group [#memory_int] : 5
[2018-01-28 23:21:46,270 INFO L238 apSepIcfgTransformer]: Finished pre analysis before partitioning
[2018-01-28 23:21:46,271 INFO L239 apSepIcfgTransformer]: array groups: Set:
[#memory_int]
[2018-01-28 23:21:46,271 INFO L241 apSepIcfgTransformer]: select infos: Set:
((select (select |v_#memory_int_2| |v_cstrcat_#t~post3.base_3|) |v_cstrcat_#t~post3.offset_3|), at (SUMMARY for call #t~mem5 := read~int(#t~post3.base, #t~post3.offset, 1); srcloc: L545''''))
((select |v_#memory_int_4| |v_cstrcat_#t~post2.base_3|), at (SUMMARY for call write~int(#t~mem5, #t~post2.base, #t~post2.offset, 1); srcloc: L545'''''))
((select |v_#memory_int_10| v_main_~nondetString2~3.base_2), at (SUMMARY for call write~int(0, ~nondetString2~3.base, ~nondetString2~3.offset + (~length3~3 - 1) * 1, 1); srcloc: L565'))
((select (select |v_#memory_int_1| v_cstrcat_~s~2.base_2) v_cstrcat_~s~2.offset_2), at (SUMMARY for call #t~mem0 := read~int(~s~2.base, ~s~2.offset, 1); srcloc: L543))
((select |v_#memory_int_8| v_main_~nondetString1~3.base_2), at (SUMMARY for call write~int(0, ~nondetString1~3.base, ~nondetString1~3.offset + (~length1~3 - 1) * 1, 1); srcloc: L565))
[2018-01-28 23:21:46,300 INFO L544 PartitionManager]: partitioning result:
[2018-01-28 23:21:46,300 INFO L549 PartitionManager]: location blocks for array group [#memory_int]
[2018-01-28 23:21:46,300 INFO L558 PartitionManager]: at dimension 0
[2018-01-28 23:21:46,300 INFO L559 PartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 1
[2018-01-28 23:21:46,301 INFO L560 PartitionManager]: # location blocks :1
[2018-01-28 23:21:46,301 INFO L558 PartitionManager]: at dimension 1
[2018-01-28 23:21:46,301 INFO L559 PartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 1
[2018-01-28 23:21:46,301 INFO L560 PartitionManager]: # location blocks :1
[2018-01-28 23:21:46,302 INFO L86 ransitionTransformer]: executing heap partitioning transformation
[2018-01-28 23:21:46,316 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 28.01 11:21:46 BasicIcfg
[2018-01-28 23:21:46,316 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer----------------------------
[2018-01-28 23:21:46,317 INFO L113 PluginConnector]: ------------------------TraceAbstraction----------------------------
[2018-01-28 23:21:46,317 INFO L271 PluginConnector]: Initializing TraceAbstraction...
[2018-01-28 23:21:46,375 INFO L276 PluginConnector]: TraceAbstraction initialized
[2018-01-28 23:21:46,376 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.01 11:20:21" (1/4) ...
[2018-01-28 23:21:46,377 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@27e1173c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.01 11:21:46, skipping insertion in model container
[2018-01-28 23:21:46,377 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:20:21" (2/4) ...
[2018-01-28 23:21:46,377 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@27e1173c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.01 11:21:46, skipping insertion in model container
[2018-01-28 23:21:46,377 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.01 11:20:22" (3/4) ...
[2018-01-28 23:21:46,377 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@27e1173c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.01 11:21:46, skipping insertion in model container
[2018-01-28 23:21:46,378 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 28.01 11:21:46" (4/4) ...
[2018-01-28 23:21:46,379 INFO L107 eAbstractionObserver]: Analyzing ICFG HeapSeparatedIcfg
[2018-01-28 23:21:46,386 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION
[2018-01-28 23:21:46,392 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 11 error locations.
[2018-01-28 23:21:46,421 INFO L322 AbstractCegarLoop]: Interprodecural is true
[2018-01-28 23:21:46,421 INFO L323 AbstractCegarLoop]: Hoare is true
[2018-01-28 23:21:46,421 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP
[2018-01-28 23:21:46,421 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK
[2018-01-28 23:21:46,422 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION
[2018-01-28 23:21:46,422 INFO L327 AbstractCegarLoop]: Difference is false
[2018-01-28 23:21:46,422 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA
[2018-01-28 23:21:46,422 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce========
[2018-01-28 23:21:46,423 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure
[2018-01-28 23:21:46,439 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states.
[2018-01-28 23:21:46,444 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18
[2018-01-28 23:21:46,445 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:46,446 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:46,446 INFO L371 AbstractCegarLoop]: === Iteration 1 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:46,449 INFO L82 PathProgramCache]: Analyzing trace with hash -1989739996, now seen corresponding path program 1 times
[2018-01-28 23:21:46,451 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:46,451 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:46,494 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:46,494 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:46,494 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:46,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:46,538 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs.
[2018-01-28 23:21:46,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:46,596 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences.
[2018-01-28 23:21:46,597 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2018-01-28 23:21:46,598 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states
[2018-01-28 23:21:46,605 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2018-01-28 23:21:46,606 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2018-01-28 23:21:46,608 INFO L87 Difference]: Start difference. First operand 79 states. Second operand 3 states.
[2018-01-28 23:21:46,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2018-01-28 23:21:46,752 INFO L93 Difference]: Finished difference Result 112 states and 124 transitions.
[2018-01-28 23:21:46,752 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2018-01-28 23:21:46,754 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 17
[2018-01-28 23:21:46,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted.
[2018-01-28 23:21:46,765 INFO L225 Difference]: With dead ends: 112
[2018-01-28 23:21:46,765 INFO L226 Difference]: Without dead ends: 75
[2018-01-28 23:21:46,769 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2018-01-28 23:21:46,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states.
[2018-01-28 23:21:46,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75.
[2018-01-28 23:21:46,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states.
[2018-01-28 23:21:46,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 81 transitions.
[2018-01-28 23:21:46,803 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 81 transitions. Word has length 17
[2018-01-28 23:21:46,804 INFO L84 Accepts]: Finished accepts. word is rejected.
[2018-01-28 23:21:46,804 INFO L432 AbstractCegarLoop]: Abstraction has 75 states and 81 transitions.
[2018-01-28 23:21:46,804 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states.
[2018-01-28 23:21:46,804 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 81 transitions.
[2018-01-28 23:21:46,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21
[2018-01-28 23:21:46,805 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:46,805 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:46,806 INFO L371 AbstractCegarLoop]: === Iteration 2 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:46,806 INFO L82 PathProgramCache]: Analyzing trace with hash -1440983707, now seen corresponding path program 1 times
[2018-01-28 23:21:46,806 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:46,806 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:46,807 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:46,807 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:46,807 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:46,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:46,829 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs.
[2018-01-28 23:21:46,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:46,900 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences.
[2018-01-28 23:21:46,900 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2018-01-28 23:21:46,902 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states
[2018-01-28 23:21:46,902 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2018-01-28 23:21:46,902 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2018-01-28 23:21:46,903 INFO L87 Difference]: Start difference. First operand 75 states and 81 transitions. Second operand 4 states.
[2018-01-28 23:21:47,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2018-01-28 23:21:47,005 INFO L93 Difference]: Finished difference Result 75 states and 81 transitions.
[2018-01-28 23:21:47,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2018-01-28 23:21:47,006 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 20
[2018-01-28 23:21:47,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted.
[2018-01-28 23:21:47,007 INFO L225 Difference]: With dead ends: 75
[2018-01-28 23:21:47,007 INFO L226 Difference]: Without dead ends: 74
[2018-01-28 23:21:47,008 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20
[2018-01-28 23:21:47,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states.
[2018-01-28 23:21:47,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 74.
[2018-01-28 23:21:47,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states.
[2018-01-28 23:21:47,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 80 transitions.
[2018-01-28 23:21:47,015 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 80 transitions. Word has length 20
[2018-01-28 23:21:47,015 INFO L84 Accepts]: Finished accepts. word is rejected.
[2018-01-28 23:21:47,015 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 80 transitions.
[2018-01-28 23:21:47,016 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states.
[2018-01-28 23:21:47,016 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 80 transitions.
[2018-01-28 23:21:47,016 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21
[2018-01-28 23:21:47,016 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:47,016 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:47,016 INFO L371 AbstractCegarLoop]: === Iteration 3 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:47,017 INFO L82 PathProgramCache]: Analyzing trace with hash -1440983705, now seen corresponding path program 1 times
[2018-01-28 23:21:47,017 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:47,017 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:47,017 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:47,018 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:47,018 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:47,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:47,033 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs.
[2018-01-28 23:21:47,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:47,158 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences.
[2018-01-28 23:21:47,158 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2018-01-28 23:21:47,158 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states
[2018-01-28 23:21:47,158 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants.
[2018-01-28 23:21:47,159 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30
[2018-01-28 23:21:47,159 INFO L87 Difference]: Start difference. First operand 74 states and 80 transitions. Second operand 6 states.
[2018-01-28 23:21:47,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2018-01-28 23:21:47,267 INFO L93 Difference]: Finished difference Result 74 states and 80 transitions.
[2018-01-28 23:21:47,267 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states.
[2018-01-28 23:21:47,267 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 20
[2018-01-28 23:21:47,268 INFO L84 Accepts]: Finished accepts. some prefix is accepted.
[2018-01-28 23:21:47,268 INFO L225 Difference]: With dead ends: 74
[2018-01-28 23:21:47,269 INFO L226 Difference]: Without dead ends: 73
[2018-01-28 23:21:47,269 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42
[2018-01-28 23:21:47,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states.
[2018-01-28 23:21:47,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73.
[2018-01-28 23:21:47,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states.
[2018-01-28 23:21:47,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 79 transitions.
[2018-01-28 23:21:47,276 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 79 transitions. Word has length 20
[2018-01-28 23:21:47,276 INFO L84 Accepts]: Finished accepts. word is rejected.
[2018-01-28 23:21:47,276 INFO L432 AbstractCegarLoop]: Abstraction has 73 states and 79 transitions.
[2018-01-28 23:21:47,277 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states.
[2018-01-28 23:21:47,277 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 79 transitions.
[2018-01-28 23:21:47,277 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22
[2018-01-28 23:21:47,277 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:47,278 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:47,278 INFO L371 AbstractCegarLoop]: === Iteration 4 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:47,278 INFO L82 PathProgramCache]: Analyzing trace with hash -1720821584, now seen corresponding path program 1 times
[2018-01-28 23:21:47,278 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:47,278 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:47,279 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:47,280 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:47,280 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:47,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:47,293 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs.
[2018-01-28 23:21:47,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:47,335 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences.
[2018-01-28 23:21:47,335 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2018-01-28 23:21:47,336 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states
[2018-01-28 23:21:47,336 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2018-01-28 23:21:47,336 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2018-01-28 23:21:47,336 INFO L87 Difference]: Start difference. First operand 73 states and 79 transitions. Second operand 4 states.
[2018-01-28 23:21:47,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2018-01-28 23:21:47,388 INFO L93 Difference]: Finished difference Result 73 states and 79 transitions.
[2018-01-28 23:21:47,388 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2018-01-28 23:21:47,388 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 21
[2018-01-28 23:21:47,389 INFO L84 Accepts]: Finished accepts. some prefix is accepted.
[2018-01-28 23:21:47,389 INFO L225 Difference]: With dead ends: 73
[2018-01-28 23:21:47,389 INFO L226 Difference]: Without dead ends: 72
[2018-01-28 23:21:47,389 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20
[2018-01-28 23:21:47,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states.
[2018-01-28 23:21:47,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 72.
[2018-01-28 23:21:47,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states.
[2018-01-28 23:21:47,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 78 transitions.
[2018-01-28 23:21:47,394 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 78 transitions. Word has length 21
[2018-01-28 23:21:47,394 INFO L84 Accepts]: Finished accepts. word is rejected.
[2018-01-28 23:21:47,394 INFO L432 AbstractCegarLoop]: Abstraction has 72 states and 78 transitions.
[2018-01-28 23:21:47,394 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states.
[2018-01-28 23:21:47,394 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 78 transitions.
[2018-01-28 23:21:47,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22
[2018-01-28 23:21:47,395 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:47,395 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:47,395 INFO L371 AbstractCegarLoop]: === Iteration 5 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:47,395 INFO L82 PathProgramCache]: Analyzing trace with hash -1720821582, now seen corresponding path program 1 times
[2018-01-28 23:21:47,395 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:47,395 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:47,396 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:47,396 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:47,396 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:47,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:47,405 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs.
[2018-01-28 23:21:47,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:47,479 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences.
[2018-01-28 23:21:47,479 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6
[2018-01-28 23:21:47,479 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states
[2018-01-28 23:21:47,480 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants.
[2018-01-28 23:21:47,480 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42
[2018-01-28 23:21:47,480 INFO L87 Difference]: Start difference. First operand 72 states and 78 transitions. Second operand 7 states.
[2018-01-28 23:21:47,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2018-01-28 23:21:47,623 INFO L93 Difference]: Finished difference Result 72 states and 78 transitions.
[2018-01-28 23:21:47,623 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states.
[2018-01-28 23:21:47,623 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 21
[2018-01-28 23:21:47,624 INFO L84 Accepts]: Finished accepts. some prefix is accepted.
[2018-01-28 23:21:47,624 INFO L225 Difference]: With dead ends: 72
[2018-01-28 23:21:47,625 INFO L226 Difference]: Without dead ends: 71
[2018-01-28 23:21:47,625 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110
[2018-01-28 23:21:47,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states.
[2018-01-28 23:21:47,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 71.
[2018-01-28 23:21:47,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states.
[2018-01-28 23:21:47,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 77 transitions.
[2018-01-28 23:21:47,631 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 77 transitions. Word has length 21
[2018-01-28 23:21:47,632 INFO L84 Accepts]: Finished accepts. word is rejected.
[2018-01-28 23:21:47,632 INFO L432 AbstractCegarLoop]: Abstraction has 71 states and 77 transitions.
[2018-01-28 23:21:47,632 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states.
[2018-01-28 23:21:47,632 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 77 transitions.
[2018-01-28 23:21:47,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28
[2018-01-28 23:21:47,633 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:47,633 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:47,633 INFO L371 AbstractCegarLoop]: === Iteration 6 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:47,633 INFO L82 PathProgramCache]: Analyzing trace with hash 1906547614, now seen corresponding path program 1 times
[2018-01-28 23:21:47,633 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:47,633 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:47,634 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:47,634 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:47,634 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:47,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:47,647 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs.
[2018-01-28 23:21:47,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:47,746 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences.
[2018-01-28 23:21:47,746 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2018-01-28 23:21:47,746 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states
[2018-01-28 23:21:47,746 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants.
[2018-01-28 23:21:47,746 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30
[2018-01-28 23:21:47,746 INFO L87 Difference]: Start difference. First operand 71 states and 77 transitions. Second operand 6 states.
[2018-01-28 23:21:47,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2018-01-28 23:21:47,831 INFO L93 Difference]: Finished difference Result 78 states and 84 transitions.
[2018-01-28 23:21:47,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states.
[2018-01-28 23:21:47,831 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 27
[2018-01-28 23:21:47,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted.
[2018-01-28 23:21:47,832 INFO L225 Difference]: With dead ends: 78
[2018-01-28 23:21:47,832 INFO L226 Difference]: Without dead ends: 77
[2018-01-28 23:21:47,832 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56
[2018-01-28 23:21:47,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states.
[2018-01-28 23:21:47,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 73.
[2018-01-28 23:21:47,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states.
[2018-01-28 23:21:47,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 80 transitions.
[2018-01-28 23:21:47,838 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 80 transitions. Word has length 27
[2018-01-28 23:21:47,838 INFO L84 Accepts]: Finished accepts. word is rejected.
[2018-01-28 23:21:47,838 INFO L432 AbstractCegarLoop]: Abstraction has 73 states and 80 transitions.
[2018-01-28 23:21:47,838 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states.
[2018-01-28 23:21:47,838 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 80 transitions.
[2018-01-28 23:21:47,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28
[2018-01-28 23:21:47,839 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:47,839 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:47,840 INFO L371 AbstractCegarLoop]: === Iteration 7 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:47,840 INFO L82 PathProgramCache]: Analyzing trace with hash 1906547616, now seen corresponding path program 1 times
[2018-01-28 23:21:47,840 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:47,840 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:47,841 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:47,841 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:47,841 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:47,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:47,855 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs.
[2018-01-28 23:21:47,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:47,961 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences.
[2018-01-28 23:21:47,961 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7
[2018-01-28 23:21:47,961 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states
[2018-01-28 23:21:47,961 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants.
[2018-01-28 23:21:47,961 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56
[2018-01-28 23:21:47,961 INFO L87 Difference]: Start difference. First operand 73 states and 80 transitions. Second operand 8 states.
[2018-01-28 23:21:48,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2018-01-28 23:21:48,126 INFO L93 Difference]: Finished difference Result 82 states and 89 transitions.
[2018-01-28 23:21:48,126 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states.
[2018-01-28 23:21:48,127 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 27
[2018-01-28 23:21:48,127 INFO L84 Accepts]: Finished accepts. some prefix is accepted.
[2018-01-28 23:21:48,128 INFO L225 Difference]: With dead ends: 82
[2018-01-28 23:21:48,128 INFO L226 Difference]: Without dead ends: 81
[2018-01-28 23:21:48,128 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=38, Invalid=118, Unknown=0, NotChecked=0, Total=156
[2018-01-28 23:21:48,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states.
[2018-01-28 23:21:48,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 73.
[2018-01-28 23:21:48,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states.
[2018-01-28 23:21:48,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 79 transitions.
[2018-01-28 23:21:48,135 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 79 transitions. Word has length 27
[2018-01-28 23:21:48,136 INFO L84 Accepts]: Finished accepts. word is rejected.
[2018-01-28 23:21:48,136 INFO L432 AbstractCegarLoop]: Abstraction has 73 states and 79 transitions.
[2018-01-28 23:21:48,136 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states.
[2018-01-28 23:21:48,136 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 79 transitions.
[2018-01-28 23:21:48,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30
[2018-01-28 23:21:48,137 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:48,137 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:48,137 INFO L371 AbstractCegarLoop]: === Iteration 8 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:48,138 INFO L82 PathProgramCache]: Analyzing trace with hash 1511374534, now seen corresponding path program 1 times
[2018-01-28 23:21:48,138 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:48,138 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:48,139 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:48,139 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:48,139 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:48,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:48,151 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs.
[2018-01-28 23:21:48,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:48,228 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences.
[2018-01-28 23:21:48,228 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2018-01-28 23:21:48,228 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states
[2018-01-28 23:21:48,228 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants.
[2018-01-28 23:21:48,228 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30
[2018-01-28 23:21:48,228 INFO L87 Difference]: Start difference. First operand 73 states and 79 transitions. Second operand 6 states.
[2018-01-28 23:21:48,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2018-01-28 23:21:48,332 INFO L93 Difference]: Finished difference Result 73 states and 79 transitions.
[2018-01-28 23:21:48,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states.
[2018-01-28 23:21:48,332 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 29
[2018-01-28 23:21:48,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted.
[2018-01-28 23:21:48,333 INFO L225 Difference]: With dead ends: 73
[2018-01-28 23:21:48,333 INFO L226 Difference]: Without dead ends: 59
[2018-01-28 23:21:48,333 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56
[2018-01-28 23:21:48,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states.
[2018-01-28 23:21:48,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59.
[2018-01-28 23:21:48,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states.
[2018-01-28 23:21:48,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 64 transitions.
[2018-01-28 23:21:48,338 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 64 transitions. Word has length 29
[2018-01-28 23:21:48,338 INFO L84 Accepts]: Finished accepts. word is rejected.
[2018-01-28 23:21:48,338 INFO L432 AbstractCegarLoop]: Abstraction has 59 states and 64 transitions.
[2018-01-28 23:21:48,338 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states.
[2018-01-28 23:21:48,338 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 64 transitions.
[2018-01-28 23:21:48,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35
[2018-01-28 23:21:48,339 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:48,340 INFO L330 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:48,340 INFO L371 AbstractCegarLoop]: === Iteration 9 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:48,340 INFO L82 PathProgramCache]: Analyzing trace with hash -1930834765, now seen corresponding path program 1 times
[2018-01-28 23:21:48,340 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:48,340 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:48,341 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:48,341 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:48,341 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:48,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:48,352 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs.
[2018-01-28 23:21:48,396 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:48,397 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences.
[2018-01-28 23:21:48,397 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2018-01-28 23:21:48,397 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states
[2018-01-28 23:21:48,397 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2018-01-28 23:21:48,398 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2018-01-28 23:21:48,398 INFO L87 Difference]: Start difference. First operand 59 states and 64 transitions. Second operand 4 states.
[2018-01-28 23:21:48,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2018-01-28 23:21:48,441 INFO L93 Difference]: Finished difference Result 62 states and 67 transitions.
[2018-01-28 23:21:48,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2018-01-28 23:21:48,442 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34
[2018-01-28 23:21:48,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted.
[2018-01-28 23:21:48,443 INFO L225 Difference]: With dead ends: 62
[2018-01-28 23:21:48,443 INFO L226 Difference]: Without dead ends: 61
[2018-01-28 23:21:48,443 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20
[2018-01-28 23:21:48,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states.
[2018-01-28 23:21:48,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 58.
[2018-01-28 23:21:48,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states.
[2018-01-28 23:21:48,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 63 transitions.
[2018-01-28 23:21:48,448 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 63 transitions. Word has length 34
[2018-01-28 23:21:48,449 INFO L84 Accepts]: Finished accepts. word is rejected.
[2018-01-28 23:21:48,449 INFO L432 AbstractCegarLoop]: Abstraction has 58 states and 63 transitions.
[2018-01-28 23:21:48,449 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states.
[2018-01-28 23:21:48,449 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 63 transitions.
[2018-01-28 23:21:48,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35
[2018-01-28 23:21:48,450 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:48,450 INFO L330 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:48,450 INFO L371 AbstractCegarLoop]: === Iteration 10 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:48,451 INFO L82 PathProgramCache]: Analyzing trace with hash -1930834763, now seen corresponding path program 1 times
[2018-01-28 23:21:48,451 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:48,451 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:48,452 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:48,452 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:48,452 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:48,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:48,463 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs.
[2018-01-28 23:21:48,582 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:48,582 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more.
[2018-01-28 23:21:48,582 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP
No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3
Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null)
Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000
[2018-01-28 23:21:48,591 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:48,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:48,639 INFO L270 TraceCheckSpWp]: Computing forward predicates...
[2018-01-28 23:21:48,682 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5
[2018-01-28 23:21:48,683 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts.
[2018-01-28 23:21:48,700 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts.
[2018-01-28 23:21:48,700 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:13, output treesize:9
[2018-01-28 23:21:48,799 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:48,836 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences.
[2018-01-28 23:21:48,836 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10
[2018-01-28 23:21:48,836 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states
[2018-01-28 23:21:48,837 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants.
[2018-01-28 23:21:48,837 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110
[2018-01-28 23:21:48,837 INFO L87 Difference]: Start difference. First operand 58 states and 63 transitions. Second operand 11 states.
[2018-01-28 23:21:49,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2018-01-28 23:21:49,041 INFO L93 Difference]: Finished difference Result 78 states and 85 transitions.
[2018-01-28 23:21:49,041 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states.
[2018-01-28 23:21:49,041 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 34
[2018-01-28 23:21:49,041 INFO L84 Accepts]: Finished accepts. some prefix is accepted.
[2018-01-28 23:21:49,041 INFO L225 Difference]: With dead ends: 78
[2018-01-28 23:21:49,042 INFO L226 Difference]: Without dead ends: 77
[2018-01-28 23:21:49,042 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 28 SyntacticMatches, 5 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=64, Invalid=242, Unknown=0, NotChecked=0, Total=306
[2018-01-28 23:21:49,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states.
[2018-01-28 23:21:49,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 65.
[2018-01-28 23:21:49,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65 states.
[2018-01-28 23:21:49,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 71 transitions.
[2018-01-28 23:21:49,046 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 71 transitions. Word has length 34
[2018-01-28 23:21:49,046 INFO L84 Accepts]: Finished accepts. word is rejected.
[2018-01-28 23:21:49,047 INFO L432 AbstractCegarLoop]: Abstraction has 65 states and 71 transitions.
[2018-01-28 23:21:49,047 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states.
[2018-01-28 23:21:49,047 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 71 transitions.
[2018-01-28 23:21:49,047 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36
[2018-01-28 23:21:49,047 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:49,048 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:49,048 INFO L371 AbstractCegarLoop]: === Iteration 11 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:49,048 INFO L82 PathProgramCache]: Analyzing trace with hash -1336935366, now seen corresponding path program 1 times
[2018-01-28 23:21:49,048 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:49,048 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:49,049 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:49,049 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:49,049 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:49,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:49,060 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs.
[2018-01-28 23:21:49,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:49,133 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences.
[2018-01-28 23:21:49,133 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2018-01-28 23:21:49,133 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states
[2018-01-28 23:21:49,134 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants.
[2018-01-28 23:21:49,134 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30
[2018-01-28 23:21:49,134 INFO L87 Difference]: Start difference. First operand 65 states and 71 transitions. Second operand 6 states.
[2018-01-28 23:21:49,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2018-01-28 23:21:49,195 INFO L93 Difference]: Finished difference Result 65 states and 71 transitions.
[2018-01-28 23:21:49,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states.
[2018-01-28 23:21:49,195 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35
[2018-01-28 23:21:49,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted.
[2018-01-28 23:21:49,196 INFO L225 Difference]: With dead ends: 65
[2018-01-28 23:21:49,196 INFO L226 Difference]: Without dead ends: 64
[2018-01-28 23:21:49,196 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56
[2018-01-28 23:21:49,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states.
[2018-01-28 23:21:49,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 64.
[2018-01-28 23:21:49,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states.
[2018-01-28 23:21:49,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 70 transitions.
[2018-01-28 23:21:49,200 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 70 transitions. Word has length 35
[2018-01-28 23:21:49,200 INFO L84 Accepts]: Finished accepts. word is rejected.
[2018-01-28 23:21:49,200 INFO L432 AbstractCegarLoop]: Abstraction has 64 states and 70 transitions.
[2018-01-28 23:21:49,200 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states.
[2018-01-28 23:21:49,201 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 70 transitions.
[2018-01-28 23:21:49,201 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36
[2018-01-28 23:21:49,202 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:49,202 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:49,202 INFO L371 AbstractCegarLoop]: === Iteration 12 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:49,202 INFO L82 PathProgramCache]: Analyzing trace with hash -1336935364, now seen corresponding path program 1 times
[2018-01-28 23:21:49,202 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:49,202 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:49,203 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:49,203 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:49,203 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:49,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:49,215 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs.
[2018-01-28 23:21:49,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:49,323 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences.
[2018-01-28 23:21:49,323 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8
[2018-01-28 23:21:49,323 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states
[2018-01-28 23:21:49,323 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants.
[2018-01-28 23:21:49,324 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72
[2018-01-28 23:21:49,324 INFO L87 Difference]: Start difference. First operand 64 states and 70 transitions. Second operand 9 states.
[2018-01-28 23:21:49,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2018-01-28 23:21:49,429 INFO L93 Difference]: Finished difference Result 71 states and 77 transitions.
[2018-01-28 23:21:49,429 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states.
[2018-01-28 23:21:49,429 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 35
[2018-01-28 23:21:49,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted.
[2018-01-28 23:21:49,430 INFO L225 Difference]: With dead ends: 71
[2018-01-28 23:21:49,430 INFO L226 Difference]: Without dead ends: 70
[2018-01-28 23:21:49,430 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=44, Invalid=138, Unknown=0, NotChecked=0, Total=182
[2018-01-28 23:21:49,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states.
[2018-01-28 23:21:49,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 70.
[2018-01-28 23:21:49,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states.
[2018-01-28 23:21:49,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 76 transitions.
[2018-01-28 23:21:49,434 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 76 transitions. Word has length 35
[2018-01-28 23:21:49,434 INFO L84 Accepts]: Finished accepts. word is rejected.
[2018-01-28 23:21:49,434 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 76 transitions.
[2018-01-28 23:21:49,434 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states.
[2018-01-28 23:21:49,434 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 76 transitions.
[2018-01-28 23:21:49,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37
[2018-01-28 23:21:49,435 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:49,435 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:49,435 INFO L371 AbstractCegarLoop]: === Iteration 13 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:49,436 INFO L82 PathProgramCache]: Analyzing trace with hash 1504677061, now seen corresponding path program 1 times
[2018-01-28 23:21:49,436 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:49,436 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:49,437 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:49,437 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:49,437 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:49,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:49,446 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs.
[2018-01-28 23:21:49,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:49,475 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences.
[2018-01-28 23:21:49,476 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2018-01-28 23:21:49,476 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states
[2018-01-28 23:21:49,476 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2018-01-28 23:21:49,476 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2018-01-28 23:21:49,476 INFO L87 Difference]: Start difference. First operand 70 states and 76 transitions. Second operand 4 states.
[2018-01-28 23:21:49,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2018-01-28 23:21:49,497 INFO L93 Difference]: Finished difference Result 70 states and 76 transitions.
[2018-01-28 23:21:49,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2018-01-28 23:21:49,498 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36
[2018-01-28 23:21:49,498 INFO L84 Accepts]: Finished accepts. some prefix is accepted.
[2018-01-28 23:21:49,498 INFO L225 Difference]: With dead ends: 70
[2018-01-28 23:21:49,498 INFO L226 Difference]: Without dead ends: 69
[2018-01-28 23:21:49,499 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20
[2018-01-28 23:21:49,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states.
[2018-01-28 23:21:49,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69.
[2018-01-28 23:21:49,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states.
[2018-01-28 23:21:49,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 75 transitions.
[2018-01-28 23:21:49,504 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 75 transitions. Word has length 36
[2018-01-28 23:21:49,504 INFO L84 Accepts]: Finished accepts. word is rejected.
[2018-01-28 23:21:49,504 INFO L432 AbstractCegarLoop]: Abstraction has 69 states and 75 transitions.
[2018-01-28 23:21:49,504 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states.
[2018-01-28 23:21:49,504 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 75 transitions.
[2018-01-28 23:21:49,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37
[2018-01-28 23:21:49,505 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:49,505 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:49,505 INFO L371 AbstractCegarLoop]: === Iteration 14 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:49,505 INFO L82 PathProgramCache]: Analyzing trace with hash 1504677063, now seen corresponding path program 1 times
[2018-01-28 23:21:49,506 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:49,506 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:49,507 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:49,507 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:49,507 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:49,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2018-01-28 23:21:49,517 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs.
[2018-01-28 23:21:49,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2018-01-28 23:21:49,621 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences.
[2018-01-28 23:21:49,621 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8
[2018-01-28 23:21:49,622 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states
[2018-01-28 23:21:49,622 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants.
[2018-01-28 23:21:49,622 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72
[2018-01-28 23:21:49,622 INFO L87 Difference]: Start difference. First operand 69 states and 75 transitions. Second operand 9 states.
[2018-01-28 23:21:49,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2018-01-28 23:21:49,756 INFO L93 Difference]: Finished difference Result 80 states and 86 transitions.
[2018-01-28 23:21:49,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states.
[2018-01-28 23:21:49,756 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 36
[2018-01-28 23:21:49,756 INFO L84 Accepts]: Finished accepts. some prefix is accepted.
[2018-01-28 23:21:49,757 INFO L225 Difference]: With dead ends: 80
[2018-01-28 23:21:49,757 INFO L226 Difference]: Without dead ends: 79
[2018-01-28 23:21:49,757 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=50, Invalid=160, Unknown=0, NotChecked=0, Total=210
[2018-01-28 23:21:49,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states.
[2018-01-28 23:21:49,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 77.
[2018-01-28 23:21:49,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states.
[2018-01-28 23:21:49,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 83 transitions.
[2018-01-28 23:21:49,763 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 83 transitions. Word has length 36
[2018-01-28 23:21:49,763 INFO L84 Accepts]: Finished accepts. word is rejected.
[2018-01-28 23:21:49,763 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 83 transitions.
[2018-01-28 23:21:49,763 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states.
[2018-01-28 23:21:49,764 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 83 transitions.
[2018-01-28 23:21:49,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42
[2018-01-28 23:21:49,764 INFO L322 BasicCegarLoop]: Found error trace
[2018-01-28 23:21:49,765 INFO L330 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2018-01-28 23:21:49,765 INFO L371 AbstractCegarLoop]: === Iteration 15 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolation, mainErr0RequiresViolation]===
[2018-01-28 23:21:49,765 INFO L82 PathProgramCache]: Analyzing trace with hash -168613376, now seen corresponding path program 2 times
[2018-01-28 23:21:49,765 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS
[2018-01-28 23:21:49,765 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy
[2018-01-28 23:21:49,766 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:49,766 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2018-01-28 23:21:49,766 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order
[2018-01-28 23:21:49,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2018-01-28 23:21:49,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2018-01-28 23:21:49,807 INFO L389 BasicCegarLoop]: Counterexample might be feasible
[2018-01-28 23:21:49,810 INFO L84 mationBacktranslator]: Skipped ATE [357] [357] ULTIMATE.startENTRY-->L1: Formula: true InVars {} OutVars{#NULL.offset=|v_#NULL.offset_2|, #NULL.base=|v_#NULL.base_2|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid, #NULL.offset, #NULL.base]
[2018-01-28 23:21:49,810 INFO L84 mationBacktranslator]: Skipped ATE [363] [363] L1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]
[2018-01-28 23:21:49,810 INFO L84 mationBacktranslator]: Skipped ATE [369] [369] mainENTRY-->L550: Formula: (and (<= |v_main_#t~nondet6_1| 2147483647) (<= 0 (+ |v_main_#t~nondet6_1| 2147483648))) InVars {main_#t~nondet6=|v_main_#t~nondet6_1|} OutVars{main_#t~nondet6=|v_main_#t~nondet6_1|} AuxVars[] AssignedVars[]
[2018-01-28 23:21:49,811 INFO L84 mationBacktranslator]: Skipped ATE [373] [373] L550-->L550': Formula: (= v_main_~length1~3_9 |v_main_#t~nondet6_2|) InVars {main_#t~nondet6=|v_main_#t~nondet6_2|} OutVars{main_~length1~3=v_main_~length1~3_9, main_#t~nondet6=|v_main_#t~nondet6_2|} AuxVars[] AssignedVars[main_~length1~3]
[2018-01-28 23:21:49,811 INFO L84 mationBacktranslator]: Skipped ATE [377] [377] L550'-->L551: Formula: true InVars {} OutVars{main_#t~nondet6=|v_main_#t~nondet6_3|} AuxVars[] AssignedVars[main_#t~nondet6]
[2018-01-28 23:21:49,811 INFO L84 mationBacktranslator]: Skipped ATE [379] [379] L551-->L551': Formula: (and (<= |v_main_#t~nondet7_3| 2147483647) (<= 0 (+ |v_main_#t~nondet7_3| 2147483648))) InVars {main_#t~nondet7=|v_main_#t~nondet7_3|} OutVars{main_#t~nondet7=|v_main_#t~nondet7_3|} AuxVars[] AssignedVars[]
[2018-01-28 23:21:49,811 INFO L84 mationBacktranslator]: Skipped ATE [381] [381] L551'-->L551'': Formula: (= v_main_~length2~3_1 |v_main_#t~nondet7_1|) InVars {main_#t~nondet7=|v_main_#t~nondet7_1|} OutVars{main_~length2~3=v_main_~length2~3_1, main_#t~nondet7=|v_main_#t~nondet7_1|} AuxVars[] AssignedVars[main_~length2~3]
[2018-01-28 23:21:49,811 INFO L84 mationBacktranslator]: Skipped ATE [383] [383] L551''-->L552: Formula: true InVars {} OutVars{main_#t~nondet7=|v_main_#t~nondet7_2|} AuxVars[] AssignedVars[main_#t~nondet7]
[2018-01-28 23:21:49,811 INFO L84 mationBacktranslator]: Skipped ATE [385] [385] L552-->L552': Formula: (and (<= 0 (+ |v_main_#t~nondet8_1| 2147483648)) (<= |v_main_#t~nondet8_1| 2147483647)) InVars {main_#t~nondet8=|v_main_#t~nondet8_1|} OutVars{main_#t~nondet8=|v_main_#t~nondet8_1|} AuxVars[] AssignedVars[]
[2018-01-28 23:21:49,811 INFO L84 mationBacktranslator]: Skipped ATE [387] [387] L552'-->L552'': Formula: (= v_main_~length3~3_1 |v_main_#t~nondet8_2|) InVars {main_#t~nondet8=|v_main_#t~nondet8_2|} OutVars{main_#t~nondet8=|v_main_#t~nondet8_2|, main_~length3~3=v_main_~length3~3_1} AuxVars[] AssignedVars[main_~length3~3]
[2018-01-28 23:21:49,811 INFO L84 mationBacktranslator]: Skipped ATE [389] [389] L552''-->L553: Formula: true InVars {} OutVars{main_#t~nondet8=|v_main_#t~nondet8_3|} AuxVars[] AssignedVars[main_#t~nondet8]
[2018-01-28 23:21:49,812 INFO L84 mationBacktranslator]: Skipped ATE [393] [393] L553-->L553'': Formula: (not (< v_main_~length1~3_3 1)) InVars {main_~length1~3=v_main_~length1~3_3} OutVars{main_~length1~3=v_main_~length1~3_3} AuxVars[] AssignedVars[]
[2018-01-28 23:21:49,812 INFO L84 mationBacktranslator]: Skipped ATE [399] [399] L553''-->L556': Formula: (not (< v_main_~length2~3_4 2)) InVars {main_~length2~3=v_main_~length2~3_4} OutVars{main_~length2~3=v_main_~length2~3_4} AuxVars[] AssignedVars[]
[2018-01-28 23:21:49,812 INFO L84 mationBacktranslator]: Skipped ATE [405] [405] L556'-->L559': Formula: (not (< v_main_~length3~3_4 1)) InVars {main_~length3~3=v_main_~length3~3_4} OutVars{main_~length3~3=v_main_~length3~3_4} AuxVars[] AssignedVars[]
[2018-01-28 23:21:49,812 INFO L84 mationBacktranslator]: Skipped ATE [411] [411] L559'-->L563: Formula: (and (not (< v_main_~length2~3_6 (+ v_main_~length1~3_5 v_main_~length3~3_6))) (not (< v_main_~length2~3_6 v_main_~length3~3_6))) InVars {main_~length2~3=v_main_~length2~3_6, main_~length3~3=v_main_~length3~3_6, main_~length1~3=v_main_~length1~3_5} OutVars{main_~length2~3=v_main_~length2~3_6, main_~length3~3=v_main_~length3~3_6, main_~length1~3=v_main_~length1~3_5} AuxVars[] AssignedVars[]
[2018-01-28 23:21:49,812 INFO L84 mationBacktranslator]: Skipped ATE [415] [415] L563-->L563': Formula: (and (not (= |v_main_#t~malloc9.base_1| 0)) (= (store |v_#length_10| |v_main_#t~malloc9.base_1| v_main_~length1~3_6) |v_#length_9|) (= |v_#valid_13| (store |v_#valid_14| |v_main_#t~malloc9.base_1| 1)) (= 0 (select |v_#valid_14| |v_main_#t~malloc9.base_1|)) (= |v_main_#t~malloc9.offset_1| 0)) InVars {#length=|v_#length_10|, main_~length1~3=v_main_~length1~3_6, #valid=|v_#valid_14|} OutVars{main_#t~malloc9.offset=|v_main_#t~malloc9.offset_1|, #length=|v_#length_9|, main_#t~malloc9.base=|v_main_#t~malloc9.base_1|, main_~length1~3=v_main_~length1~3_6, #valid=|v_#valid_13|} AuxVars[] AssignedVars[main_#t~malloc9.base, #valid, main_#t~malloc9.offset, #length]
[2018-01-28 23:21:49,812 INFO L84 mationBacktranslator]: Skipped ATE [421] [421] L563'-->L564: Formula: (and (= v_main_~nondetString1~3.base_1 |v_main_#t~malloc9.base_2|) (= v_main_~nondetString1~3.offset_1 |v_main_#t~malloc9.offset_2|)) InVars {main_#t~malloc9.offset=|v_main_#t~malloc9.offset_2|, main_#t~malloc9.base=|v_main_#t~malloc9.base_2|} OutVars{main_#t~malloc9.offset=|v_main_#t~malloc9.offset_2|, main_#t~malloc9.base=|v_main_#t~malloc9.base_2|, main_~nondetString1~3.offset=v_main_~nondetString1~3.offset_1, main_~nondetString1~3.base=v_main_~nondetString1~3.base_1} AuxVars[] AssignedVars[main_~nondetString1~3.offset, main_~nondetString1~3.base]
[2018-01-28 23:21:49,812 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L564-->L564': Formula: (and (= (store |v_#length_12| |v_main_#t~malloc10.base_1| v_main_~length2~3_7) |v_#length_11|) (= |v_#valid_15| (store |v_#valid_16| |v_main_#t~malloc10.base_1| 1)) (= (select |v_#valid_16| |v_main_#t~malloc10.base_1|) 0) (not (= 0 |v_main_#t~malloc10.base_1|)) (= |v_main_#t~malloc10.offset_1| 0)) InVars {main_~length2~3=v_main_~length2~3_7, #length=|v_#length_12|, #valid=|v_#valid_16|} OutVars{main_~length2~3=v_main_~length2~3_7, #length=|v_#length_11|, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_1|, main_#t~malloc10.base=|v_main_#t~malloc10.base_1|, #valid=|v_#valid_15|} AuxVars[] AssignedVars[#valid, #length, main_#t~malloc10.offset, main_#t~malloc10.base]
[2018-01-28 23:21:49,813 INFO L84 mationBacktranslator]: Skipped ATE [425] [425] L564'-->L565: Formula: (and (= v_main_~nondetString2~3.offset_1 |v_main_#t~malloc10.offset_2|) (= v_main_~nondetString2~3.base_1 |v_main_#t~malloc10.base_2|)) InVars {main_#t~malloc10.base=|v_main_#t~malloc10.base_2|, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_2|} OutVars{main_#t~malloc10.offset=|v_main_#t~malloc10.offset_2|, main_~nondetString2~3.offset=v_main_~nondetString2~3.offset_1, main_#t~malloc10.base=|v_main_#t~malloc10.base_2|, main_~nondetString2~3.base=v_main_~nondetString2~3.base_1} AuxVars[] AssignedVars[main_~nondetString2~3.offset, main_~nondetString2~3.base]
[2018-01-28 23:21:49,813 INFO L84 mationBacktranslator]: Skipped ATE [427] [427] L565-->L565': Formula: (let ((.cse0 (+ v_main_~length1~3_7 v_main_~nondetString1~3.offset_2))) (and (= 1 (select |v_#valid_17| v_main_~nondetString1~3.base_2)) (<= 1 .cse0) (= |v_#memory_int_part_locs_0_locs_0_1| |v_#memory_int_part_locs_0_locs_0_2|) (<= .cse0 (select |v_#length_13| v_main_~nondetString1~3.base_2)))) InVars {#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_1|, main_~length1~3=v_main_~length1~3_7, main_~nondetString1~3.offset=v_main_~nondetString1~3.offset_2, main_~nondetString1~3.base=v_main_~nondetString1~3.base_2, #valid=|v_#valid_17|, #length=|v_#length_13|} OutVars{#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_2|, main_~length1~3=v_main_~length1~3_7, main_~nondetString1~3.offset=v_main_~nondetString1~3.offset_2, main_~nondetString1~3.base=v_main_~nondetString1~3.base_2, #valid=|v_#valid_17|, #memory_int=|v_#memory_int_7|, #length=|v_#length_13|} AuxVars[] AssignedVars[#memory_int_part_locs_0_locs_0, #memory_int]
[2018-01-28 23:21:49,813 INFO L84 mationBacktranslator]: Skipped ATE [433] [433] L565'-->L566: Formula: (let ((.cse0 (+ v_main_~length3~3_7 v_main_~nondetString2~3.offset_2))) (and (<= 1 .cse0) (= |v_#memory_int_part_locs_0_locs_0_3| |v_#memory_int_part_locs_0_locs_0_4|) (= 1 (select |v_#valid_19| v_main_~nondetString2~3.base_2)) (<= .cse0 (select |v_#length_15| v_main_~nondetString2~3.base_2)))) InVars {#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_4|, main_~nondetString2~3.offset=v_main_~nondetString2~3.offset_2, #valid=|v_#valid_19|, #length=|v_#length_15|, main_~length3~3=v_main_~length3~3_7, main_~nondetString2~3.base=v_main_~nondetString2~3.base_2} OutVars{#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_3|, main_~nondetString2~3.offset=v_main_~nondetString2~3.offset_2, #valid=|v_#valid_19|, #memory_int=|v_#memory_int_9|, #length=|v_#length_15|, main_~length3~3=v_main_~length3~3_7, main_~nondetString2~3.base=v_main_~nondetString2~3.base_2} AuxVars[] AssignedVars[#memory_int_part_locs_0_locs_0, #memory_int]
[2018-01-28 23:21:49,813 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L566-->cstrcatENTRY: Formula: (and (= |v_cstrcat_#in~s1.baseInParam_1| v_main_~nondetString2~3.base_6) (= |v_cstrcat_#in~s2.baseInParam_1| v_main_~nondetString1~3.base_6) (= |v_cstrcat_#in~s1.offsetInParam_1| v_main_~nondetString2~3.offset_5) (= |v_cstrcat_#in~s2.offsetInParam_1| v_main_~nondetString1~3.offset_5)) InVars {main_~nondetString2~3.offset=v_main_~nondetString2~3.offset_5, main_~nondetString1~3.offset=v_main_~nondetString1~3.offset_5, main_~nondetString1~3.base=v_main_~nondetString1~3.base_6, main_~nondetString2~3.base=v_main_~nondetString2~3.base_6} OutVars{cstrcat_#in~s1.base=|v_cstrcat_#in~s1.baseInParam_1|, cstrcat_#in~s2.base=|v_cstrcat_#in~s2.baseInParam_1|, cstrcat_#in~s1.offset=|v_cstrcat_#in~s1.offsetInParam_1|, cstrcat_#in~s2.offset=|v_cstrcat_#in~s2.offsetInParam_1|} AuxVars[] AssignedVars[cstrcat_#in~s1.base, cstrcat_#in~s2.base, cstrcat_#in~s1.offset, cstrcat_#in~s2.offset]
[2018-01-28 23:21:49,813 INFO L84 mationBacktranslator]: Skipped ATE [445] [445] cstrcatENTRY-->L540: Formula: (and (= v_cstrcat_~s1.base_1 |v_cstrcat_#in~s1.base_1|) (= v_cstrcat_~s1.offset_1 |v_cstrcat_#in~s1.offset_1|)) InVars {cstrcat_#in~s1.offset=|v_cstrcat_#in~s1.offset_1|, cstrcat_#in~s1.base=|v_cstrcat_#in~s1.base_1|} OutVars{cstrcat_~s1.offset=v_cstrcat_~s1.offset_1, cstrcat_#in~s1.base=|v_cstrcat_#in~s1.base_1|, cstrcat_#in~s1.offset=|v_cstrcat_#in~s1.offset_1|, cstrcat_~s1.base=v_cstrcat_~s1.base_1} AuxVars[] AssignedVars[cstrcat_~s1.offset, cstrcat_~s1.base]
[2018-01-28 23:21:49,813 INFO L84 mationBacktranslator]: Skipped ATE [449] [449] L540-->L542: Formula: (and (= v_cstrcat_~s2.base_1 |v_cstrcat_#in~s2.base_1|) (= v_cstrcat_~s2.offset_1 |v_cstrcat_#in~s2.offset_1|)) InVars {cstrcat_#in~s2.offset=|v_cstrcat_#in~s2.offset_1|, cstrcat_#in~s2.base=|v_cstrcat_#in~s2.base_1|} OutVars{cstrcat_~s2.offset=v_cstrcat_~s2.offset_1, cstrcat_#in~s2.base=|v_cstrcat_#in~s2.base_1|, cstrcat_#in~s2.offset=|v_cstrcat_#in~s2.offset_1|, cstrcat_~s2.base=v_cstrcat_~s2.base_1} AuxVars[] AssignedVars[cstrcat_~s2.base, cstrcat_~s2.offset]
[2018-01-28 23:21:49,813 INFO L84 mationBacktranslator]: Skipped ATE [453] [453] L542-->L543''''': Formula: (and (= v_cstrcat_~s~2.base_1 v_cstrcat_~s1.base_2) (= v_cstrcat_~s~2.offset_1 v_cstrcat_~s1.offset_2)) InVars {cstrcat_~s1.offset=v_cstrcat_~s1.offset_2, cstrcat_~s1.base=v_cstrcat_~s1.base_2} OutVars{cstrcat_~s1.offset=v_cstrcat_~s1.offset_2, cstrcat_~s~2.base=v_cstrcat_~s~2.base_1, cstrcat_~s~2.offset=v_cstrcat_~s~2.offset_1, cstrcat_~s1.base=v_cstrcat_~s1.base_2} AuxVars[] AssignedVars[cstrcat_~s~2.base, cstrcat_~s~2.offset]
[2018-01-28 23:21:49,814 INFO L84 mationBacktranslator]: Skipped ATE [457] [457] L543'''''-->L543: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]
[2018-01-28 23:21:49,814 INFO L84 mationBacktranslator]: Skipped ATE [463] [463] L543-->L543': Formula: (and (<= (+ v_cstrcat_~s~2.offset_2 1) (select |v_#length_1| v_cstrcat_~s~2.base_2)) (= (select |v_#valid_3| v_cstrcat_~s~2.base_2) 1) (= |v_cstrcat_#t~mem0_1| (select (select |v_#memory_int_part_locs_0_locs_0_5| v_cstrcat_~s~2.base_2) v_cstrcat_~s~2.offset_2)) (<= 0 v_cstrcat_~s~2.offset_2)) InVars {#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_5|, #length=|v_#length_1|, cstrcat_~s~2.base=v_cstrcat_~s~2.base_2, cstrcat_~s~2.offset=v_cstrcat_~s~2.offset_2, #valid=|v_#valid_3|} OutVars{#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_5|, cstrcat_~s~2.base=v_cstrcat_~s~2.base_2, cstrcat_~s~2.offset=v_cstrcat_~s~2.offset_2, #valid=|v_#valid_3|, #length=|v_#length_1|, cstrcat_#t~mem0=|v_cstrcat_#t~mem0_1|} AuxVars[] AssignedVars[cstrcat_#t~mem0]
[2018-01-28 23:21:49,814 INFO L84 mationBacktranslator]: Skipped ATE [477] [477] L543'-->L543'''': Formula: (not (= |v_cstrcat_#t~mem0_4| 0)) InVars {cstrcat_#t~mem0=|v_cstrcat_#t~mem0_4|} OutVars{cstrcat_#t~mem0=|v_cstrcat_#t~mem0_4|} AuxVars[] AssignedVars[]
[2018-01-28 23:21:49,814 INFO L84 mationBacktranslator]: Skipped ATE [485] [485] L543''''-->L544: Formula: true InVars {} OutVars{cstrcat_#t~mem0=|v_cstrcat_#t~mem0_5|} AuxVars[] AssignedVars[cstrcat_#t~mem0]
[2018-01-28 23:21:49,814 INFO L84 mationBacktranslator]: Skipped ATE [491] [491] L544-->L544': Formula: (and (= |v_cstrcat_#t~post1.offset_1| v_cstrcat_~s~2.offset_4) (= |v_cstrcat_#t~post1.base_1| v_cstrcat_~s~2.base_5)) InVars {cstrcat_~s~2.base=v_cstrcat_~s~2.base_5, cstrcat_~s~2.offset=v_cstrcat_~s~2.offset_4} OutVars{cstrcat_#t~post1.base=|v_cstrcat_#t~post1.base_1|, cstrcat_~s~2.base=v_cstrcat_~s~2.base_5, cstrcat_~s~2.offset=v_cstrcat_~s~2.offset_4, cstrcat_#t~post1.offset=|v_cstrcat_#t~post1.offset_1|} AuxVars[] AssignedVars[cstrcat_#t~post1.base, cstrcat_#t~post1.offset]
[2018-01-28 23:21:49,814 INFO L84 mationBacktranslator]: Skipped ATE [495] [495] L544'-->L544'': Formula: (and (= v_cstrcat_~s~2.base_6 |v_cstrcat_#t~post1.base_2|) (= v_cstrcat_~s~2.offset_5 (+ |v_cstrcat_#t~post1.offset_2| 1))) InVars {cstrcat_#t~post1.base=|v_cstrcat_#t~post1.base_2|, cstrcat_#t~post1.offset=|v_cstrcat_#t~post1.offset_2|} OutVars{cstrcat_#t~post1.base=|v_cstrcat_#t~post1.base_2|, cstrcat_~s~2.base=v_cstrcat_~s~2.base_6, cstrcat_~s~2.offset=v_cstrcat_~s~2.offset_5, cstrcat_#t~post1.offset=|v_cstrcat_#t~post1.offset_2|} AuxVars[] AssignedVars[cstrcat_~s~2.base, cstrcat_~s~2.offset]
[2018-01-28 23:21:49,814 INFO L84 mationBacktranslator]: Skipped ATE [499] [499] L544''-->L543''''': Formula: true InVars {} OutVars{cstrcat_#t~post1.base=|v_cstrcat_#t~post1.base_3|, cstrcat_#t~post1.offset=|v_cstrcat_#t~post1.offset_3|} AuxVars[] AssignedVars[cstrcat_#t~post1.base, cstrcat_#t~post1.offset]
[2018-01-28 23:21:49,815 INFO L84 mationBacktranslator]: Skipped ATE [457] [457] L543'''''-->L543: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]
[2018-01-28 23:21:49,815 INFO L84 mationBacktranslator]: Skipped ATE [463] [463] L543-->L543': Formula: (and (<= (+ v_cstrcat_~s~2.offset_2 1) (select |v_#length_1| v_cstrcat_~s~2.base_2)) (= (select |v_#valid_3| v_cstrcat_~s~2.base_2) 1) (= |v_cstrcat_#t~mem0_1| (select (select |v_#memory_int_part_locs_0_locs_0_5| v_cstrcat_~s~2.base_2) v_cstrcat_~s~2.offset_2)) (<= 0 v_cstrcat_~s~2.offset_2)) InVars {#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_5|, #length=|v_#length_1|, cstrcat_~s~2.base=v_cstrcat_~s~2.base_2, cstrcat_~s~2.offset=v_cstrcat_~s~2.offset_2, #valid=|v_#valid_3|} OutVars{#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_5|, cstrcat_~s~2.base=v_cstrcat_~s~2.base_2, cstrcat_~s~2.offset=v_cstrcat_~s~2.offset_2, #valid=|v_#valid_3|, #length=|v_#length_1|, cstrcat_#t~mem0=|v_cstrcat_#t~mem0_1|} AuxVars[] AssignedVars[cstrcat_#t~mem0]
[2018-01-28 23:21:49,815 INFO L84 mationBacktranslator]: Skipped ATE [477] [477] L543'-->L543'''': Formula: (not (= |v_cstrcat_#t~mem0_4| 0)) InVars {cstrcat_#t~mem0=|v_cstrcat_#t~mem0_4|} OutVars{cstrcat_#t~mem0=|v_cstrcat_#t~mem0_4|} AuxVars[] AssignedVars[]
[2018-01-28 23:21:49,815 INFO L84 mationBacktranslator]: Skipped ATE [485] [485] L543''''-->L544: Formula: true InVars {} OutVars{cstrcat_#t~mem0=|v_cstrcat_#t~mem0_5|} AuxVars[] AssignedVars[cstrcat_#t~mem0]
[2018-01-28 23:21:49,815 INFO L84 mationBacktranslator]: Skipped ATE [491] [491] L544-->L544': Formula: (and (= |v_cstrcat_#t~post1.offset_1| v_cstrcat_~s~2.offset_4) (= |v_cstrcat_#t~post1.base_1| v_cstrcat_~s~2.base_5)) InVars {cstrcat_~s~2.base=v_cstrcat_~s~2.base_5, cstrcat_~s~2.offset=v_cstrcat_~s~2.offset_4} OutVars{cstrcat_#t~post1.base=|v_cstrcat_#t~post1.base_1|, cstrcat_~s~2.base=v_cstrcat_~s~2.base_5, cstrcat_~s~2.offset=v_cstrcat_~s~2.offset_4, cstrcat_#t~post1.offset=|v_cstrcat_#t~post1.offset_1|} AuxVars[] AssignedVars[cstrcat_#t~post1.base, cstrcat_#t~post1.offset]
[2018-01-28 23:21:49,815 INFO L84 mationBacktranslator]: Skipped ATE [495] [495] L544'-->L544'': Formula: (and (= v_cstrcat_~s~2.base_6 |v_cstrcat_#t~post1.base_2|) (= v_cstrcat_~s~2.offset_5 (+ |v_cstrcat_#t~post1.offset_2| 1))) InVars {cstrcat_#t~post1.base=|v_cstrcat_#t~post1.base_2|, cstrcat_#t~post1.offset=|v_cstrcat_#t~post1.offset_2|} OutVars{cstrcat_#t~post1.base=|v_cstrcat_#t~post1.base_2|, cstrcat_~s~2.base=v_cstrcat_~s~2.base_6, cstrcat_~s~2.offset=v_cstrcat_~s~2.offset_5, cstrcat_#t~post1.offset=|v_cstrcat_#t~post1.offset_2|} AuxVars[] AssignedVars[cstrcat_~s~2.base, cstrcat_~s~2.offset]
[2018-01-28 23:21:49,815 INFO L84 mationBacktranslator]: Skipped ATE [499] [499] L544''-->L543''''': Formula: true InVars {} OutVars{cstrcat_#t~post1.base=|v_cstrcat_#t~post1.base_3|, cstrcat_#t~post1.offset=|v_cstrcat_#t~post1.offset_3|} AuxVars[] AssignedVars[cstrcat_#t~post1.base, cstrcat_#t~post1.offset]
[2018-01-28 23:21:49,815 INFO L84 mationBacktranslator]: Skipped ATE [457] [457] L543'''''-->L543: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]
[2018-01-28 23:21:49,816 INFO L84 mationBacktranslator]: Skipped ATE [467] [467] L543-->cstrcatErr1RequiresViolation: Formula: (or (not (<= 0 v_cstrcat_~s~2.offset_3)) (not (<= (+ v_cstrcat_~s~2.offset_3 1) (select |v_#length_2| v_cstrcat_~s~2.base_4)))) InVars {#length=|v_#length_2|, cstrcat_~s~2.offset=v_cstrcat_~s~2.offset_3, cstrcat_~s~2.base=v_cstrcat_~s~2.base_4} OutVars{#length=|v_#length_2|, cstrcat_~s~2.offset=v_cstrcat_~s~2.offset_3, cstrcat_~s~2.base=v_cstrcat_~s~2.base_4} AuxVars[] AssignedVars[]
[2018-01-28 23:21:49,821 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.01 11:21:49 BasicIcfg
[2018-01-28 23:21:49,821 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction----------------------------
[2018-01-28 23:21:49,822 INFO L168 Benchmark]: Toolchain (without parser) took 88365.42 ms. Allocated memory was 301.5 MB in the beginning and 2.3 GB in the end (delta: 2.0 GB). Free memory was 261.5 MB in the beginning and 1.7 GB in the end (delta: -1.4 GB). Peak memory consumption was 549.7 MB. Max. memory is 5.3 GB.
[2018-01-28 23:21:49,823 INFO L168 Benchmark]: CDTParser took 0.23 ms. Allocated memory is still 301.5 MB. Free memory is still 267.5 MB. There was no memory consumed. Max. memory is 5.3 GB.
[2018-01-28 23:21:49,823 INFO L168 Benchmark]: CACSL2BoogieTranslator took 203.40 ms. Allocated memory is still 301.5 MB. Free memory was 260.5 MB in the beginning and 250.5 MB in the end (delta: 10.0 MB). Peak memory consumption was 10.0 MB. Max. memory is 5.3 GB.
[2018-01-28 23:21:49,824 INFO L168 Benchmark]: Boogie Preprocessor took 41.95 ms. Allocated memory is still 301.5 MB. Free memory was 250.5 MB in the beginning and 248.5 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB.
[2018-01-28 23:21:49,824 INFO L168 Benchmark]: RCFGBuilder took 327.43 ms. Allocated memory is still 301.5 MB. Free memory was 248.5 MB in the beginning and 227.8 MB in the end (delta: 20.7 MB). Peak memory consumption was 20.7 MB. Max. memory is 5.3 GB.
[2018-01-28 23:21:49,824 INFO L168 Benchmark]: IcfgTransformer took 84281.19 ms. Allocated memory was 301.5 MB in the beginning and 2.1 GB in the end (delta: 1.8 GB). Free memory was 227.8 MB in the beginning and 234.9 MB in the end (delta: -7.1 MB). Peak memory consumption was 1.8 GB. Max. memory is 5.3 GB.
[2018-01-28 23:21:49,825 INFO L168 Benchmark]: TraceAbstraction took 3504.45 ms. Allocated memory was 2.1 GB in the beginning and 2.3 GB in the end (delta: 119.5 MB). Free memory was 234.9 MB in the beginning and 1.7 GB in the end (delta: -1.4 GB). There was no memory consumed. Max. memory is 5.3 GB.
[2018-01-28 23:21:49,826 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] #######################
--- Results ---
* Results from de.uni_freiburg.informatik.ultimate.core:
- StatisticsResult: Toolchain Benchmarks
Benchmark results are:
* CDTParser took 0.23 ms. Allocated memory is still 301.5 MB. Free memory is still 267.5 MB. There was no memory consumed. Max. memory is 5.3 GB.
* CACSL2BoogieTranslator took 203.40 ms. Allocated memory is still 301.5 MB. Free memory was 260.5 MB in the beginning and 250.5 MB in the end (delta: 10.0 MB). Peak memory consumption was 10.0 MB. Max. memory is 5.3 GB.
* Boogie Preprocessor took 41.95 ms. Allocated memory is still 301.5 MB. Free memory was 250.5 MB in the beginning and 248.5 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB.
* RCFGBuilder took 327.43 ms. Allocated memory is still 301.5 MB. Free memory was 248.5 MB in the beginning and 227.8 MB in the end (delta: 20.7 MB). Peak memory consumption was 20.7 MB. Max. memory is 5.3 GB.
* IcfgTransformer took 84281.19 ms. Allocated memory was 301.5 MB in the beginning and 2.1 GB in the end (delta: 1.8 GB). Free memory was 227.8 MB in the beginning and 234.9 MB in the end (delta: -7.1 MB). Peak memory consumption was 1.8 GB. Max. memory is 5.3 GB.
* TraceAbstraction took 3504.45 ms. Allocated memory was 2.1 GB in the beginning and 2.3 GB in the end (delta: 119.5 MB). Free memory was 234.9 MB in the beginning and 1.7 GB in the end (delta: -1.4 GB). There was no memory consumed. Max. memory is 5.3 GB.
* Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2:
- StatisticsResult: ArrayEqualityDomainStatistics
#Locations : 73
LocStat_MAX_WEQGRAPH_SIZE : 5
LocStat_MAX_SIZEOF_WEQEDGELABEL : 3
LocStat_NO_SUPPORTING_EQUALITIES : 1069
LocStat_NO_SUPPORTING_DISEQUALITIES : 450
LocStat_NO_DISJUNCTIONS : -146
LocStat_MAX_NO_DISJUNCTIONS : -1
#Transitions : 98
TransStat_MAX_WEQGRAPH_SIZE : 2
TransStat_MAX_SIZEOF_WEQEDGELABEL : 1
TransStat_NO_SUPPORTING_EQUALITIES : 120
TransStat_NO_SUPPORTING_DISEQUALITIES : 12
TransStat_NO_DISJUNCTIONS : 101
TransStat_MAX_NO_DISJUNCTIONS : 2
- StatisticsResult: EqConstraintFactoryStatistics
CONJOIN_DISJUNCTIVE(MILLISECONDS) : 7.608823
RENAME_VARIABLES(MILLISECONDS) : 0.675444
UNFREEZE(MILLISECONDS) : 0.000000
CONJOIN(MILLISECONDS) : 3.798415
PROJECTAWAY(MILLISECONDS) : 0.083439
ADD_WEAK_EQUALITY(MILLISECONDS) : 0.037068
DISJOIN(MILLISECONDS) : 0.125525
RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.693289
ADD_EQUALITY(MILLISECONDS) : 0.008388
DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000
ADD_DISEQUALITY(MILLISECONDS) : 0.019610
#CONJOIN_DISJUNCTIVE : 1912
#RENAME_VARIABLES : 4189
#UNFREEZE : 0
#CONJOIN : 2499
#PROJECTAWAY : 2319
#ADD_WEAK_EQUALITY : 13
#DISJOIN : 543
#RENAME_VARIABLES_DISJUNCTIVE : 4099
#ADD_EQUALITY : 123
#DISJOIN_DISJUNCTIVE : 0
#ADD_DISEQUALITY : 10
* Results from de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation:
- StatisticsResult: HeapSeparatorStatistics
COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_0 : 1
COUNT_BLOCKS_for_[#memory_int]_at_dim_0 : 1
COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_1 : 1
COUNT_BLOCKS_for_[#memory_int]_at_dim_1 : 1
COUNT_ARRAY_READS for [#memory_int] : 5
* Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction:
- CounterExampleResult [Line: 1]: pointer dereference may fail
pointer dereference may fail
We found a FailurePath:
- StatisticsResult: Ultimate Automizer benchmark data
CFG has 4 procedures, 79 locations, 11 error locations. UNSAFE Result, 3.4s OverallTime, 15 OverallIterations, 3 TraceHistogramMax, 1.5s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 850 SDtfs, 791 SDslu, 2124 SDs, 0 SdLazy, 966 SolverSat, 48 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 146 GetRequests, 44 SyntacticMatches, 5 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 66 ImplicationChecksByTransitivity, 1.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=79occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 14 MinimizatonAttempts, 29 StatesRemovedByMinimization, 5 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.1s SatisfiabilityAnalysisTime, 1.2s InterpolantComputationTime, 467 NumberOfCodeBlocks, 467 NumberOfCodeBlocksAsserted, 16 NumberOfCheckSat, 411 ConstructedInterpolants, 0 QuantifiedInterpolants, 47961 SizeOfPredicates, 11 NumberOfNonLiveVariables, 104 ConjunctsInSsa, 29 ConjunctsInUnsatCore, 15 InterpolantComputations, 13 PerfectInterpolantSequences, 2/6 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available
RESULT: Ultimate proved your program to be incorrect!
Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrcat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-Benchmark-0-2018-01-28_23-21-49-836.csv
Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrcat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-VPDomainBenchmark-0-2018-01-28_23-21-49-836.csv
Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrcat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-0-2018-01-28_23-21-49-836.csv
Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrcat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-HeapSeparatorBenchmark-0-2018-01-28_23-21-49-836.csv
Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrcat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-28_23-21-49-836.csv
Received shutdown request...