java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/memsafety/960521-1_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 12:59:20,817 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 12:59:20,819 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 12:59:20,834 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 12:59:20,834 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 12:59:20,835 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 12:59:20,836 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 12:59:20,838 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 12:59:20,840 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 12:59:20,841 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 12:59:20,842 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 12:59:20,842 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 12:59:20,843 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 12:59:20,844 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 12:59:20,845 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 12:59:20,848 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 12:59:20,850 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 12:59:20,852 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 12:59:20,853 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 12:59:20,854 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 12:59:20,856 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 12:59:20,857 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 12:59:20,857 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 12:59:20,858 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 12:59:20,859 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 12:59:20,860 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 12:59:20,860 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 12:59:20,861 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 12:59:20,861 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 12:59:20,861 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 12:59:20,862 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 12:59:20,862 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf [2018-01-24 12:59:20,871 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 12:59:20,871 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 12:59:20,872 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 12:59:20,872 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 12:59:20,872 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 12:59:20,872 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 12:59:20,873 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 12:59:20,873 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 12:59:20,873 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 12:59:20,873 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 12:59:20,873 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 12:59:20,873 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 12:59:20,874 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 12:59:20,874 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 12:59:20,874 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 12:59:20,874 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 12:59:20,874 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 12:59:20,874 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 12:59:20,874 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 12:59:20,875 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 12:59:20,875 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 12:59:20,875 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 12:59:20,875 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 12:59:20,875 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 12:59:20,876 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 12:59:20,876 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 12:59:20,876 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 12:59:20,876 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 12:59:20,876 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-01-24 12:59:20,876 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 12:59:20,877 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 12:59:20,877 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 12:59:20,877 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 12:59:20,877 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 12:59:20,908 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 12:59:20,919 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 12:59:20,923 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 12:59:20,924 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 12:59:20,924 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 12:59:20,925 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/memsafety/960521-1_false-valid-deref.i [2018-01-24 12:59:21,093 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 12:59:21,098 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 12:59:21,098 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 12:59:21,099 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 12:59:21,104 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 12:59:21,105 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 12:59:21" (1/1) ... [2018-01-24 12:59:21,108 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@53037d43 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:59:21, skipping insertion in model container [2018-01-24 12:59:21,108 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 12:59:21" (1/1) ... [2018-01-24 12:59:21,121 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 12:59:21,160 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 12:59:21,280 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 12:59:21,297 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 12:59:21,305 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:59:21 WrapperNode [2018-01-24 12:59:21,305 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 12:59:21,306 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 12:59:21,306 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 12:59:21,306 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 12:59:21,322 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:59:21" (1/1) ... [2018-01-24 12:59:21,323 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:59:21" (1/1) ... [2018-01-24 12:59:21,332 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:59:21" (1/1) ... [2018-01-24 12:59:21,333 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:59:21" (1/1) ... [2018-01-24 12:59:21,337 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:59:21" (1/1) ... [2018-01-24 12:59:21,340 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:59:21" (1/1) ... [2018-01-24 12:59:21,341 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:59:21" (1/1) ... [2018-01-24 12:59:21,343 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 12:59:21,343 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 12:59:21,343 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 12:59:21,344 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 12:59:21,345 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:59:21" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 12:59:21,390 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 12:59:21,390 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 12:59:21,391 INFO L136 BoogieDeclarations]: Found implementation of procedure foo [2018-01-24 12:59:21,391 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 12:59:21,391 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 12:59:21,391 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 12:59:21,391 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 12:59:21,391 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 12:59:21,391 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 12:59:21,391 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-01-24 12:59:21,391 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-01-24 12:59:21,391 INFO L128 BoogieDeclarations]: Found specification of procedure foo [2018-01-24 12:59:21,392 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 12:59:21,392 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 12:59:21,392 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 12:59:21,618 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 12:59:21,619 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 12:59:21 BoogieIcfgContainer [2018-01-24 12:59:21,619 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 12:59:21,619 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 12:59:21,620 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 12:59:21,622 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 12:59:21,622 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 12:59:21" (1/3) ... [2018-01-24 12:59:21,623 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@32ebad9a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 12:59:21, skipping insertion in model container [2018-01-24 12:59:21,623 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:59:21" (2/3) ... [2018-01-24 12:59:21,623 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@32ebad9a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 12:59:21, skipping insertion in model container [2018-01-24 12:59:21,623 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 12:59:21" (3/3) ... [2018-01-24 12:59:21,625 INFO L105 eAbstractionObserver]: Analyzing ICFG 960521-1_false-valid-deref.i [2018-01-24 12:59:21,631 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 12:59:21,637 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 17 error locations. [2018-01-24 12:59:21,684 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 12:59:21,684 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 12:59:21,685 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 12:59:21,685 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 12:59:21,685 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 12:59:21,685 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 12:59:21,685 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 12:59:21,685 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 12:59:21,686 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 12:59:21,707 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states. [2018-01-24 12:59:21,713 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-01-24 12:59:21,713 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:21,714 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:21,715 INFO L371 AbstractCegarLoop]: === Iteration 1 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:21,720 INFO L82 PathProgramCache]: Analyzing trace with hash 1993989713, now seen corresponding path program 1 times [2018-01-24 12:59:21,724 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:21,770 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:21,770 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:21,771 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:21,771 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:21,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:21,834 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:21,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:21,922 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:59:21,922 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 12:59:21,923 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 12:59:21,925 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 12:59:21,935 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 12:59:21,936 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 12:59:21,938 INFO L87 Difference]: Start difference. First operand 53 states. Second operand 4 states. [2018-01-24 12:59:22,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:22,188 INFO L93 Difference]: Finished difference Result 84 states and 90 transitions. [2018-01-24 12:59:22,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 12:59:22,190 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2018-01-24 12:59:22,191 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:22,201 INFO L225 Difference]: With dead ends: 84 [2018-01-24 12:59:22,202 INFO L226 Difference]: Without dead ends: 49 [2018-01-24 12:59:22,205 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 12:59:22,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-01-24 12:59:22,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2018-01-24 12:59:22,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-01-24 12:59:22,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 51 transitions. [2018-01-24 12:59:22,233 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 51 transitions. Word has length 11 [2018-01-24 12:59:22,233 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:22,233 INFO L432 AbstractCegarLoop]: Abstraction has 49 states and 51 transitions. [2018-01-24 12:59:22,234 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 12:59:22,234 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 51 transitions. [2018-01-24 12:59:22,234 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-01-24 12:59:22,234 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:22,234 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:22,234 INFO L371 AbstractCegarLoop]: === Iteration 2 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:22,235 INFO L82 PathProgramCache]: Analyzing trace with hash 1993989714, now seen corresponding path program 1 times [2018-01-24 12:59:22,235 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:22,236 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:22,236 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:22,236 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:22,237 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:22,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:22,258 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:22,361 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:22,361 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:59:22,361 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 12:59:22,361 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 12:59:22,363 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 12:59:22,363 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 12:59:22,364 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 12:59:22,364 INFO L87 Difference]: Start difference. First operand 49 states and 51 transitions. Second operand 5 states. [2018-01-24 12:59:22,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:22,458 INFO L93 Difference]: Finished difference Result 49 states and 51 transitions. [2018-01-24 12:59:22,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 12:59:22,459 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 11 [2018-01-24 12:59:22,459 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:22,460 INFO L225 Difference]: With dead ends: 49 [2018-01-24 12:59:22,460 INFO L226 Difference]: Without dead ends: 48 [2018-01-24 12:59:22,461 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-01-24 12:59:22,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-01-24 12:59:22,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2018-01-24 12:59:22,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-01-24 12:59:22,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 50 transitions. [2018-01-24 12:59:22,469 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 50 transitions. Word has length 11 [2018-01-24 12:59:22,469 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:22,469 INFO L432 AbstractCegarLoop]: Abstraction has 48 states and 50 transitions. [2018-01-24 12:59:22,469 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 12:59:22,469 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 50 transitions. [2018-01-24 12:59:22,470 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 12:59:22,470 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:22,470 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:22,470 INFO L371 AbstractCegarLoop]: === Iteration 3 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:22,471 INFO L82 PathProgramCache]: Analyzing trace with hash -1188525484, now seen corresponding path program 1 times [2018-01-24 12:59:22,471 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:22,472 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:22,472 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:22,472 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:22,472 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:22,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:22,495 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:22,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:22,611 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:59:22,611 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 12:59:22,611 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 12:59:22,612 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 12:59:22,612 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 12:59:22,612 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 12:59:22,612 INFO L87 Difference]: Start difference. First operand 48 states and 50 transitions. Second operand 6 states. [2018-01-24 12:59:22,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:22,753 INFO L93 Difference]: Finished difference Result 48 states and 50 transitions. [2018-01-24 12:59:22,754 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 12:59:22,754 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-01-24 12:59:22,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:22,755 INFO L225 Difference]: With dead ends: 48 [2018-01-24 12:59:22,755 INFO L226 Difference]: Without dead ends: 45 [2018-01-24 12:59:22,755 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-01-24 12:59:22,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2018-01-24 12:59:22,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2018-01-24 12:59:22,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-01-24 12:59:22,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 47 transitions. [2018-01-24 12:59:22,763 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 47 transitions. Word has length 17 [2018-01-24 12:59:22,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:22,763 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 47 transitions. [2018-01-24 12:59:22,763 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 12:59:22,763 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 47 transitions. [2018-01-24 12:59:22,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 12:59:22,764 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:22,764 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:22,764 INFO L371 AbstractCegarLoop]: === Iteration 4 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:22,765 INFO L82 PathProgramCache]: Analyzing trace with hash -1188525483, now seen corresponding path program 1 times [2018-01-24 12:59:22,765 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:22,766 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:22,766 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:22,766 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:22,766 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:22,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:22,785 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:22,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:22,922 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:59:22,922 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 12:59:22,922 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 12:59:22,922 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 12:59:22,922 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 12:59:22,923 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-01-24 12:59:22,923 INFO L87 Difference]: Start difference. First operand 45 states and 47 transitions. Second operand 7 states. [2018-01-24 12:59:23,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:23,062 INFO L93 Difference]: Finished difference Result 80 states and 87 transitions. [2018-01-24 12:59:23,062 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 12:59:23,062 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 17 [2018-01-24 12:59:23,063 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:23,063 INFO L225 Difference]: With dead ends: 80 [2018-01-24 12:59:23,063 INFO L226 Difference]: Without dead ends: 53 [2018-01-24 12:59:23,064 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-01-24 12:59:23,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2018-01-24 12:59:23,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 48. [2018-01-24 12:59:23,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-01-24 12:59:23,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 50 transitions. [2018-01-24 12:59:23,072 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 50 transitions. Word has length 17 [2018-01-24 12:59:23,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:23,073 INFO L432 AbstractCegarLoop]: Abstraction has 48 states and 50 transitions. [2018-01-24 12:59:23,073 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 12:59:23,073 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 50 transitions. [2018-01-24 12:59:23,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-01-24 12:59:23,073 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:23,073 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:23,074 INFO L371 AbstractCegarLoop]: === Iteration 5 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:23,074 INFO L82 PathProgramCache]: Analyzing trace with hash -2106816852, now seen corresponding path program 1 times [2018-01-24 12:59:23,074 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:23,075 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:23,075 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:23,075 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:23,075 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:23,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:23,094 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:23,261 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:23,261 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:23,262 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:23,273 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:23,273 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:59:23,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:23,303 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:23,337 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 12:59:23,340 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:23,351 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:23,351 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:15, output treesize:14 [2018-01-24 12:59:23,374 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-01-24 12:59:23,375 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:23,395 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 12:59:23,395 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:22, output treesize:21 [2018-01-24 12:59:23,532 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:23,533 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:24,007 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 12:59:24,022 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 5 [2018-01-24 12:59:24,022 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:24,023 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:24,025 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:24,026 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:15, output treesize:5 [2018-01-24 12:59:24,066 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:24,096 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:24,097 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:24,101 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:24,101 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:59:24,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:24,138 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:24,144 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 12:59:24,145 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:24,151 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 12:59:24,152 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:24,156 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:24,157 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-01-24 12:59:24,191 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:59:24,193 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 12:59:24,193 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:24,203 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:59:24,204 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:59:24,204 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 12:59:24,205 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:24,212 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 12:59:24,212 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:32, output treesize:25 [2018-01-24 12:59:24,328 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:24,329 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:24,452 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-01-24 12:59:24,453 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:24,456 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 12:59:24,466 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 1 [2018-01-24 12:59:24,467 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:24,468 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:24,470 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:24,470 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:25, output treesize:5 [2018-01-24 12:59:24,474 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:24,476 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:24,476 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8, 7, 7, 7] total 24 [2018-01-24 12:59:24,476 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:24,476 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 12:59:24,477 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 12:59:24,477 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=477, Unknown=1, NotChecked=0, Total=600 [2018-01-24 12:59:24,477 INFO L87 Difference]: Start difference. First operand 48 states and 50 transitions. Second operand 12 states. [2018-01-24 12:59:24,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:24,718 INFO L93 Difference]: Finished difference Result 90 states and 95 transitions. [2018-01-24 12:59:24,719 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 12:59:24,719 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 21 [2018-01-24 12:59:24,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:24,720 INFO L225 Difference]: With dead ends: 90 [2018-01-24 12:59:24,720 INFO L226 Difference]: Without dead ends: 63 [2018-01-24 12:59:24,721 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 64 SyntacticMatches, 4 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 232 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=162, Invalid=593, Unknown=1, NotChecked=0, Total=756 [2018-01-24 12:59:24,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-01-24 12:59:24,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 56. [2018-01-24 12:59:24,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2018-01-24 12:59:24,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 60 transitions. [2018-01-24 12:59:24,728 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 60 transitions. Word has length 21 [2018-01-24 12:59:24,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:24,729 INFO L432 AbstractCegarLoop]: Abstraction has 56 states and 60 transitions. [2018-01-24 12:59:24,729 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 12:59:24,729 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 60 transitions. [2018-01-24 12:59:24,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-24 12:59:24,730 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:24,730 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:24,730 INFO L371 AbstractCegarLoop]: === Iteration 6 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:24,730 INFO L82 PathProgramCache]: Analyzing trace with hash -702775421, now seen corresponding path program 2 times [2018-01-24 12:59:24,730 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:24,731 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:24,732 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:24,732 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:24,732 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:24,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:24,748 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:25,000 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:25,000 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:25,000 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:25,007 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:59:25,008 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:25,022 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:25,025 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:25,026 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:25,028 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:25,033 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 12:59:25,033 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,038 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 12:59:25,039 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,043 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,043 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-01-24 12:59:25,070 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:59:25,070 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:59:25,071 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 12:59:25,071 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,079 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 12:59:25,080 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,086 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 12:59:25,086 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:32, output treesize:25 [2018-01-24 12:59:25,298 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:25,298 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:25,481 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-01-24 12:59:25,481 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,485 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 12:59:25,498 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 1 [2018-01-24 12:59:25,498 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,499 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,519 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,519 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:25, output treesize:5 [2018-01-24 12:59:25,540 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:25,560 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:25,560 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:25,563 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:59:25,564 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:25,583 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:25,612 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:25,623 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:25,627 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:25,631 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 12:59:25,631 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,644 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 12:59:25,645 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,660 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,660 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-01-24 12:59:25,665 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:59:25,666 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 12:59:25,666 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,679 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:59:25,679 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:59:25,680 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 12:59:25,680 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,690 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 12:59:25,690 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:32, output treesize:25 [2018-01-24 12:59:25,733 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:25,733 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:25,793 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-01-24 12:59:25,793 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,797 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 12:59:25,808 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 5 [2018-01-24 12:59:25,808 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,810 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,835 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:25,835 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:25, output treesize:5 [2018-01-24 12:59:25,841 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:25,844 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:25,844 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8, 8, 8] total 23 [2018-01-24 12:59:25,844 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:25,845 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 12:59:25,845 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 12:59:25,845 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=442, Unknown=0, NotChecked=0, Total=552 [2018-01-24 12:59:25,846 INFO L87 Difference]: Start difference. First operand 56 states and 60 transitions. Second operand 17 states. [2018-01-24 12:59:26,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:26,389 INFO L93 Difference]: Finished difference Result 104 states and 111 transitions. [2018-01-24 12:59:26,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 12:59:26,389 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 25 [2018-01-24 12:59:26,389 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:26,390 INFO L225 Difference]: With dead ends: 104 [2018-01-24 12:59:26,390 INFO L226 Difference]: Without dead ends: 73 [2018-01-24 12:59:26,391 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 83 SyntacticMatches, 3 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 257 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=208, Invalid=722, Unknown=0, NotChecked=0, Total=930 [2018-01-24 12:59:26,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-01-24 12:59:26,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 64. [2018-01-24 12:59:26,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-01-24 12:59:26,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 70 transitions. [2018-01-24 12:59:26,400 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 70 transitions. Word has length 25 [2018-01-24 12:59:26,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:26,400 INFO L432 AbstractCegarLoop]: Abstraction has 64 states and 70 transitions. [2018-01-24 12:59:26,400 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 12:59:26,400 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 70 transitions. [2018-01-24 12:59:26,401 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-01-24 12:59:26,401 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:26,401 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:26,401 INFO L371 AbstractCegarLoop]: === Iteration 7 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:26,402 INFO L82 PathProgramCache]: Analyzing trace with hash 1827026138, now seen corresponding path program 3 times [2018-01-24 12:59:26,402 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:26,403 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:26,403 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:26,403 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:26,403 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:26,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:26,419 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:26,663 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:26,663 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:26,663 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:26,672 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:26,673 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:26,686 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:26,690 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:26,691 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:26,694 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:26,698 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 12:59:26,699 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:26,705 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 12:59:26,705 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:26,709 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:26,710 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-01-24 12:59:26,734 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:59:26,735 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:59:26,735 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 12:59:26,736 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:26,749 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 12:59:26,750 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:26,754 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:26,755 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:29, output treesize:22 [2018-01-24 12:59:26,878 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 12:59:26,878 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:27,081 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 12:59:27,101 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:27,101 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:27,104 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:27,105 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:27,123 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:27,151 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:27,162 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:27,166 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:27,186 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 12:59:27,186 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:27,194 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 12:59:27,194 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:27,198 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:27,198 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-01-24 12:59:27,238 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:59:27,239 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:59:27,245 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 12:59:27,245 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:27,252 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 12:59:27,252 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:27,258 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 12:59:27,258 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:29, output treesize:22 [2018-01-24 12:59:27,424 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 12:59:27,424 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:28,013 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 12:59:28,015 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:28,015 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8, 7, 7, 7] total 29 [2018-01-24 12:59:28,015 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:28,015 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 12:59:28,015 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 12:59:28,016 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=730, Unknown=0, NotChecked=0, Total=870 [2018-01-24 12:59:28,016 INFO L87 Difference]: Start difference. First operand 64 states and 70 transitions. Second operand 18 states. [2018-01-24 12:59:28,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:28,961 INFO L93 Difference]: Finished difference Result 125 states and 137 transitions. [2018-01-24 12:59:28,961 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 12:59:28,962 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2018-01-24 12:59:28,962 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:28,965 INFO L225 Difference]: With dead ends: 125 [2018-01-24 12:59:28,965 INFO L226 Difference]: Without dead ends: 90 [2018-01-24 12:59:28,966 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 92 SyntacticMatches, 5 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 461 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=338, Invalid=1302, Unknown=0, NotChecked=0, Total=1640 [2018-01-24 12:59:28,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-01-24 12:59:28,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 70. [2018-01-24 12:59:28,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-01-24 12:59:28,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 76 transitions. [2018-01-24 12:59:28,977 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 76 transitions. Word has length 29 [2018-01-24 12:59:28,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:28,978 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 76 transitions. [2018-01-24 12:59:28,978 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 12:59:28,978 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 76 transitions. [2018-01-24 12:59:28,979 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-01-24 12:59:28,979 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:28,979 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:28,980 INFO L371 AbstractCegarLoop]: === Iteration 8 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:28,980 INFO L82 PathProgramCache]: Analyzing trace with hash -645884181, now seen corresponding path program 1 times [2018-01-24 12:59:28,980 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:28,981 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:28,981 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:28,981 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:28,981 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:28,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:28,996 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:29,193 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:29,194 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:29,194 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:29,206 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:29,206 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:59:29,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:29,233 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:29,475 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:29,476 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:29,585 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:29,607 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:29,607 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:29,615 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:29,615 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:59:29,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:29,674 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:29,682 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:29,682 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:29,708 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:29,709 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:29,710 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 22 [2018-01-24 12:59:29,710 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:29,710 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 12:59:29,710 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 12:59:29,711 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=199, Invalid=263, Unknown=0, NotChecked=0, Total=462 [2018-01-24 12:59:29,711 INFO L87 Difference]: Start difference. First operand 70 states and 76 transitions. Second operand 15 states. [2018-01-24 12:59:29,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:29,845 INFO L93 Difference]: Finished difference Result 136 states and 147 transitions. [2018-01-24 12:59:29,846 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 12:59:29,846 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 40 [2018-01-24 12:59:29,846 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:29,847 INFO L225 Difference]: With dead ends: 136 [2018-01-24 12:59:29,847 INFO L226 Difference]: Without dead ends: 102 [2018-01-24 12:59:29,848 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 167 GetRequests, 147 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 164 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=199, Invalid=263, Unknown=0, NotChecked=0, Total=462 [2018-01-24 12:59:29,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-01-24 12:59:29,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 86. [2018-01-24 12:59:29,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-01-24 12:59:29,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 98 transitions. [2018-01-24 12:59:29,859 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 98 transitions. Word has length 40 [2018-01-24 12:59:29,859 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:29,860 INFO L432 AbstractCegarLoop]: Abstraction has 86 states and 98 transitions. [2018-01-24 12:59:29,860 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 12:59:29,860 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 98 transitions. [2018-01-24 12:59:29,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-24 12:59:29,861 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:29,861 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:29,861 INFO L371 AbstractCegarLoop]: === Iteration 9 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:29,861 INFO L82 PathProgramCache]: Analyzing trace with hash -2113361740, now seen corresponding path program 2 times [2018-01-24 12:59:29,861 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:29,862 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:29,862 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:29,863 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:29,863 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:29,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:29,875 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:29,969 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:29,969 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:29,970 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:29,979 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:59:29,979 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:29,997 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:30,000 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:30,003 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:30,010 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 12:59:30,010 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:30,014 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 12:59:30,014 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:15, output treesize:14 [2018-01-24 12:59:30,149 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 12:59:30,149 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:30,371 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 12:59:30,392 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 12:59:30,392 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7, 7] imperfect sequences [10] total 20 [2018-01-24 12:59:30,392 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 12:59:30,393 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 12:59:30,393 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 12:59:30,393 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=305, Unknown=0, NotChecked=0, Total=380 [2018-01-24 12:59:30,393 INFO L87 Difference]: Start difference. First operand 86 states and 98 transitions. Second operand 8 states. [2018-01-24 12:59:30,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:30,623 INFO L93 Difference]: Finished difference Result 86 states and 98 transitions. [2018-01-24 12:59:30,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 12:59:30,624 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 44 [2018-01-24 12:59:30,624 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:30,626 INFO L225 Difference]: With dead ends: 86 [2018-01-24 12:59:30,626 INFO L226 Difference]: Without dead ends: 73 [2018-01-24 12:59:30,626 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 78 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 120 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=138, Invalid=564, Unknown=0, NotChecked=0, Total=702 [2018-01-24 12:59:30,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-01-24 12:59:30,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2018-01-24 12:59:30,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-01-24 12:59:30,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 79 transitions. [2018-01-24 12:59:30,640 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 79 transitions. Word has length 44 [2018-01-24 12:59:30,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:30,641 INFO L432 AbstractCegarLoop]: Abstraction has 73 states and 79 transitions. [2018-01-24 12:59:30,641 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 12:59:30,641 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 79 transitions. [2018-01-24 12:59:30,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-24 12:59:30,642 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:30,642 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:30,642 INFO L371 AbstractCegarLoop]: === Iteration 10 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:30,643 INFO L82 PathProgramCache]: Analyzing trace with hash -2113361741, now seen corresponding path program 1 times [2018-01-24 12:59:30,643 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:30,643 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:30,644 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:30,644 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:30,644 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:30,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:30,654 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:30,698 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 12:59:30,698 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:59:30,698 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 12:59:30,698 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 12:59:30,699 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 12:59:30,699 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 12:59:30,699 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 12:59:30,699 INFO L87 Difference]: Start difference. First operand 73 states and 79 transitions. Second operand 4 states. [2018-01-24 12:59:30,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:30,735 INFO L93 Difference]: Finished difference Result 73 states and 79 transitions. [2018-01-24 12:59:30,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 12:59:30,735 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 44 [2018-01-24 12:59:30,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:30,736 INFO L225 Difference]: With dead ends: 73 [2018-01-24 12:59:30,736 INFO L226 Difference]: Without dead ends: 71 [2018-01-24 12:59:30,736 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 12:59:30,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-01-24 12:59:30,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 71. [2018-01-24 12:59:30,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-01-24 12:59:30,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 72 transitions. [2018-01-24 12:59:30,744 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 72 transitions. Word has length 44 [2018-01-24 12:59:30,744 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:30,744 INFO L432 AbstractCegarLoop]: Abstraction has 71 states and 72 transitions. [2018-01-24 12:59:30,744 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 12:59:30,744 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 72 transitions. [2018-01-24 12:59:30,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-01-24 12:59:30,746 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:30,746 INFO L322 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:30,746 INFO L371 AbstractCegarLoop]: === Iteration 11 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:30,746 INFO L82 PathProgramCache]: Analyzing trace with hash -747893621, now seen corresponding path program 1 times [2018-01-24 12:59:30,746 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:30,747 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:30,747 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:30,747 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:30,747 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:30,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:30,762 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:30,864 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 12:59:30,864 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:30,864 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:30,872 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:30,872 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:59:30,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:30,899 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:31,005 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 12:59:31,005 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:31,202 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 12:59:31,234 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:31,234 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:31,239 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:31,239 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:59:31,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:31,302 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:31,311 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 12:59:31,312 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:31,381 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 12:59:31,383 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:31,383 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 11, 10, 11] total 26 [2018-01-24 12:59:31,383 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:31,384 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 12:59:31,384 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 12:59:31,384 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=238, Invalid=412, Unknown=0, NotChecked=0, Total=650 [2018-01-24 12:59:31,384 INFO L87 Difference]: Start difference. First operand 71 states and 72 transitions. Second operand 18 states. [2018-01-24 12:59:31,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:31,559 INFO L93 Difference]: Finished difference Result 114 states and 117 transitions. [2018-01-24 12:59:31,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 12:59:31,559 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 70 [2018-01-24 12:59:31,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:31,560 INFO L225 Difference]: With dead ends: 114 [2018-01-24 12:59:31,560 INFO L226 Difference]: Without dead ends: 83 [2018-01-24 12:59:31,561 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 290 GetRequests, 261 SyntacticMatches, 4 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 227 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=263, Invalid=439, Unknown=0, NotChecked=0, Total=702 [2018-01-24 12:59:31,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-01-24 12:59:31,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 79. [2018-01-24 12:59:31,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-01-24 12:59:31,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 80 transitions. [2018-01-24 12:59:31,573 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 80 transitions. Word has length 70 [2018-01-24 12:59:31,573 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:31,573 INFO L432 AbstractCegarLoop]: Abstraction has 79 states and 80 transitions. [2018-01-24 12:59:31,573 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 12:59:31,573 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 80 transitions. [2018-01-24 12:59:31,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-24 12:59:31,574 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:31,575 INFO L322 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:31,575 INFO L371 AbstractCegarLoop]: === Iteration 12 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:31,575 INFO L82 PathProgramCache]: Analyzing trace with hash 1885472427, now seen corresponding path program 2 times [2018-01-24 12:59:31,575 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:31,576 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:31,576 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:31,576 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:31,576 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:31,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:31,591 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:31,943 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 12:59:31,943 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:31,943 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:31,952 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:59:31,952 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:31,968 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:31,989 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:32,002 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:32,005 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:32,227 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 12:59:32,227 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:32,417 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 12:59:32,439 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:32,439 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:32,443 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:59:32,443 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:32,466 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:32,509 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:32,527 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:32,532 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:32,546 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 12:59:32,546 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:32,634 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 12:59:32,636 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:32,636 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 12, 11, 12] total 29 [2018-01-24 12:59:32,636 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:32,637 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 12:59:32,637 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 12:59:32,638 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=299, Invalid=513, Unknown=0, NotChecked=0, Total=812 [2018-01-24 12:59:32,638 INFO L87 Difference]: Start difference. First operand 79 states and 80 transitions. Second operand 20 states. [2018-01-24 12:59:32,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:32,776 INFO L93 Difference]: Finished difference Result 126 states and 129 transitions. [2018-01-24 12:59:32,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 12:59:32,777 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 78 [2018-01-24 12:59:32,777 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:32,778 INFO L225 Difference]: With dead ends: 126 [2018-01-24 12:59:32,778 INFO L226 Difference]: Without dead ends: 91 [2018-01-24 12:59:32,779 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 323 GetRequests, 291 SyntacticMatches, 4 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 296 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=327, Invalid=543, Unknown=0, NotChecked=0, Total=870 [2018-01-24 12:59:32,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-01-24 12:59:32,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 87. [2018-01-24 12:59:32,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-01-24 12:59:32,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 88 transitions. [2018-01-24 12:59:32,789 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 88 transitions. Word has length 78 [2018-01-24 12:59:32,790 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:32,790 INFO L432 AbstractCegarLoop]: Abstraction has 87 states and 88 transitions. [2018-01-24 12:59:32,790 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 12:59:32,790 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 88 transitions. [2018-01-24 12:59:32,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-01-24 12:59:32,791 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:32,792 INFO L322 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:32,792 INFO L371 AbstractCegarLoop]: === Iteration 13 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:32,792 INFO L82 PathProgramCache]: Analyzing trace with hash 2069780427, now seen corresponding path program 3 times [2018-01-24 12:59:32,792 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:32,793 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:32,793 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:32,793 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:32,793 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:32,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:32,810 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:32,945 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 12:59:32,945 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:32,945 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:32,951 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:32,951 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:32,969 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:32,975 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:32,979 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:32,987 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:32,993 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,004 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,027 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,055 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,074 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,076 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:33,079 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:33,178 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 12:59:33,178 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:33,391 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 158 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 12:59:33,412 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:33,412 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:33,415 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:33,415 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:33,433 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,465 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,501 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,542 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,595 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,661 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,756 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,885 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,019 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,039 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:34,044 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:34,061 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 12:59:34,061 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:34,132 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 12:59:34,134 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:34,134 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 15, 12, 13] total 36 [2018-01-24 12:59:34,134 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:34,134 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 12:59:34,135 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 12:59:34,135 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=418, Invalid=842, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 12:59:34,135 INFO L87 Difference]: Start difference. First operand 87 states and 88 transitions. Second operand 24 states. [2018-01-24 12:59:34,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:34,326 INFO L93 Difference]: Finished difference Result 138 states and 141 transitions. [2018-01-24 12:59:34,326 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 12:59:34,326 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 86 [2018-01-24 12:59:34,326 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:34,327 INFO L225 Difference]: With dead ends: 138 [2018-01-24 12:59:34,327 INFO L226 Difference]: Without dead ends: 99 [2018-01-24 12:59:34,328 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 357 GetRequests, 317 SyntacticMatches, 4 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 498 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=457, Invalid=949, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 12:59:34,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-01-24 12:59:34,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 95. [2018-01-24 12:59:34,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-01-24 12:59:34,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 96 transitions. [2018-01-24 12:59:34,339 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 96 transitions. Word has length 86 [2018-01-24 12:59:34,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:34,339 INFO L432 AbstractCegarLoop]: Abstraction has 95 states and 96 transitions. [2018-01-24 12:59:34,339 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 12:59:34,339 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 96 transitions. [2018-01-24 12:59:34,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-01-24 12:59:34,340 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:34,341 INFO L322 BasicCegarLoop]: trace histogram [10, 10, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:34,341 INFO L371 AbstractCegarLoop]: === Iteration 14 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:34,341 INFO L82 PathProgramCache]: Analyzing trace with hash 67534827, now seen corresponding path program 4 times [2018-01-24 12:59:34,341 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:34,342 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:34,342 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:34,342 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:34,342 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:34,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:34,356 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:34,558 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 162 trivial. 0 not checked. [2018-01-24 12:59:34,558 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:34,558 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:34,565 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:59:34,565 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:59:34,598 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:34,602 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:34,613 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 12:59:34,614 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:34,615 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:34,615 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:8, output treesize:7 [2018-01-24 12:59:34,955 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 162 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:34,955 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:36,455 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 162 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:36,475 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:36,476 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:36,480 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:59:36,480 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:59:36,535 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:36,540 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:36,542 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 12:59:36,543 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:36,547 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:36,547 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-01-24 12:59:36,611 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 162 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:36,611 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:37,860 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 162 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:37,862 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:37,862 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 25, 27, 24, 25] total 64 [2018-01-24 12:59:37,862 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:37,862 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-01-24 12:59:37,863 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-01-24 12:59:37,863 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=803, Invalid=3229, Unknown=0, NotChecked=0, Total=4032 [2018-01-24 12:59:37,864 INFO L87 Difference]: Start difference. First operand 95 states and 96 transitions. Second operand 37 states. [2018-01-24 12:59:38,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:38,368 INFO L93 Difference]: Finished difference Result 150 states and 153 transitions. [2018-01-24 12:59:38,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 12:59:38,368 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 94 [2018-01-24 12:59:38,368 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:38,369 INFO L225 Difference]: With dead ends: 150 [2018-01-24 12:59:38,369 INFO L226 Difference]: Without dead ends: 107 [2018-01-24 12:59:38,370 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 404 GetRequests, 293 SyntacticMatches, 34 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 4185 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=1199, Invalid=4963, Unknown=0, NotChecked=0, Total=6162 [2018-01-24 12:59:38,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-01-24 12:59:38,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 103. [2018-01-24 12:59:38,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-01-24 12:59:38,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 104 transitions. [2018-01-24 12:59:38,379 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 104 transitions. Word has length 94 [2018-01-24 12:59:38,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:38,380 INFO L432 AbstractCegarLoop]: Abstraction has 103 states and 104 transitions. [2018-01-24 12:59:38,380 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-01-24 12:59:38,380 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 104 transitions. [2018-01-24 12:59:38,380 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-01-24 12:59:38,381 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:38,381 INFO L322 BasicCegarLoop]: trace histogram [11, 11, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:38,381 INFO L371 AbstractCegarLoop]: === Iteration 15 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:38,381 INFO L82 PathProgramCache]: Analyzing trace with hash 306183947, now seen corresponding path program 5 times [2018-01-24 12:59:38,381 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:38,382 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:38,382 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:38,382 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:38,382 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:38,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:38,396 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:38,705 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 12:59:38,706 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:38,706 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:38,711 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:59:38,711 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:38,721 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:38,725 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:38,728 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:38,733 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:38,741 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:38,765 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:38,793 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:38,830 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:39,029 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:39,073 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:39,700 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:39,703 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:39,707 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:39,719 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 12:59:39,719 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:39,846 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 12:59:39,867 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:39,867 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:39,870 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:59:39,871 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:39,880 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:39,885 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:39,894 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:39,907 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:39,935 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:39,973 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:40,025 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:40,095 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:40,304 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:40,593 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:41,048 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:41,084 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:41,089 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:41,097 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 12:59:41,097 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:41,117 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 12:59:41,119 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:41,119 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 13, 13, 13, 13] total 27 [2018-01-24 12:59:41,119 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:41,119 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 12:59:41,119 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 12:59:41,120 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=304, Invalid=398, Unknown=0, NotChecked=0, Total=702 [2018-01-24 12:59:41,120 INFO L87 Difference]: Start difference. First operand 103 states and 104 transitions. Second operand 16 states. [2018-01-24 12:59:41,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:41,282 INFO L93 Difference]: Finished difference Result 162 states and 165 transitions. [2018-01-24 12:59:41,283 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 12:59:41,283 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 102 [2018-01-24 12:59:41,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:41,283 INFO L225 Difference]: With dead ends: 162 [2018-01-24 12:59:41,283 INFO L226 Difference]: Without dead ends: 115 [2018-01-24 12:59:41,284 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 443 GetRequests, 407 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 114 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=580, Invalid=826, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 12:59:41,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-01-24 12:59:41,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 111. [2018-01-24 12:59:41,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-01-24 12:59:41,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 112 transitions. [2018-01-24 12:59:41,296 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 112 transitions. Word has length 102 [2018-01-24 12:59:41,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:41,296 INFO L432 AbstractCegarLoop]: Abstraction has 111 states and 112 transitions. [2018-01-24 12:59:41,296 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 12:59:41,296 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 112 transitions. [2018-01-24 12:59:41,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-01-24 12:59:41,297 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:41,297 INFO L322 BasicCegarLoop]: trace histogram [12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:41,297 INFO L371 AbstractCegarLoop]: === Iteration 16 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:41,298 INFO L82 PathProgramCache]: Analyzing trace with hash -2043652821, now seen corresponding path program 6 times [2018-01-24 12:59:41,298 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:41,298 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:41,298 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:41,298 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:41,298 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:41,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:41,313 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:41,464 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 12:59:41,464 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:41,465 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:41,469 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:59:41,470 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:59:41,483 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:41,486 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:41,489 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:41,494 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:41,503 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:41,516 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:41,540 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:41,621 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:41,656 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:41,683 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:41,746 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:41,793 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:41,795 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:41,799 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:41,815 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 12:59:41,815 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:41,958 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 12:59:41,978 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:41,978 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:41,981 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:59:41,981 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:59:42,000 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:42,029 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:42,063 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:42,110 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:42,204 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:42,271 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:42,343 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:42,486 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:42,591 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:42,763 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:42,934 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:43,176 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:43,202 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:43,208 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:43,217 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 12:59:43,217 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:43,252 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 12:59:43,254 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:43,254 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 14, 14, 14, 14] total 29 [2018-01-24 12:59:43,254 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:43,255 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 12:59:43,255 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 12:59:43,255 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=355, Invalid=457, Unknown=0, NotChecked=0, Total=812 [2018-01-24 12:59:43,255 INFO L87 Difference]: Start difference. First operand 111 states and 112 transitions. Second operand 17 states. [2018-01-24 12:59:43,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:43,439 INFO L93 Difference]: Finished difference Result 174 states and 177 transitions. [2018-01-24 12:59:43,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 12:59:43,439 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 110 [2018-01-24 12:59:43,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:43,440 INFO L225 Difference]: With dead ends: 174 [2018-01-24 12:59:43,440 INFO L226 Difference]: Without dead ends: 123 [2018-01-24 12:59:43,441 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 478 GetRequests, 439 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 131 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=680, Invalid=960, Unknown=0, NotChecked=0, Total=1640 [2018-01-24 12:59:43,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states. [2018-01-24 12:59:43,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 119. [2018-01-24 12:59:43,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-01-24 12:59:43,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 120 transitions. [2018-01-24 12:59:43,453 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 120 transitions. Word has length 110 [2018-01-24 12:59:43,453 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:43,453 INFO L432 AbstractCegarLoop]: Abstraction has 119 states and 120 transitions. [2018-01-24 12:59:43,453 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 12:59:43,453 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 120 transitions. [2018-01-24 12:59:43,454 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-01-24 12:59:43,455 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:43,455 INFO L322 BasicCegarLoop]: trace histogram [13, 13, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:43,455 INFO L371 AbstractCegarLoop]: === Iteration 17 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:43,455 INFO L82 PathProgramCache]: Analyzing trace with hash -130219445, now seen corresponding path program 7 times [2018-01-24 12:59:43,455 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:43,456 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:43,456 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:43,456 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:43,456 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:43,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:43,478 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:43,664 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 12:59:43,664 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:43,664 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:43,669 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:43,669 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:59:43,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:43,702 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:43,870 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 12:59:43,870 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:44,161 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 12:59:44,181 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:44,181 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:44,184 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:44,184 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:59:44,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:44,250 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:44,265 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 12:59:44,265 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:44,356 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 12:59:44,357 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:44,357 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16, 17, 16, 17] total 44 [2018-01-24 12:59:44,358 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:44,358 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 12:59:44,358 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 12:59:44,358 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=709, Invalid=1183, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 12:59:44,359 INFO L87 Difference]: Start difference. First operand 119 states and 120 transitions. Second operand 30 states. [2018-01-24 12:59:44,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:44,519 INFO L93 Difference]: Finished difference Result 186 states and 189 transitions. [2018-01-24 12:59:44,519 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 12:59:44,519 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 118 [2018-01-24 12:59:44,520 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:44,520 INFO L225 Difference]: With dead ends: 186 [2018-01-24 12:59:44,520 INFO L226 Difference]: Without dead ends: 131 [2018-01-24 12:59:44,521 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 488 GetRequests, 441 SyntacticMatches, 4 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 776 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=752, Invalid=1228, Unknown=0, NotChecked=0, Total=1980 [2018-01-24 12:59:44,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states. [2018-01-24 12:59:44,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 127. [2018-01-24 12:59:44,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 127 states. [2018-01-24 12:59:44,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 128 transitions. [2018-01-24 12:59:44,539 INFO L78 Accepts]: Start accepts. Automaton has 127 states and 128 transitions. Word has length 118 [2018-01-24 12:59:44,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:44,539 INFO L432 AbstractCegarLoop]: Abstraction has 127 states and 128 transitions. [2018-01-24 12:59:44,540 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 12:59:44,540 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 128 transitions. [2018-01-24 12:59:44,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-01-24 12:59:44,541 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:44,541 INFO L322 BasicCegarLoop]: trace histogram [14, 14, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:44,541 INFO L371 AbstractCegarLoop]: === Iteration 18 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:44,541 INFO L82 PathProgramCache]: Analyzing trace with hash -1727297941, now seen corresponding path program 8 times [2018-01-24 12:59:44,541 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:44,542 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:44,542 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:44,542 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:44,542 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:44,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:44,564 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:44,798 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 12:59:44,798 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:44,798 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:44,803 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:59:44,803 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:44,818 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:44,837 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:44,840 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:44,843 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:44,987 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 12:59:44,988 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:45,318 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 12:59:45,340 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:45,340 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:45,343 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:59:45,343 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:45,364 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:45,418 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:45,444 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:45,450 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:45,467 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 12:59:45,467 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:45,579 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 12:59:45,581 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:45,581 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17, 18, 17, 18] total 47 [2018-01-24 12:59:45,581 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:45,581 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-01-24 12:59:45,581 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-01-24 12:59:45,582 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=812, Invalid=1350, Unknown=0, NotChecked=0, Total=2162 [2018-01-24 12:59:45,582 INFO L87 Difference]: Start difference. First operand 127 states and 128 transitions. Second operand 32 states. [2018-01-24 12:59:45,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:45,753 INFO L93 Difference]: Finished difference Result 198 states and 201 transitions. [2018-01-24 12:59:45,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 12:59:45,753 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 126 [2018-01-24 12:59:45,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:45,754 INFO L225 Difference]: With dead ends: 198 [2018-01-24 12:59:45,754 INFO L226 Difference]: Without dead ends: 139 [2018-01-24 12:59:45,755 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 521 GetRequests, 471 SyntacticMatches, 4 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 899 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=858, Invalid=1398, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 12:59:45,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-01-24 12:59:45,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 135. [2018-01-24 12:59:45,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-01-24 12:59:45,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 136 transitions. [2018-01-24 12:59:45,771 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 136 transitions. Word has length 126 [2018-01-24 12:59:45,771 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:45,771 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 136 transitions. [2018-01-24 12:59:45,771 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-01-24 12:59:45,771 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 136 transitions. [2018-01-24 12:59:45,772 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-01-24 12:59:45,772 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:45,772 INFO L322 BasicCegarLoop]: trace histogram [15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:45,772 INFO L371 AbstractCegarLoop]: === Iteration 19 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:45,772 INFO L82 PathProgramCache]: Analyzing trace with hash 293691787, now seen corresponding path program 9 times [2018-01-24 12:59:45,772 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:45,773 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:45,773 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:45,773 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:45,773 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:45,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:45,793 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:46,058 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 12:59:46,058 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:46,058 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:46,063 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:46,063 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:46,076 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,080 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,083 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,087 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,092 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,102 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,112 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,135 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,155 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,173 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,224 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,357 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,438 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,499 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,850 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:46,852 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:46,856 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:46,890 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 12:59:46,890 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:47,121 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 12:59:47,143 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:47,143 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:47,146 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:47,146 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:47,180 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:47,231 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:47,291 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:47,362 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:47,421 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:47,491 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:47,587 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:47,718 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:47,856 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:48,030 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:48,264 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:48,564 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:48,876 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:49,301 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:49,855 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:49,896 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:49,904 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:50,117 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 12:59:50,117 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:50,357 WARN L143 SmtUtils]: Spent 137ms on a formula simplification that was a NOOP. DAG size: 50 [2018-01-24 12:59:50,879 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 12:59:50,881 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:50,881 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 17, 17, 18, 19] total 66 [2018-01-24 12:59:50,882 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:50,882 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 12:59:50,882 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 12:59:50,883 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1555, Invalid=2735, Unknown=0, NotChecked=0, Total=4290 [2018-01-24 12:59:50,884 INFO L87 Difference]: Start difference. First operand 135 states and 136 transitions. Second operand 20 states. [2018-01-24 12:59:51,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:51,086 INFO L93 Difference]: Finished difference Result 210 states and 213 transitions. [2018-01-24 12:59:51,086 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 12:59:51,087 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 134 [2018-01-24 12:59:51,087 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:51,087 INFO L225 Difference]: With dead ends: 210 [2018-01-24 12:59:51,087 INFO L226 Difference]: Without dead ends: 147 [2018-01-24 12:59:51,088 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 583 GetRequests, 516 SyntacticMatches, 2 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2061 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1620, Invalid=2802, Unknown=0, NotChecked=0, Total=4422 [2018-01-24 12:59:51,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-01-24 12:59:51,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 143. [2018-01-24 12:59:51,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-01-24 12:59:51,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 144 transitions. [2018-01-24 12:59:51,103 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 144 transitions. Word has length 134 [2018-01-24 12:59:51,103 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:51,103 INFO L432 AbstractCegarLoop]: Abstraction has 143 states and 144 transitions. [2018-01-24 12:59:51,103 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 12:59:51,103 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 144 transitions. [2018-01-24 12:59:51,104 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-01-24 12:59:51,104 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:51,104 INFO L322 BasicCegarLoop]: trace histogram [16, 16, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:51,104 INFO L371 AbstractCegarLoop]: === Iteration 20 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:51,105 INFO L82 PathProgramCache]: Analyzing trace with hash 1657017259, now seen corresponding path program 10 times [2018-01-24 12:59:51,105 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:51,106 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:51,106 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:51,106 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:51,106 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:51,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:51,129 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:51,368 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 450 trivial. 0 not checked. [2018-01-24 12:59:51,368 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:51,368 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:51,374 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:59:51,374 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:59:51,411 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:51,416 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:51,423 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 12:59:51,424 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:51,432 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:51,433 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:8, output treesize:7 [2018-01-24 12:59:52,501 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 450 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:52,501 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:52,985 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,026 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,069 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,114 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:53,182 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,185 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,187 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,192 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:53,250 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,252 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,254 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,256 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:53,313 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,315 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,318 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,321 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:53,379 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,381 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,384 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,389 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:53,494 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,496 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,498 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,500 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:53,569 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,571 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,574 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,576 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:53,641 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,643 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,645 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,647 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:53,713 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,715 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,716 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,719 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:53,798 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,800 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,802 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,804 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:53,881 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,882 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,884 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:53,887 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:54,232 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:55,194 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 450 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:55,215 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:55,228 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:55,231 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:59:55,232 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:59:55,305 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:55,313 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:55,315 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 12:59:55,315 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:59:55,321 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:59:55,321 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-01-24 12:59:55,417 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 450 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:55,417 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:55,787 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,831 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,874 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,916 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:55,962 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,963 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,965 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,968 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:55,970 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,972 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,974 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,976 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:55,979 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,982 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,985 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,988 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:55,991 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,994 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,996 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:55,999 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:56,001 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,003 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,004 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,006 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:56,008 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,009 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,011 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,013 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:56,016 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,017 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,019 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,021 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:56,023 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,024 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,026 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,028 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 12:59:56,030 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,031 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,040 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,128 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,129 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,131 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 12:59:56,604 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 450 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:56,605 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:56,605 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 37, 38, 36, 37] total 93 [2018-01-24 12:59:56,606 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:56,606 INFO L409 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-01-24 12:59:56,606 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-01-24 12:59:56,608 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1757, Invalid=6799, Unknown=0, NotChecked=0, Total=8556 [2018-01-24 12:59:56,608 INFO L87 Difference]: Start difference. First operand 143 states and 144 transitions. Second operand 55 states. [2018-01-24 12:59:57,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:57,473 INFO L93 Difference]: Finished difference Result 222 states and 225 transitions. [2018-01-24 12:59:57,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 12:59:57,473 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 142 [2018-01-24 12:59:57,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:57,474 INFO L225 Difference]: With dead ends: 222 [2018-01-24 12:59:57,474 INFO L226 Difference]: Without dead ends: 155 [2018-01-24 12:59:57,476 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 608 GetRequests, 473 SyntacticMatches, 23 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7199 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=2600, Invalid=10282, Unknown=0, NotChecked=0, Total=12882 [2018-01-24 12:59:57,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states. [2018-01-24 12:59:57,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 151. [2018-01-24 12:59:57,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-01-24 12:59:57,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 152 transitions. [2018-01-24 12:59:57,489 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 152 transitions. Word has length 142 [2018-01-24 12:59:57,489 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:57,489 INFO L432 AbstractCegarLoop]: Abstraction has 151 states and 152 transitions. [2018-01-24 12:59:57,489 INFO L433 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-01-24 12:59:57,490 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 152 transitions. [2018-01-24 12:59:57,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-01-24 12:59:57,490 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:57,490 INFO L322 BasicCegarLoop]: trace histogram [17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:57,490 INFO L371 AbstractCegarLoop]: === Iteration 21 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 12:59:57,491 INFO L82 PathProgramCache]: Analyzing trace with hash -969335605, now seen corresponding path program 11 times [2018-01-24 12:59:57,491 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:57,491 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:57,491 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:57,491 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:57,492 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:57,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:57,508 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:57,786 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 12:59:57,786 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:57,786 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:57,793 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:59:57,793 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:57,802 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:57,804 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:57,807 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:57,810 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:57,814 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:57,829 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:57,893 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:57,925 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:57,963 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:57,978 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:58,081 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:58,113 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:58,134 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:58,173 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:58,208 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:58,241 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:03,432 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:03,445 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:00:03,453 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:00:03,473 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 13:00:03,473 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:00:03,751 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 13:00:03,775 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:00:03,775 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:00:03,778 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:00:03,779 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:00:03,792 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:03,800 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:03,816 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:03,831 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:03,854 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:03,887 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:03,959 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:04,053 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:04,184 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:04,345 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:04,908 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:05,669 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:06,626 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:07,778 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:10,790 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:14,439 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command Received shutdown request... [2018-01-24 13:00:16,966 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:00:17,038 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:00:17,046 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:00:17,050 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-01-24 13:00:17,050 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 13:00:17,055 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 13:00:17,056 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 01:00:17 BoogieIcfgContainer [2018-01-24 13:00:17,056 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 13:00:17,057 INFO L168 Benchmark]: Toolchain (without parser) took 55963.55 ms. Allocated memory was 306.7 MB in the beginning and 678.4 MB in the end (delta: 371.7 MB). Free memory was 266.7 MB in the beginning and 541.7 MB in the end (delta: -275.0 MB). Peak memory consumption was 96.7 MB. Max. memory is 5.3 GB. [2018-01-24 13:00:17,058 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 306.7 MB. Free memory is still 272.7 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 13:00:17,059 INFO L168 Benchmark]: CACSL2BoogieTranslator took 206.81 ms. Allocated memory is still 306.7 MB. Free memory was 265.8 MB in the beginning and 255.7 MB in the end (delta: 10.1 MB). Peak memory consumption was 10.1 MB. Max. memory is 5.3 GB. [2018-01-24 13:00:17,059 INFO L168 Benchmark]: Boogie Preprocessor took 37.33 ms. Allocated memory is still 306.7 MB. Free memory was 255.7 MB in the beginning and 253.7 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 13:00:17,059 INFO L168 Benchmark]: RCFGBuilder took 275.68 ms. Allocated memory is still 306.7 MB. Free memory was 253.7 MB in the beginning and 236.1 MB in the end (delta: 17.6 MB). Peak memory consumption was 17.6 MB. Max. memory is 5.3 GB. [2018-01-24 13:00:17,060 INFO L168 Benchmark]: TraceAbstraction took 55436.32 ms. Allocated memory was 306.7 MB in the beginning and 678.4 MB in the end (delta: 371.7 MB). Free memory was 236.1 MB in the beginning and 541.7 MB in the end (delta: -305.7 MB). Peak memory consumption was 66.1 MB. Max. memory is 5.3 GB. [2018-01-24 13:00:17,062 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 306.7 MB. Free memory is still 272.7 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 206.81 ms. Allocated memory is still 306.7 MB. Free memory was 265.8 MB in the beginning and 255.7 MB in the end (delta: 10.1 MB). Peak memory consumption was 10.1 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 37.33 ms. Allocated memory is still 306.7 MB. Free memory was 255.7 MB in the beginning and 253.7 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 275.68 ms. Allocated memory is still 306.7 MB. Free memory was 253.7 MB in the beginning and 236.1 MB in the end (delta: 17.6 MB). Peak memory consumption was 17.6 MB. Max. memory is 5.3 GB. * TraceAbstraction took 55436.32 ms. Allocated memory was 306.7 MB in the beginning and 678.4 MB in the end (delta: 371.7 MB). Free memory was 236.1 MB in the beginning and 541.7 MB in the end (delta: -305.7 MB). Peak memory consumption was 66.1 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 625). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 625). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 627). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 627). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 637). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 634). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 639). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 634). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 636). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 637). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 639). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 639). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 639). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 636). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 637). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 637). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 629]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 629). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 53 locations, 17 error locations. TIMEOUT Result, 55.3s OverallTime, 21 OverallIterations, 17 TraceHistogramMax, 5.5s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 481 SDtfs, 2945 SDslu, 2858 SDs, 0 SdLazy, 3341 SolverSat, 707 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 5140 GetRequests, 4379 SyntacticMatches, 93 SemanticMatches, 668 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 17623 ImplicationChecksByTransitivity, 16.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=151occurred in iteration=20, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 20 MinimizatonAttempts, 97 StatesRemovedByMinimization, 15 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 9.0s SatisfiabilityAnalysisTime, 19.8s InterpolantComputationTime, 3713 NumberOfCodeBlocks, 3617 NumberOfCodeBlocksAsserted, 143 NumberOfCheckSat, 6029 ConstructedInterpolants, 636 QuantifiedInterpolants, 4455927 SizeOfPredicates, 102 NumberOfNonLiveVariables, 7465 ConjunctsInSsa, 493 ConjunctsInUnsatCore, 78 InterpolantComputations, 7 PerfectInterpolantSequences, 12092/24408 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_13-00-17-071.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_13-00-17-071.csv Completed graceful shutdown