java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/memsafety/960521-1_true-valid-memsafety.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 13:03:44,864 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 13:03:44,866 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 13:03:44,882 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 13:03:44,882 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 13:03:44,883 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 13:03:44,885 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 13:03:44,886 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 13:03:44,889 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 13:03:44,890 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 13:03:44,890 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 13:03:44,891 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 13:03:44,892 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 13:03:44,893 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 13:03:44,894 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 13:03:44,897 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 13:03:44,899 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 13:03:44,901 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 13:03:44,902 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 13:03:44,903 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 13:03:44,906 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 13:03:44,906 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 13:03:44,906 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 13:03:44,907 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 13:03:44,908 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 13:03:44,909 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 13:03:44,909 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 13:03:44,910 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 13:03:44,910 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 13:03:44,910 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 13:03:44,911 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 13:03:44,911 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf [2018-01-24 13:03:44,920 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 13:03:44,920 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 13:03:44,921 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 13:03:44,921 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 13:03:44,921 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 13:03:44,921 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 13:03:44,921 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 13:03:44,921 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 13:03:44,922 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 13:03:44,922 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 13:03:44,922 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 13:03:44,922 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 13:03:44,922 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 13:03:44,922 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 13:03:44,922 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 13:03:44,923 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 13:03:44,923 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 13:03:44,923 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 13:03:44,923 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 13:03:44,923 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 13:03:44,923 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 13:03:44,924 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 13:03:44,924 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 13:03:44,924 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:03:44,924 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 13:03:44,924 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 13:03:44,925 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 13:03:44,925 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 13:03:44,925 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-01-24 13:03:44,925 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 13:03:44,925 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 13:03:44,925 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 13:03:44,926 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 13:03:44,926 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 13:03:44,959 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 13:03:44,969 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 13:03:44,972 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 13:03:44,973 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 13:03:44,973 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 13:03:44,974 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/memsafety/960521-1_true-valid-memsafety.i [2018-01-24 13:03:45,127 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 13:03:45,132 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 13:03:45,133 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 13:03:45,133 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 13:03:45,138 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 13:03:45,139 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:03:45" (1/1) ... [2018-01-24 13:03:45,142 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2ddc1bba and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:03:45, skipping insertion in model container [2018-01-24 13:03:45,142 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:03:45" (1/1) ... [2018-01-24 13:03:45,155 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:03:45,195 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:03:45,313 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:03:45,331 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:03:45,338 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:03:45 WrapperNode [2018-01-24 13:03:45,339 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 13:03:45,340 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 13:03:45,340 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 13:03:45,340 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 13:03:45,351 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:03:45" (1/1) ... [2018-01-24 13:03:45,351 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:03:45" (1/1) ... [2018-01-24 13:03:45,360 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:03:45" (1/1) ... [2018-01-24 13:03:45,360 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:03:45" (1/1) ... [2018-01-24 13:03:45,364 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:03:45" (1/1) ... [2018-01-24 13:03:45,368 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:03:45" (1/1) ... [2018-01-24 13:03:45,369 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:03:45" (1/1) ... [2018-01-24 13:03:45,371 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 13:03:45,371 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 13:03:45,372 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 13:03:45,372 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 13:03:45,373 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:03:45" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:03:45,423 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 13:03:45,423 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 13:03:45,423 INFO L136 BoogieDeclarations]: Found implementation of procedure foo [2018-01-24 13:03:45,423 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 13:03:45,423 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 13:03:45,423 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 13:03:45,423 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 13:03:45,424 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 13:03:45,424 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 13:03:45,424 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-01-24 13:03:45,424 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-01-24 13:03:45,424 INFO L128 BoogieDeclarations]: Found specification of procedure foo [2018-01-24 13:03:45,424 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 13:03:45,424 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 13:03:45,425 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 13:03:45,676 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 13:03:45,677 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:03:45 BoogieIcfgContainer [2018-01-24 13:03:45,677 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 13:03:45,678 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 13:03:45,678 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 13:03:45,680 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 13:03:45,681 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 01:03:45" (1/3) ... [2018-01-24 13:03:45,682 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@8483cce and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:03:45, skipping insertion in model container [2018-01-24 13:03:45,682 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:03:45" (2/3) ... [2018-01-24 13:03:45,682 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@8483cce and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:03:45, skipping insertion in model container [2018-01-24 13:03:45,683 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:03:45" (3/3) ... [2018-01-24 13:03:45,684 INFO L105 eAbstractionObserver]: Analyzing ICFG 960521-1_true-valid-memsafety.i [2018-01-24 13:03:45,690 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 13:03:45,696 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 17 error locations. [2018-01-24 13:03:45,731 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 13:03:45,731 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 13:03:45,731 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 13:03:45,732 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 13:03:45,732 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 13:03:45,732 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 13:03:45,732 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 13:03:45,732 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 13:03:45,733 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 13:03:45,755 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states. [2018-01-24 13:03:45,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-01-24 13:03:45,762 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:45,763 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:45,763 INFO L371 AbstractCegarLoop]: === Iteration 1 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:45,769 INFO L82 PathProgramCache]: Analyzing trace with hash 1993989713, now seen corresponding path program 1 times [2018-01-24 13:03:45,772 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:45,815 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:45,816 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:45,816 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:45,816 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:45,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:45,876 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:45,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:45,968 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:03:45,968 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 13:03:45,968 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:03:45,970 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 13:03:45,980 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 13:03:45,981 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 13:03:45,983 INFO L87 Difference]: Start difference. First operand 53 states. Second operand 4 states. [2018-01-24 13:03:46,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:03:46,188 INFO L93 Difference]: Finished difference Result 84 states and 90 transitions. [2018-01-24 13:03:46,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 13:03:46,190 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2018-01-24 13:03:46,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:03:46,201 INFO L225 Difference]: With dead ends: 84 [2018-01-24 13:03:46,201 INFO L226 Difference]: Without dead ends: 49 [2018-01-24 13:03:46,205 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:03:46,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-01-24 13:03:46,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2018-01-24 13:03:46,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-01-24 13:03:46,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 51 transitions. [2018-01-24 13:03:46,236 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 51 transitions. Word has length 11 [2018-01-24 13:03:46,236 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:03:46,236 INFO L432 AbstractCegarLoop]: Abstraction has 49 states and 51 transitions. [2018-01-24 13:03:46,236 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 13:03:46,237 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 51 transitions. [2018-01-24 13:03:46,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-01-24 13:03:46,237 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:46,237 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:46,237 INFO L371 AbstractCegarLoop]: === Iteration 2 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:46,238 INFO L82 PathProgramCache]: Analyzing trace with hash 1993989714, now seen corresponding path program 1 times [2018-01-24 13:03:46,238 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:46,239 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:46,239 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:46,239 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:46,239 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:46,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:46,261 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:46,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:46,355 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:03:46,355 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 13:03:46,355 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:03:46,357 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 13:03:46,357 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 13:03:46,357 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:03:46,357 INFO L87 Difference]: Start difference. First operand 49 states and 51 transitions. Second operand 5 states. [2018-01-24 13:03:46,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:03:46,472 INFO L93 Difference]: Finished difference Result 49 states and 51 transitions. [2018-01-24 13:03:46,472 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:03:46,472 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 11 [2018-01-24 13:03:46,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:03:46,473 INFO L225 Difference]: With dead ends: 49 [2018-01-24 13:03:46,474 INFO L226 Difference]: Without dead ends: 48 [2018-01-24 13:03:46,475 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:03:46,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-01-24 13:03:46,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2018-01-24 13:03:46,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-01-24 13:03:46,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 50 transitions. [2018-01-24 13:03:46,482 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 50 transitions. Word has length 11 [2018-01-24 13:03:46,482 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:03:46,482 INFO L432 AbstractCegarLoop]: Abstraction has 48 states and 50 transitions. [2018-01-24 13:03:46,483 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 13:03:46,483 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 50 transitions. [2018-01-24 13:03:46,483 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 13:03:46,484 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:46,484 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:46,484 INFO L371 AbstractCegarLoop]: === Iteration 3 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:46,484 INFO L82 PathProgramCache]: Analyzing trace with hash -1188525484, now seen corresponding path program 1 times [2018-01-24 13:03:46,484 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:46,485 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:46,486 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:46,486 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:46,486 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:46,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:46,509 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:46,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:46,603 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:03:46,603 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 13:03:46,603 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:03:46,603 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:03:46,604 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:03:46,604 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:03:46,604 INFO L87 Difference]: Start difference. First operand 48 states and 50 transitions. Second operand 6 states. [2018-01-24 13:03:46,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:03:46,692 INFO L93 Difference]: Finished difference Result 48 states and 50 transitions. [2018-01-24 13:03:46,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:03:46,693 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-01-24 13:03:46,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:03:46,694 INFO L225 Difference]: With dead ends: 48 [2018-01-24 13:03:46,694 INFO L226 Difference]: Without dead ends: 45 [2018-01-24 13:03:46,694 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:03:46,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2018-01-24 13:03:46,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2018-01-24 13:03:46,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-01-24 13:03:46,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 47 transitions. [2018-01-24 13:03:46,701 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 47 transitions. Word has length 17 [2018-01-24 13:03:46,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:03:46,702 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 47 transitions. [2018-01-24 13:03:46,702 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:03:46,702 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 47 transitions. [2018-01-24 13:03:46,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 13:03:46,702 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:46,703 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:46,703 INFO L371 AbstractCegarLoop]: === Iteration 4 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:46,703 INFO L82 PathProgramCache]: Analyzing trace with hash -1188525483, now seen corresponding path program 1 times [2018-01-24 13:03:46,703 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:46,704 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:46,704 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:46,705 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:46,705 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:46,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:46,722 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:46,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:46,876 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:03:46,876 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 13:03:46,876 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:03:46,876 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 13:03:46,877 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 13:03:46,877 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:03:46,877 INFO L87 Difference]: Start difference. First operand 45 states and 47 transitions. Second operand 7 states. [2018-01-24 13:03:47,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:03:47,025 INFO L93 Difference]: Finished difference Result 80 states and 87 transitions. [2018-01-24 13:03:47,025 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 13:03:47,025 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 17 [2018-01-24 13:03:47,026 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:03:47,026 INFO L225 Difference]: With dead ends: 80 [2018-01-24 13:03:47,026 INFO L226 Difference]: Without dead ends: 53 [2018-01-24 13:03:47,027 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:03:47,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2018-01-24 13:03:47,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 48. [2018-01-24 13:03:47,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-01-24 13:03:47,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 50 transitions. [2018-01-24 13:03:47,034 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 50 transitions. Word has length 17 [2018-01-24 13:03:47,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:03:47,034 INFO L432 AbstractCegarLoop]: Abstraction has 48 states and 50 transitions. [2018-01-24 13:03:47,034 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 13:03:47,035 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 50 transitions. [2018-01-24 13:03:47,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-01-24 13:03:47,035 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:47,036 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:47,036 INFO L371 AbstractCegarLoop]: === Iteration 5 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:47,036 INFO L82 PathProgramCache]: Analyzing trace with hash -2106816852, now seen corresponding path program 1 times [2018-01-24 13:03:47,036 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:47,037 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:47,037 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:47,037 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:47,037 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:47,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:47,053 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:47,209 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:47,209 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:47,209 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:03:47,221 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:47,221 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:03:47,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:47,250 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:47,284 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 13:03:47,286 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:47,291 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:47,291 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:15, output treesize:14 [2018-01-24 13:03:47,324 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-01-24 13:03:47,325 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:47,335 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 13:03:47,335 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:22, output treesize:21 [2018-01-24 13:03:47,496 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:47,496 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:48,163 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 13:03:48,177 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 5 [2018-01-24 13:03:48,192 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:48,194 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:48,195 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:48,195 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:15, output treesize:5 [2018-01-24 13:03:48,232 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:48,254 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:48,254 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:03:48,259 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:48,259 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:03:48,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:48,307 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:48,313 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 13:03:48,313 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:48,324 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 13:03:48,324 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:48,330 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:48,330 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-01-24 13:03:48,372 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:48,375 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 13:03:48,376 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:48,395 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:48,396 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:48,396 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 13:03:48,397 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:48,403 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 13:03:48,404 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:32, output treesize:25 [2018-01-24 13:03:48,517 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:48,517 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:48,601 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-01-24 13:03:48,601 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:48,606 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 13:03:48,616 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 1 [2018-01-24 13:03:48,617 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:48,618 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:48,620 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:48,621 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:25, output treesize:5 [2018-01-24 13:03:48,625 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:48,626 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:03:48,626 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8, 7, 7, 7] total 24 [2018-01-24 13:03:48,627 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:03:48,627 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 13:03:48,627 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 13:03:48,627 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=477, Unknown=1, NotChecked=0, Total=600 [2018-01-24 13:03:48,628 INFO L87 Difference]: Start difference. First operand 48 states and 50 transitions. Second operand 12 states. [2018-01-24 13:03:48,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:03:48,917 INFO L93 Difference]: Finished difference Result 90 states and 95 transitions. [2018-01-24 13:03:48,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 13:03:48,918 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 21 [2018-01-24 13:03:48,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:03:48,919 INFO L225 Difference]: With dead ends: 90 [2018-01-24 13:03:48,919 INFO L226 Difference]: Without dead ends: 63 [2018-01-24 13:03:48,920 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 64 SyntacticMatches, 4 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 233 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=162, Invalid=593, Unknown=1, NotChecked=0, Total=756 [2018-01-24 13:03:48,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-01-24 13:03:48,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 56. [2018-01-24 13:03:48,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2018-01-24 13:03:48,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 60 transitions. [2018-01-24 13:03:48,927 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 60 transitions. Word has length 21 [2018-01-24 13:03:48,927 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:03:48,927 INFO L432 AbstractCegarLoop]: Abstraction has 56 states and 60 transitions. [2018-01-24 13:03:48,927 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 13:03:48,927 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 60 transitions. [2018-01-24 13:03:48,928 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-24 13:03:48,928 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:48,928 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:48,928 INFO L371 AbstractCegarLoop]: === Iteration 6 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:48,928 INFO L82 PathProgramCache]: Analyzing trace with hash -702775421, now seen corresponding path program 2 times [2018-01-24 13:03:48,929 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:48,929 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:48,929 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:48,929 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:48,930 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:48,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:48,945 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:49,157 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:49,158 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:49,158 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:03:49,164 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:03:49,164 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:03:49,179 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:03:49,182 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:03:49,183 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:03:49,185 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:49,189 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 13:03:49,189 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,200 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 13:03:49,200 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,206 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,206 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-01-24 13:03:49,232 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:49,233 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:49,234 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 13:03:49,234 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,247 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 13:03:49,248 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,254 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 13:03:49,255 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:32, output treesize:25 [2018-01-24 13:03:49,485 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:49,486 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:49,654 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-01-24 13:03:49,655 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,658 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 13:03:49,670 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 1 [2018-01-24 13:03:49,670 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,671 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,674 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,674 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:25, output treesize:5 [2018-01-24 13:03:49,693 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:49,714 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:49,714 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:03:49,717 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:03:49,717 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:03:49,739 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:03:49,768 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:03:49,780 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:03:49,785 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:49,788 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 13:03:49,788 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,809 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 13:03:49,809 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,816 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,816 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-01-24 13:03:49,828 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:49,829 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 13:03:49,829 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,843 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:49,844 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:49,845 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 13:03:49,845 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,855 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 13:03:49,855 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:32, output treesize:25 [2018-01-24 13:03:49,902 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:49,902 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:49,948 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-01-24 13:03:49,948 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,953 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 13:03:49,964 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 5 [2018-01-24 13:03:49,964 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,965 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,968 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:49,969 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:25, output treesize:5 [2018-01-24 13:03:49,974 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:49,976 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:03:49,976 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8, 8, 8] total 23 [2018-01-24 13:03:49,976 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:03:49,976 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 13:03:49,977 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 13:03:49,977 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=442, Unknown=0, NotChecked=0, Total=552 [2018-01-24 13:03:49,977 INFO L87 Difference]: Start difference. First operand 56 states and 60 transitions. Second operand 17 states. [2018-01-24 13:03:50,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:03:50,587 INFO L93 Difference]: Finished difference Result 104 states and 111 transitions. [2018-01-24 13:03:50,587 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 13:03:50,588 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 25 [2018-01-24 13:03:50,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:03:50,588 INFO L225 Difference]: With dead ends: 104 [2018-01-24 13:03:50,588 INFO L226 Difference]: Without dead ends: 73 [2018-01-24 13:03:50,589 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 83 SyntacticMatches, 3 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 257 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=208, Invalid=722, Unknown=0, NotChecked=0, Total=930 [2018-01-24 13:03:50,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-01-24 13:03:50,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 64. [2018-01-24 13:03:50,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-01-24 13:03:50,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 70 transitions. [2018-01-24 13:03:50,598 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 70 transitions. Word has length 25 [2018-01-24 13:03:50,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:03:50,598 INFO L432 AbstractCegarLoop]: Abstraction has 64 states and 70 transitions. [2018-01-24 13:03:50,598 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 13:03:50,598 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 70 transitions. [2018-01-24 13:03:50,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-01-24 13:03:50,599 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:50,600 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:50,600 INFO L371 AbstractCegarLoop]: === Iteration 7 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:50,600 INFO L82 PathProgramCache]: Analyzing trace with hash 1827026138, now seen corresponding path program 3 times [2018-01-24 13:03:50,600 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:50,601 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:50,601 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:03:50,601 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:50,601 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:50,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:50,619 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:50,854 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:50,855 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:50,855 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:03:50,865 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:03:50,865 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:03:50,879 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:50,882 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:50,883 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:03:50,886 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:50,890 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 13:03:50,890 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:50,896 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 13:03:50,896 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:50,901 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:50,901 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-01-24 13:03:50,926 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:50,927 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:50,928 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 13:03:50,928 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:50,934 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 13:03:50,935 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:50,940 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:50,940 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:29, output treesize:22 [2018-01-24 13:03:51,066 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:03:51,066 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:51,277 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:03:51,297 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:51,298 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:03:51,301 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:03:51,301 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:03:51,318 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:51,348 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:51,359 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:03:51,364 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:51,370 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 13:03:51,370 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:51,381 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 13:03:51,382 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:51,389 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:51,389 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-01-24 13:03:51,430 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:51,431 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:51,431 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 13:03:51,431 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:51,439 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 13:03:51,439 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:51,445 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 13:03:51,445 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:29, output treesize:22 [2018-01-24 13:03:51,641 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:03:51,641 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:52,208 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:03:52,210 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:03:52,210 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8, 7, 7, 7] total 29 [2018-01-24 13:03:52,210 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:03:52,210 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 13:03:52,210 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 13:03:52,211 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=730, Unknown=0, NotChecked=0, Total=870 [2018-01-24 13:03:52,211 INFO L87 Difference]: Start difference. First operand 64 states and 70 transitions. Second operand 18 states. [2018-01-24 13:03:53,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:03:53,227 INFO L93 Difference]: Finished difference Result 125 states and 137 transitions. [2018-01-24 13:03:53,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 13:03:53,270 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2018-01-24 13:03:53,270 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:03:53,273 INFO L225 Difference]: With dead ends: 125 [2018-01-24 13:03:53,274 INFO L226 Difference]: Without dead ends: 90 [2018-01-24 13:03:53,275 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 92 SyntacticMatches, 5 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 460 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=338, Invalid=1302, Unknown=0, NotChecked=0, Total=1640 [2018-01-24 13:03:53,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-01-24 13:03:53,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 70. [2018-01-24 13:03:53,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-01-24 13:03:53,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 76 transitions. [2018-01-24 13:03:53,287 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 76 transitions. Word has length 29 [2018-01-24 13:03:53,287 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:03:53,287 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 76 transitions. [2018-01-24 13:03:53,287 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 13:03:53,288 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 76 transitions. [2018-01-24 13:03:53,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-01-24 13:03:53,289 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:53,289 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:53,289 INFO L371 AbstractCegarLoop]: === Iteration 8 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:53,289 INFO L82 PathProgramCache]: Analyzing trace with hash -645884181, now seen corresponding path program 1 times [2018-01-24 13:03:53,290 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:53,291 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:53,291 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:03:53,291 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:53,292 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:53,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:53,308 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:53,427 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:53,427 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:53,428 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:03:53,447 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:53,447 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:03:53,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:53,476 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:53,594 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:53,595 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:53,782 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:53,816 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:53,817 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:03:53,823 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:53,823 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:03:53,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:53,867 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:53,874 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:53,874 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:53,884 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:53,885 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:03:53,886 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 22 [2018-01-24 13:03:53,886 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:03:53,886 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 13:03:53,886 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 13:03:53,887 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=199, Invalid=263, Unknown=0, NotChecked=0, Total=462 [2018-01-24 13:03:53,887 INFO L87 Difference]: Start difference. First operand 70 states and 76 transitions. Second operand 15 states. [2018-01-24 13:03:53,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:03:53,997 INFO L93 Difference]: Finished difference Result 136 states and 147 transitions. [2018-01-24 13:03:53,997 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 13:03:53,997 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 40 [2018-01-24 13:03:53,998 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:03:53,998 INFO L225 Difference]: With dead ends: 136 [2018-01-24 13:03:53,999 INFO L226 Difference]: Without dead ends: 102 [2018-01-24 13:03:53,999 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 167 GetRequests, 147 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 164 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=199, Invalid=263, Unknown=0, NotChecked=0, Total=462 [2018-01-24 13:03:53,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-01-24 13:03:54,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 86. [2018-01-24 13:03:54,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-01-24 13:03:54,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 98 transitions. [2018-01-24 13:03:54,012 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 98 transitions. Word has length 40 [2018-01-24 13:03:54,012 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:03:54,013 INFO L432 AbstractCegarLoop]: Abstraction has 86 states and 98 transitions. [2018-01-24 13:03:54,013 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 13:03:54,013 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 98 transitions. [2018-01-24 13:03:54,014 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-24 13:03:54,014 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:54,014 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:54,014 INFO L371 AbstractCegarLoop]: === Iteration 9 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:54,014 INFO L82 PathProgramCache]: Analyzing trace with hash -2113361740, now seen corresponding path program 2 times [2018-01-24 13:03:54,015 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:54,015 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:54,015 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:54,016 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:54,016 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:54,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:54,028 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:54,106 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:03:54,106 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:54,106 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:03:54,113 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:03:54,114 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:03:54,128 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:03:54,133 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:03:54,136 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:54,145 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 13:03:54,145 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:54,166 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 13:03:54,166 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:15, output treesize:14 [2018-01-24 13:03:54,362 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 13:03:54,362 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:54,597 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 13:03:54,618 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:03:54,619 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7, 7] imperfect sequences [10] total 20 [2018-01-24 13:03:54,619 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:03:54,619 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 13:03:54,619 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 13:03:54,619 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=305, Unknown=0, NotChecked=0, Total=380 [2018-01-24 13:03:54,620 INFO L87 Difference]: Start difference. First operand 86 states and 98 transitions. Second operand 8 states. [2018-01-24 13:03:54,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:03:54,862 INFO L93 Difference]: Finished difference Result 89 states and 100 transitions. [2018-01-24 13:03:54,863 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:03:54,863 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 44 [2018-01-24 13:03:54,863 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:03:54,865 INFO L225 Difference]: With dead ends: 89 [2018-01-24 13:03:54,865 INFO L226 Difference]: Without dead ends: 83 [2018-01-24 13:03:54,866 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 78 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 120 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=138, Invalid=564, Unknown=0, NotChecked=0, Total=702 [2018-01-24 13:03:54,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-01-24 13:03:54,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2018-01-24 13:03:54,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2018-01-24 13:03:54,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 89 transitions. [2018-01-24 13:03:54,882 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 89 transitions. Word has length 44 [2018-01-24 13:03:54,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:03:54,882 INFO L432 AbstractCegarLoop]: Abstraction has 83 states and 89 transitions. [2018-01-24 13:03:54,883 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 13:03:54,883 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 89 transitions. [2018-01-24 13:03:54,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-24 13:03:54,884 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:54,884 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:54,884 INFO L371 AbstractCegarLoop]: === Iteration 10 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:54,884 INFO L82 PathProgramCache]: Analyzing trace with hash -2113361741, now seen corresponding path program 1 times [2018-01-24 13:03:54,884 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:54,885 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:54,885 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:03:54,885 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:54,885 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:54,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:54,897 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:54,943 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 13:03:54,943 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:03:54,943 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 13:03:54,944 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:03:54,944 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 13:03:54,944 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 13:03:54,944 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 13:03:54,945 INFO L87 Difference]: Start difference. First operand 83 states and 89 transitions. Second operand 4 states. [2018-01-24 13:03:55,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:03:55,019 INFO L93 Difference]: Finished difference Result 83 states and 89 transitions. [2018-01-24 13:03:55,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:03:55,019 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 44 [2018-01-24 13:03:55,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:03:55,021 INFO L225 Difference]: With dead ends: 83 [2018-01-24 13:03:55,021 INFO L226 Difference]: Without dead ends: 81 [2018-01-24 13:03:55,021 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:03:55,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-01-24 13:03:55,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2018-01-24 13:03:55,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-01-24 13:03:55,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 82 transitions. [2018-01-24 13:03:55,035 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 82 transitions. Word has length 44 [2018-01-24 13:03:55,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:03:55,036 INFO L432 AbstractCegarLoop]: Abstraction has 81 states and 82 transitions. [2018-01-24 13:03:55,036 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 13:03:55,036 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 82 transitions. [2018-01-24 13:03:55,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-01-24 13:03:55,038 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:55,038 INFO L322 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:55,038 INFO L371 AbstractCegarLoop]: === Iteration 11 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:55,038 INFO L82 PathProgramCache]: Analyzing trace with hash 1791473437, now seen corresponding path program 1 times [2018-01-24 13:03:55,038 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:55,039 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:55,039 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:55,040 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:55,040 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:55,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:55,059 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:55,207 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 13:03:55,207 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:55,207 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:03:55,218 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:55,219 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:03:55,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:55,262 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:55,471 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 13:03:55,471 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:55,656 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 13:03:55,679 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:55,679 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:03:55,682 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:55,682 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:03:55,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:55,740 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:55,750 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 13:03:55,750 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:55,819 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 13:03:55,821 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:03:55,822 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 11, 10, 11] total 26 [2018-01-24 13:03:55,822 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:03:55,822 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 13:03:55,823 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 13:03:55,823 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=238, Invalid=412, Unknown=0, NotChecked=0, Total=650 [2018-01-24 13:03:55,823 INFO L87 Difference]: Start difference. First operand 81 states and 82 transitions. Second operand 18 states. [2018-01-24 13:03:56,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:03:56,015 INFO L93 Difference]: Finished difference Result 134 states and 137 transitions. [2018-01-24 13:03:56,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 13:03:56,015 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 73 [2018-01-24 13:03:56,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:03:56,016 INFO L225 Difference]: With dead ends: 134 [2018-01-24 13:03:56,016 INFO L226 Difference]: Without dead ends: 93 [2018-01-24 13:03:56,017 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 302 GetRequests, 273 SyntacticMatches, 4 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 227 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=263, Invalid=439, Unknown=0, NotChecked=0, Total=702 [2018-01-24 13:03:56,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-01-24 13:03:56,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 89. [2018-01-24 13:03:56,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-01-24 13:03:56,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 90 transitions. [2018-01-24 13:03:56,030 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 90 transitions. Word has length 73 [2018-01-24 13:03:56,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:03:56,031 INFO L432 AbstractCegarLoop]: Abstraction has 89 states and 90 transitions. [2018-01-24 13:03:56,031 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 13:03:56,031 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 90 transitions. [2018-01-24 13:03:56,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-01-24 13:03:56,033 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:56,033 INFO L322 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:56,033 INFO L371 AbstractCegarLoop]: === Iteration 12 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:56,033 INFO L82 PathProgramCache]: Analyzing trace with hash 526780669, now seen corresponding path program 2 times [2018-01-24 13:03:56,033 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:56,034 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:56,034 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:56,034 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:56,034 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:56,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:56,049 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:56,323 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 13:03:56,323 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:56,324 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:03:56,338 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:03:56,338 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:03:56,355 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:03:56,360 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:03:56,363 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:56,370 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 13:03:56,370 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:56,381 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:56,381 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:11, output treesize:10 [2018-01-24 13:03:56,442 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:56,443 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:56,444 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 13:03:56,444 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:56,447 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:03:56,447 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:15, output treesize:9 [2018-01-24 13:03:56,528 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:03:56,529 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-01-24 13:03:56,529 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:56,537 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 13:03:56,538 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:20, output treesize:15 [2018-01-24 13:03:56,560 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 196 trivial. 0 not checked. [2018-01-24 13:03:56,561 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:56,576 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 8 [2018-01-24 13:03:56,576 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:56,579 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-01-24 13:03:56,580 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:19, output treesize:13 [2018-01-24 13:03:56,592 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 13:03:56,593 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:56,598 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 13:03:56,598 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:03:56,601 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-01-24 13:03:56,601 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:23, output treesize:9 [2018-01-24 13:03:56,663 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 196 trivial. 0 not checked. [2018-01-24 13:03:56,685 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:03:56,686 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7, 7] imperfect sequences [12] total 21 [2018-01-24 13:03:56,686 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:03:56,686 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 13:03:56,686 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 13:03:56,686 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=348, Unknown=0, NotChecked=0, Total=420 [2018-01-24 13:03:56,687 INFO L87 Difference]: Start difference. First operand 89 states and 90 transitions. Second operand 8 states. [2018-01-24 13:03:56,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:03:56,869 INFO L93 Difference]: Finished difference Result 89 states and 90 transitions. [2018-01-24 13:03:56,869 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 13:03:56,869 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 81 [2018-01-24 13:03:56,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:03:56,870 INFO L225 Difference]: With dead ends: 89 [2018-01-24 13:03:56,870 INFO L226 Difference]: Without dead ends: 87 [2018-01-24 13:03:56,871 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 181 GetRequests, 153 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 108 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=139, Invalid=673, Unknown=0, NotChecked=0, Total=812 [2018-01-24 13:03:56,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-01-24 13:03:56,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2018-01-24 13:03:56,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-01-24 13:03:56,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 88 transitions. [2018-01-24 13:03:56,879 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 88 transitions. Word has length 81 [2018-01-24 13:03:56,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:03:56,879 INFO L432 AbstractCegarLoop]: Abstraction has 87 states and 88 transitions. [2018-01-24 13:03:56,879 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 13:03:56,879 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 88 transitions. [2018-01-24 13:03:56,881 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-01-24 13:03:56,881 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:56,881 INFO L322 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:56,881 INFO L371 AbstractCegarLoop]: === Iteration 13 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:56,881 INFO L82 PathProgramCache]: Analyzing trace with hash 526772724, now seen corresponding path program 1 times [2018-01-24 13:03:56,882 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:56,882 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:56,882 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:03:56,883 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:56,883 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:56,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:56,898 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:57,195 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 13:03:57,195 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:57,196 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:03:57,200 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:57,201 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:03:57,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:57,226 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:57,304 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 13:03:57,304 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:57,450 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 13:03:57,470 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:57,470 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:03:57,473 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:57,474 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:03:57,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:57,531 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:57,540 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 13:03:57,541 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:57,597 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 13:03:57,599 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:03:57,599 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 12, 11, 12] total 29 [2018-01-24 13:03:57,599 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:03:57,599 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 13:03:57,599 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 13:03:57,600 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=299, Invalid=513, Unknown=0, NotChecked=0, Total=812 [2018-01-24 13:03:57,600 INFO L87 Difference]: Start difference. First operand 87 states and 88 transitions. Second operand 20 states. [2018-01-24 13:03:57,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:03:57,720 INFO L93 Difference]: Finished difference Result 142 states and 145 transitions. [2018-01-24 13:03:57,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 13:03:57,721 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 81 [2018-01-24 13:03:57,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:03:57,722 INFO L225 Difference]: With dead ends: 142 [2018-01-24 13:03:57,722 INFO L226 Difference]: Without dead ends: 99 [2018-01-24 13:03:57,723 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 335 GetRequests, 303 SyntacticMatches, 4 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 296 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=327, Invalid=543, Unknown=0, NotChecked=0, Total=870 [2018-01-24 13:03:57,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-01-24 13:03:57,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 95. [2018-01-24 13:03:57,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-01-24 13:03:57,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 96 transitions. [2018-01-24 13:03:57,735 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 96 transitions. Word has length 81 [2018-01-24 13:03:57,735 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:03:57,735 INFO L432 AbstractCegarLoop]: Abstraction has 95 states and 96 transitions. [2018-01-24 13:03:57,735 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 13:03:57,735 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 96 transitions. [2018-01-24 13:03:57,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-01-24 13:03:57,736 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:57,736 INFO L322 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:57,736 INFO L371 AbstractCegarLoop]: === Iteration 14 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:57,737 INFO L82 PathProgramCache]: Analyzing trace with hash -2016770860, now seen corresponding path program 2 times [2018-01-24 13:03:57,737 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:57,737 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:57,737 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:03:57,738 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:57,738 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:57,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:57,753 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:57,872 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 13:03:57,872 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:57,872 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:03:57,877 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:03:57,878 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:03:57,892 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:03:57,905 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:03:57,907 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:03:57,909 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:58,007 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 13:03:58,007 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:58,214 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 13:03:58,235 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:58,235 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:03:58,272 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:03:58,272 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:03:58,298 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:03:58,372 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:03:58,391 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:03:58,397 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:58,412 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 13:03:58,413 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:58,483 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 13:03:58,485 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:03:58,485 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12, 13, 12, 13] total 32 [2018-01-24 13:03:58,486 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:03:58,486 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 13:03:58,486 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 13:03:58,486 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=367, Invalid=625, Unknown=0, NotChecked=0, Total=992 [2018-01-24 13:03:58,486 INFO L87 Difference]: Start difference. First operand 95 states and 96 transitions. Second operand 22 states. [2018-01-24 13:03:58,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:03:58,654 INFO L93 Difference]: Finished difference Result 154 states and 157 transitions. [2018-01-24 13:03:58,654 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 13:03:58,654 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 89 [2018-01-24 13:03:58,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:03:58,655 INFO L225 Difference]: With dead ends: 154 [2018-01-24 13:03:58,655 INFO L226 Difference]: Without dead ends: 107 [2018-01-24 13:03:58,656 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 368 GetRequests, 333 SyntacticMatches, 4 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 374 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=398, Invalid=658, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 13:03:58,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-01-24 13:03:58,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 103. [2018-01-24 13:03:58,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-01-24 13:03:58,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 104 transitions. [2018-01-24 13:03:58,666 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 104 transitions. Word has length 89 [2018-01-24 13:03:58,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:03:58,666 INFO L432 AbstractCegarLoop]: Abstraction has 103 states and 104 transitions. [2018-01-24 13:03:58,666 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 13:03:58,666 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 104 transitions. [2018-01-24 13:03:58,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-01-24 13:03:58,668 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:03:58,668 INFO L322 BasicCegarLoop]: trace histogram [10, 10, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:03:58,668 INFO L371 AbstractCegarLoop]: === Iteration 15 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:03:58,668 INFO L82 PathProgramCache]: Analyzing trace with hash 1885333684, now seen corresponding path program 3 times [2018-01-24 13:03:58,668 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:03:58,669 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:58,669 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:03:58,669 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:03:58,669 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:03:58,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:03:58,690 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:03:58,872 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 162 trivial. 0 not checked. [2018-01-24 13:03:58,872 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:58,872 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:03:58,877 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:03:58,877 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:03:58,893 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:58,898 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:58,902 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:58,908 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:58,914 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:58,920 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:58,934 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:58,957 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:58,992 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:59,009 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:59,010 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:03:59,013 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:03:59,032 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 162 trivial. 0 not checked. [2018-01-24 13:03:59,032 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:03:59,152 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 162 trivial. 0 not checked. [2018-01-24 13:03:59,173 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:03:59,173 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:03:59,176 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:03:59,176 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:03:59,197 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:59,250 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:59,313 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:59,392 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:59,568 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:03:59,869 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:04:00,317 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:04:12,349 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:04:24,393 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:04:36,428 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:04:36,491 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:04:36,498 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:04:36,592 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 162 trivial. 0 not checked. [2018-01-24 13:04:36,593 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:04:36,805 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 162 trivial. 0 not checked. [2018-01-24 13:04:36,807 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:04:36,807 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 12, 12, 13, 14] total 46 [2018-01-24 13:04:36,807 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:04:36,808 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 13:04:36,808 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 13:04:36,808 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=740, Invalid=1330, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 13:04:36,809 INFO L87 Difference]: Start difference. First operand 103 states and 104 transitions. Second operand 15 states. [2018-01-24 13:04:36,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:04:36,896 INFO L93 Difference]: Finished difference Result 166 states and 169 transitions. [2018-01-24 13:04:36,896 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 13:04:36,897 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 97 [2018-01-24 13:04:36,897 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:04:36,897 INFO L225 Difference]: With dead ends: 166 [2018-01-24 13:04:36,897 INFO L226 Difference]: Without dead ends: 115 [2018-01-24 13:04:36,898 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 420 GetRequests, 373 SyntacticMatches, 2 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 946 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=785, Invalid=1377, Unknown=0, NotChecked=0, Total=2162 [2018-01-24 13:04:36,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-01-24 13:04:36,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 111. [2018-01-24 13:04:36,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-01-24 13:04:36,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 112 transitions. [2018-01-24 13:04:36,908 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 112 transitions. Word has length 97 [2018-01-24 13:04:36,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:04:36,909 INFO L432 AbstractCegarLoop]: Abstraction has 111 states and 112 transitions. [2018-01-24 13:04:36,909 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 13:04:36,909 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 112 transitions. [2018-01-24 13:04:36,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-01-24 13:04:36,909 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:04:36,910 INFO L322 BasicCegarLoop]: trace histogram [11, 11, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:04:36,910 INFO L371 AbstractCegarLoop]: === Iteration 16 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:04:36,910 INFO L82 PathProgramCache]: Analyzing trace with hash -984574572, now seen corresponding path program 4 times [2018-01-24 13:04:36,910 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:04:36,911 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:04:36,911 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:04:36,911 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:04:36,911 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:04:36,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:04:36,931 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:04:37,101 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 13:04:37,101 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:04:37,101 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:04:37,106 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:04:37,106 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:04:37,133 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:04:37,136 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:04:37,138 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 13:04:37,138 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:04:37,140 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:04:37,140 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:8, output treesize:7 [2018-01-24 13:04:37,461 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 10 [2018-01-24 13:04:37,462 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:04:37,465 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 13:04:37,465 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 4 variables, input treesize:24, output treesize:17 [2018-01-24 13:04:37,515 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 171 proven. 229 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:04:37,515 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:04:37,809 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:37,854 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:37,894 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:38,044 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:38,080 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:38,118 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 13:04:38,405 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 13:04:38,461 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:38,463 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:38,465 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:38,468 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 13:04:38,636 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 13:04:38,690 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:38,692 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:38,693 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:38,696 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 13:04:38,999 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:39,064 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:39,121 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:39,728 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 171 proven. 229 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:04:39,749 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:04:39,749 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:04:39,753 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:04:39,753 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:04:39,817 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:04:39,823 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:04:39,826 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 13:04:39,826 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:04:39,829 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:04:39,829 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:8, output treesize:7 [2018-01-24 13:04:39,854 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 10 [2018-01-24 13:04:39,855 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:04:39,867 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 13:04:39,867 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 4 variables, input treesize:24, output treesize:17 [2018-01-24 13:04:39,888 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 171 proven. 229 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:04:39,888 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:04:40,154 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:40,194 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:40,240 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:40,306 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:40,341 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:40,383 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:40,440 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 13:04:40,683 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:40,686 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:40,688 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:40,693 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 13:04:40,827 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 13:04:40,830 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:40,832 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:40,834 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:40,836 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 13:04:40,970 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 13:04:41,017 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:41,067 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:41,112 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 13:04:41,159 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 13:04:41,266 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 171 proven. 229 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:04:41,268 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:04:41,268 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 28, 29, 28, 28] total 68 [2018-01-24 13:04:41,268 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:04:41,268 INFO L409 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-01-24 13:04:41,269 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-01-24 13:04:41,269 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=900, Invalid=3656, Unknown=0, NotChecked=0, Total=4556 [2018-01-24 13:04:41,269 INFO L87 Difference]: Start difference. First operand 111 states and 112 transitions. Second operand 41 states. [2018-01-24 13:04:41,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:04:41,817 INFO L93 Difference]: Finished difference Result 178 states and 181 transitions. [2018-01-24 13:04:41,817 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 13:04:41,817 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 105 [2018-01-24 13:04:41,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:04:41,818 INFO L225 Difference]: With dead ends: 178 [2018-01-24 13:04:41,818 INFO L226 Difference]: Without dead ends: 123 [2018-01-24 13:04:41,820 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 450 GetRequests, 324 SyntacticMatches, 44 SemanticMatches, 82 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 5568 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=1336, Invalid=5636, Unknown=0, NotChecked=0, Total=6972 [2018-01-24 13:04:41,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states. [2018-01-24 13:04:41,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 119. [2018-01-24 13:04:41,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-01-24 13:04:41,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 120 transitions. [2018-01-24 13:04:41,837 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 120 transitions. Word has length 105 [2018-01-24 13:04:41,837 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:04:41,837 INFO L432 AbstractCegarLoop]: Abstraction has 119 states and 120 transitions. [2018-01-24 13:04:41,837 INFO L433 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-01-24 13:04:41,837 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 120 transitions. [2018-01-24 13:04:41,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-01-24 13:04:41,838 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:04:41,838 INFO L322 BasicCegarLoop]: trace histogram [12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:04:41,838 INFO L371 AbstractCegarLoop]: === Iteration 17 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:04:41,838 INFO L82 PathProgramCache]: Analyzing trace with hash -1299772556, now seen corresponding path program 5 times [2018-01-24 13:04:41,838 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:04:41,839 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:04:41,839 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:04:41,839 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:04:41,839 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:04:41,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:04:41,859 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:04:42,029 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 13:04:42,029 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:04:42,029 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:04:42,034 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:04:42,034 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:04:42,044 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,046 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,049 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,053 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,061 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,072 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,098 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,145 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,183 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,197 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,260 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,446 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,450 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:04:42,454 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:04:42,467 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 13:04:42,467 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:04:42,633 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 13:04:42,655 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:04:42,655 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:04:42,657 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:04:42,658 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:04:42,673 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,679 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,689 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,702 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,722 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,767 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,827 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:42,910 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:43,018 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:43,381 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:43,859 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:44,498 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:04:44,540 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:04:44,547 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:04:44,556 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 13:04:44,556 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:04:44,582 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 13:04:44,584 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:04:44,584 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 14, 14, 14, 14] total 29 [2018-01-24 13:04:44,584 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:04:44,585 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 13:04:44,585 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 13:04:44,585 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=355, Invalid=457, Unknown=0, NotChecked=0, Total=812 [2018-01-24 13:04:44,585 INFO L87 Difference]: Start difference. First operand 119 states and 120 transitions. Second operand 17 states. [2018-01-24 13:04:44,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:04:44,761 INFO L93 Difference]: Finished difference Result 190 states and 193 transitions. [2018-01-24 13:04:44,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 13:04:44,761 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 113 [2018-01-24 13:04:44,761 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:04:44,762 INFO L225 Difference]: With dead ends: 190 [2018-01-24 13:04:44,762 INFO L226 Difference]: Without dead ends: 131 [2018-01-24 13:04:44,762 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 451 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 131 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=680, Invalid=960, Unknown=0, NotChecked=0, Total=1640 [2018-01-24 13:04:44,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states. [2018-01-24 13:04:44,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 127. [2018-01-24 13:04:44,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 127 states. [2018-01-24 13:04:44,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 128 transitions. [2018-01-24 13:04:44,775 INFO L78 Accepts]: Start accepts. Automaton has 127 states and 128 transitions. Word has length 113 [2018-01-24 13:04:44,775 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:04:44,776 INFO L432 AbstractCegarLoop]: Abstraction has 127 states and 128 transitions. [2018-01-24 13:04:44,776 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 13:04:44,776 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 128 transitions. [2018-01-24 13:04:44,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-01-24 13:04:44,776 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:04:44,776 INFO L322 BasicCegarLoop]: trace histogram [13, 13, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:04:44,776 INFO L371 AbstractCegarLoop]: === Iteration 18 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 13:04:44,777 INFO L82 PathProgramCache]: Analyzing trace with hash -1012020652, now seen corresponding path program 6 times [2018-01-24 13:04:44,777 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:04:44,777 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:04:44,777 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:04:44,777 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:04:44,778 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:04:44,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:04:44,795 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:04:45,003 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 13:04:45,004 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:04:45,004 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:04:45,009 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:04:45,009 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:04:45,024 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:45,028 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:45,031 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:45,036 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:45,044 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:45,063 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:45,084 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:45,216 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:45,293 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:45,474 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:45,569 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:45,856 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:46,098 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:46,101 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:04:46,107 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:04:46,130 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 13:04:46,130 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:04:46,312 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 13:04:46,335 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:04:46,335 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:04:46,338 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:04:46,338 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:04:46,359 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:46,415 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:46,484 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:46,582 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:46,742 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:46,887 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:04:47,271 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command Received shutdown request... [2018-01-24 13:04:48,349 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command Cannot interrupt operation gracefully because timeout expired. Forcing shutdown