java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_2_false-valid-memtrack_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 13:28:00,102 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 13:28:00,104 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 13:28:00,120 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 13:28:00,120 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 13:28:00,121 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 13:28:00,122 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 13:28:00,124 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 13:28:00,126 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 13:28:00,127 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 13:28:00,128 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 13:28:00,128 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 13:28:00,129 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 13:28:00,131 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 13:28:00,131 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 13:28:00,134 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 13:28:00,136 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 13:28:00,138 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 13:28:00,140 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 13:28:00,141 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 13:28:00,143 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 13:28:00,144 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 13:28:00,144 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 13:28:00,145 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 13:28:00,146 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 13:28:00,147 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 13:28:00,147 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 13:28:00,148 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 13:28:00,148 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 13:28:00,149 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 13:28:00,149 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 13:28:00,150 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf [2018-01-24 13:28:00,158 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 13:28:00,158 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 13:28:00,159 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 13:28:00,159 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 13:28:00,159 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 13:28:00,159 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 13:28:00,160 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 13:28:00,160 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 13:28:00,160 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 13:28:00,160 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 13:28:00,160 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 13:28:00,160 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 13:28:00,161 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 13:28:00,161 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 13:28:00,161 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 13:28:00,161 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 13:28:00,161 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 13:28:00,161 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 13:28:00,162 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 13:28:00,162 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 13:28:00,162 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 13:28:00,162 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 13:28:00,162 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 13:28:00,162 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:28:00,163 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 13:28:00,163 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 13:28:00,163 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 13:28:00,163 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 13:28:00,163 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-01-24 13:28:00,163 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 13:28:00,164 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 13:28:00,164 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 13:28:00,164 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 13:28:00,165 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 13:28:00,198 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 13:28:00,209 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 13:28:00,213 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 13:28:00,214 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 13:28:00,214 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 13:28:00,215 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_2_false-valid-memtrack_true-termination.i [2018-01-24 13:28:00,404 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 13:28:00,410 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 13:28:00,411 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 13:28:00,411 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 13:28:00,417 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 13:28:00,418 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:28:00" (1/1) ... [2018-01-24 13:28:00,422 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@71d0b9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:28:00, skipping insertion in model container [2018-01-24 13:28:00,422 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:28:00" (1/1) ... [2018-01-24 13:28:00,441 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:28:00,494 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:28:00,606 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:28:00,624 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:28:00,634 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:28:00 WrapperNode [2018-01-24 13:28:00,634 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 13:28:00,634 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 13:28:00,635 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 13:28:00,635 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 13:28:00,646 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:28:00" (1/1) ... [2018-01-24 13:28:00,646 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:28:00" (1/1) ... [2018-01-24 13:28:00,659 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:28:00" (1/1) ... [2018-01-24 13:28:00,659 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:28:00" (1/1) ... [2018-01-24 13:28:00,664 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:28:00" (1/1) ... [2018-01-24 13:28:00,667 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:28:00" (1/1) ... [2018-01-24 13:28:00,668 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:28:00" (1/1) ... [2018-01-24 13:28:00,670 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 13:28:00,670 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 13:28:00,670 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 13:28:00,671 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 13:28:00,672 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:28:00" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:28:00,718 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 13:28:00,719 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 13:28:00,719 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-01-24 13:28:00,719 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-01-24 13:28:00,719 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_init [2018-01-24 13:28:00,719 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init_internal [2018-01-24 13:28:00,720 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init [2018-01-24 13:28:00,720 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_create [2018-01-24 13:28:00,720 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-01-24 13:28:00,720 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 13:28:00,720 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-01-24 13:28:00,720 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-01-24 13:28:00,721 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 13:28:00,721 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 13:28:00,721 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 13:28:00,721 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 13:28:00,721 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 13:28:00,721 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-01-24 13:28:00,722 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-01-24 13:28:00,722 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-01-24 13:28:00,722 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-24 13:28:00,722 INFO L128 BoogieDeclarations]: Found specification of procedure memset [2018-01-24 13:28:00,722 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-01-24 13:28:00,722 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-01-24 13:28:00,723 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_init [2018-01-24 13:28:00,723 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init_internal [2018-01-24 13:28:00,723 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init [2018-01-24 13:28:00,723 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_create [2018-01-24 13:28:00,723 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-01-24 13:28:00,723 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 13:28:00,724 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 13:28:00,724 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 13:28:00,847 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-01-24 13:28:00,942 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 13:28:00,943 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:28:00 BoogieIcfgContainer [2018-01-24 13:28:00,943 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 13:28:00,943 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 13:28:00,943 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 13:28:00,945 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 13:28:00,945 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 01:28:00" (1/3) ... [2018-01-24 13:28:00,946 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@21d47761 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:28:00, skipping insertion in model container [2018-01-24 13:28:00,946 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:28:00" (2/3) ... [2018-01-24 13:28:00,946 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@21d47761 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:28:00, skipping insertion in model container [2018-01-24 13:28:00,947 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:28:00" (3/3) ... [2018-01-24 13:28:00,949 INFO L105 eAbstractionObserver]: Analyzing ICFG memleaks_test22_2_false-valid-memtrack_true-termination.i [2018-01-24 13:28:00,957 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 13:28:00,963 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 9 error locations. [2018-01-24 13:28:01,011 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 13:28:01,011 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 13:28:01,011 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 13:28:01,011 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 13:28:01,011 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 13:28:01,011 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 13:28:01,011 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 13:28:01,011 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 13:28:01,012 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 13:28:01,027 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states. [2018-01-24 13:28:01,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 13:28:01,032 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:01,033 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:01,033 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:01,037 INFO L82 PathProgramCache]: Analyzing trace with hash 13572496, now seen corresponding path program 1 times [2018-01-24 13:28:01,039 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:01,085 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:01,085 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:01,085 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:01,085 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:01,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:01,139 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:01,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:01,304 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:28:01,304 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 13:28:01,304 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:28:01,307 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 13:28:01,389 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 13:28:01,390 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:28:01,424 INFO L87 Difference]: Start difference. First operand 65 states. Second operand 5 states. [2018-01-24 13:28:01,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:01,471 INFO L93 Difference]: Finished difference Result 118 states and 125 transitions. [2018-01-24 13:28:01,472 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:28:01,473 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-01-24 13:28:01,474 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:01,488 INFO L225 Difference]: With dead ends: 118 [2018-01-24 13:28:01,488 INFO L226 Difference]: Without dead ends: 68 [2018-01-24 13:28:01,492 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:28:01,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2018-01-24 13:28:01,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 66. [2018-01-24 13:28:01,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-01-24 13:28:01,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 70 transitions. [2018-01-24 13:28:01,535 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 70 transitions. Word has length 17 [2018-01-24 13:28:01,535 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:01,535 INFO L432 AbstractCegarLoop]: Abstraction has 66 states and 70 transitions. [2018-01-24 13:28:01,536 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 13:28:01,536 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 70 transitions. [2018-01-24 13:28:01,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-01-24 13:28:01,537 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:01,537 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:01,537 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:01,537 INFO L82 PathProgramCache]: Analyzing trace with hash 64872882, now seen corresponding path program 1 times [2018-01-24 13:28:01,538 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:01,539 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:01,539 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:01,539 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:01,540 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:01,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:01,563 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:01,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:01,635 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:28:01,635 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 13:28:01,635 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:28:01,636 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:28:01,636 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:28:01,637 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:28:01,637 INFO L87 Difference]: Start difference. First operand 66 states and 70 transitions. Second operand 6 states. [2018-01-24 13:28:01,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:01,812 INFO L93 Difference]: Finished difference Result 68 states and 72 transitions. [2018-01-24 13:28:01,812 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:28:01,812 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2018-01-24 13:28:01,812 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:01,814 INFO L225 Difference]: With dead ends: 68 [2018-01-24 13:28:01,814 INFO L226 Difference]: Without dead ends: 67 [2018-01-24 13:28:01,816 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:28:01,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-01-24 13:28:01,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 65. [2018-01-24 13:28:01,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65 states. [2018-01-24 13:28:01,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 69 transitions. [2018-01-24 13:28:01,825 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 69 transitions. Word has length 19 [2018-01-24 13:28:01,826 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:01,826 INFO L432 AbstractCegarLoop]: Abstraction has 65 states and 69 transitions. [2018-01-24 13:28:01,826 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:28:01,826 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 69 transitions. [2018-01-24 13:28:01,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-01-24 13:28:01,827 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:01,827 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:01,827 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:01,827 INFO L82 PathProgramCache]: Analyzing trace with hash 64872883, now seen corresponding path program 1 times [2018-01-24 13:28:01,828 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:01,829 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:01,829 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:01,830 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:01,830 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:01,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:01,851 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:02,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:02,082 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:28:02,082 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 13:28:02,082 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:28:02,082 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 13:28:02,082 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 13:28:02,083 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:28:02,084 INFO L87 Difference]: Start difference. First operand 65 states and 69 transitions. Second operand 7 states. [2018-01-24 13:28:02,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:02,264 INFO L93 Difference]: Finished difference Result 67 states and 71 transitions. [2018-01-24 13:28:02,266 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 13:28:02,266 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2018-01-24 13:28:02,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:02,268 INFO L225 Difference]: With dead ends: 67 [2018-01-24 13:28:02,268 INFO L226 Difference]: Without dead ends: 66 [2018-01-24 13:28:02,269 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-01-24 13:28:02,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-01-24 13:28:02,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 64. [2018-01-24 13:28:02,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-01-24 13:28:02,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 68 transitions. [2018-01-24 13:28:02,279 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 68 transitions. Word has length 19 [2018-01-24 13:28:02,279 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:02,279 INFO L432 AbstractCegarLoop]: Abstraction has 64 states and 68 transitions. [2018-01-24 13:28:02,279 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 13:28:02,280 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 68 transitions. [2018-01-24 13:28:02,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-01-24 13:28:02,281 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:02,281 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:02,281 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:02,281 INFO L82 PathProgramCache]: Analyzing trace with hash -1610907055, now seen corresponding path program 1 times [2018-01-24 13:28:02,281 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:02,282 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:02,283 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:02,283 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:02,283 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:02,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:02,297 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:02,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:02,332 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:28:02,332 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 13:28:02,332 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:28:02,333 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 13:28:02,333 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 13:28:02,333 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 13:28:02,333 INFO L87 Difference]: Start difference. First operand 64 states and 68 transitions. Second operand 3 states. [2018-01-24 13:28:02,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:02,387 INFO L93 Difference]: Finished difference Result 71 states and 74 transitions. [2018-01-24 13:28:02,387 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 13:28:02,387 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 22 [2018-01-24 13:28:02,387 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:02,388 INFO L225 Difference]: With dead ends: 71 [2018-01-24 13:28:02,388 INFO L226 Difference]: Without dead ends: 60 [2018-01-24 13:28:02,389 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 13:28:02,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-01-24 13:28:02,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2018-01-24 13:28:02,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-01-24 13:28:02,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 63 transitions. [2018-01-24 13:28:02,395 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 63 transitions. Word has length 22 [2018-01-24 13:28:02,395 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:02,395 INFO L432 AbstractCegarLoop]: Abstraction has 60 states and 63 transitions. [2018-01-24 13:28:02,395 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 13:28:02,395 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 63 transitions. [2018-01-24 13:28:02,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-01-24 13:28:02,396 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:02,396 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:02,396 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:02,396 INFO L82 PathProgramCache]: Analyzing trace with hash -655458449, now seen corresponding path program 1 times [2018-01-24 13:28:02,397 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:02,398 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:02,398 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:02,398 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:02,398 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:02,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:02,410 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:02,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:02,453 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:28:02,453 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 13:28:02,453 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:28:02,454 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:28:02,454 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:28:02,454 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:28:02,455 INFO L87 Difference]: Start difference. First operand 60 states and 63 transitions. Second operand 6 states. [2018-01-24 13:28:02,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:02,485 INFO L93 Difference]: Finished difference Result 67 states and 69 transitions. [2018-01-24 13:28:02,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:28:02,485 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 24 [2018-01-24 13:28:02,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:02,486 INFO L225 Difference]: With dead ends: 67 [2018-01-24 13:28:02,486 INFO L226 Difference]: Without dead ends: 60 [2018-01-24 13:28:02,486 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:28:02,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-01-24 13:28:02,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2018-01-24 13:28:02,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-01-24 13:28:02,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 62 transitions. [2018-01-24 13:28:02,493 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 62 transitions. Word has length 24 [2018-01-24 13:28:02,493 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:02,493 INFO L432 AbstractCegarLoop]: Abstraction has 60 states and 62 transitions. [2018-01-24 13:28:02,493 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:28:02,493 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 62 transitions. [2018-01-24 13:28:02,494 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-24 13:28:02,494 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:02,494 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:02,494 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:02,494 INFO L82 PathProgramCache]: Analyzing trace with hash -1673666846, now seen corresponding path program 1 times [2018-01-24 13:28:02,494 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:02,495 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:02,496 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:02,496 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:02,496 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:02,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:02,513 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:02,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:02,588 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:28:02,588 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-01-24 13:28:02,588 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:28:02,589 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:28:02,589 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:28:02,589 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:28:02,589 INFO L87 Difference]: Start difference. First operand 60 states and 62 transitions. Second operand 10 states. [2018-01-24 13:28:02,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:02,835 INFO L93 Difference]: Finished difference Result 60 states and 62 transitions. [2018-01-24 13:28:02,836 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:28:02,836 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 34 [2018-01-24 13:28:02,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:02,837 INFO L225 Difference]: With dead ends: 60 [2018-01-24 13:28:02,837 INFO L226 Difference]: Without dead ends: 59 [2018-01-24 13:28:02,837 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:28:02,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-01-24 13:28:02,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2018-01-24 13:28:02,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2018-01-24 13:28:02,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 61 transitions. [2018-01-24 13:28:02,846 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 61 transitions. Word has length 34 [2018-01-24 13:28:02,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:02,847 INFO L432 AbstractCegarLoop]: Abstraction has 59 states and 61 transitions. [2018-01-24 13:28:02,847 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:28:02,847 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 61 transitions. [2018-01-24 13:28:02,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-24 13:28:02,848 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:02,848 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:02,849 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:02,849 INFO L82 PathProgramCache]: Analyzing trace with hash -1673666845, now seen corresponding path program 1 times [2018-01-24 13:28:02,849 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:02,850 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:02,851 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:02,851 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:02,851 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:02,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:02,867 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:02,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:02,918 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:28:02,918 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 13:28:02,918 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:28:02,919 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 13:28:02,919 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 13:28:02,919 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 13:28:02,919 INFO L87 Difference]: Start difference. First operand 59 states and 61 transitions. Second operand 4 states. [2018-01-24 13:28:02,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:02,987 INFO L93 Difference]: Finished difference Result 97 states and 101 transitions. [2018-01-24 13:28:02,987 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 13:28:02,987 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34 [2018-01-24 13:28:02,987 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:02,988 INFO L225 Difference]: With dead ends: 97 [2018-01-24 13:28:02,988 INFO L226 Difference]: Without dead ends: 60 [2018-01-24 13:28:02,989 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:28:02,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-01-24 13:28:02,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2018-01-24 13:28:02,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-01-24 13:28:02,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 62 transitions. [2018-01-24 13:28:02,997 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 62 transitions. Word has length 34 [2018-01-24 13:28:02,997 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:02,998 INFO L432 AbstractCegarLoop]: Abstraction has 60 states and 62 transitions. [2018-01-24 13:28:02,998 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 13:28:02,998 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 62 transitions. [2018-01-24 13:28:02,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-01-24 13:28:02,999 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:02,999 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:02,999 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:02,999 INFO L82 PathProgramCache]: Analyzing trace with hash -1908152085, now seen corresponding path program 1 times [2018-01-24 13:28:03,000 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:03,001 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:03,001 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:03,001 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:03,001 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:03,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:03,018 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:03,088 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:03,088 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:03,088 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:28:03,112 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:03,112 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:28:03,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:03,152 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:03,185 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:03,185 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:03,308 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:03,333 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:03,333 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:28:03,337 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:03,337 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:28:03,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:03,388 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:03,394 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:03,395 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:03,460 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:03,462 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:28:03,462 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 13:28:03,462 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:28:03,463 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:28:03,463 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:28:03,463 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2018-01-24 13:28:03,463 INFO L87 Difference]: Start difference. First operand 60 states and 62 transitions. Second operand 6 states. [2018-01-24 13:28:03,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:03,501 INFO L93 Difference]: Finished difference Result 98 states and 102 transitions. [2018-01-24 13:28:03,502 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:28:03,502 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-01-24 13:28:03,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:03,503 INFO L225 Difference]: With dead ends: 98 [2018-01-24 13:28:03,503 INFO L226 Difference]: Without dead ends: 61 [2018-01-24 13:28:03,504 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 144 GetRequests, 134 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=53, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:28:03,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-01-24 13:28:03,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2018-01-24 13:28:03,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-01-24 13:28:03,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 63 transitions. [2018-01-24 13:28:03,511 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 63 transitions. Word has length 35 [2018-01-24 13:28:03,512 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:03,512 INFO L432 AbstractCegarLoop]: Abstraction has 61 states and 63 transitions. [2018-01-24 13:28:03,512 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:28:03,512 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 63 transitions. [2018-01-24 13:28:03,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-24 13:28:03,513 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:03,513 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:03,513 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:03,514 INFO L82 PathProgramCache]: Analyzing trace with hash -587259933, now seen corresponding path program 2 times [2018-01-24 13:28:03,514 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:03,515 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:03,515 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:03,515 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:03,515 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:03,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:03,532 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:03,608 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:03,608 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:03,609 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:28:03,621 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:28:03,621 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:28:03,650 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:03,653 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:03,658 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:03,693 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:28:03,695 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:28:03,726 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:28:03,727 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:28:03,745 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:28:03,745 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:28:04,494 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:28:04,494 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:04,900 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:28:04,926 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:28:04,926 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [14, 13] imperfect sequences [6] total 31 [2018-01-24 13:28:04,926 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:28:04,927 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 13:28:04,927 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 13:28:04,927 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=840, Unknown=0, NotChecked=0, Total=930 [2018-01-24 13:28:04,927 INFO L87 Difference]: Start difference. First operand 61 states and 63 transitions. Second operand 15 states. [2018-01-24 13:28:05,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:05,546 INFO L93 Difference]: Finished difference Result 61 states and 63 transitions. [2018-01-24 13:28:05,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 13:28:05,546 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 36 [2018-01-24 13:28:05,547 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:05,547 INFO L225 Difference]: With dead ends: 61 [2018-01-24 13:28:05,547 INFO L226 Difference]: Without dead ends: 60 [2018-01-24 13:28:05,548 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 81 GetRequests, 47 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 251 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=118, Invalid=1072, Unknown=0, NotChecked=0, Total=1190 [2018-01-24 13:28:05,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-01-24 13:28:05,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2018-01-24 13:28:05,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-01-24 13:28:05,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 62 transitions. [2018-01-24 13:28:05,565 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 62 transitions. Word has length 36 [2018-01-24 13:28:05,565 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:05,565 INFO L432 AbstractCegarLoop]: Abstraction has 60 states and 62 transitions. [2018-01-24 13:28:05,565 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 13:28:05,565 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 62 transitions. [2018-01-24 13:28:05,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-24 13:28:05,567 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:05,567 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:05,567 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:05,567 INFO L82 PathProgramCache]: Analyzing trace with hash -789525114, now seen corresponding path program 1 times [2018-01-24 13:28:05,568 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:05,569 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:05,569 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:28:05,569 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:05,569 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:05,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:05,583 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:05,705 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:28:05,705 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:28:05,706 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-01-24 13:28:05,706 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:28:05,706 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:28:05,706 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:28:05,707 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:28:05,707 INFO L87 Difference]: Start difference. First operand 60 states and 62 transitions. Second operand 10 states. [2018-01-24 13:28:05,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:05,932 INFO L93 Difference]: Finished difference Result 60 states and 62 transitions. [2018-01-24 13:28:05,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:28:05,933 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 41 [2018-01-24 13:28:05,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:05,934 INFO L225 Difference]: With dead ends: 60 [2018-01-24 13:28:05,934 INFO L226 Difference]: Without dead ends: 58 [2018-01-24 13:28:05,934 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:28:05,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-01-24 13:28:05,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 58. [2018-01-24 13:28:05,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-01-24 13:28:05,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 60 transitions. [2018-01-24 13:28:05,946 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 60 transitions. Word has length 41 [2018-01-24 13:28:05,946 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:05,946 INFO L432 AbstractCegarLoop]: Abstraction has 58 states and 60 transitions. [2018-01-24 13:28:05,946 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:28:05,946 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 60 transitions. [2018-01-24 13:28:05,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-24 13:28:05,947 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:05,947 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:05,947 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:05,948 INFO L82 PathProgramCache]: Analyzing trace with hash -789525113, now seen corresponding path program 1 times [2018-01-24 13:28:05,948 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:05,949 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:05,949 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:05,949 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:05,949 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:05,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:05,965 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:06,009 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:06,009 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:06,009 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:28:06,017 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:06,017 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:28:06,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:06,041 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:06,049 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:06,050 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:06,160 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:06,180 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:06,180 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:28:06,183 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:06,183 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:28:06,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:06,236 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:06,242 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:06,242 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:06,262 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:06,263 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:28:06,264 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 13:28:06,264 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:28:06,264 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 13:28:06,264 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 13:28:06,264 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=63, Unknown=0, NotChecked=0, Total=110 [2018-01-24 13:28:06,264 INFO L87 Difference]: Start difference. First operand 58 states and 60 transitions. Second operand 7 states. [2018-01-24 13:28:06,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:06,288 INFO L93 Difference]: Finished difference Result 93 states and 97 transitions. [2018-01-24 13:28:06,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:28:06,289 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 41 [2018-01-24 13:28:06,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:06,289 INFO L225 Difference]: With dead ends: 93 [2018-01-24 13:28:06,290 INFO L226 Difference]: Without dead ends: 59 [2018-01-24 13:28:06,290 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 169 GetRequests, 157 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=77, Unknown=0, NotChecked=0, Total=132 [2018-01-24 13:28:06,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-01-24 13:28:06,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2018-01-24 13:28:06,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2018-01-24 13:28:06,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 61 transitions. [2018-01-24 13:28:06,300 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 61 transitions. Word has length 41 [2018-01-24 13:28:06,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:06,300 INFO L432 AbstractCegarLoop]: Abstraction has 59 states and 61 transitions. [2018-01-24 13:28:06,300 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 13:28:06,301 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 61 transitions. [2018-01-24 13:28:06,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 13:28:06,302 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:06,302 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:06,302 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:06,302 INFO L82 PathProgramCache]: Analyzing trace with hash -1225463169, now seen corresponding path program 2 times [2018-01-24 13:28:06,302 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:06,303 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:06,303 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:06,303 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:06,304 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:06,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:06,319 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:06,360 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:06,360 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:06,360 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:28:06,370 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:28:06,370 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:28:06,389 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:06,391 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:06,395 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:06,438 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:28:06,438 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:28:06,449 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:28:06,449 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:28:06,459 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:28:06,460 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:28:06,928 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:28:06,928 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:07,598 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:28:07,619 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:28:07,619 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15, 13] imperfect sequences [7] total 33 [2018-01-24 13:28:07,619 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:28:07,620 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 13:28:07,620 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 13:28:07,621 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=951, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 13:28:07,621 INFO L87 Difference]: Start difference. First operand 59 states and 61 transitions. Second operand 16 states. [2018-01-24 13:28:08,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:08,058 INFO L93 Difference]: Finished difference Result 59 states and 61 transitions. [2018-01-24 13:28:08,058 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 13:28:08,058 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 42 [2018-01-24 13:28:08,059 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:08,059 INFO L225 Difference]: With dead ends: 59 [2018-01-24 13:28:08,059 INFO L226 Difference]: Without dead ends: 57 [2018-01-24 13:28:08,060 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 57 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 317 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=136, Invalid=1196, Unknown=0, NotChecked=0, Total=1332 [2018-01-24 13:28:08,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2018-01-24 13:28:08,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 57. [2018-01-24 13:28:08,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-01-24 13:28:08,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 59 transitions. [2018-01-24 13:28:08,072 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 59 transitions. Word has length 42 [2018-01-24 13:28:08,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:08,072 INFO L432 AbstractCegarLoop]: Abstraction has 57 states and 59 transitions. [2018-01-24 13:28:08,073 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 13:28:08,073 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 59 transitions. [2018-01-24 13:28:08,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-01-24 13:28:08,074 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:08,074 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:08,074 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:08,074 INFO L82 PathProgramCache]: Analyzing trace with hash 1869907629, now seen corresponding path program 1 times [2018-01-24 13:28:08,074 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:08,075 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:08,075 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:28:08,075 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:08,075 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:08,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:08,087 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:08,152 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:28:08,153 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:28:08,153 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-01-24 13:28:08,153 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:28:08,153 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 13:28:08,154 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 13:28:08,154 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:28:08,154 INFO L87 Difference]: Start difference. First operand 57 states and 59 transitions. Second operand 8 states. [2018-01-24 13:28:08,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:08,236 INFO L93 Difference]: Finished difference Result 67 states and 68 transitions. [2018-01-24 13:28:08,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 13:28:08,236 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 40 [2018-01-24 13:28:08,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:08,237 INFO L225 Difference]: With dead ends: 67 [2018-01-24 13:28:08,237 INFO L226 Difference]: Without dead ends: 57 [2018-01-24 13:28:08,237 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:28:08,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2018-01-24 13:28:08,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 57. [2018-01-24 13:28:08,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-01-24 13:28:08,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 58 transitions. [2018-01-24 13:28:08,245 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 58 transitions. Word has length 40 [2018-01-24 13:28:08,246 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:08,246 INFO L432 AbstractCegarLoop]: Abstraction has 57 states and 58 transitions. [2018-01-24 13:28:08,246 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 13:28:08,246 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 58 transitions. [2018-01-24 13:28:08,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-01-24 13:28:08,247 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:08,247 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:08,247 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:08,247 INFO L82 PathProgramCache]: Analyzing trace with hash 946199638, now seen corresponding path program 1 times [2018-01-24 13:28:08,247 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:08,248 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:08,248 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:08,248 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:08,248 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:08,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:08,260 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:08,317 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:28:08,317 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:28:08,317 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-01-24 13:28:08,317 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:28:08,318 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:28:08,318 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:28:08,318 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:28:08,318 INFO L87 Difference]: Start difference. First operand 57 states and 58 transitions. Second operand 10 states. [2018-01-24 13:28:08,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:08,376 INFO L93 Difference]: Finished difference Result 69 states and 69 transitions. [2018-01-24 13:28:08,376 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:28:08,376 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 45 [2018-01-24 13:28:08,376 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:08,377 INFO L225 Difference]: With dead ends: 69 [2018-01-24 13:28:08,377 INFO L226 Difference]: Without dead ends: 57 [2018-01-24 13:28:08,377 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:28:08,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2018-01-24 13:28:08,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 57. [2018-01-24 13:28:08,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-01-24 13:28:08,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 57 transitions. [2018-01-24 13:28:08,384 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 57 transitions. Word has length 45 [2018-01-24 13:28:08,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:08,384 INFO L432 AbstractCegarLoop]: Abstraction has 57 states and 57 transitions. [2018-01-24 13:28:08,385 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:28:08,385 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2018-01-24 13:28:08,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-01-24 13:28:08,385 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:08,386 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:08,386 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:08,386 INFO L82 PathProgramCache]: Analyzing trace with hash -1294061430, now seen corresponding path program 1 times [2018-01-24 13:28:08,386 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:08,387 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:08,387 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:08,387 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:08,387 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:08,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:08,404 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:08,455 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:08,455 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:08,455 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:28:08,460 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:08,461 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:28:08,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:08,489 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:08,497 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:08,497 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:08,607 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:08,628 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:08,628 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:28:08,631 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:08,631 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:28:08,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:08,686 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:08,691 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:08,691 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:08,786 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:08,788 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:28:08,788 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 13:28:08,788 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:28:08,789 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 13:28:08,789 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 13:28:08,789 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=88, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:28:08,789 INFO L87 Difference]: Start difference. First operand 57 states and 57 transitions. Second operand 8 states. [2018-01-24 13:28:08,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:08,818 INFO L93 Difference]: Finished difference Result 90 states and 90 transitions. [2018-01-24 13:28:08,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 13:28:08,819 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 56 [2018-01-24 13:28:08,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:08,819 INFO L225 Difference]: With dead ends: 90 [2018-01-24 13:28:08,819 INFO L226 Difference]: Without dead ends: 58 [2018-01-24 13:28:08,820 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 230 GetRequests, 216 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=77, Invalid=105, Unknown=0, NotChecked=0, Total=182 [2018-01-24 13:28:08,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-01-24 13:28:08,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 58. [2018-01-24 13:28:08,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-01-24 13:28:08,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 58 transitions. [2018-01-24 13:28:08,830 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 58 transitions. Word has length 56 [2018-01-24 13:28:08,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:08,830 INFO L432 AbstractCegarLoop]: Abstraction has 58 states and 58 transitions. [2018-01-24 13:28:08,830 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 13:28:08,830 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 58 transitions. [2018-01-24 13:28:08,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-01-24 13:28:08,831 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:08,831 INFO L322 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:08,831 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:08,832 INFO L82 PathProgramCache]: Analyzing trace with hash -34765678, now seen corresponding path program 2 times [2018-01-24 13:28:08,832 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:08,833 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:08,833 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:08,833 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:08,833 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:08,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:08,850 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:08,906 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:08,907 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:08,907 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:28:08,912 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:28:08,912 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:28:08,931 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:08,939 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:08,940 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:08,942 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:08,951 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:08,951 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:09,144 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:09,176 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:09,176 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:28:09,180 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:28:09,180 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:28:09,215 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:09,245 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:09,265 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:09,271 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:09,277 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:09,277 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:09,405 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:09,407 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:28:09,407 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 13:28:09,407 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:28:09,407 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 13:28:09,408 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 13:28:09,408 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=117, Unknown=0, NotChecked=0, Total=210 [2018-01-24 13:28:09,408 INFO L87 Difference]: Start difference. First operand 58 states and 58 transitions. Second operand 9 states. [2018-01-24 13:28:09,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:09,454 INFO L93 Difference]: Finished difference Result 91 states and 91 transitions. [2018-01-24 13:28:09,454 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 13:28:09,454 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 57 [2018-01-24 13:28:09,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:09,455 INFO L225 Difference]: With dead ends: 91 [2018-01-24 13:28:09,456 INFO L226 Difference]: Without dead ends: 59 [2018-01-24 13:28:09,456 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 235 GetRequests, 219 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=103, Invalid=137, Unknown=0, NotChecked=0, Total=240 [2018-01-24 13:28:09,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-01-24 13:28:09,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2018-01-24 13:28:09,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2018-01-24 13:28:09,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 59 transitions. [2018-01-24 13:28:09,468 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 59 transitions. Word has length 57 [2018-01-24 13:28:09,468 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:09,469 INFO L432 AbstractCegarLoop]: Abstraction has 59 states and 59 transitions. [2018-01-24 13:28:09,469 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 13:28:09,469 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 59 transitions. [2018-01-24 13:28:09,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-01-24 13:28:09,470 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:09,470 INFO L322 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:09,470 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:09,470 INFO L82 PathProgramCache]: Analyzing trace with hash 348696970, now seen corresponding path program 3 times [2018-01-24 13:28:09,470 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:09,471 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:09,471 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:28:09,471 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:09,472 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:09,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:09,489 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:09,554 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:09,554 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:09,554 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:28:09,559 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:28:09,559 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:28:09,580 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:09,588 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:09,616 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:09,772 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:09,773 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:09,775 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:09,792 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:09,793 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:09,945 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:09,973 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:09,973 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:28:09,976 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:28:09,976 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:28:10,009 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:10,036 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:10,151 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:10,463 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:10,486 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:10,492 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:10,496 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:10,496 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:10,611 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:10,612 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:28:10,612 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 13:28:10,612 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:28:10,613 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:28:10,613 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:28:10,613 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=150, Unknown=0, NotChecked=0, Total=272 [2018-01-24 13:28:10,613 INFO L87 Difference]: Start difference. First operand 59 states and 59 transitions. Second operand 10 states. [2018-01-24 13:28:10,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:10,644 INFO L93 Difference]: Finished difference Result 92 states and 92 transitions. [2018-01-24 13:28:10,644 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 13:28:10,644 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 58 [2018-01-24 13:28:10,645 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:10,645 INFO L225 Difference]: With dead ends: 92 [2018-01-24 13:28:10,645 INFO L226 Difference]: Without dead ends: 60 [2018-01-24 13:28:10,645 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 240 GetRequests, 222 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=133, Invalid=173, Unknown=0, NotChecked=0, Total=306 [2018-01-24 13:28:10,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-01-24 13:28:10,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2018-01-24 13:28:10,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-01-24 13:28:10,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 60 transitions. [2018-01-24 13:28:10,655 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 60 transitions. Word has length 58 [2018-01-24 13:28:10,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:10,655 INFO L432 AbstractCegarLoop]: Abstraction has 60 states and 60 transitions. [2018-01-24 13:28:10,655 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:28:10,655 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 60 transitions. [2018-01-24 13:28:10,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-01-24 13:28:10,656 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:10,656 INFO L322 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:10,657 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:10,657 INFO L82 PathProgramCache]: Analyzing trace with hash -648862830, now seen corresponding path program 4 times [2018-01-24 13:28:10,657 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:10,658 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:10,658 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:28:10,658 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:10,658 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:10,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:10,676 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:10,771 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:10,771 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:10,771 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:28:10,781 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:28:10,781 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:28:10,824 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:10,828 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:10,841 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:10,841 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:11,044 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:11,065 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:11,065 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:28:11,068 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:28:11,068 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:28:11,145 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:11,150 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:11,155 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:11,155 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:11,254 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:11,256 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:28:11,256 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 13:28:11,256 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:28:11,257 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 13:28:11,257 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 13:28:11,257 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=187, Unknown=0, NotChecked=0, Total=342 [2018-01-24 13:28:11,258 INFO L87 Difference]: Start difference. First operand 60 states and 60 transitions. Second operand 11 states. [2018-01-24 13:28:11,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:11,286 INFO L93 Difference]: Finished difference Result 93 states and 93 transitions. [2018-01-24 13:28:11,286 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:28:11,286 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 59 [2018-01-24 13:28:11,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:11,287 INFO L225 Difference]: With dead ends: 93 [2018-01-24 13:28:11,287 INFO L226 Difference]: Without dead ends: 61 [2018-01-24 13:28:11,288 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 245 GetRequests, 225 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=167, Invalid=213, Unknown=0, NotChecked=0, Total=380 [2018-01-24 13:28:11,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-01-24 13:28:11,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2018-01-24 13:28:11,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-01-24 13:28:11,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 61 transitions. [2018-01-24 13:28:11,300 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 61 transitions. Word has length 59 [2018-01-24 13:28:11,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:11,300 INFO L432 AbstractCegarLoop]: Abstraction has 61 states and 61 transitions. [2018-01-24 13:28:11,300 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 13:28:11,301 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 61 transitions. [2018-01-24 13:28:11,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-01-24 13:28:11,301 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:11,302 INFO L322 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:11,302 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:11,302 INFO L82 PathProgramCache]: Analyzing trace with hash -1508445558, now seen corresponding path program 5 times [2018-01-24 13:28:11,302 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:11,303 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:11,303 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:28:11,303 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:11,303 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:11,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:11,322 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:11,475 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:11,475 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:11,475 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:28:11,486 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:28:11,486 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:28:11,501 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:11,504 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:11,510 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:11,526 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:11,588 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:11,593 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:11,596 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:11,608 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:11,608 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:11,944 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:11,965 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:11,965 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:28:11,968 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:28:11,968 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:28:11,980 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:11,984 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:11,993 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:12,010 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:12,057 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:12,078 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:12,083 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:12,089 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:12,089 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:12,192 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:12,193 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:28:12,193 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 13:28:12,193 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:28:12,194 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 13:28:12,194 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 13:28:12,194 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=228, Unknown=0, NotChecked=0, Total=420 [2018-01-24 13:28:12,194 INFO L87 Difference]: Start difference. First operand 61 states and 61 transitions. Second operand 12 states. [2018-01-24 13:28:12,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:12,227 INFO L93 Difference]: Finished difference Result 94 states and 94 transitions. [2018-01-24 13:28:12,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 13:28:12,227 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 60 [2018-01-24 13:28:12,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:12,227 INFO L225 Difference]: With dead ends: 94 [2018-01-24 13:28:12,228 INFO L226 Difference]: Without dead ends: 62 [2018-01-24 13:28:12,228 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 250 GetRequests, 228 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=205, Invalid=257, Unknown=0, NotChecked=0, Total=462 [2018-01-24 13:28:12,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-01-24 13:28:12,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 62. [2018-01-24 13:28:12,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-01-24 13:28:12,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 62 transitions. [2018-01-24 13:28:12,239 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 62 transitions. Word has length 60 [2018-01-24 13:28:12,239 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:12,239 INFO L432 AbstractCegarLoop]: Abstraction has 62 states and 62 transitions. [2018-01-24 13:28:12,240 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 13:28:12,240 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 62 transitions. [2018-01-24 13:28:12,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-01-24 13:28:12,240 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:12,241 INFO L322 BasicCegarLoop]: trace histogram [8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:12,241 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:12,241 INFO L82 PathProgramCache]: Analyzing trace with hash 1909260946, now seen corresponding path program 6 times [2018-01-24 13:28:12,241 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:12,242 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:12,242 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:28:12,242 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:12,242 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:12,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:12,260 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:12,406 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:12,406 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:12,406 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:28:12,418 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:28:12,418 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:28:12,441 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:28:12,448 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:28:12,478 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:28:12,574 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:28:12,873 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:28:12,874 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:12,876 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:12,884 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:12,884 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:13,171 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:13,191 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:13,191 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:28:13,196 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:28:13,196 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:28:13,244 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:28:13,286 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:28:13,973 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:28:25,995 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:28:38,035 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:28:38,093 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:38,100 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:38,116 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:38,116 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:38,237 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:38,239 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:28:38,240 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 13:28:38,240 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:28:38,240 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 13:28:38,240 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 13:28:38,240 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=232, Invalid=274, Unknown=0, NotChecked=0, Total=506 [2018-01-24 13:28:38,240 INFO L87 Difference]: Start difference. First operand 62 states and 62 transitions. Second operand 13 states. [2018-01-24 13:28:38,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:38,273 INFO L93 Difference]: Finished difference Result 95 states and 95 transitions. [2018-01-24 13:28:38,273 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 13:28:38,273 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 61 [2018-01-24 13:28:38,273 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:38,274 INFO L225 Difference]: With dead ends: 95 [2018-01-24 13:28:38,274 INFO L226 Difference]: Without dead ends: 63 [2018-01-24 13:28:38,275 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 255 GetRequests, 231 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 59 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=246, Invalid=306, Unknown=0, NotChecked=0, Total=552 [2018-01-24 13:28:38,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-01-24 13:28:38,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2018-01-24 13:28:38,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-01-24 13:28:38,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 63 transitions. [2018-01-24 13:28:38,287 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 63 transitions. Word has length 61 [2018-01-24 13:28:38,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:38,288 INFO L432 AbstractCegarLoop]: Abstraction has 63 states and 63 transitions. [2018-01-24 13:28:38,288 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 13:28:38,288 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 63 transitions. [2018-01-24 13:28:38,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 13:28:38,289 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:38,289 INFO L322 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:38,289 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:38,289 INFO L82 PathProgramCache]: Analyzing trace with hash 483980170, now seen corresponding path program 7 times [2018-01-24 13:28:38,289 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:38,290 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:38,291 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:28:38,291 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:38,291 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:38,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:38,309 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:38,434 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:38,434 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:38,434 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:28:38,439 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:38,439 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:28:38,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:38,469 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:38,476 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:38,477 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:38,781 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:38,801 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:38,801 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:28:38,804 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:38,804 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:28:38,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:38,866 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:38,871 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:38,871 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:39,002 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:39,004 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:28:39,004 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 13:28:39,004 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:28:39,005 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 13:28:39,005 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 13:28:39,005 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=272, Invalid=328, Unknown=0, NotChecked=0, Total=600 [2018-01-24 13:28:39,005 INFO L87 Difference]: Start difference. First operand 63 states and 63 transitions. Second operand 14 states. [2018-01-24 13:28:39,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:39,062 INFO L93 Difference]: Finished difference Result 96 states and 96 transitions. [2018-01-24 13:28:39,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 13:28:39,063 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 62 [2018-01-24 13:28:39,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:39,064 INFO L225 Difference]: With dead ends: 96 [2018-01-24 13:28:39,064 INFO L226 Difference]: Without dead ends: 64 [2018-01-24 13:28:39,065 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 260 GetRequests, 234 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 84 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=287, Invalid=363, Unknown=0, NotChecked=0, Total=650 [2018-01-24 13:28:39,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-01-24 13:28:39,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 64. [2018-01-24 13:28:39,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-01-24 13:28:39,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 64 transitions. [2018-01-24 13:28:39,078 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 64 transitions. Word has length 62 [2018-01-24 13:28:39,078 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:39,078 INFO L432 AbstractCegarLoop]: Abstraction has 64 states and 64 transitions. [2018-01-24 13:28:39,078 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 13:28:39,078 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 64 transitions. [2018-01-24 13:28:39,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-01-24 13:28:39,079 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:39,079 INFO L322 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:39,079 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:39,080 INFO L82 PathProgramCache]: Analyzing trace with hash -750050926, now seen corresponding path program 8 times [2018-01-24 13:28:39,080 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:39,081 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:39,081 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:28:39,081 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:39,081 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:39,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:39,098 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:39,214 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:39,215 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:39,215 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:28:39,224 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:28:39,225 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:28:39,244 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:39,253 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:39,254 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:39,256 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:39,264 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:39,265 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:39,624 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:39,644 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:39,645 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:28:39,651 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:28:39,651 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:28:39,689 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:39,729 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:28:39,751 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:39,758 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:39,765 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:39,765 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:39,956 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:39,958 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:28:39,959 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 27 [2018-01-24 13:28:39,959 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:28:39,959 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 13:28:39,959 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 13:28:39,960 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=312, Invalid=390, Unknown=0, NotChecked=0, Total=702 [2018-01-24 13:28:39,960 INFO L87 Difference]: Start difference. First operand 64 states and 64 transitions. Second operand 15 states. [2018-01-24 13:28:40,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:28:40,017 INFO L93 Difference]: Finished difference Result 97 states and 97 transitions. [2018-01-24 13:28:40,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 13:28:40,019 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 63 [2018-01-24 13:28:40,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:28:40,020 INFO L225 Difference]: With dead ends: 97 [2018-01-24 13:28:40,020 INFO L226 Difference]: Without dead ends: 65 [2018-01-24 13:28:40,021 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 265 GetRequests, 237 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 113 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=328, Invalid=428, Unknown=0, NotChecked=0, Total=756 [2018-01-24 13:28:40,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2018-01-24 13:28:40,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 65. [2018-01-24 13:28:40,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65 states. [2018-01-24 13:28:40,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 65 transitions. [2018-01-24 13:28:40,034 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 65 transitions. Word has length 63 [2018-01-24 13:28:40,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:28:40,034 INFO L432 AbstractCegarLoop]: Abstraction has 65 states and 65 transitions. [2018-01-24 13:28:40,034 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 13:28:40,034 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 65 transitions. [2018-01-24 13:28:40,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-01-24 13:28:40,035 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:28:40,035 INFO L322 BasicCegarLoop]: trace histogram [11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:28:40,035 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:28:40,036 INFO L82 PathProgramCache]: Analyzing trace with hash -350309238, now seen corresponding path program 9 times [2018-01-24 13:28:40,036 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:28:40,037 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:40,037 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:28:40,037 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:28:40,037 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:28:40,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:28:40,055 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:28:40,239 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:40,239 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:40,239 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:28:40,249 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:28:40,249 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:28:40,278 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:40,288 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:40,317 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:40,466 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:41,031 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:41,999 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:42,683 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:42,684 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:28:42,723 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:28:42,733 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:42,733 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:28:43,031 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:28:43,065 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:28:43,065 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:28:43,071 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:28:43,071 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:28:43,102 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:43,128 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:43,235 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:43,505 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:28:55,521 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command Received shutdown request... [2018-01-24 13:29:07,565 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command Cannot interrupt operation gracefully because timeout expired. Forcing shutdown