java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_2_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 13:33:05,197 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 13:33:05,199 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 13:33:05,214 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 13:33:05,215 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 13:33:05,215 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 13:33:05,216 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 13:33:05,217 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 13:33:05,219 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 13:33:05,219 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 13:33:05,220 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 13:33:05,220 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 13:33:05,221 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 13:33:05,221 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 13:33:05,222 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 13:33:05,225 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 13:33:05,227 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 13:33:05,229 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 13:33:05,230 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 13:33:05,231 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 13:33:05,234 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 13:33:05,234 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 13:33:05,234 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 13:33:05,235 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 13:33:05,236 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 13:33:05,237 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 13:33:05,238 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 13:33:05,238 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 13:33:05,238 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 13:33:05,239 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 13:33:05,239 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 13:33:05,240 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf [2018-01-24 13:33:05,249 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 13:33:05,250 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 13:33:05,250 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 13:33:05,251 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 13:33:05,251 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 13:33:05,251 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 13:33:05,251 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 13:33:05,252 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 13:33:05,252 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 13:33:05,252 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 13:33:05,252 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 13:33:05,253 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 13:33:05,253 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 13:33:05,253 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 13:33:05,253 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 13:33:05,253 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 13:33:05,253 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 13:33:05,254 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 13:33:05,254 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 13:33:05,254 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 13:33:05,254 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 13:33:05,255 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 13:33:05,255 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 13:33:05,255 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:33:05,255 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 13:33:05,255 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 13:33:05,256 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 13:33:05,256 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 13:33:05,256 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-01-24 13:33:05,256 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 13:33:05,256 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 13:33:05,256 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 13:33:05,257 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 13:33:05,257 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 13:33:05,292 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 13:33:05,305 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 13:33:05,309 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 13:33:05,310 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 13:33:05,311 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 13:33:05,312 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_2_true-valid-memsafety_true-termination.i [2018-01-24 13:33:05,519 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 13:33:05,526 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 13:33:05,527 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 13:33:05,527 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 13:33:05,533 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 13:33:05,534 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:33:05" (1/1) ... [2018-01-24 13:33:05,536 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@71d0b9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:33:05, skipping insertion in model container [2018-01-24 13:33:05,536 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:33:05" (1/1) ... [2018-01-24 13:33:05,550 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:33:05,598 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:33:05,719 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:33:05,743 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:33:05,756 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:33:05 WrapperNode [2018-01-24 13:33:05,757 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 13:33:05,758 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 13:33:05,758 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 13:33:05,758 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 13:33:05,771 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:33:05" (1/1) ... [2018-01-24 13:33:05,772 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:33:05" (1/1) ... [2018-01-24 13:33:05,786 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:33:05" (1/1) ... [2018-01-24 13:33:05,786 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:33:05" (1/1) ... [2018-01-24 13:33:05,794 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:33:05" (1/1) ... [2018-01-24 13:33:05,797 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:33:05" (1/1) ... [2018-01-24 13:33:05,799 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:33:05" (1/1) ... [2018-01-24 13:33:05,802 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 13:33:05,802 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 13:33:05,802 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 13:33:05,802 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 13:33:05,803 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:33:05" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:33:05,849 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 13:33:05,849 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 13:33:05,849 INFO L136 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2018-01-24 13:33:05,849 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-01-24 13:33:05,849 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-01-24 13:33:05,850 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_atomic_add_return [2018-01-24 13:33:05,850 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_atomic_sub_return [2018-01-24 13:33:05,850 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_sub [2018-01-24 13:33:05,850 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_init [2018-01-24 13:33:05,850 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_get [2018-01-24 13:33:05,850 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_put [2018-01-24 13:33:05,850 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-01-24 13:33:05,850 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-01-24 13:33:05,850 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_put [2018-01-24 13:33:05,850 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_get [2018-01-24 13:33:05,851 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init_internal [2018-01-24 13:33:05,851 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init [2018-01-24 13:33:05,851 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_create [2018-01-24 13:33:05,851 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-01-24 13:33:05,851 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 13:33:05,851 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 13:33:05,851 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 13:33:05,852 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-01-24 13:33:05,852 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-01-24 13:33:05,852 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 13:33:05,852 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 13:33:05,852 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 13:33:05,852 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-01-24 13:33:05,853 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-01-24 13:33:05,853 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-01-24 13:33:05,853 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-01-24 13:33:05,853 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-24 13:33:05,853 INFO L128 BoogieDeclarations]: Found specification of procedure memset [2018-01-24 13:33:05,854 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-01-24 13:33:05,854 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-01-24 13:33:05,854 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_atomic_add_return [2018-01-24 13:33:05,854 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_atomic_sub_return [2018-01-24 13:33:05,854 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_sub [2018-01-24 13:33:05,854 INFO L128 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2018-01-24 13:33:05,854 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_init [2018-01-24 13:33:05,854 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_get [2018-01-24 13:33:05,855 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_put [2018-01-24 13:33:05,855 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-01-24 13:33:05,855 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-01-24 13:33:05,855 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_put [2018-01-24 13:33:05,855 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_get [2018-01-24 13:33:05,855 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init_internal [2018-01-24 13:33:05,855 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init [2018-01-24 13:33:05,856 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_create [2018-01-24 13:33:05,856 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-01-24 13:33:05,856 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 13:33:05,856 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 13:33:05,856 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 13:33:06,147 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-01-24 13:33:06,368 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 13:33:06,369 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:33:06 BoogieIcfgContainer [2018-01-24 13:33:06,369 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 13:33:06,370 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 13:33:06,370 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 13:33:06,372 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 13:33:06,372 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 01:33:05" (1/3) ... [2018-01-24 13:33:06,373 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@58088d20 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:33:06, skipping insertion in model container [2018-01-24 13:33:06,373 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:33:05" (2/3) ... [2018-01-24 13:33:06,373 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@58088d20 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:33:06, skipping insertion in model container [2018-01-24 13:33:06,373 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:33:06" (3/3) ... [2018-01-24 13:33:06,375 INFO L105 eAbstractionObserver]: Analyzing ICFG memleaks_test22_2_true-valid-memsafety_true-termination.i [2018-01-24 13:33:06,382 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 13:33:06,390 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2018-01-24 13:33:06,445 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 13:33:06,445 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 13:33:06,445 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 13:33:06,446 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 13:33:06,446 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 13:33:06,446 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 13:33:06,446 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 13:33:06,446 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 13:33:06,447 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 13:33:06,470 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states. [2018-01-24 13:33:06,476 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 13:33:06,477 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:06,478 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:06,478 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:06,483 INFO L82 PathProgramCache]: Analyzing trace with hash -998986606, now seen corresponding path program 1 times [2018-01-24 13:33:06,486 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:06,532 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:06,532 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:06,533 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:06,533 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:06,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:06,586 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:06,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:06,780 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:06,781 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 13:33:06,781 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:06,785 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 13:33:06,799 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 13:33:06,800 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:33:06,802 INFO L87 Difference]: Start difference. First operand 143 states. Second operand 5 states. [2018-01-24 13:33:06,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:06,877 INFO L93 Difference]: Finished difference Result 274 states and 291 transitions. [2018-01-24 13:33:06,878 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:33:06,879 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-01-24 13:33:06,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:06,893 INFO L225 Difference]: With dead ends: 274 [2018-01-24 13:33:06,893 INFO L226 Difference]: Without dead ends: 146 [2018-01-24 13:33:06,897 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:33:06,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-01-24 13:33:06,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 144. [2018-01-24 13:33:06,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-01-24 13:33:06,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 153 transitions. [2018-01-24 13:33:06,944 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 153 transitions. Word has length 17 [2018-01-24 13:33:06,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:06,944 INFO L432 AbstractCegarLoop]: Abstraction has 144 states and 153 transitions. [2018-01-24 13:33:06,944 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 13:33:06,945 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 153 transitions. [2018-01-24 13:33:06,945 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-01-24 13:33:06,946 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:06,946 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:06,946 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:06,946 INFO L82 PathProgramCache]: Analyzing trace with hash -2077747980, now seen corresponding path program 1 times [2018-01-24 13:33:06,946 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:06,948 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:06,948 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:06,948 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:06,948 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:06,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:06,969 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:07,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:07,012 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:07,012 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 13:33:07,012 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:07,014 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:33:07,015 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:33:07,015 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:33:07,015 INFO L87 Difference]: Start difference. First operand 144 states and 153 transitions. Second operand 6 states. [2018-01-24 13:33:07,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:07,268 INFO L93 Difference]: Finished difference Result 146 states and 155 transitions. [2018-01-24 13:33:07,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:33:07,269 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2018-01-24 13:33:07,269 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:07,270 INFO L225 Difference]: With dead ends: 146 [2018-01-24 13:33:07,271 INFO L226 Difference]: Without dead ends: 145 [2018-01-24 13:33:07,271 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:33:07,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-01-24 13:33:07,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 143. [2018-01-24 13:33:07,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-01-24 13:33:07,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 152 transitions. [2018-01-24 13:33:07,282 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 152 transitions. Word has length 19 [2018-01-24 13:33:07,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:07,283 INFO L432 AbstractCegarLoop]: Abstraction has 143 states and 152 transitions. [2018-01-24 13:33:07,283 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:33:07,283 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 152 transitions. [2018-01-24 13:33:07,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-01-24 13:33:07,283 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:07,283 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:07,284 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:07,284 INFO L82 PathProgramCache]: Analyzing trace with hash -2077747979, now seen corresponding path program 1 times [2018-01-24 13:33:07,284 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:07,285 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:07,285 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:07,285 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:07,285 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:07,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:07,308 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:07,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:07,574 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:07,574 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 13:33:07,574 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:07,575 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 13:33:07,575 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 13:33:07,575 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:33:07,575 INFO L87 Difference]: Start difference. First operand 143 states and 152 transitions. Second operand 7 states. [2018-01-24 13:33:07,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:07,773 INFO L93 Difference]: Finished difference Result 145 states and 154 transitions. [2018-01-24 13:33:07,774 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 13:33:07,774 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2018-01-24 13:33:07,775 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:07,777 INFO L225 Difference]: With dead ends: 145 [2018-01-24 13:33:07,777 INFO L226 Difference]: Without dead ends: 144 [2018-01-24 13:33:07,778 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-01-24 13:33:07,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-01-24 13:33:07,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 142. [2018-01-24 13:33:07,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-01-24 13:33:07,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 151 transitions. [2018-01-24 13:33:07,809 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 151 transitions. Word has length 19 [2018-01-24 13:33:07,809 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:07,809 INFO L432 AbstractCegarLoop]: Abstraction has 142 states and 151 transitions. [2018-01-24 13:33:07,809 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 13:33:07,809 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 151 transitions. [2018-01-24 13:33:07,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 13:33:07,810 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:07,810 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:07,811 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:07,811 INFO L82 PathProgramCache]: Analyzing trace with hash -471802203, now seen corresponding path program 1 times [2018-01-24 13:33:07,811 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:07,812 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:07,812 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:07,812 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:07,812 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:07,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:07,831 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:07,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:07,913 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:07,913 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-01-24 13:33:07,913 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:07,913 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 13:33:07,914 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 13:33:07,914 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:33:07,914 INFO L87 Difference]: Start difference. First operand 142 states and 151 transitions. Second operand 7 states. [2018-01-24 13:33:07,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:07,981 INFO L93 Difference]: Finished difference Result 238 states and 253 transitions. [2018-01-24 13:33:07,981 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 13:33:07,981 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 27 [2018-01-24 13:33:07,982 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:07,984 INFO L225 Difference]: With dead ends: 238 [2018-01-24 13:33:07,984 INFO L226 Difference]: Without dead ends: 159 [2018-01-24 13:33:07,985 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:33:07,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2018-01-24 13:33:08,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 151. [2018-01-24 13:33:08,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-01-24 13:33:08,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 160 transitions. [2018-01-24 13:33:08,002 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 160 transitions. Word has length 27 [2018-01-24 13:33:08,003 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:08,003 INFO L432 AbstractCegarLoop]: Abstraction has 151 states and 160 transitions. [2018-01-24 13:33:08,003 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 13:33:08,003 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 160 transitions. [2018-01-24 13:33:08,004 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-24 13:33:08,004 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:08,005 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:08,005 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:08,005 INFO L82 PathProgramCache]: Analyzing trace with hash 131109242, now seen corresponding path program 1 times [2018-01-24 13:33:08,005 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:08,007 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:08,007 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:08,007 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:08,007 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:08,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:08,028 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:08,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:08,140 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:08,141 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-01-24 13:33:08,141 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:08,141 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:33:08,142 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:33:08,142 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:33:08,142 INFO L87 Difference]: Start difference. First operand 151 states and 160 transitions. Second operand 10 states. [2018-01-24 13:33:08,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:08,351 INFO L93 Difference]: Finished difference Result 151 states and 160 transitions. [2018-01-24 13:33:08,351 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:33:08,351 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 34 [2018-01-24 13:33:08,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:08,353 INFO L225 Difference]: With dead ends: 151 [2018-01-24 13:33:08,353 INFO L226 Difference]: Without dead ends: 150 [2018-01-24 13:33:08,353 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:33:08,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-01-24 13:33:08,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 150. [2018-01-24 13:33:08,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-01-24 13:33:08,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 159 transitions. [2018-01-24 13:33:08,365 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 159 transitions. Word has length 34 [2018-01-24 13:33:08,365 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:08,365 INFO L432 AbstractCegarLoop]: Abstraction has 150 states and 159 transitions. [2018-01-24 13:33:08,365 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:33:08,365 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 159 transitions. [2018-01-24 13:33:08,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-24 13:33:08,367 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:08,367 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:08,367 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:08,367 INFO L82 PathProgramCache]: Analyzing trace with hash 131109243, now seen corresponding path program 1 times [2018-01-24 13:33:08,367 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:08,368 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:08,369 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:08,369 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:08,369 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:08,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:08,385 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:08,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:08,418 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:08,418 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 13:33:08,418 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:08,418 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 13:33:08,418 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 13:33:08,419 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 13:33:08,419 INFO L87 Difference]: Start difference. First operand 150 states and 159 transitions. Second operand 4 states. [2018-01-24 13:33:08,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:08,444 INFO L93 Difference]: Finished difference Result 266 states and 282 transitions. [2018-01-24 13:33:08,453 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 13:33:08,453 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34 [2018-01-24 13:33:08,454 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:08,455 INFO L225 Difference]: With dead ends: 266 [2018-01-24 13:33:08,455 INFO L226 Difference]: Without dead ends: 151 [2018-01-24 13:33:08,456 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:33:08,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-01-24 13:33:08,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 151. [2018-01-24 13:33:08,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-01-24 13:33:08,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 160 transitions. [2018-01-24 13:33:08,467 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 160 transitions. Word has length 34 [2018-01-24 13:33:08,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:08,468 INFO L432 AbstractCegarLoop]: Abstraction has 151 states and 160 transitions. [2018-01-24 13:33:08,468 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 13:33:08,468 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 160 transitions. [2018-01-24 13:33:08,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-01-24 13:33:08,469 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:08,469 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:08,469 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:08,469 INFO L82 PathProgramCache]: Analyzing trace with hash -2110897305, now seen corresponding path program 1 times [2018-01-24 13:33:08,470 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:08,471 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:08,471 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:08,471 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:08,471 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:08,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:08,486 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:08,540 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:08,540 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:08,540 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:08,547 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:08,548 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:33:08,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:08,620 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:08,649 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:08,649 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:08,755 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:08,790 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:08,790 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:33:08,794 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:08,794 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:33:08,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:08,847 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:08,854 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:08,854 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:08,898 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:08,918 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:33:08,918 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 13:33:08,919 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:33:08,919 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:33:08,919 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:33:08,919 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2018-01-24 13:33:08,920 INFO L87 Difference]: Start difference. First operand 151 states and 160 transitions. Second operand 6 states. [2018-01-24 13:33:08,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:08,959 INFO L93 Difference]: Finished difference Result 267 states and 283 transitions. [2018-01-24 13:33:08,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:33:08,962 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-01-24 13:33:08,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:08,964 INFO L225 Difference]: With dead ends: 267 [2018-01-24 13:33:08,964 INFO L226 Difference]: Without dead ends: 152 [2018-01-24 13:33:08,965 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 144 GetRequests, 134 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=53, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:33:08,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-01-24 13:33:08,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 152. [2018-01-24 13:33:08,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-01-24 13:33:08,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 161 transitions. [2018-01-24 13:33:08,977 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 161 transitions. Word has length 35 [2018-01-24 13:33:08,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:08,978 INFO L432 AbstractCegarLoop]: Abstraction has 152 states and 161 transitions. [2018-01-24 13:33:08,978 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:33:08,978 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 161 transitions. [2018-01-24 13:33:08,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-24 13:33:08,980 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:08,980 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:08,980 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:08,980 INFO L82 PathProgramCache]: Analyzing trace with hash 1181841647, now seen corresponding path program 1 times [2018-01-24 13:33:08,981 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:08,982 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:08,982 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:08,982 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:08,982 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:08,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:08,999 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:09,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:09,074 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:09,074 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-01-24 13:33:09,074 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:09,075 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 13:33:09,075 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 13:33:09,076 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:33:09,076 INFO L87 Difference]: Start difference. First operand 152 states and 161 transitions. Second operand 7 states. [2018-01-24 13:33:09,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:09,169 INFO L93 Difference]: Finished difference Result 220 states and 236 transitions. [2018-01-24 13:33:09,169 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 13:33:09,169 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 36 [2018-01-24 13:33:09,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:09,171 INFO L225 Difference]: With dead ends: 220 [2018-01-24 13:33:09,171 INFO L226 Difference]: Without dead ends: 163 [2018-01-24 13:33:09,172 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:33:09,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-01-24 13:33:09,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 159. [2018-01-24 13:33:09,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-01-24 13:33:09,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 169 transitions. [2018-01-24 13:33:09,190 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 169 transitions. Word has length 36 [2018-01-24 13:33:09,190 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:09,190 INFO L432 AbstractCegarLoop]: Abstraction has 159 states and 169 transitions. [2018-01-24 13:33:09,191 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 13:33:09,191 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 169 transitions. [2018-01-24 13:33:09,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-24 13:33:09,192 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:09,192 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:09,192 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:09,193 INFO L82 PathProgramCache]: Analyzing trace with hash 1401343739, now seen corresponding path program 2 times [2018-01-24 13:33:09,193 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:09,194 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:09,194 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:09,194 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:09,195 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:09,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:09,213 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:09,287 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:09,287 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:09,287 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:09,292 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:33:09,292 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:33:09,318 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:09,327 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:33:09,332 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:09,362 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:33:09,364 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:09,380 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:33:09,381 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:09,392 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:33:09,392 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:33:11,649 WARN L143 SmtUtils]: Spent 2051ms on a formula simplification that was a NOOP. DAG size: 27 [2018-01-24 13:33:11,984 WARN L146 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 45 DAG size of output 17 [2018-01-24 13:33:12,231 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:33:12,231 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:12,771 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:33:12,796 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:33:12,796 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [14, 13] imperfect sequences [6] total 31 [2018-01-24 13:33:12,796 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:12,796 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 13:33:12,797 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 13:33:12,797 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=840, Unknown=0, NotChecked=0, Total=930 [2018-01-24 13:33:12,797 INFO L87 Difference]: Start difference. First operand 159 states and 169 transitions. Second operand 15 states. [2018-01-24 13:33:13,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:14,245 INFO L93 Difference]: Finished difference Result 179 states and 189 transitions. [2018-01-24 13:33:14,246 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 13:33:14,246 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 36 [2018-01-24 13:33:14,247 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:14,248 INFO L225 Difference]: With dead ends: 179 [2018-01-24 13:33:14,248 INFO L226 Difference]: Without dead ends: 178 [2018-01-24 13:33:14,249 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 81 GetRequests, 47 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 251 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=118, Invalid=1072, Unknown=0, NotChecked=0, Total=1190 [2018-01-24 13:33:14,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states. [2018-01-24 13:33:14,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 158. [2018-01-24 13:33:14,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-01-24 13:33:14,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 168 transitions. [2018-01-24 13:33:14,267 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 168 transitions. Word has length 36 [2018-01-24 13:33:14,267 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:14,267 INFO L432 AbstractCegarLoop]: Abstraction has 158 states and 168 transitions. [2018-01-24 13:33:14,267 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 13:33:14,267 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 168 transitions. [2018-01-24 13:33:14,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-24 13:33:14,269 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:14,269 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:14,269 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:14,269 INFO L82 PathProgramCache]: Analyzing trace with hash 599601906, now seen corresponding path program 1 times [2018-01-24 13:33:14,269 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:14,271 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:14,271 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:33:14,271 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:14,271 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:14,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:14,287 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:14,371 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:33:14,372 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:14,372 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-01-24 13:33:14,372 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:14,372 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:33:14,373 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:33:14,373 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:33:14,373 INFO L87 Difference]: Start difference. First operand 158 states and 168 transitions. Second operand 10 states. [2018-01-24 13:33:14,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:14,640 INFO L93 Difference]: Finished difference Result 158 states and 168 transitions. [2018-01-24 13:33:14,640 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:33:14,640 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 41 [2018-01-24 13:33:14,641 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:14,641 INFO L225 Difference]: With dead ends: 158 [2018-01-24 13:33:14,641 INFO L226 Difference]: Without dead ends: 156 [2018-01-24 13:33:14,642 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:33:14,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-01-24 13:33:14,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 156. [2018-01-24 13:33:14,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-01-24 13:33:14,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 166 transitions. [2018-01-24 13:33:14,659 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 166 transitions. Word has length 41 [2018-01-24 13:33:14,660 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:14,660 INFO L432 AbstractCegarLoop]: Abstraction has 156 states and 166 transitions. [2018-01-24 13:33:14,660 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:33:14,660 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 166 transitions. [2018-01-24 13:33:14,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-24 13:33:14,661 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:14,661 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:14,661 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:14,662 INFO L82 PathProgramCache]: Analyzing trace with hash 599601907, now seen corresponding path program 1 times [2018-01-24 13:33:14,662 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:14,663 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:14,663 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:14,663 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:14,663 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:14,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:14,677 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:14,734 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:14,734 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:14,735 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:14,744 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:14,745 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:33:14,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:14,792 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:14,816 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:14,817 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:14,898 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:14,930 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:14,930 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:33:14,934 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:14,934 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:33:14,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:14,997 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:15,003 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:15,003 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:15,041 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:15,042 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:33:15,042 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 13:33:15,042 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:33:15,043 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 13:33:15,043 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 13:33:15,043 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=63, Unknown=0, NotChecked=0, Total=110 [2018-01-24 13:33:15,043 INFO L87 Difference]: Start difference. First operand 156 states and 166 transitions. Second operand 7 states. [2018-01-24 13:33:15,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:15,076 INFO L93 Difference]: Finished difference Result 269 states and 286 transitions. [2018-01-24 13:33:15,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:33:15,077 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 41 [2018-01-24 13:33:15,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:15,078 INFO L225 Difference]: With dead ends: 269 [2018-01-24 13:33:15,078 INFO L226 Difference]: Without dead ends: 157 [2018-01-24 13:33:15,079 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 169 GetRequests, 157 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=77, Unknown=0, NotChecked=0, Total=132 [2018-01-24 13:33:15,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-01-24 13:33:15,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 157. [2018-01-24 13:33:15,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-01-24 13:33:15,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 167 transitions. [2018-01-24 13:33:15,091 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 167 transitions. Word has length 41 [2018-01-24 13:33:15,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:15,091 INFO L432 AbstractCegarLoop]: Abstraction has 157 states and 167 transitions. [2018-01-24 13:33:15,091 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 13:33:15,091 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 167 transitions. [2018-01-24 13:33:15,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-01-24 13:33:15,092 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:15,092 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:15,092 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:15,093 INFO L82 PathProgramCache]: Analyzing trace with hash -1379512829, now seen corresponding path program 1 times [2018-01-24 13:33:15,093 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:15,094 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:15,094 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:15,094 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:15,094 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:15,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:15,104 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:15,142 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 13:33:15,143 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:15,143 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 13:33:15,143 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:15,143 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 13:33:15,144 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 13:33:15,144 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 13:33:15,144 INFO L87 Difference]: Start difference. First operand 157 states and 167 transitions. Second operand 3 states. [2018-01-24 13:33:15,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:15,349 INFO L93 Difference]: Finished difference Result 176 states and 189 transitions. [2018-01-24 13:33:15,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 13:33:15,350 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 39 [2018-01-24 13:33:15,350 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:15,351 INFO L225 Difference]: With dead ends: 176 [2018-01-24 13:33:15,351 INFO L226 Difference]: Without dead ends: 161 [2018-01-24 13:33:15,351 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 11 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 13:33:15,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-01-24 13:33:15,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 153. [2018-01-24 13:33:15,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2018-01-24 13:33:15,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 162 transitions. [2018-01-24 13:33:15,365 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 162 transitions. Word has length 39 [2018-01-24 13:33:15,365 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:15,365 INFO L432 AbstractCegarLoop]: Abstraction has 153 states and 162 transitions. [2018-01-24 13:33:15,365 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 13:33:15,365 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 162 transitions. [2018-01-24 13:33:15,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 13:33:15,366 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:15,366 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:15,366 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:15,366 INFO L82 PathProgramCache]: Analyzing trace with hash 710655879, now seen corresponding path program 2 times [2018-01-24 13:33:15,366 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:15,367 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:15,368 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:15,368 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:15,368 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:15,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:15,382 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:15,478 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:15,478 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:15,478 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:15,483 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:33:15,483 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:33:15,502 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:15,505 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:33:15,508 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:15,513 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:33:15,514 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:15,526 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:33:15,526 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:15,540 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:33:15,540 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:33:16,138 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:33:16,138 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:16,577 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:33:16,599 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:33:16,600 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15, 13] imperfect sequences [7] total 33 [2018-01-24 13:33:16,600 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:16,600 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 13:33:16,600 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 13:33:16,601 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=951, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 13:33:16,601 INFO L87 Difference]: Start difference. First operand 153 states and 162 transitions. Second operand 16 states. [2018-01-24 13:33:17,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:17,521 INFO L93 Difference]: Finished difference Result 157 states and 165 transitions. [2018-01-24 13:33:17,521 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 13:33:17,521 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 42 [2018-01-24 13:33:17,521 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:17,522 INFO L225 Difference]: With dead ends: 157 [2018-01-24 13:33:17,522 INFO L226 Difference]: Without dead ends: 155 [2018-01-24 13:33:17,523 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 57 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 317 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=136, Invalid=1196, Unknown=0, NotChecked=0, Total=1332 [2018-01-24 13:33:17,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states. [2018-01-24 13:33:17,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 151. [2018-01-24 13:33:17,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-01-24 13:33:17,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 160 transitions. [2018-01-24 13:33:17,538 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 160 transitions. Word has length 42 [2018-01-24 13:33:17,538 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:17,538 INFO L432 AbstractCegarLoop]: Abstraction has 151 states and 160 transitions. [2018-01-24 13:33:17,538 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 13:33:17,538 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 160 transitions. [2018-01-24 13:33:17,539 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-24 13:33:17,539 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:17,539 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:17,539 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:17,539 INFO L82 PathProgramCache]: Analyzing trace with hash -495427355, now seen corresponding path program 1 times [2018-01-24 13:33:17,539 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:17,540 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:17,540 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:33:17,540 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:17,541 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:17,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:17,546 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:17,577 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 13:33:17,577 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:17,577 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 13:33:17,578 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:17,578 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:33:17,578 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:33:17,578 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:33:17,578 INFO L87 Difference]: Start difference. First operand 151 states and 160 transitions. Second operand 6 states. [2018-01-24 13:33:17,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:17,603 INFO L93 Difference]: Finished difference Result 155 states and 163 transitions. [2018-01-24 13:33:17,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:33:17,604 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 41 [2018-01-24 13:33:17,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:17,604 INFO L225 Difference]: With dead ends: 155 [2018-01-24 13:33:17,605 INFO L226 Difference]: Without dead ends: 135 [2018-01-24 13:33:17,605 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:33:17,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-01-24 13:33:17,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 135. [2018-01-24 13:33:17,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-01-24 13:33:17,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 142 transitions. [2018-01-24 13:33:17,617 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 142 transitions. Word has length 41 [2018-01-24 13:33:17,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:17,617 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 142 transitions. [2018-01-24 13:33:17,617 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:33:17,617 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 142 transitions. [2018-01-24 13:33:17,617 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-01-24 13:33:17,618 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:17,618 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:17,618 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:17,618 INFO L82 PathProgramCache]: Analyzing trace with hash -961369019, now seen corresponding path program 1 times [2018-01-24 13:33:17,618 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:17,619 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:17,619 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:17,619 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:17,619 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:17,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:17,629 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:17,701 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:33:17,702 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:17,702 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-01-24 13:33:17,702 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:17,702 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 13:33:17,702 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 13:33:17,703 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:33:17,703 INFO L87 Difference]: Start difference. First operand 135 states and 142 transitions. Second operand 8 states. [2018-01-24 13:33:17,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:17,790 INFO L93 Difference]: Finished difference Result 223 states and 234 transitions. [2018-01-24 13:33:17,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 13:33:17,790 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 45 [2018-01-24 13:33:17,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:17,791 INFO L225 Difference]: With dead ends: 223 [2018-01-24 13:33:17,791 INFO L226 Difference]: Without dead ends: 135 [2018-01-24 13:33:17,791 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:33:17,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-01-24 13:33:17,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 135. [2018-01-24 13:33:17,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-01-24 13:33:17,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 141 transitions. [2018-01-24 13:33:17,805 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 141 transitions. Word has length 45 [2018-01-24 13:33:17,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:17,805 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 141 transitions. [2018-01-24 13:33:17,805 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 13:33:17,805 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 141 transitions. [2018-01-24 13:33:17,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-01-24 13:33:17,806 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:17,806 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:17,806 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:17,806 INFO L82 PathProgramCache]: Analyzing trace with hash -1966279804, now seen corresponding path program 1 times [2018-01-24 13:33:17,806 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:17,807 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:17,807 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:17,807 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:17,807 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:17,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:17,816 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:17,938 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:33:17,938 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:17,938 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-01-24 13:33:17,938 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:17,939 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:33:17,939 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:33:17,939 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:33:17,939 INFO L87 Difference]: Start difference. First operand 135 states and 141 transitions. Second operand 10 states. [2018-01-24 13:33:18,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:18,058 INFO L93 Difference]: Finished difference Result 225 states and 235 transitions. [2018-01-24 13:33:18,058 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:33:18,059 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 50 [2018-01-24 13:33:18,059 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:18,060 INFO L225 Difference]: With dead ends: 225 [2018-01-24 13:33:18,060 INFO L226 Difference]: Without dead ends: 135 [2018-01-24 13:33:18,061 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:33:18,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-01-24 13:33:18,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 135. [2018-01-24 13:33:18,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-01-24 13:33:18,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 140 transitions. [2018-01-24 13:33:18,079 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 140 transitions. Word has length 50 [2018-01-24 13:33:18,080 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:18,080 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 140 transitions. [2018-01-24 13:33:18,080 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:33:18,080 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 140 transitions. [2018-01-24 13:33:18,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-01-24 13:33:18,081 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:18,081 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:18,081 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:18,081 INFO L82 PathProgramCache]: Analyzing trace with hash 273504900, now seen corresponding path program 1 times [2018-01-24 13:33:18,081 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:18,082 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:18,082 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:18,082 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:18,082 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:18,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:18,099 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:18,309 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:33:18,309 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:18,309 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-01-24 13:33:18,309 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:18,310 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 13:33:18,310 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 13:33:18,310 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=133, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:33:18,310 INFO L87 Difference]: Start difference. First operand 135 states and 140 transitions. Second operand 13 states. [2018-01-24 13:33:19,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:19,060 INFO L93 Difference]: Finished difference Result 135 states and 140 transitions. [2018-01-24 13:33:19,060 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 13:33:19,060 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 61 [2018-01-24 13:33:19,060 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:19,061 INFO L225 Difference]: With dead ends: 135 [2018-01-24 13:33:19,061 INFO L226 Difference]: Without dead ends: 133 [2018-01-24 13:33:19,061 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=39, Invalid=233, Unknown=0, NotChecked=0, Total=272 [2018-01-24 13:33:19,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-01-24 13:33:19,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 133. [2018-01-24 13:33:19,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 133 states. [2018-01-24 13:33:19,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 138 transitions. [2018-01-24 13:33:19,073 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 138 transitions. Word has length 61 [2018-01-24 13:33:19,073 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:19,073 INFO L432 AbstractCegarLoop]: Abstraction has 133 states and 138 transitions. [2018-01-24 13:33:19,073 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 13:33:19,074 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 138 transitions. [2018-01-24 13:33:19,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-01-24 13:33:19,074 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:19,074 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:19,074 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:19,074 INFO L82 PathProgramCache]: Analyzing trace with hash 273504901, now seen corresponding path program 1 times [2018-01-24 13:33:19,074 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:19,075 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:19,075 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:19,075 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:19,075 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:19,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:19,088 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:19,186 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:19,186 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:19,186 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:19,198 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:19,198 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:33:19,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:19,232 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:19,244 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:19,244 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:19,388 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:19,414 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:19,414 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:33:19,419 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:19,419 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:33:19,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:19,494 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:19,503 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:19,503 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:19,607 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:19,610 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:33:19,610 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 13:33:19,610 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:33:19,611 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 13:33:19,611 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 13:33:19,611 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=88, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:33:19,611 INFO L87 Difference]: Start difference. First operand 133 states and 138 transitions. Second operand 8 states. [2018-01-24 13:33:19,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:19,646 INFO L93 Difference]: Finished difference Result 242 states and 252 transitions. [2018-01-24 13:33:19,647 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 13:33:19,647 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 61 [2018-01-24 13:33:19,647 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:19,648 INFO L225 Difference]: With dead ends: 242 [2018-01-24 13:33:19,648 INFO L226 Difference]: Without dead ends: 134 [2018-01-24 13:33:19,649 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 250 GetRequests, 236 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=77, Invalid=105, Unknown=0, NotChecked=0, Total=182 [2018-01-24 13:33:19,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-01-24 13:33:19,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2018-01-24 13:33:19,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-01-24 13:33:19,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 139 transitions. [2018-01-24 13:33:19,667 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 139 transitions. Word has length 61 [2018-01-24 13:33:19,667 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:19,667 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 139 transitions. [2018-01-24 13:33:19,667 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 13:33:19,668 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 139 transitions. [2018-01-24 13:33:19,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 13:33:19,668 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:19,668 INFO L322 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:19,669 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:19,669 INFO L82 PathProgramCache]: Analyzing trace with hash -1969498855, now seen corresponding path program 2 times [2018-01-24 13:33:19,669 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:19,670 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:19,670 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:19,670 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:19,670 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:19,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:19,688 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:19,738 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:19,738 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:19,739 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:19,746 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:33:19,747 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:33:19,774 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:19,778 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:33:19,782 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:19,787 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:33:19,788 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:19,810 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:33:19,810 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:19,826 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:33:19,827 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:33:20,401 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:33:20,401 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:20,937 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:33:20,958 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:33:20,958 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [18, 16] imperfect sequences [8] total 40 [2018-01-24 13:33:20,958 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:20,958 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 13:33:20,958 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 13:33:20,959 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=132, Invalid=1428, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 13:33:20,959 INFO L87 Difference]: Start difference. First operand 134 states and 139 transitions. Second operand 19 states. [2018-01-24 13:33:21,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:21,855 INFO L93 Difference]: Finished difference Result 134 states and 139 transitions. [2018-01-24 13:33:21,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 13:33:21,855 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 62 [2018-01-24 13:33:21,856 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:21,857 INFO L225 Difference]: With dead ends: 134 [2018-01-24 13:33:21,857 INFO L226 Difference]: Without dead ends: 132 [2018-01-24 13:33:21,858 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 91 SyntacticMatches, 2 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 507 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=173, Invalid=1807, Unknown=0, NotChecked=0, Total=1980 [2018-01-24 13:33:21,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-01-24 13:33:21,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 132. [2018-01-24 13:33:21,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-01-24 13:33:21,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 137 transitions. [2018-01-24 13:33:21,878 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 137 transitions. Word has length 62 [2018-01-24 13:33:21,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:21,879 INFO L432 AbstractCegarLoop]: Abstraction has 132 states and 137 transitions. [2018-01-24 13:33:21,879 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 13:33:21,879 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 137 transitions. [2018-01-24 13:33:21,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-01-24 13:33:21,880 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:21,880 INFO L322 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:21,880 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:21,881 INFO L82 PathProgramCache]: Analyzing trace with hash -525790244, now seen corresponding path program 1 times [2018-01-24 13:33:21,881 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:21,882 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:21,882 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:33:21,882 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:21,882 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:21,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:21,900 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:21,992 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:33:21,992 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:21,992 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-01-24 13:33:21,992 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:21,993 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 13:33:21,993 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 13:33:21,993 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-01-24 13:33:21,993 INFO L87 Difference]: Start difference. First operand 132 states and 137 transitions. Second operand 11 states. [2018-01-24 13:33:22,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:22,099 INFO L93 Difference]: Finished difference Result 194 states and 202 transitions. [2018-01-24 13:33:22,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 13:33:22,100 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 71 [2018-01-24 13:33:22,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:22,101 INFO L225 Difference]: With dead ends: 194 [2018-01-24 13:33:22,101 INFO L226 Difference]: Without dead ends: 132 [2018-01-24 13:33:22,102 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-01-24 13:33:22,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-01-24 13:33:22,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 132. [2018-01-24 13:33:22,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-01-24 13:33:22,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 136 transitions. [2018-01-24 13:33:22,122 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 136 transitions. Word has length 71 [2018-01-24 13:33:22,122 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:22,122 INFO L432 AbstractCegarLoop]: Abstraction has 132 states and 136 transitions. [2018-01-24 13:33:22,122 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 13:33:22,123 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 136 transitions. [2018-01-24 13:33:22,123 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-01-24 13:33:22,124 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:22,124 INFO L322 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:22,124 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:22,124 INFO L82 PathProgramCache]: Analyzing trace with hash -1264904852, now seen corresponding path program 1 times [2018-01-24 13:33:22,124 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:22,125 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:22,125 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:22,125 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:22,125 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:22,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:22,146 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:22,359 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:33:22,360 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:22,360 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2018-01-24 13:33:22,360 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:22,360 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 13:33:22,361 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 13:33:22,361 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=271, Unknown=0, NotChecked=0, Total=306 [2018-01-24 13:33:22,361 INFO L87 Difference]: Start difference. First operand 132 states and 136 transitions. Second operand 18 states. [2018-01-24 13:33:22,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:22,724 INFO L93 Difference]: Finished difference Result 162 states and 174 transitions. [2018-01-24 13:33:22,725 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 13:33:22,725 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 84 [2018-01-24 13:33:22,725 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:22,726 INFO L225 Difference]: With dead ends: 162 [2018-01-24 13:33:22,726 INFO L226 Difference]: Without dead ends: 160 [2018-01-24 13:33:22,726 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=59, Invalid=493, Unknown=0, NotChecked=0, Total=552 [2018-01-24 13:33:22,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-01-24 13:33:22,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 155. [2018-01-24 13:33:22,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 155 states. [2018-01-24 13:33:22,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 167 transitions. [2018-01-24 13:33:22,750 INFO L78 Accepts]: Start accepts. Automaton has 155 states and 167 transitions. Word has length 84 [2018-01-24 13:33:22,751 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:22,751 INFO L432 AbstractCegarLoop]: Abstraction has 155 states and 167 transitions. [2018-01-24 13:33:22,751 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 13:33:22,751 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 167 transitions. [2018-01-24 13:33:22,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-01-24 13:33:22,752 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:22,752 INFO L322 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:22,752 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:22,753 INFO L82 PathProgramCache]: Analyzing trace with hash -1264904851, now seen corresponding path program 1 times [2018-01-24 13:33:22,753 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:22,754 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:22,754 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:22,754 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:22,754 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:22,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:22,776 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:22,860 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:22,860 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:22,860 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:22,869 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:22,869 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:33:22,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:22,910 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:22,923 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:22,923 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:23,035 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:23,055 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:23,055 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:33:23,058 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:23,058 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:33:23,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:23,144 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:23,152 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:23,152 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:23,354 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:23,356 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:33:23,356 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 13:33:23,356 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:33:23,357 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 13:33:23,357 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 13:33:23,357 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=117, Unknown=0, NotChecked=0, Total=210 [2018-01-24 13:33:23,357 INFO L87 Difference]: Start difference. First operand 155 states and 167 transitions. Second operand 9 states. [2018-01-24 13:33:23,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:23,391 INFO L93 Difference]: Finished difference Result 285 states and 309 transitions. [2018-01-24 13:33:23,392 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 13:33:23,392 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 84 [2018-01-24 13:33:23,393 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:23,393 INFO L225 Difference]: With dead ends: 285 [2018-01-24 13:33:23,393 INFO L226 Difference]: Without dead ends: 156 [2018-01-24 13:33:23,394 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 327 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=103, Invalid=137, Unknown=0, NotChecked=0, Total=240 [2018-01-24 13:33:23,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-01-24 13:33:23,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 156. [2018-01-24 13:33:23,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-01-24 13:33:23,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 168 transitions. [2018-01-24 13:33:23,436 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 168 transitions. Word has length 84 [2018-01-24 13:33:23,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:23,436 INFO L432 AbstractCegarLoop]: Abstraction has 156 states and 168 transitions. [2018-01-24 13:33:23,436 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 13:33:23,436 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 168 transitions. [2018-01-24 13:33:23,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-01-24 13:33:23,437 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:23,438 INFO L322 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:23,438 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:23,438 INFO L82 PathProgramCache]: Analyzing trace with hash -242617255, now seen corresponding path program 2 times [2018-01-24 13:33:23,438 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:23,439 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:23,439 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:23,439 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:23,440 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:23,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:23,462 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:23,556 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:23,556 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:23,557 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:23,565 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:33:23,565 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:33:23,615 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:23,624 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:33:23,630 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:23,635 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:33:23,635 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:23,654 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:33:23,655 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:23,672 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:33:23,672 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:33:24,526 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 13:33:24,527 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:25,189 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 13:33:25,209 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:33:25,209 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [20, 18] imperfect sequences [9] total 45 [2018-01-24 13:33:25,209 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:25,210 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 13:33:25,210 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 13:33:25,210 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=1827, Unknown=0, NotChecked=0, Total=1980 [2018-01-24 13:33:25,211 INFO L87 Difference]: Start difference. First operand 156 states and 168 transitions. Second operand 21 states. [2018-01-24 13:33:26,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:26,347 INFO L93 Difference]: Finished difference Result 156 states and 168 transitions. [2018-01-24 13:33:26,347 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 13:33:26,347 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 85 [2018-01-24 13:33:26,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:26,348 INFO L225 Difference]: With dead ends: 156 [2018-01-24 13:33:26,348 INFO L226 Difference]: Without dead ends: 154 [2018-01-24 13:33:26,349 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 131 SyntacticMatches, 4 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 686 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=202, Invalid=2348, Unknown=0, NotChecked=0, Total=2550 [2018-01-24 13:33:26,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-01-24 13:33:26,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 154. [2018-01-24 13:33:26,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-01-24 13:33:26,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 164 transitions. [2018-01-24 13:33:26,373 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 164 transitions. Word has length 85 [2018-01-24 13:33:26,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:26,373 INFO L432 AbstractCegarLoop]: Abstraction has 154 states and 164 transitions. [2018-01-24 13:33:26,373 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 13:33:26,373 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 164 transitions. [2018-01-24 13:33:26,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-01-24 13:33:26,374 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:26,375 INFO L322 BasicCegarLoop]: trace histogram [5, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:26,375 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:26,375 INFO L82 PathProgramCache]: Analyzing trace with hash 1137159674, now seen corresponding path program 1 times [2018-01-24 13:33:26,375 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:26,376 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:26,376 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:33:26,377 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:26,377 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:26,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:26,401 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:26,643 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-01-24 13:33:26,644 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:26,644 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:26,651 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:26,651 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:33:26,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:26,694 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:26,780 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 13:33:26,780 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:27,047 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 13:33:27,069 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:27,069 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:33:27,072 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:27,072 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:33:27,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:27,207 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:27,299 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 13:33:27,299 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:27,496 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-01-24 13:33:27,498 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 4 imperfect interpolant sequences. [2018-01-24 13:33:27,498 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [11, 9, 9, 11] total 26 [2018-01-24 13:33:27,498 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:27,499 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 13:33:27,499 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 13:33:27,499 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=520, Unknown=0, NotChecked=0, Total=650 [2018-01-24 13:33:27,499 INFO L87 Difference]: Start difference. First operand 154 states and 164 transitions. Second operand 11 states. [2018-01-24 13:33:27,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:27,583 INFO L93 Difference]: Finished difference Result 215 states and 225 transitions. [2018-01-24 13:33:27,584 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 13:33:27,584 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 88 [2018-01-24 13:33:27,584 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:27,585 INFO L225 Difference]: With dead ends: 215 [2018-01-24 13:33:27,585 INFO L226 Difference]: Without dead ends: 151 [2018-01-24 13:33:27,585 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 364 GetRequests, 331 SyntacticMatches, 6 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=143, Invalid=669, Unknown=0, NotChecked=0, Total=812 [2018-01-24 13:33:27,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-01-24 13:33:27,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 151. [2018-01-24 13:33:27,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-01-24 13:33:27,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 157 transitions. [2018-01-24 13:33:27,603 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 157 transitions. Word has length 88 [2018-01-24 13:33:27,603 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:27,603 INFO L432 AbstractCegarLoop]: Abstraction has 151 states and 157 transitions. [2018-01-24 13:33:27,603 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 13:33:27,603 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 157 transitions. [2018-01-24 13:33:27,604 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-01-24 13:33:27,604 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:27,604 INFO L322 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:27,604 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:27,605 INFO L82 PathProgramCache]: Analyzing trace with hash -1746979988, now seen corresponding path program 1 times [2018-01-24 13:33:27,605 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:27,605 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:27,606 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:27,606 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:27,606 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:27,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:27,625 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:28,326 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 13:33:28,326 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:33:28,326 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2018-01-24 13:33:28,326 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:28,327 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 13:33:28,327 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 13:33:28,327 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=381, Unknown=0, NotChecked=0, Total=420 [2018-01-24 13:33:28,327 INFO L87 Difference]: Start difference. First operand 151 states and 157 transitions. Second operand 21 states. [2018-01-24 13:33:28,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:28,821 INFO L93 Difference]: Finished difference Result 163 states and 173 transitions. [2018-01-24 13:33:28,822 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 13:33:28,822 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 99 [2018-01-24 13:33:28,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:28,823 INFO L225 Difference]: With dead ends: 163 [2018-01-24 13:33:28,823 INFO L226 Difference]: Without dead ends: 161 [2018-01-24 13:33:28,824 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=75, Invalid=795, Unknown=0, NotChecked=0, Total=870 [2018-01-24 13:33:28,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-01-24 13:33:28,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 157. [2018-01-24 13:33:28,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-01-24 13:33:28,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 167 transitions. [2018-01-24 13:33:28,846 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 167 transitions. Word has length 99 [2018-01-24 13:33:28,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:28,846 INFO L432 AbstractCegarLoop]: Abstraction has 157 states and 167 transitions. [2018-01-24 13:33:28,847 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 13:33:28,847 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 167 transitions. [2018-01-24 13:33:28,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-01-24 13:33:28,847 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:28,848 INFO L322 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:28,848 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:28,848 INFO L82 PathProgramCache]: Analyzing trace with hash -1746979987, now seen corresponding path program 1 times [2018-01-24 13:33:28,848 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:28,849 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:28,849 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:28,849 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:28,849 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:28,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:28,872 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:29,057 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:29,058 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:29,064 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:29,083 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:29,083 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:33:29,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:29,161 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:29,177 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:29,177 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:29,342 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:29,362 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:29,362 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:33:29,365 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:29,366 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:33:29,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:29,472 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:29,479 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:29,479 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:29,649 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:29,651 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:33:29,652 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 13:33:29,652 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:33:29,652 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:33:29,653 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:33:29,653 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=150, Unknown=0, NotChecked=0, Total=272 [2018-01-24 13:33:29,653 INFO L87 Difference]: Start difference. First operand 157 states and 167 transitions. Second operand 10 states. [2018-01-24 13:33:29,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:29,714 INFO L93 Difference]: Finished difference Result 288 states and 308 transitions. [2018-01-24 13:33:29,714 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 13:33:29,714 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 99 [2018-01-24 13:33:29,715 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:29,716 INFO L225 Difference]: With dead ends: 288 [2018-01-24 13:33:29,716 INFO L226 Difference]: Without dead ends: 158 [2018-01-24 13:33:29,717 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 404 GetRequests, 386 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=133, Invalid=173, Unknown=0, NotChecked=0, Total=306 [2018-01-24 13:33:29,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2018-01-24 13:33:29,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 158. [2018-01-24 13:33:29,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-01-24 13:33:29,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 168 transitions. [2018-01-24 13:33:29,747 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 168 transitions. Word has length 99 [2018-01-24 13:33:29,747 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:29,747 INFO L432 AbstractCegarLoop]: Abstraction has 158 states and 168 transitions. [2018-01-24 13:33:29,747 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:33:29,747 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 168 transitions. [2018-01-24 13:33:29,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-01-24 13:33:29,748 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:29,748 INFO L322 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:29,748 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:29,748 INFO L82 PathProgramCache]: Analyzing trace with hash -1844371711, now seen corresponding path program 2 times [2018-01-24 13:33:29,748 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:29,749 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:29,749 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:29,750 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:29,750 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:29,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:29,772 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:29,949 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:29,949 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:29,950 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:29,957 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:33:29,957 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:33:30,007 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:30,013 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:33:30,019 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:30,026 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:33:30,027 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:30,058 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:33:30,059 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:30,071 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:33:30,071 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:33:31,726 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 13:33:31,726 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:32,700 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 13:33:32,722 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:33:32,722 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [24, 22] imperfect sequences [10] total 54 [2018-01-24 13:33:32,722 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:33:32,722 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-24 13:33:32,722 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-24 13:33:32,723 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=189, Invalid=2673, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 13:33:32,723 INFO L87 Difference]: Start difference. First operand 158 states and 168 transitions. Second operand 25 states. [2018-01-24 13:33:34,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:34,176 INFO L93 Difference]: Finished difference Result 158 states and 168 transitions. [2018-01-24 13:33:34,176 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 13:33:34,176 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 100 [2018-01-24 13:33:34,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:34,177 INFO L225 Difference]: With dead ends: 158 [2018-01-24 13:33:34,177 INFO L226 Difference]: Without dead ends: 156 [2018-01-24 13:33:34,178 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 151 SyntacticMatches, 6 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1053 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=254, Invalid=3528, Unknown=0, NotChecked=0, Total=3782 [2018-01-24 13:33:34,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-01-24 13:33:34,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 156. [2018-01-24 13:33:34,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-01-24 13:33:34,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 165 transitions. [2018-01-24 13:33:34,204 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 165 transitions. Word has length 100 [2018-01-24 13:33:34,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:34,204 INFO L432 AbstractCegarLoop]: Abstraction has 156 states and 165 transitions. [2018-01-24 13:33:34,204 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-24 13:33:34,204 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 165 transitions. [2018-01-24 13:33:34,205 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-01-24 13:33:34,205 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:34,205 INFO L322 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:34,205 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:34,205 INFO L82 PathProgramCache]: Analyzing trace with hash -695287998, now seen corresponding path program 1 times [2018-01-24 13:33:34,205 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:34,206 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:34,206 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:33:34,206 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:34,206 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:34,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:34,228 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:34,322 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:34,322 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:34,322 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:34,333 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:34,333 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:33:34,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:34,392 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:34,402 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:34,402 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:34,559 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:34,579 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:34,579 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:33:34,582 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:34,582 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:33:34,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:34,691 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:34,698 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:34,699 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:34,784 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:34,786 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:33:34,786 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 13:33:34,786 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:33:34,787 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 13:33:34,787 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 13:33:34,787 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=187, Unknown=0, NotChecked=0, Total=342 [2018-01-24 13:33:34,787 INFO L87 Difference]: Start difference. First operand 156 states and 165 transitions. Second operand 11 states. [2018-01-24 13:33:34,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:34,828 INFO L93 Difference]: Finished difference Result 285 states and 303 transitions. [2018-01-24 13:33:34,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:33:34,829 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 104 [2018-01-24 13:33:34,829 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:34,830 INFO L225 Difference]: With dead ends: 285 [2018-01-24 13:33:34,830 INFO L226 Difference]: Without dead ends: 157 [2018-01-24 13:33:34,830 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 425 GetRequests, 405 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=167, Invalid=213, Unknown=0, NotChecked=0, Total=380 [2018-01-24 13:33:34,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-01-24 13:33:34,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 157. [2018-01-24 13:33:34,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-01-24 13:33:34,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 166 transitions. [2018-01-24 13:33:34,858 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 166 transitions. Word has length 104 [2018-01-24 13:33:34,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:34,858 INFO L432 AbstractCegarLoop]: Abstraction has 157 states and 166 transitions. [2018-01-24 13:33:34,858 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 13:33:34,859 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 166 transitions. [2018-01-24 13:33:34,859 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-01-24 13:33:34,860 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:34,860 INFO L322 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:34,860 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:34,860 INFO L82 PathProgramCache]: Analyzing trace with hash -1838878674, now seen corresponding path program 2 times [2018-01-24 13:33:34,860 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:34,861 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:34,861 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:33:34,861 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:34,861 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:34,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:34,884 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:35,036 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:35,036 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:35,036 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:35,041 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:33:35,041 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:33:35,084 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:35,092 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:33:35,099 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:35,173 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 13:33:35,174 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 13:33:35,174 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:35,176 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:33:35,177 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:33:35,177 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:11, output treesize:7 [2018-01-24 13:33:35,554 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 13:33:35,556 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 13:33:35,560 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 13:33:35,561 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:38, output treesize:26 [2018-01-24 13:33:35,616 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 27 [2018-01-24 13:33:35,618 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:33:35,621 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 35 [2018-01-24 13:33:35,625 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:33:35,626 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:33:35,630 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 37 [2018-01-24 13:33:35,630 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:35,636 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:33:35,639 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:33:35,644 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:33:35,644 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:37, output treesize:9 [2018-01-24 13:33:35,990 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:33:35,990 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 36 [2018-01-24 13:33:35,992 INFO L682 Elim1Store]: detected equality via solver [2018-01-24 13:33:35,997 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:33:35,998 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 15 [2018-01-24 13:33:35,999 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:36,001 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:33:36,003 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:33:36,003 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:32, output treesize:13 [2018-01-24 13:33:36,720 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 13 [2018-01-24 13:33:36,721 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 5 [2018-01-24 13:33:36,722 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:36,722 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:33:36,723 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:33:36,723 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:17, output treesize:5 [2018-01-24 13:33:36,764 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-01-24 13:33:36,764 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:38,129 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2018-01-24 13:33:38,132 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 3 [2018-01-24 13:33:38,132 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:33:38,133 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:33:38,139 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 13:33:38,139 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:43, output treesize:34 [2018-01-24 13:33:39,000 INFO L682 Elim1Store]: detected equality via solver [2018-01-24 13:33:39,001 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 85 treesize of output 79 [2018-01-24 13:33:39,002 FATAL L292 ToolchainWalker]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction has thrown an exception: java.lang.UnsupportedOperationException: alternation not yet supported at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.applyNonSddEliminations(ElimStorePlain.java:347) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimOneRec(ElimStorePlain.java:223) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimAllRec(ElimStorePlain.java:247) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.elimAllRec(ElimStorePlain.java:199) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.PartialQuantifierElimination.elim(PartialQuantifierElimination.java:270) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.PartialQuantifierElimination.tryToEliminate(PartialQuantifierElimination.java:101) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer$QuantifierEliminationPostprocessor.postprocess(IterativePredicateTransformer.java:243) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.applyPostprocessors(IterativePredicateTransformer.java:445) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.computeBackwardSequence(IterativePredicateTransformer.java:421) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.computeWeakestPreconditionSequence(IterativePredicateTransformer.java:292) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolantsUsingUnsatCore(TraceCheckSpWp.java:328) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolants(TraceCheckSpWp.java:173) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.(TraceCheckSpWp.java:160) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructForwardBackward(TraceCheckConstructor.java:237) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.get(TraceCheckConstructor.java:185) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseTaipanRefinementStrategy.getTraceCheck(BaseTaipanRefinementStrategy.java:213) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.checkFeasibility(BaseRefinementStrategy.java:231) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.executeStrategy(BaseRefinementStrategy.java:205) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:68) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:368) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:381) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:316) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:294) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:149) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:113) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:117) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:324) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.runToolchainDefault(DefaultToolchainJob.java:221) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.BasicToolchainJob.run(BasicToolchainJob.java:134) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) [2018-01-24 13:33:39,008 INFO L168 Benchmark]: Toolchain (without parser) took 33488.66 ms. Allocated memory was 305.7 MB in the beginning and 776.5 MB in the end (delta: 470.8 MB). Free memory was 264.7 MB in the beginning and 516.5 MB in the end (delta: -251.8 MB). Peak memory consumption was 219.0 MB. Max. memory is 5.3 GB. [2018-01-24 13:33:39,009 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 305.7 MB. Free memory is still 270.7 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 13:33:39,009 INFO L168 Benchmark]: CACSL2BoogieTranslator took 230.73 ms. Allocated memory is still 305.7 MB. Free memory was 264.7 MB in the beginning and 250.6 MB in the end (delta: 14.1 MB). Peak memory consumption was 14.1 MB. Max. memory is 5.3 GB. [2018-01-24 13:33:39,010 INFO L168 Benchmark]: Boogie Preprocessor took 44.26 ms. Allocated memory is still 305.7 MB. Free memory was 250.6 MB in the beginning and 248.5 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 5.3 GB. [2018-01-24 13:33:39,010 INFO L168 Benchmark]: RCFGBuilder took 566.91 ms. Allocated memory is still 305.7 MB. Free memory was 248.5 MB in the beginning and 214.0 MB in the end (delta: 34.5 MB). Peak memory consumption was 34.5 MB. Max. memory is 5.3 GB. [2018-01-24 13:33:39,010 INFO L168 Benchmark]: TraceAbstraction took 32637.76 ms. Allocated memory was 305.7 MB in the beginning and 776.5 MB in the end (delta: 470.8 MB). Free memory was 214.0 MB in the beginning and 516.5 MB in the end (delta: -302.5 MB). Peak memory consumption was 168.4 MB. Max. memory is 5.3 GB. [2018-01-24 13:33:39,015 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 305.7 MB. Free memory is still 270.7 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 230.73 ms. Allocated memory is still 305.7 MB. Free memory was 264.7 MB in the beginning and 250.6 MB in the end (delta: 14.1 MB). Peak memory consumption was 14.1 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 44.26 ms. Allocated memory is still 305.7 MB. Free memory was 250.6 MB in the beginning and 248.5 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 5.3 GB. * RCFGBuilder took 566.91 ms. Allocated memory is still 305.7 MB. Free memory was 248.5 MB in the beginning and 214.0 MB in the end (delta: 34.5 MB). Peak memory consumption was 34.5 MB. Max. memory is 5.3 GB. * TraceAbstraction took 32637.76 ms. Allocated memory was 305.7 MB in the beginning and 776.5 MB in the end (delta: 470.8 MB). Free memory was 214.0 MB in the beginning and 516.5 MB in the end (delta: -302.5 MB). Peak memory consumption was 168.4 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: UnsupportedOperationException: alternation not yet supported de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: UnsupportedOperationException: alternation not yet supported: de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.applyNonSddEliminations(ElimStorePlain.java:347) RESULT: Ultimate could not prove your program: Toolchain returned no result. Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test22_2_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_13-33-39-024.csv Received shutdown request...