java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/array-examples/sanfoundry_24_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 12:57:52,291 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 12:57:52,293 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 12:57:52,305 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 12:57:52,305 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 12:57:52,305 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 12:57:52,306 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 12:57:52,307 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 12:57:52,309 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 12:57:52,309 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 12:57:52,310 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 12:57:52,310 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 12:57:52,311 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 12:57:52,312 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 12:57:52,313 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 12:57:52,316 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 12:57:52,318 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 12:57:52,320 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 12:57:52,321 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 12:57:52,322 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 12:57:52,324 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 12:57:52,325 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 12:57:52,325 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 12:57:52,326 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 12:57:52,327 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 12:57:52,328 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 12:57:52,328 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 12:57:52,329 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 12:57:52,329 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 12:57:52,329 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 12:57:52,330 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 12:57:52,330 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf [2018-01-24 12:57:52,339 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 12:57:52,339 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 12:57:52,340 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 12:57:52,340 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 12:57:52,340 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 12:57:52,341 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 12:57:52,341 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 12:57:52,341 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 12:57:52,342 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 12:57:52,342 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 12:57:52,342 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 12:57:52,342 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 12:57:52,342 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 12:57:52,343 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 12:57:52,343 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 12:57:52,343 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 12:57:52,343 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 12:57:52,343 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 12:57:52,344 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 12:57:52,344 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 12:57:52,344 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 12:57:52,344 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 12:57:52,344 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 12:57:52,345 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 12:57:52,345 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 12:57:52,345 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 12:57:52,345 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 12:57:52,345 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 12:57:52,346 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-01-24 12:57:52,346 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 12:57:52,346 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 12:57:52,346 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 12:57:52,347 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 12:57:52,347 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 12:57:52,382 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 12:57:52,394 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 12:57:52,398 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 12:57:52,400 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 12:57:52,400 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 12:57:52,401 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/sanfoundry_24_false-valid-deref.i [2018-01-24 12:57:52,543 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 12:57:52,549 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 12:57:52,549 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 12:57:52,550 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 12:57:52,555 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 12:57:52,556 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 12:57:52" (1/1) ... [2018-01-24 12:57:52,558 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2fe1083d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:57:52, skipping insertion in model container [2018-01-24 12:57:52,559 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 12:57:52" (1/1) ... [2018-01-24 12:57:52,577 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 12:57:52,597 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 12:57:52,709 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 12:57:52,720 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 12:57:52,725 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:57:52 WrapperNode [2018-01-24 12:57:52,726 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 12:57:52,726 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 12:57:52,727 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 12:57:52,727 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 12:57:52,742 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:57:52" (1/1) ... [2018-01-24 12:57:52,743 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:57:52" (1/1) ... [2018-01-24 12:57:52,751 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:57:52" (1/1) ... [2018-01-24 12:57:52,752 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:57:52" (1/1) ... [2018-01-24 12:57:52,753 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:57:52" (1/1) ... [2018-01-24 12:57:52,756 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:57:52" (1/1) ... [2018-01-24 12:57:52,757 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:57:52" (1/1) ... [2018-01-24 12:57:52,758 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 12:57:52,758 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 12:57:52,758 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 12:57:52,759 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 12:57:52,759 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:57:52" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 12:57:52,803 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 12:57:52,803 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 12:57:52,803 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 12:57:52,803 INFO L136 BoogieDeclarations]: Found implementation of procedure printEven [2018-01-24 12:57:52,803 INFO L136 BoogieDeclarations]: Found implementation of procedure printOdd [2018-01-24 12:57:52,803 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 12:57:52,803 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 12:57:52,803 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 12:57:52,804 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-24 12:57:52,804 INFO L128 BoogieDeclarations]: Found specification of procedure printEven [2018-01-24 12:57:52,804 INFO L128 BoogieDeclarations]: Found specification of procedure printOdd [2018-01-24 12:57:52,804 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 12:57:52,804 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 12:57:52,804 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 12:57:52,942 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 12:57:52,943 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 12:57:52 BoogieIcfgContainer [2018-01-24 12:57:52,943 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 12:57:52,944 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 12:57:52,944 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 12:57:52,946 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 12:57:52,946 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 12:57:52" (1/3) ... [2018-01-24 12:57:52,948 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2629eb00 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 12:57:52, skipping insertion in model container [2018-01-24 12:57:52,948 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:57:52" (2/3) ... [2018-01-24 12:57:52,948 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2629eb00 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 12:57:52, skipping insertion in model container [2018-01-24 12:57:52,948 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 12:57:52" (3/3) ... [2018-01-24 12:57:52,950 INFO L105 eAbstractionObserver]: Analyzing ICFG sanfoundry_24_false-valid-deref.i [2018-01-24 12:57:52,960 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 12:57:52,967 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 4 error locations. [2018-01-24 12:57:53,004 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 12:57:53,004 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 12:57:53,004 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 12:57:53,004 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 12:57:53,004 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 12:57:53,005 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 12:57:53,005 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 12:57:53,005 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 12:57:53,005 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 12:57:53,024 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states. [2018-01-24 12:57:53,031 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 12:57:53,031 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:57:53,032 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:57:53,032 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:57:53,038 INFO L82 PathProgramCache]: Analyzing trace with hash 529177341, now seen corresponding path program 1 times [2018-01-24 12:57:53,042 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:57:53,085 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:53,085 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:57:53,086 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:53,086 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:57:53,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:53,128 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:57:53,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:53,194 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:57:53,194 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 12:57:53,195 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 12:57:53,197 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 12:57:53,211 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 12:57:53,212 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 12:57:53,214 INFO L87 Difference]: Start difference. First operand 42 states. Second operand 3 states. [2018-01-24 12:57:53,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:57:53,326 INFO L93 Difference]: Finished difference Result 97 states and 129 transitions. [2018-01-24 12:57:53,326 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 12:57:53,328 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 8 [2018-01-24 12:57:53,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:57:53,337 INFO L225 Difference]: With dead ends: 97 [2018-01-24 12:57:53,338 INFO L226 Difference]: Without dead ends: 51 [2018-01-24 12:57:53,342 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 12:57:53,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-01-24 12:57:53,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 46. [2018-01-24 12:57:53,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-01-24 12:57:53,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 53 transitions. [2018-01-24 12:57:53,438 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 53 transitions. Word has length 8 [2018-01-24 12:57:53,438 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:57:53,438 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 53 transitions. [2018-01-24 12:57:53,438 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 12:57:53,438 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 53 transitions. [2018-01-24 12:57:53,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-01-24 12:57:53,439 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:57:53,439 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:57:53,439 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:57:53,440 INFO L82 PathProgramCache]: Analyzing trace with hash -2078569521, now seen corresponding path program 1 times [2018-01-24 12:57:53,440 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:57:53,440 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:53,441 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:57:53,441 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:53,441 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:57:53,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:53,452 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:57:53,504 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:53,505 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:53,505 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:57:53,516 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:57:53,516 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:57:53,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:53,545 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:53,564 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:53,564 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:53,644 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:53,674 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:53,674 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:57:53,678 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:57:53,678 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:57:53,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:53,693 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:53,700 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:53,700 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:53,706 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:53,708 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:57:53,708 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3, 3, 3] total 5 [2018-01-24 12:57:53,708 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:57:53,709 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 12:57:53,709 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 12:57:53,709 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 12:57:53,710 INFO L87 Difference]: Start difference. First operand 46 states and 53 transitions. Second operand 4 states. [2018-01-24 12:57:53,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:57:53,816 INFO L93 Difference]: Finished difference Result 70 states and 84 transitions. [2018-01-24 12:57:53,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 12:57:53,817 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2018-01-24 12:57:53,817 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:57:53,818 INFO L225 Difference]: With dead ends: 70 [2018-01-24 12:57:53,819 INFO L226 Difference]: Without dead ends: 66 [2018-01-24 12:57:53,820 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 47 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 12:57:53,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-01-24 12:57:53,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 60. [2018-01-24 12:57:53,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-01-24 12:57:53,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 72 transitions. [2018-01-24 12:57:53,829 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 72 transitions. Word has length 13 [2018-01-24 12:57:53,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:57:53,830 INFO L432 AbstractCegarLoop]: Abstraction has 60 states and 72 transitions. [2018-01-24 12:57:53,830 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 12:57:53,830 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 72 transitions. [2018-01-24 12:57:53,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-01-24 12:57:53,831 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:57:53,831 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 12:57:53,831 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:57:53,831 INFO L82 PathProgramCache]: Analyzing trace with hash 1794788925, now seen corresponding path program 2 times [2018-01-24 12:57:53,831 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:57:53,832 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:53,832 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:57:53,832 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:53,832 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:57:53,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:53,841 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:57:53,908 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:53,909 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:53,909 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:57:53,918 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:57:53,918 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:57:53,925 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:53,928 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:53,929 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:53,930 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:53,942 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:53,942 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:54,024 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:54,055 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:54,055 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:57:54,059 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:57:54,059 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:57:54,063 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:54,066 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:54,070 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:54,072 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:54,079 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:54,079 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:54,091 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:54,092 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:57:54,093 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 7 [2018-01-24 12:57:54,093 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:57:54,093 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 12:57:54,093 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 12:57:54,093 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 12:57:54,094 INFO L87 Difference]: Start difference. First operand 60 states and 72 transitions. Second operand 5 states. [2018-01-24 12:57:54,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:57:54,214 INFO L93 Difference]: Finished difference Result 85 states and 104 transitions. [2018-01-24 12:57:54,215 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 12:57:54,215 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 18 [2018-01-24 12:57:54,215 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:57:54,217 INFO L225 Difference]: With dead ends: 85 [2018-01-24 12:57:54,218 INFO L226 Difference]: Without dead ends: 81 [2018-01-24 12:57:54,218 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 66 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 12:57:54,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-01-24 12:57:54,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 74. [2018-01-24 12:57:54,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-24 12:57:54,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 91 transitions. [2018-01-24 12:57:54,231 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 91 transitions. Word has length 18 [2018-01-24 12:57:54,231 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:57:54,231 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 91 transitions. [2018-01-24 12:57:54,232 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 12:57:54,232 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 91 transitions. [2018-01-24 12:57:54,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-01-24 12:57:54,233 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:57:54,233 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1] [2018-01-24 12:57:54,234 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:57:54,234 INFO L82 PathProgramCache]: Analyzing trace with hash -424025969, now seen corresponding path program 3 times [2018-01-24 12:57:54,234 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:57:54,235 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:54,235 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:57:54,235 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:54,235 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:57:54,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:54,249 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:57:54,341 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:54,341 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:54,378 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:57:54,385 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:57:54,385 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:57:54,390 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:54,392 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:54,394 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:54,396 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:54,396 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:54,398 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:54,410 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:54,410 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:54,473 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:54,504 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:54,504 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:57:54,507 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:57:54,507 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:57:54,511 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:54,514 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:54,518 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:54,524 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:54,529 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:54,532 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:54,539 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:54,539 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:54,545 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:54,546 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:57:54,547 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 12:57:54,547 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:57:54,547 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 12:57:54,547 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 12:57:54,547 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 12:57:54,548 INFO L87 Difference]: Start difference. First operand 74 states and 91 transitions. Second operand 6 states. [2018-01-24 12:57:54,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:57:54,697 INFO L93 Difference]: Finished difference Result 100 states and 124 transitions. [2018-01-24 12:57:54,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 12:57:54,698 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 23 [2018-01-24 12:57:54,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:57:54,699 INFO L225 Difference]: With dead ends: 100 [2018-01-24 12:57:54,700 INFO L226 Difference]: Without dead ends: 96 [2018-01-24 12:57:54,700 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 85 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 12:57:54,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-01-24 12:57:54,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 88. [2018-01-24 12:57:54,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-01-24 12:57:54,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 110 transitions. [2018-01-24 12:57:54,709 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 110 transitions. Word has length 23 [2018-01-24 12:57:54,710 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:57:54,710 INFO L432 AbstractCegarLoop]: Abstraction has 88 states and 110 transitions. [2018-01-24 12:57:54,710 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 12:57:54,710 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 110 transitions. [2018-01-24 12:57:54,711 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-01-24 12:57:54,711 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:57:54,711 INFO L322 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1] [2018-01-24 12:57:54,711 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:57:54,711 INFO L82 PathProgramCache]: Analyzing trace with hash -1714228867, now seen corresponding path program 4 times [2018-01-24 12:57:54,711 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:57:54,712 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:54,712 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:57:54,712 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:54,712 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:57:54,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:54,722 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:57:54,808 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:54,808 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:54,808 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:57:54,819 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:57:54,820 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:57:54,829 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:54,832 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:54,840 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:54,840 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:54,919 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:54,939 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:54,939 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:57:54,942 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:57:54,942 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:57:54,959 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:54,962 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:54,970 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:54,970 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:54,980 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:54,981 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:57:54,982 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 12:57:54,982 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:57:54,982 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 12:57:54,983 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 12:57:54,983 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 12:57:54,983 INFO L87 Difference]: Start difference. First operand 88 states and 110 transitions. Second operand 7 states. [2018-01-24 12:57:55,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:57:55,269 INFO L93 Difference]: Finished difference Result 115 states and 144 transitions. [2018-01-24 12:57:55,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 12:57:55,269 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 28 [2018-01-24 12:57:55,270 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:57:55,271 INFO L225 Difference]: With dead ends: 115 [2018-01-24 12:57:55,271 INFO L226 Difference]: Without dead ends: 111 [2018-01-24 12:57:55,271 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 116 GetRequests, 104 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 12:57:55,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-01-24 12:57:55,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 102. [2018-01-24 12:57:55,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-01-24 12:57:55,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 129 transitions. [2018-01-24 12:57:55,284 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 129 transitions. Word has length 28 [2018-01-24 12:57:55,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:57:55,285 INFO L432 AbstractCegarLoop]: Abstraction has 102 states and 129 transitions. [2018-01-24 12:57:55,285 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 12:57:55,285 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 129 transitions. [2018-01-24 12:57:55,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-01-24 12:57:55,287 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:57:55,287 INFO L322 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1] [2018-01-24 12:57:55,287 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:57:55,287 INFO L82 PathProgramCache]: Analyzing trace with hash -771406513, now seen corresponding path program 5 times [2018-01-24 12:57:55,287 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:57:55,288 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:55,288 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:57:55,289 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:55,289 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:57:55,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:55,303 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:57:55,407 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:55,408 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:55,408 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:57:55,416 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:57:55,416 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:57:55,419 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:55,420 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:55,421 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:55,423 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:55,424 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:55,426 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:55,427 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:55,429 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:55,442 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:55,442 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:55,514 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:55,534 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:55,534 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:57:55,537 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:57:55,537 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:57:55,540 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:55,543 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:55,548 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:55,556 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:55,563 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:55,572 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:55,578 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:55,581 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:55,599 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:55,599 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:55,611 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:55,613 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:57:55,613 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 12:57:55,613 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:57:55,614 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 12:57:55,614 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 12:57:55,614 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 12:57:55,615 INFO L87 Difference]: Start difference. First operand 102 states and 129 transitions. Second operand 8 states. [2018-01-24 12:57:55,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:57:55,858 INFO L93 Difference]: Finished difference Result 130 states and 164 transitions. [2018-01-24 12:57:55,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 12:57:55,859 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 33 [2018-01-24 12:57:55,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:57:55,860 INFO L225 Difference]: With dead ends: 130 [2018-01-24 12:57:55,860 INFO L226 Difference]: Without dead ends: 126 [2018-01-24 12:57:55,861 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 123 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 12:57:55,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-01-24 12:57:55,868 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 116. [2018-01-24 12:57:55,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 116 states. [2018-01-24 12:57:55,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 148 transitions. [2018-01-24 12:57:55,870 INFO L78 Accepts]: Start accepts. Automaton has 116 states and 148 transitions. Word has length 33 [2018-01-24 12:57:55,870 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:57:55,870 INFO L432 AbstractCegarLoop]: Abstraction has 116 states and 148 transitions. [2018-01-24 12:57:55,870 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 12:57:55,870 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 148 transitions. [2018-01-24 12:57:55,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-01-24 12:57:55,871 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:57:55,872 INFO L322 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 6, 1, 1, 1, 1, 1, 1] [2018-01-24 12:57:55,872 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:57:55,872 INFO L82 PathProgramCache]: Analyzing trace with hash -240614211, now seen corresponding path program 6 times [2018-01-24 12:57:55,872 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:57:55,873 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:55,873 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:57:55,873 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:55,873 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:57:55,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:55,886 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:57:55,969 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:55,969 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:55,970 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:57:55,976 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:57:55,976 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:57:55,980 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:57:55,981 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:57:55,982 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:57:55,983 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:57:55,984 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:57:55,985 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:57:55,986 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:57:55,987 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:55,989 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:55,998 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:55,999 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:56,091 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:56,110 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:56,111 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:57:56,114 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:57:56,114 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:57:56,117 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:57:56,120 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:57:56,124 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:57:56,129 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:57:56,136 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:57:56,144 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:57:56,152 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:57:56,159 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:56,162 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:56,169 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:56,169 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:56,177 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:56,178 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:57:56,178 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 12:57:56,179 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:57:56,179 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 12:57:56,179 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 12:57:56,179 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 12:57:56,179 INFO L87 Difference]: Start difference. First operand 116 states and 148 transitions. Second operand 9 states. [2018-01-24 12:57:56,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:57:56,447 INFO L93 Difference]: Finished difference Result 145 states and 184 transitions. [2018-01-24 12:57:56,447 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 12:57:56,447 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 38 [2018-01-24 12:57:56,448 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:57:56,448 INFO L225 Difference]: With dead ends: 145 [2018-01-24 12:57:56,449 INFO L226 Difference]: Without dead ends: 141 [2018-01-24 12:57:56,449 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 142 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 12:57:56,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-01-24 12:57:56,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 130. [2018-01-24 12:57:56,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-01-24 12:57:56,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 167 transitions. [2018-01-24 12:57:56,458 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 167 transitions. Word has length 38 [2018-01-24 12:57:56,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:57:56,458 INFO L432 AbstractCegarLoop]: Abstraction has 130 states and 167 transitions. [2018-01-24 12:57:56,458 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 12:57:56,458 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 167 transitions. [2018-01-24 12:57:56,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-01-24 12:57:56,460 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:57:56,460 INFO L322 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 7, 1, 1, 1, 1, 1, 1] [2018-01-24 12:57:56,460 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:57:56,461 INFO L82 PathProgramCache]: Analyzing trace with hash 1558821391, now seen corresponding path program 7 times [2018-01-24 12:57:56,461 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:57:56,462 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:56,462 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:57:56,462 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:56,462 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:57:56,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:56,473 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:57:56,583 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:56,583 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:56,583 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:57:56,593 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:57:56,593 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:57:56,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:56,605 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:56,615 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:56,616 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:56,710 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:56,730 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:56,730 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:57:56,733 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:57:56,734 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:57:56,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:56,753 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:56,763 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:56,763 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:56,773 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:56,774 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:57:56,774 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 12:57:56,774 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:57:56,775 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 12:57:56,775 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 12:57:56,775 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 12:57:56,775 INFO L87 Difference]: Start difference. First operand 130 states and 167 transitions. Second operand 10 states. [2018-01-24 12:57:57,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:57:57,144 INFO L93 Difference]: Finished difference Result 160 states and 204 transitions. [2018-01-24 12:57:57,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 12:57:57,144 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 43 [2018-01-24 12:57:57,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:57:57,146 INFO L225 Difference]: With dead ends: 160 [2018-01-24 12:57:57,146 INFO L226 Difference]: Without dead ends: 156 [2018-01-24 12:57:57,146 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 179 GetRequests, 161 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 12:57:57,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-01-24 12:57:57,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 144. [2018-01-24 12:57:57,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-01-24 12:57:57,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 186 transitions. [2018-01-24 12:57:57,155 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 186 transitions. Word has length 43 [2018-01-24 12:57:57,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:57:57,155 INFO L432 AbstractCegarLoop]: Abstraction has 144 states and 186 transitions. [2018-01-24 12:57:57,155 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 12:57:57,155 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 186 transitions. [2018-01-24 12:57:57,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-01-24 12:57:57,157 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:57:57,157 INFO L322 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 8, 1, 1, 1, 1, 1, 1] [2018-01-24 12:57:57,157 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:57:57,157 INFO L82 PathProgramCache]: Analyzing trace with hash -821098499, now seen corresponding path program 8 times [2018-01-24 12:57:57,157 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:57:57,158 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:57,158 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:57:57,158 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:57,158 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:57:57,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:57,169 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:57:57,315 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:57,315 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:57,315 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:57:57,326 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:57:57,326 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:57:57,329 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:57,333 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:57,335 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:57,337 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:57,345 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:57,346 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:57,485 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:57,513 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:57,513 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:57:57,516 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:57:57,516 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:57:57,521 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:57,527 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:57:57,536 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:57,539 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:57,547 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:57,547 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:57,560 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:57,561 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:57:57,561 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 12:57:57,562 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:57:57,562 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 12:57:57,562 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 12:57:57,562 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 12:57:57,562 INFO L87 Difference]: Start difference. First operand 144 states and 186 transitions. Second operand 11 states. [2018-01-24 12:57:58,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:57:58,212 INFO L93 Difference]: Finished difference Result 175 states and 224 transitions. [2018-01-24 12:57:58,212 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 12:57:58,212 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 48 [2018-01-24 12:57:58,212 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:57:58,213 INFO L225 Difference]: With dead ends: 175 [2018-01-24 12:57:58,213 INFO L226 Difference]: Without dead ends: 171 [2018-01-24 12:57:58,214 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 200 GetRequests, 180 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 12:57:58,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-01-24 12:57:58,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 158. [2018-01-24 12:57:58,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-01-24 12:57:58,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 205 transitions. [2018-01-24 12:57:58,224 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 205 transitions. Word has length 48 [2018-01-24 12:57:58,224 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:57:58,224 INFO L432 AbstractCegarLoop]: Abstraction has 158 states and 205 transitions. [2018-01-24 12:57:58,225 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 12:57:58,225 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 205 transitions. [2018-01-24 12:57:58,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-01-24 12:57:58,226 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:57:58,226 INFO L322 BasicCegarLoop]: trace histogram [10, 10, 9, 9, 9, 1, 1, 1, 1, 1, 1] [2018-01-24 12:57:58,226 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:57:58,226 INFO L82 PathProgramCache]: Analyzing trace with hash -413974833, now seen corresponding path program 9 times [2018-01-24 12:57:58,226 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:57:58,227 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:58,227 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:57:58,227 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:58,227 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:57:58,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:58,240 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:57:58,475 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:58,475 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:58,475 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:57:58,481 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:57:58,481 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:57:58,484 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,485 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,486 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,487 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,488 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,490 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,491 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,492 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,494 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,495 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,496 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:58,497 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:58,508 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:58,508 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:58,674 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:58,694 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:58,694 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:57:58,697 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:57:58,697 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:57:58,701 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,703 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,707 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,713 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,719 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,726 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,735 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,744 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,755 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,767 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:57:58,776 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:58,780 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:58,790 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:58,790 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:58,804 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:58,806 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:57:58,806 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 12:57:58,806 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:57:58,806 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 12:57:58,806 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 12:57:58,807 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 12:57:58,807 INFO L87 Difference]: Start difference. First operand 158 states and 205 transitions. Second operand 12 states. [2018-01-24 12:57:59,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:57:59,308 INFO L93 Difference]: Finished difference Result 190 states and 244 transitions. [2018-01-24 12:57:59,308 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 12:57:59,308 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 53 [2018-01-24 12:57:59,308 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:57:59,309 INFO L225 Difference]: With dead ends: 190 [2018-01-24 12:57:59,309 INFO L226 Difference]: Without dead ends: 186 [2018-01-24 12:57:59,310 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 221 GetRequests, 199 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 12:57:59,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-01-24 12:57:59,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 172. [2018-01-24 12:57:59,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-01-24 12:57:59,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 224 transitions. [2018-01-24 12:57:59,321 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 224 transitions. Word has length 53 [2018-01-24 12:57:59,322 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:57:59,322 INFO L432 AbstractCegarLoop]: Abstraction has 172 states and 224 transitions. [2018-01-24 12:57:59,322 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 12:57:59,322 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 224 transitions. [2018-01-24 12:57:59,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-01-24 12:57:59,323 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:57:59,324 INFO L322 BasicCegarLoop]: trace histogram [11, 11, 10, 10, 10, 1, 1, 1, 1, 1, 1] [2018-01-24 12:57:59,324 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:57:59,324 INFO L82 PathProgramCache]: Analyzing trace with hash -442860739, now seen corresponding path program 10 times [2018-01-24 12:57:59,324 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:57:59,325 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:59,325 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:57:59,325 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:57:59,325 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:57:59,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:57:59,337 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:57:59,465 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:59,465 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:59,499 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:57:59,504 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:57:59,504 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:57:59,518 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:59,520 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:59,530 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:59,530 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:59,679 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:59,699 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:57:59,699 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:57:59,704 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:57:59,705 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:57:59,735 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:57:59,738 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:57:59,748 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:59,748 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:57:59,759 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:57:59,760 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:57:59,760 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 12:57:59,760 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:57:59,761 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 12:57:59,761 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 12:57:59,761 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 12:57:59,761 INFO L87 Difference]: Start difference. First operand 172 states and 224 transitions. Second operand 13 states. [2018-01-24 12:58:00,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:00,280 INFO L93 Difference]: Finished difference Result 205 states and 264 transitions. [2018-01-24 12:58:00,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 12:58:00,280 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 58 [2018-01-24 12:58:00,280 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:00,281 INFO L225 Difference]: With dead ends: 205 [2018-01-24 12:58:00,281 INFO L226 Difference]: Without dead ends: 201 [2018-01-24 12:58:00,282 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 242 GetRequests, 218 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 12:58:00,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2018-01-24 12:58:00,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 186. [2018-01-24 12:58:00,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-01-24 12:58:00,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 243 transitions. [2018-01-24 12:58:00,293 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 243 transitions. Word has length 58 [2018-01-24 12:58:00,293 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:00,293 INFO L432 AbstractCegarLoop]: Abstraction has 186 states and 243 transitions. [2018-01-24 12:58:00,293 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 12:58:00,293 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 243 transitions. [2018-01-24 12:58:00,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-01-24 12:58:00,295 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:00,295 INFO L322 BasicCegarLoop]: trace histogram [12, 12, 11, 11, 11, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:00,295 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:00,295 INFO L82 PathProgramCache]: Analyzing trace with hash -634530929, now seen corresponding path program 11 times [2018-01-24 12:58:00,296 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:00,296 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:00,296 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:00,296 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:00,296 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:00,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:00,308 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:00,443 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:00,443 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:00,443 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:00,448 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:00,448 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:00,451 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,452 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,454 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,455 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,457 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,458 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,460 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,461 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,462 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,464 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,465 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,468 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,468 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:00,469 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:00,480 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:00,480 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:00,657 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:00,677 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:00,677 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:00,680 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:00,680 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:00,683 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,685 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,690 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,696 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,703 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,710 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,719 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,730 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,740 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,752 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,766 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,782 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:00,792 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:00,796 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:00,810 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:00,810 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:00,827 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:00,829 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:00,829 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 12:58:00,829 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:00,830 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 12:58:00,830 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 12:58:00,830 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 12:58:00,831 INFO L87 Difference]: Start difference. First operand 186 states and 243 transitions. Second operand 14 states. [2018-01-24 12:58:01,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:01,465 INFO L93 Difference]: Finished difference Result 220 states and 284 transitions. [2018-01-24 12:58:01,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 12:58:01,465 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 63 [2018-01-24 12:58:01,465 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:01,466 INFO L225 Difference]: With dead ends: 220 [2018-01-24 12:58:01,467 INFO L226 Difference]: Without dead ends: 216 [2018-01-24 12:58:01,467 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 263 GetRequests, 237 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 12:58:01,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-01-24 12:58:01,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 200. [2018-01-24 12:58:01,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 200 states. [2018-01-24 12:58:01,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200 states to 200 states and 262 transitions. [2018-01-24 12:58:01,478 INFO L78 Accepts]: Start accepts. Automaton has 200 states and 262 transitions. Word has length 63 [2018-01-24 12:58:01,478 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:01,478 INFO L432 AbstractCegarLoop]: Abstraction has 200 states and 262 transitions. [2018-01-24 12:58:01,478 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 12:58:01,478 INFO L276 IsEmpty]: Start isEmpty. Operand 200 states and 262 transitions. [2018-01-24 12:58:01,480 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-01-24 12:58:01,480 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:01,480 INFO L322 BasicCegarLoop]: trace histogram [13, 13, 12, 12, 12, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:01,480 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:01,480 INFO L82 PathProgramCache]: Analyzing trace with hash 2145312381, now seen corresponding path program 12 times [2018-01-24 12:58:01,481 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:01,481 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:01,481 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:01,482 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:01,482 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:01,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:01,494 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:01,689 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:01,690 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:01,690 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:01,696 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:01,696 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:01,700 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:01,702 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:01,703 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:01,705 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:01,706 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:01,708 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:01,710 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:01,712 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:01,714 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:01,716 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:01,719 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:01,721 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:01,724 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:01,725 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:01,726 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:01,740 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:01,741 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:02,060 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:02,092 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:02,092 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:02,096 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:02,097 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:02,101 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:02,104 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:02,110 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:02,118 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:02,128 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:02,139 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:02,153 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:02,167 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:02,180 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:02,193 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:02,206 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:02,220 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:02,236 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:02,247 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:02,251 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:02,267 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:02,267 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:02,288 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:02,290 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:02,290 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 27 [2018-01-24 12:58:02,290 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:02,290 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 12:58:02,291 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 12:58:02,291 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 12:58:02,291 INFO L87 Difference]: Start difference. First operand 200 states and 262 transitions. Second operand 15 states. [2018-01-24 12:58:03,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:03,015 INFO L93 Difference]: Finished difference Result 235 states and 304 transitions. [2018-01-24 12:58:03,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 12:58:03,015 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2018-01-24 12:58:03,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:03,017 INFO L225 Difference]: With dead ends: 235 [2018-01-24 12:58:03,017 INFO L226 Difference]: Without dead ends: 231 [2018-01-24 12:58:03,017 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 284 GetRequests, 256 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 12:58:03,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states. [2018-01-24 12:58:03,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 214. [2018-01-24 12:58:03,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-01-24 12:58:03,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 281 transitions. [2018-01-24 12:58:03,026 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 281 transitions. Word has length 68 [2018-01-24 12:58:03,026 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:03,026 INFO L432 AbstractCegarLoop]: Abstraction has 214 states and 281 transitions. [2018-01-24 12:58:03,026 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 12:58:03,026 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 281 transitions. [2018-01-24 12:58:03,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-01-24 12:58:03,027 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:03,027 INFO L322 BasicCegarLoop]: trace histogram [14, 14, 13, 13, 13, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:03,027 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:03,027 INFO L82 PathProgramCache]: Analyzing trace with hash 1734703183, now seen corresponding path program 13 times [2018-01-24 12:58:03,027 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:03,028 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:03,028 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:03,028 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:03,028 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:03,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:03,038 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:03,205 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:03,205 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:03,205 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:03,210 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:03,210 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:03,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:03,221 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:03,232 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:03,232 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:03,463 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:03,483 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:03,483 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:03,486 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:03,486 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:03,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:03,514 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:03,527 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:03,528 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:03,545 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:03,546 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:03,547 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 29 [2018-01-24 12:58:03,547 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:03,547 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 12:58:03,547 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 12:58:03,547 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 12:58:03,548 INFO L87 Difference]: Start difference. First operand 214 states and 281 transitions. Second operand 16 states. [2018-01-24 12:58:04,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:04,390 INFO L93 Difference]: Finished difference Result 250 states and 324 transitions. [2018-01-24 12:58:04,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 12:58:04,390 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 73 [2018-01-24 12:58:04,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:04,391 INFO L225 Difference]: With dead ends: 250 [2018-01-24 12:58:04,391 INFO L226 Difference]: Without dead ends: 246 [2018-01-24 12:58:04,392 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 305 GetRequests, 275 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 12:58:04,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-01-24 12:58:04,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 228. [2018-01-24 12:58:04,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-01-24 12:58:04,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 300 transitions. [2018-01-24 12:58:04,403 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 300 transitions. Word has length 73 [2018-01-24 12:58:04,403 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:04,403 INFO L432 AbstractCegarLoop]: Abstraction has 228 states and 300 transitions. [2018-01-24 12:58:04,403 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 12:58:04,403 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 300 transitions. [2018-01-24 12:58:04,404 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-24 12:58:04,404 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:04,404 INFO L322 BasicCegarLoop]: trace histogram [15, 15, 14, 14, 14, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:04,404 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:04,405 INFO L82 PathProgramCache]: Analyzing trace with hash -1083166275, now seen corresponding path program 14 times [2018-01-24 12:58:04,405 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:04,405 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:04,405 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:04,406 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:04,406 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:04,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:04,417 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:04,853 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:04,853 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:04,853 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:04,858 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:04,858 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:04,861 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:04,866 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:04,868 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:04,870 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:04,883 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:04,883 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:05,138 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:05,158 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:05,158 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:05,161 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:05,162 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:05,166 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:05,176 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:05,190 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:05,194 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:05,211 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:05,212 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:05,227 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:05,229 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:05,229 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 31 [2018-01-24 12:58:05,229 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:05,229 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 12:58:05,229 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 12:58:05,229 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 12:58:05,230 INFO L87 Difference]: Start difference. First operand 228 states and 300 transitions. Second operand 17 states. [2018-01-24 12:58:06,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:06,156 INFO L93 Difference]: Finished difference Result 265 states and 344 transitions. [2018-01-24 12:58:06,157 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 12:58:06,157 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 78 [2018-01-24 12:58:06,157 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:06,158 INFO L225 Difference]: With dead ends: 265 [2018-01-24 12:58:06,158 INFO L226 Difference]: Without dead ends: 261 [2018-01-24 12:58:06,158 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 326 GetRequests, 294 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 12:58:06,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 261 states. [2018-01-24 12:58:06,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 261 to 242. [2018-01-24 12:58:06,170 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 242 states. [2018-01-24 12:58:06,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242 states to 242 states and 319 transitions. [2018-01-24 12:58:06,172 INFO L78 Accepts]: Start accepts. Automaton has 242 states and 319 transitions. Word has length 78 [2018-01-24 12:58:06,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:06,172 INFO L432 AbstractCegarLoop]: Abstraction has 242 states and 319 transitions. [2018-01-24 12:58:06,172 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 12:58:06,172 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 319 transitions. [2018-01-24 12:58:06,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-01-24 12:58:06,174 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:06,174 INFO L322 BasicCegarLoop]: trace histogram [16, 16, 15, 15, 15, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:06,175 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:06,175 INFO L82 PathProgramCache]: Analyzing trace with hash 1239821583, now seen corresponding path program 15 times [2018-01-24 12:58:06,175 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:06,176 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:06,176 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:06,176 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:06,176 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:06,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:06,191 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:06,407 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:06,407 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:06,407 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:06,412 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:06,412 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:06,415 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,416 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,417 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,418 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,420 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,421 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,422 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,423 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,425 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,426 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,428 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,429 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,431 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,433 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,435 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,437 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,437 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:06,439 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:06,452 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:06,453 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:06,794 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:06,814 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:06,814 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:06,816 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:06,817 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:06,821 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,822 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,827 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,832 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,838 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,845 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,854 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,863 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,874 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,885 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,898 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,911 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,927 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,943 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,960 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,977 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:06,998 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:07,002 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:07,020 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:07,020 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:07,045 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:07,046 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:07,047 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 33 [2018-01-24 12:58:07,047 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:07,047 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 12:58:07,047 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 12:58:07,047 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 12:58:07,048 INFO L87 Difference]: Start difference. First operand 242 states and 319 transitions. Second operand 18 states. [2018-01-24 12:58:08,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:08,173 INFO L93 Difference]: Finished difference Result 280 states and 364 transitions. [2018-01-24 12:58:08,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 12:58:08,174 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 83 [2018-01-24 12:58:08,174 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:08,175 INFO L225 Difference]: With dead ends: 280 [2018-01-24 12:58:08,175 INFO L226 Difference]: Without dead ends: 276 [2018-01-24 12:58:08,175 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 347 GetRequests, 313 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 12:58:08,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states. [2018-01-24 12:58:08,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 256. [2018-01-24 12:58:08,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 256 states. [2018-01-24 12:58:08,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 256 states to 256 states and 338 transitions. [2018-01-24 12:58:08,185 INFO L78 Accepts]: Start accepts. Automaton has 256 states and 338 transitions. Word has length 83 [2018-01-24 12:58:08,186 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:08,186 INFO L432 AbstractCegarLoop]: Abstraction has 256 states and 338 transitions. [2018-01-24 12:58:08,186 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 12:58:08,186 INFO L276 IsEmpty]: Start isEmpty. Operand 256 states and 338 transitions. [2018-01-24 12:58:08,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-01-24 12:58:08,188 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:08,188 INFO L322 BasicCegarLoop]: trace histogram [17, 17, 16, 16, 16, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:08,188 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:08,188 INFO L82 PathProgramCache]: Analyzing trace with hash -589138691, now seen corresponding path program 16 times [2018-01-24 12:58:08,188 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:08,189 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:08,189 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:08,189 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:08,189 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:08,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:08,202 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:08,518 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:08,518 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:08,518 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:08,525 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:08,525 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:08,544 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:08,547 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:08,567 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:08,567 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:08,874 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:08,893 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:08,894 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:08,896 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:08,896 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:08,945 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:08,949 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:08,963 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:08,964 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:08,980 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:08,981 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:08,982 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 35 [2018-01-24 12:58:08,982 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:08,982 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 12:58:08,982 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 12:58:08,983 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 12:58:08,983 INFO L87 Difference]: Start difference. First operand 256 states and 338 transitions. Second operand 19 states. [2018-01-24 12:58:10,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:10,150 INFO L93 Difference]: Finished difference Result 295 states and 384 transitions. [2018-01-24 12:58:10,150 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 12:58:10,150 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 88 [2018-01-24 12:58:10,151 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:10,152 INFO L225 Difference]: With dead ends: 295 [2018-01-24 12:58:10,152 INFO L226 Difference]: Without dead ends: 291 [2018-01-24 12:58:10,152 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 368 GetRequests, 332 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 12:58:10,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states. [2018-01-24 12:58:10,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 270. [2018-01-24 12:58:10,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2018-01-24 12:58:10,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 357 transitions. [2018-01-24 12:58:10,162 INFO L78 Accepts]: Start accepts. Automaton has 270 states and 357 transitions. Word has length 88 [2018-01-24 12:58:10,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:10,162 INFO L432 AbstractCegarLoop]: Abstraction has 270 states and 357 transitions. [2018-01-24 12:58:10,162 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 12:58:10,162 INFO L276 IsEmpty]: Start isEmpty. Operand 270 states and 357 transitions. [2018-01-24 12:58:10,164 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-01-24 12:58:10,164 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:10,165 INFO L322 BasicCegarLoop]: trace histogram [18, 18, 17, 17, 17, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:10,165 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:10,165 INFO L82 PathProgramCache]: Analyzing trace with hash -2053377585, now seen corresponding path program 17 times [2018-01-24 12:58:10,165 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:10,166 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:10,166 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:10,166 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:10,166 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:10,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:10,177 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:10,717 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:10,717 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:10,717 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:10,723 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:10,724 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:10,727 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,729 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,730 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,731 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,733 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,734 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,736 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,738 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,740 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,742 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,745 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,747 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,750 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,753 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,756 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,758 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,761 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,765 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:10,766 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:10,768 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:10,800 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:10,800 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:11,246 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:11,265 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:11,266 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:11,268 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:11,268 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:11,272 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,274 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,279 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,285 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,292 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,300 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,309 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,319 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,330 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,342 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,355 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,370 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,385 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,401 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,426 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,445 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,465 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,487 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:11,506 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:11,511 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:11,526 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:11,526 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:11,549 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:11,550 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:11,551 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 37 [2018-01-24 12:58:11,551 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:11,551 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 12:58:11,551 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 12:58:11,551 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 12:58:11,552 INFO L87 Difference]: Start difference. First operand 270 states and 357 transitions. Second operand 20 states. [2018-01-24 12:58:12,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:12,892 INFO L93 Difference]: Finished difference Result 310 states and 404 transitions. [2018-01-24 12:58:12,892 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 12:58:12,892 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 93 [2018-01-24 12:58:12,893 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:12,894 INFO L225 Difference]: With dead ends: 310 [2018-01-24 12:58:12,895 INFO L226 Difference]: Without dead ends: 306 [2018-01-24 12:58:12,895 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 389 GetRequests, 351 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 12:58:12,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306 states. [2018-01-24 12:58:12,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306 to 284. [2018-01-24 12:58:12,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 284 states. [2018-01-24 12:58:12,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 376 transitions. [2018-01-24 12:58:12,909 INFO L78 Accepts]: Start accepts. Automaton has 284 states and 376 transitions. Word has length 93 [2018-01-24 12:58:12,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:12,909 INFO L432 AbstractCegarLoop]: Abstraction has 284 states and 376 transitions. [2018-01-24 12:58:12,909 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 12:58:12,909 INFO L276 IsEmpty]: Start isEmpty. Operand 284 states and 376 transitions. [2018-01-24 12:58:12,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-01-24 12:58:12,911 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:12,911 INFO L322 BasicCegarLoop]: trace histogram [19, 19, 18, 18, 18, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:12,911 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:12,912 INFO L82 PathProgramCache]: Analyzing trace with hash 1741269053, now seen corresponding path program 18 times [2018-01-24 12:58:12,912 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:12,912 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:12,913 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:12,913 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:12,913 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:12,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:12,928 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:13,273 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:13,273 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:13,273 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:13,278 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:13,278 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:13,282 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,286 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,287 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,288 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,302 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,303 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,305 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,306 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,309 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,311 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,313 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,316 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,318 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,321 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,324 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,328 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,331 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,335 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,338 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,339 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:13,341 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:13,363 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:13,363 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:13,859 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:13,880 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:13,880 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:13,883 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:13,884 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:13,888 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,890 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,895 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,901 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,907 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,915 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,924 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,933 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,944 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,955 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,968 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,982 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:13,998 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:14,014 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:14,032 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:14,059 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:14,079 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:14,101 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:14,123 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:14,147 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:14,151 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:14,169 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:14,169 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:14,197 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:14,198 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:14,198 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 39 [2018-01-24 12:58:14,198 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:14,199 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 12:58:14,199 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 12:58:14,199 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 12:58:14,199 INFO L87 Difference]: Start difference. First operand 284 states and 376 transitions. Second operand 21 states. [2018-01-24 12:58:16,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:16,319 INFO L93 Difference]: Finished difference Result 325 states and 424 transitions. [2018-01-24 12:58:16,320 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 12:58:16,320 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 98 [2018-01-24 12:58:16,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:16,322 INFO L225 Difference]: With dead ends: 325 [2018-01-24 12:58:16,322 INFO L226 Difference]: Without dead ends: 321 [2018-01-24 12:58:16,323 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 410 GetRequests, 370 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 12:58:16,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2018-01-24 12:58:16,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 298. [2018-01-24 12:58:16,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 298 states. [2018-01-24 12:58:16,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 395 transitions. [2018-01-24 12:58:16,340 INFO L78 Accepts]: Start accepts. Automaton has 298 states and 395 transitions. Word has length 98 [2018-01-24 12:58:16,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:16,341 INFO L432 AbstractCegarLoop]: Abstraction has 298 states and 395 transitions. [2018-01-24 12:58:16,341 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 12:58:16,341 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 395 transitions. [2018-01-24 12:58:16,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2018-01-24 12:58:16,343 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:16,343 INFO L322 BasicCegarLoop]: trace histogram [20, 20, 19, 19, 19, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:16,343 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:16,344 INFO L82 PathProgramCache]: Analyzing trace with hash 661833359, now seen corresponding path program 19 times [2018-01-24 12:58:16,344 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:16,344 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:16,345 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:16,345 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:16,345 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:16,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:16,361 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:16,680 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:16,680 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:16,680 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:16,685 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:16,685 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:16,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:16,699 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:16,724 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:16,724 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:17,228 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:17,248 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:17,248 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:17,251 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:17,251 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:17,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:17,290 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:17,308 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:17,308 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:17,329 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:17,330 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:17,330 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 41 [2018-01-24 12:58:17,330 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:17,331 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 12:58:17,331 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 12:58:17,331 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 12:58:17,331 INFO L87 Difference]: Start difference. First operand 298 states and 395 transitions. Second operand 22 states. [2018-01-24 12:58:18,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:18,943 INFO L93 Difference]: Finished difference Result 340 states and 444 transitions. [2018-01-24 12:58:18,943 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 12:58:18,944 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 103 [2018-01-24 12:58:18,944 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:18,945 INFO L225 Difference]: With dead ends: 340 [2018-01-24 12:58:18,946 INFO L226 Difference]: Without dead ends: 336 [2018-01-24 12:58:18,946 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 431 GetRequests, 389 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 12:58:18,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 336 states. [2018-01-24 12:58:18,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 336 to 312. [2018-01-24 12:58:18,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 312 states. [2018-01-24 12:58:18,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312 states to 312 states and 414 transitions. [2018-01-24 12:58:18,960 INFO L78 Accepts]: Start accepts. Automaton has 312 states and 414 transitions. Word has length 103 [2018-01-24 12:58:18,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:18,960 INFO L432 AbstractCegarLoop]: Abstraction has 312 states and 414 transitions. [2018-01-24 12:58:18,960 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 12:58:18,960 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 414 transitions. [2018-01-24 12:58:18,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-01-24 12:58:18,962 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:18,962 INFO L322 BasicCegarLoop]: trace histogram [21, 21, 20, 20, 20, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:18,962 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:18,962 INFO L82 PathProgramCache]: Analyzing trace with hash -2034644099, now seen corresponding path program 20 times [2018-01-24 12:58:18,962 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:18,963 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:18,963 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:18,963 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:18,963 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:18,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:18,980 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:19,271 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:19,271 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:19,271 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:19,276 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:19,276 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:19,280 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:19,288 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:19,290 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:19,292 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:19,311 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:19,311 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:19,882 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:19,902 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:19,902 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:19,905 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:19,905 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:19,910 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:19,924 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:19,944 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:19,949 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:19,968 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:19,968 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:20,018 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:20,019 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:20,019 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 43 [2018-01-24 12:58:20,020 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:20,020 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 12:58:20,020 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 12:58:20,021 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 12:58:20,021 INFO L87 Difference]: Start difference. First operand 312 states and 414 transitions. Second operand 23 states. [2018-01-24 12:58:21,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:21,893 INFO L93 Difference]: Finished difference Result 355 states and 464 transitions. [2018-01-24 12:58:21,893 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 12:58:21,893 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 108 [2018-01-24 12:58:21,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:21,895 INFO L225 Difference]: With dead ends: 355 [2018-01-24 12:58:21,895 INFO L226 Difference]: Without dead ends: 351 [2018-01-24 12:58:21,896 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 452 GetRequests, 408 SyntacticMatches, 2 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 12:58:21,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 351 states. [2018-01-24 12:58:21,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 351 to 326. [2018-01-24 12:58:21,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 326 states. [2018-01-24 12:58:21,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 326 states to 326 states and 433 transitions. [2018-01-24 12:58:21,909 INFO L78 Accepts]: Start accepts. Automaton has 326 states and 433 transitions. Word has length 108 [2018-01-24 12:58:21,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:21,910 INFO L432 AbstractCegarLoop]: Abstraction has 326 states and 433 transitions. [2018-01-24 12:58:21,910 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 12:58:21,910 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 433 transitions. [2018-01-24 12:58:21,912 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-01-24 12:58:21,912 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:21,913 INFO L322 BasicCegarLoop]: trace histogram [22, 22, 21, 21, 21, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:21,913 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:21,913 INFO L82 PathProgramCache]: Analyzing trace with hash 89566031, now seen corresponding path program 21 times [2018-01-24 12:58:21,913 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:21,914 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:21,914 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:21,914 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:21,914 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:21,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:21,930 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:22,245 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:22,245 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:22,245 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:22,250 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:22,250 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:22,254 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,255 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,256 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,257 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,258 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,259 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,260 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,262 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,263 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,265 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,266 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,268 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,270 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,272 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,273 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,275 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,277 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,280 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,283 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,285 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,287 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,290 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,290 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:22,293 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:22,312 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:22,312 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:22,806 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:22,826 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:22,826 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:22,829 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:22,829 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:22,835 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,836 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,841 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,847 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,853 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,861 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,869 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,879 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,890 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,901 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,914 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,928 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,944 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,960 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,977 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:22,995 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:23,023 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:23,044 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:23,065 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:23,089 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:23,121 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:23,146 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:23,166 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:23,180 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:23,211 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:23,212 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:23,268 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:23,270 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:23,271 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 45 [2018-01-24 12:58:23,271 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:23,271 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 12:58:23,271 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 12:58:23,272 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 12:58:23,272 INFO L87 Difference]: Start difference. First operand 326 states and 433 transitions. Second operand 24 states. [2018-01-24 12:58:25,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:25,227 INFO L93 Difference]: Finished difference Result 370 states and 484 transitions. [2018-01-24 12:58:25,228 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 12:58:25,228 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 113 [2018-01-24 12:58:25,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:25,229 INFO L225 Difference]: With dead ends: 370 [2018-01-24 12:58:25,229 INFO L226 Difference]: Without dead ends: 366 [2018-01-24 12:58:25,230 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 473 GetRequests, 427 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 12:58:25,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states. [2018-01-24 12:58:25,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 340. [2018-01-24 12:58:25,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 340 states. [2018-01-24 12:58:25,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 452 transitions. [2018-01-24 12:58:25,245 INFO L78 Accepts]: Start accepts. Automaton has 340 states and 452 transitions. Word has length 113 [2018-01-24 12:58:25,245 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:25,245 INFO L432 AbstractCegarLoop]: Abstraction has 340 states and 452 transitions. [2018-01-24 12:58:25,245 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 12:58:25,246 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 452 transitions. [2018-01-24 12:58:25,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-01-24 12:58:25,247 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:25,248 INFO L322 BasicCegarLoop]: trace histogram [23, 23, 22, 22, 22, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:25,248 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:25,248 INFO L82 PathProgramCache]: Analyzing trace with hash 927391421, now seen corresponding path program 22 times [2018-01-24 12:58:25,248 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:25,249 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:25,249 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:25,249 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:25,249 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:25,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:25,261 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:25,623 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:25,623 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:25,623 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:25,629 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:25,629 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:25,657 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:25,660 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:25,706 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:25,706 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:26,307 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:26,327 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:26,327 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:26,330 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:26,330 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:26,396 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:26,401 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:26,424 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:26,425 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:26,453 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:26,455 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:26,455 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 47 [2018-01-24 12:58:26,455 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:26,455 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-24 12:58:26,455 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-24 12:58:26,456 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 12:58:26,456 INFO L87 Difference]: Start difference. First operand 340 states and 452 transitions. Second operand 25 states. [2018-01-24 12:58:28,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:28,526 INFO L93 Difference]: Finished difference Result 385 states and 504 transitions. [2018-01-24 12:58:28,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 12:58:28,527 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 118 [2018-01-24 12:58:28,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:28,528 INFO L225 Difference]: With dead ends: 385 [2018-01-24 12:58:28,528 INFO L226 Difference]: Without dead ends: 381 [2018-01-24 12:58:28,529 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 494 GetRequests, 446 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 12:58:28,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 381 states. [2018-01-24 12:58:28,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 381 to 354. [2018-01-24 12:58:28,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354 states. [2018-01-24 12:58:28,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354 states to 354 states and 471 transitions. [2018-01-24 12:58:28,544 INFO L78 Accepts]: Start accepts. Automaton has 354 states and 471 transitions. Word has length 118 [2018-01-24 12:58:28,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:28,544 INFO L432 AbstractCegarLoop]: Abstraction has 354 states and 471 transitions. [2018-01-24 12:58:28,544 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-24 12:58:28,545 INFO L276 IsEmpty]: Start isEmpty. Operand 354 states and 471 transitions. [2018-01-24 12:58:28,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-01-24 12:58:28,546 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:28,546 INFO L322 BasicCegarLoop]: trace histogram [24, 24, 23, 23, 23, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:28,547 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:28,547 INFO L82 PathProgramCache]: Analyzing trace with hash 2117312527, now seen corresponding path program 23 times [2018-01-24 12:58:28,547 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:28,547 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:28,548 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:28,548 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:28,548 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:28,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:28,565 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:28,937 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:28,937 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:28,937 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:28,942 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:28,942 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:28,946 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,947 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,948 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,949 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,950 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,951 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,953 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,954 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,955 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,957 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,959 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,960 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,962 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,964 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,966 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,968 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,970 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,972 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,974 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,977 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,979 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,982 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,984 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,987 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:28,988 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:28,990 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:29,012 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:29,013 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:29,587 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:29,607 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:29,607 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:29,610 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:29,610 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:29,615 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,617 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,622 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,628 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,635 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,643 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,652 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,662 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,673 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,684 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,697 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,712 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,727 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,744 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,769 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,788 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,808 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,829 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,851 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,884 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,909 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,934 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,967 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:29,995 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:30,025 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:30,032 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:30,054 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:30,054 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:30,086 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:30,088 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:30,088 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 49 [2018-01-24 12:58:30,088 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:30,088 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 12:58:30,088 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 12:58:30,089 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 12:58:30,089 INFO L87 Difference]: Start difference. First operand 354 states and 471 transitions. Second operand 26 states. [2018-01-24 12:58:32,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:32,397 INFO L93 Difference]: Finished difference Result 400 states and 524 transitions. [2018-01-24 12:58:32,398 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 12:58:32,398 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 123 [2018-01-24 12:58:32,398 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:32,399 INFO L225 Difference]: With dead ends: 400 [2018-01-24 12:58:32,400 INFO L226 Difference]: Without dead ends: 396 [2018-01-24 12:58:32,400 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 515 GetRequests, 465 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 12:58:32,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 396 states. [2018-01-24 12:58:32,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 396 to 368. [2018-01-24 12:58:32,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2018-01-24 12:58:32,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 490 transitions. [2018-01-24 12:58:32,410 INFO L78 Accepts]: Start accepts. Automaton has 368 states and 490 transitions. Word has length 123 [2018-01-24 12:58:32,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:32,410 INFO L432 AbstractCegarLoop]: Abstraction has 368 states and 490 transitions. [2018-01-24 12:58:32,410 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 12:58:32,410 INFO L276 IsEmpty]: Start isEmpty. Operand 368 states and 490 transitions. [2018-01-24 12:58:32,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-01-24 12:58:32,411 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:32,412 INFO L322 BasicCegarLoop]: trace histogram [25, 25, 24, 24, 24, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:32,412 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:32,412 INFO L82 PathProgramCache]: Analyzing trace with hash -1912282627, now seen corresponding path program 24 times [2018-01-24 12:58:32,412 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:32,413 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:32,413 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:32,413 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:32,413 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:32,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:32,425 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:32,846 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:32,846 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:32,846 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:32,851 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:32,851 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:32,855 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,856 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,857 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,858 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,860 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,861 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,862 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,864 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,865 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,867 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,869 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,870 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,872 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,875 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,877 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,879 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,881 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,884 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,886 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,888 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,891 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,893 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,896 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,899 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,902 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:32,902 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:32,905 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:32,929 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:32,929 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:33,655 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:33,675 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:33,676 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:33,679 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:33,679 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:33,684 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,686 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,691 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,697 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,704 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,712 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,721 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,731 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,743 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,756 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,770 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,785 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,803 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,820 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,839 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,870 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,893 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,917 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,941 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:33,975 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:34,002 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:34,029 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:34,069 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:34,099 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:34,141 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:34,166 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:34,172 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:34,200 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,201 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:34,235 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,236 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:34,237 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 51 [2018-01-24 12:58:34,237 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:34,237 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 12:58:34,237 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 12:58:34,238 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 12:58:34,238 INFO L87 Difference]: Start difference. First operand 368 states and 490 transitions. Second operand 27 states. [2018-01-24 12:58:36,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:36,843 INFO L93 Difference]: Finished difference Result 415 states and 544 transitions. [2018-01-24 12:58:36,843 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 12:58:36,843 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 128 [2018-01-24 12:58:36,844 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:36,845 INFO L225 Difference]: With dead ends: 415 [2018-01-24 12:58:36,845 INFO L226 Difference]: Without dead ends: 411 [2018-01-24 12:58:36,846 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 536 GetRequests, 484 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 12:58:36,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 411 states. [2018-01-24 12:58:36,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 411 to 382. [2018-01-24 12:58:36,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2018-01-24 12:58:36,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 509 transitions. [2018-01-24 12:58:36,862 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 509 transitions. Word has length 128 [2018-01-24 12:58:36,862 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:36,862 INFO L432 AbstractCegarLoop]: Abstraction has 382 states and 509 transitions. [2018-01-24 12:58:36,863 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 12:58:36,863 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 509 transitions. [2018-01-24 12:58:36,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2018-01-24 12:58:36,865 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:36,865 INFO L322 BasicCegarLoop]: trace histogram [26, 26, 25, 25, 25, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:36,865 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:36,865 INFO L82 PathProgramCache]: Analyzing trace with hash 972399823, now seen corresponding path program 25 times [2018-01-24 12:58:36,866 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:36,866 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:36,866 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:36,867 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:36,867 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:36,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:36,885 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:37,338 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:37,339 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:37,339 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:37,344 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:37,344 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:37,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:37,362 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:37,390 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:37,390 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:38,101 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:38,120 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:38,121 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:38,124 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:38,124 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:38,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:38,178 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:38,204 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:38,205 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:38,242 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:38,243 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:38,243 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 53 [2018-01-24 12:58:38,244 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:38,244 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 12:58:38,244 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 12:58:38,245 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 12:58:38,245 INFO L87 Difference]: Start difference. First operand 382 states and 509 transitions. Second operand 28 states. [2018-01-24 12:58:41,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:41,036 INFO L93 Difference]: Finished difference Result 430 states and 564 transitions. [2018-01-24 12:58:41,036 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 12:58:41,036 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 133 [2018-01-24 12:58:41,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:41,038 INFO L225 Difference]: With dead ends: 430 [2018-01-24 12:58:41,038 INFO L226 Difference]: Without dead ends: 426 [2018-01-24 12:58:41,039 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 557 GetRequests, 503 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 12:58:41,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 426 states. [2018-01-24 12:58:41,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 426 to 396. [2018-01-24 12:58:41,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 396 states. [2018-01-24 12:58:41,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 396 states to 396 states and 528 transitions. [2018-01-24 12:58:41,055 INFO L78 Accepts]: Start accepts. Automaton has 396 states and 528 transitions. Word has length 133 [2018-01-24 12:58:41,055 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:41,055 INFO L432 AbstractCegarLoop]: Abstraction has 396 states and 528 transitions. [2018-01-24 12:58:41,055 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 12:58:41,055 INFO L276 IsEmpty]: Start isEmpty. Operand 396 states and 528 transitions. [2018-01-24 12:58:41,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-01-24 12:58:41,058 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:41,058 INFO L322 BasicCegarLoop]: trace histogram [27, 27, 26, 26, 26, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:41,058 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:41,058 INFO L82 PathProgramCache]: Analyzing trace with hash -158870211, now seen corresponding path program 26 times [2018-01-24 12:58:41,058 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:41,059 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:41,059 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:41,059 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:41,059 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:41,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:41,077 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:41,542 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:41,543 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:41,543 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:41,548 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:41,548 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:41,554 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:41,566 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:41,569 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:41,572 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:41,617 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:41,618 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:42,406 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:42,426 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:42,426 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:42,429 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:42,429 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:42,435 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:42,453 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:42,478 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:42,483 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:42,514 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:42,514 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:42,554 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:42,555 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:42,555 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 55 [2018-01-24 12:58:42,555 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:42,555 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 12:58:42,556 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 12:58:42,556 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 12:58:42,556 INFO L87 Difference]: Start difference. First operand 396 states and 528 transitions. Second operand 29 states. [2018-01-24 12:58:45,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:45,564 INFO L93 Difference]: Finished difference Result 445 states and 584 transitions. [2018-01-24 12:58:45,564 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 12:58:45,564 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 138 [2018-01-24 12:58:45,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:45,566 INFO L225 Difference]: With dead ends: 445 [2018-01-24 12:58:45,566 INFO L226 Difference]: Without dead ends: 441 [2018-01-24 12:58:45,567 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 578 GetRequests, 522 SyntacticMatches, 2 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 12:58:45,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 441 states. [2018-01-24 12:58:45,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 441 to 410. [2018-01-24 12:58:45,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 410 states. [2018-01-24 12:58:45,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 410 states to 410 states and 547 transitions. [2018-01-24 12:58:45,576 INFO L78 Accepts]: Start accepts. Automaton has 410 states and 547 transitions. Word has length 138 [2018-01-24 12:58:45,577 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:45,577 INFO L432 AbstractCegarLoop]: Abstraction has 410 states and 547 transitions. [2018-01-24 12:58:45,577 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-24 12:58:45,577 INFO L276 IsEmpty]: Start isEmpty. Operand 410 states and 547 transitions. [2018-01-24 12:58:45,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 144 [2018-01-24 12:58:45,579 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:45,579 INFO L322 BasicCegarLoop]: trace histogram [28, 28, 27, 27, 27, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:45,579 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:45,579 INFO L82 PathProgramCache]: Analyzing trace with hash -376915569, now seen corresponding path program 27 times [2018-01-24 12:58:45,579 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:45,580 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:45,580 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:45,580 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:45,580 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:45,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:45,593 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:46,071 INFO L134 CoverageAnalysis]: Checked inductivity of 1836 backedges. 0 proven. 1836 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:46,071 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:46,071 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:46,076 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:46,076 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:46,082 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,084 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,085 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,087 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,089 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,090 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,092 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,093 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,095 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,096 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,098 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,100 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,102 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,104 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,106 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,108 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,112 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,115 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,117 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,120 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,122 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,125 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,128 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,131 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,134 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,138 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,143 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,148 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,149 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:46,151 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:46,183 INFO L134 CoverageAnalysis]: Checked inductivity of 1836 backedges. 0 proven. 1836 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:46,183 INFO L314 TraceCheckSpWp]: Computing backward predicates... Received shutdown request... [2018-01-24 12:58:46,513 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-01-24 12:58:46,514 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 12:58:46,517 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 12:58:46,517 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 12:58:46 BoogieIcfgContainer [2018-01-24 12:58:46,517 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 12:58:46,518 INFO L168 Benchmark]: Toolchain (without parser) took 53974.82 ms. Allocated memory was 296.7 MB in the beginning and 730.3 MB in the end (delta: 433.6 MB). Free memory was 257.8 MB in the beginning and 283.3 MB in the end (delta: -25.5 MB). Peak memory consumption was 408.1 MB. Max. memory is 5.3 GB. [2018-01-24 12:58:46,519 INFO L168 Benchmark]: CDTParser took 0.23 ms. Allocated memory is still 296.7 MB. Free memory is still 262.8 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 12:58:46,519 INFO L168 Benchmark]: CACSL2BoogieTranslator took 176.74 ms. Allocated memory is still 296.7 MB. Free memory was 256.8 MB in the beginning and 248.7 MB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 5.3 GB. [2018-01-24 12:58:46,519 INFO L168 Benchmark]: Boogie Preprocessor took 31.61 ms. Allocated memory is still 296.7 MB. Free memory was 248.7 MB in the beginning and 246.7 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 12:58:46,520 INFO L168 Benchmark]: RCFGBuilder took 184.58 ms. Allocated memory is still 296.7 MB. Free memory was 246.7 MB in the beginning and 234.1 MB in the end (delta: 12.6 MB). Peak memory consumption was 12.6 MB. Max. memory is 5.3 GB. [2018-01-24 12:58:46,520 INFO L168 Benchmark]: TraceAbstraction took 53573.83 ms. Allocated memory was 296.7 MB in the beginning and 730.3 MB in the end (delta: 433.6 MB). Free memory was 233.1 MB in the beginning and 283.3 MB in the end (delta: -50.1 MB). Peak memory consumption was 383.5 MB. Max. memory is 5.3 GB. [2018-01-24 12:58:46,521 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.23 ms. Allocated memory is still 296.7 MB. Free memory is still 262.8 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 176.74 ms. Allocated memory is still 296.7 MB. Free memory was 256.8 MB in the beginning and 248.7 MB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 31.61 ms. Allocated memory is still 296.7 MB. Free memory was 248.7 MB in the beginning and 246.7 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 184.58 ms. Allocated memory is still 296.7 MB. Free memory was 246.7 MB in the beginning and 234.1 MB in the end (delta: 12.6 MB). Peak memory consumption was 12.6 MB. Max. memory is 5.3 GB. * TraceAbstraction took 53573.83 ms. Allocated memory was 296.7 MB in the beginning and 730.3 MB in the end (delta: 433.6 MB). Free memory was 233.1 MB in the beginning and 283.3 MB in the end (delta: -50.1 MB). Peak memory consumption was 383.5 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 17]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 17). Cancelled while BasicCegarLoop was analyzing trace of length 144 with TraceHistMax 28, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 44 known predicates. - TimeoutResultAtElement [Line: 24]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 24). Cancelled while BasicCegarLoop was analyzing trace of length 144 with TraceHistMax 28, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 44 known predicates. - TimeoutResultAtElement [Line: 26]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 26). Cancelled while BasicCegarLoop was analyzing trace of length 144 with TraceHistMax 28, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 44 known predicates. - TimeoutResultAtElement [Line: 19]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 19). Cancelled while BasicCegarLoop was analyzing trace of length 144 with TraceHistMax 28, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 44 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 6 procedures, 42 locations, 4 error locations. TIMEOUT Result, 53.5s OverallTime, 28 OverallIterations, 28 TraceHistogramMax, 30.5s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4757 SDtfs, 3459 SDslu, 59609 SDs, 0 SdLazy, 83952 SolverSat, 837 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 24.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 8205 GetRequests, 7398 SyntacticMatches, 52 SemanticMatches, 755 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 377 ImplicationChecksByTransitivity, 12.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=410occurred in iteration=27, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.3s AutomataMinimizationTime, 27 MinimizatonAttempts, 486 StatesRemovedByMinimization, 27 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 3.5s SatisfiabilityAnalysisTime, 16.5s InterpolantComputationTime, 5897 NumberOfCodeBlocks, 5897 NumberOfCodeBlocksAsserted, 425 NumberOfCheckSat, 9692 ConstructedInterpolants, 0 QuantifiedInterpolants, 6767390 SizeOfPredicates, 0 NumberOfNonLiveVariables, 5200 ConjunctsInSsa, 1560 ConjunctsInUnsatCore, 131 InterpolantComputations, 1 PerfectInterpolantSequences, 0/78390 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sanfoundry_24_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_12-58-46-528.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sanfoundry_24_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_12-58-46-528.csv Completed graceful shutdown