java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/array-examples/sanfoundry_24_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 15:24:21,857 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 15:24:21,859 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 15:24:21,871 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 15:24:21,871 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 15:24:21,871 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 15:24:21,872 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 15:24:21,874 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 15:24:21,876 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 15:24:21,877 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 15:24:21,877 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 15:24:21,877 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 15:24:21,878 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 15:24:21,879 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 15:24:21,880 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 15:24:21,882 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 15:24:21,884 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 15:24:21,886 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 15:24:21,888 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 15:24:21,889 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 15:24:21,891 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-01-24 15:24:21,896 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 15:24:21,896 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 15:24:21,896 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf [2018-01-24 15:24:21,906 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 15:24:21,906 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 15:24:21,907 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 15:24:21,907 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 15:24:21,907 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 15:24:21,908 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 15:24:21,908 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 15:24:21,908 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 15:24:21,909 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 15:24:21,909 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 15:24:21,909 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 15:24:21,909 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 15:24:21,909 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 15:24:21,910 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 15:24:21,910 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 15:24:21,910 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 15:24:21,910 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 15:24:21,910 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 15:24:21,911 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 15:24:21,911 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 15:24:21,911 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 15:24:21,911 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 15:24:21,911 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 15:24:21,912 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 15:24:21,912 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 15:24:21,912 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 15:24:21,912 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 15:24:21,913 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 15:24:21,913 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 15:24:21,913 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 15:24:21,913 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 15:24:21,913 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 15:24:21,913 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 15:24:21,914 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 15:24:21,915 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 15:24:21,949 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 15:24:21,961 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 15:24:21,965 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 15:24:21,967 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 15:24:21,967 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 15:24:21,968 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/sanfoundry_24_false-valid-deref.i [2018-01-24 15:24:22,132 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 15:24:22,138 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 15:24:22,139 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 15:24:22,139 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 15:24:22,144 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 15:24:22,145 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 03:24:22" (1/1) ... [2018-01-24 15:24:22,147 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@700b35a5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:24:22, skipping insertion in model container [2018-01-24 15:24:22,148 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 03:24:22" (1/1) ... [2018-01-24 15:24:22,166 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 15:24:22,185 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 15:24:22,301 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 15:24:22,312 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 15:24:22,316 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:24:22 WrapperNode [2018-01-24 15:24:22,316 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 15:24:22,317 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 15:24:22,317 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 15:24:22,317 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 15:24:22,330 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:24:22" (1/1) ... [2018-01-24 15:24:22,330 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:24:22" (1/1) ... [2018-01-24 15:24:22,336 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:24:22" (1/1) ... [2018-01-24 15:24:22,337 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:24:22" (1/1) ... [2018-01-24 15:24:22,338 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:24:22" (1/1) ... [2018-01-24 15:24:22,342 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:24:22" (1/1) ... [2018-01-24 15:24:22,343 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:24:22" (1/1) ... [2018-01-24 15:24:22,344 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 15:24:22,345 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 15:24:22,345 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 15:24:22,345 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 15:24:22,346 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:24:22" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 15:24:22,388 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 15:24:22,389 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 15:24:22,389 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 15:24:22,389 INFO L136 BoogieDeclarations]: Found implementation of procedure printEven [2018-01-24 15:24:22,389 INFO L136 BoogieDeclarations]: Found implementation of procedure printOdd [2018-01-24 15:24:22,389 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 15:24:22,389 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 15:24:22,389 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 15:24:22,390 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-24 15:24:22,390 INFO L128 BoogieDeclarations]: Found specification of procedure printEven [2018-01-24 15:24:22,390 INFO L128 BoogieDeclarations]: Found specification of procedure printOdd [2018-01-24 15:24:22,390 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 15:24:22,390 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 15:24:22,390 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 15:24:22,519 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 15:24:22,519 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 03:24:22 BoogieIcfgContainer [2018-01-24 15:24:22,519 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 15:24:22,520 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 15:24:22,520 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 15:24:22,523 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 15:24:22,523 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 03:24:22" (1/3) ... [2018-01-24 15:24:22,525 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e9d5320 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 03:24:22, skipping insertion in model container [2018-01-24 15:24:22,525 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:24:22" (2/3) ... [2018-01-24 15:24:22,526 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e9d5320 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 03:24:22, skipping insertion in model container [2018-01-24 15:24:22,526 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 03:24:22" (3/3) ... [2018-01-24 15:24:22,527 INFO L105 eAbstractionObserver]: Analyzing ICFG sanfoundry_24_false-valid-deref.i [2018-01-24 15:24:22,534 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 15:24:22,540 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 4 error locations. [2018-01-24 15:24:22,577 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 15:24:22,577 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 15:24:22,577 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 15:24:22,578 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 15:24:22,578 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 15:24:22,578 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 15:24:22,578 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 15:24:22,578 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 15:24:22,579 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 15:24:22,598 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states. [2018-01-24 15:24:22,604 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 15:24:22,605 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:22,606 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:22,606 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:22,611 INFO L82 PathProgramCache]: Analyzing trace with hash 529177341, now seen corresponding path program 1 times [2018-01-24 15:24:22,614 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:22,659 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:22,659 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:24:22,659 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:22,660 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:22,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:22,702 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:22,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:22,764 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 15:24:22,764 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 15:24:22,765 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:24:22,766 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 15:24:22,777 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 15:24:22,778 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 15:24:22,780 INFO L87 Difference]: Start difference. First operand 42 states. Second operand 3 states. [2018-01-24 15:24:22,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:22,893 INFO L93 Difference]: Finished difference Result 97 states and 129 transitions. [2018-01-24 15:24:22,893 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 15:24:22,895 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 8 [2018-01-24 15:24:22,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:22,903 INFO L225 Difference]: With dead ends: 97 [2018-01-24 15:24:22,903 INFO L226 Difference]: Without dead ends: 51 [2018-01-24 15:24:22,906 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 15:24:22,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-01-24 15:24:23,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 46. [2018-01-24 15:24:23,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-01-24 15:24:23,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 53 transitions. [2018-01-24 15:24:23,003 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 53 transitions. Word has length 8 [2018-01-24 15:24:23,003 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:23,003 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 53 transitions. [2018-01-24 15:24:23,004 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 15:24:23,004 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 53 transitions. [2018-01-24 15:24:23,004 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-01-24 15:24:23,004 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:23,005 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:23,005 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:23,005 INFO L82 PathProgramCache]: Analyzing trace with hash -2078569521, now seen corresponding path program 1 times [2018-01-24 15:24:23,005 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:23,006 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:23,006 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:24:23,006 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:23,006 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:23,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:23,023 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:23,070 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:23,070 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:23,070 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:23,071 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 14 with the following transitions: [2018-01-24 15:24:23,072 INFO L201 CegarAbsIntRunner]: [0], [10], [14], [19], [20], [21], [29], [31], [74], [75], [76] [2018-01-24 15:24:23,116 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 15:24:23,116 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 15:24:23,198 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 15:24:23,199 INFO L268 AbstractInterpreter]: Visited 11 different actions 17 times. Merged at 6 different actions 6 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 5 variables. [2018-01-24 15:24:23,210 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 15:24:23,211 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:23,211 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:23,220 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:24:23,220 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:24:23,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:23,236 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:23,253 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:23,253 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:23,301 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:23,336 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:23,336 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:23,342 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:24:23,342 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:24:23,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:23,357 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:23,365 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:23,365 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:23,375 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:23,377 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:23,377 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3, 3, 3] total 5 [2018-01-24 15:24:23,377 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:23,378 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 15:24:23,378 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 15:24:23,378 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 15:24:23,379 INFO L87 Difference]: Start difference. First operand 46 states and 53 transitions. Second operand 4 states. [2018-01-24 15:24:23,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:23,495 INFO L93 Difference]: Finished difference Result 70 states and 84 transitions. [2018-01-24 15:24:23,495 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 15:24:23,495 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2018-01-24 15:24:23,495 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:23,496 INFO L225 Difference]: With dead ends: 70 [2018-01-24 15:24:23,496 INFO L226 Difference]: Without dead ends: 66 [2018-01-24 15:24:23,497 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 47 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 15:24:23,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-01-24 15:24:23,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 60. [2018-01-24 15:24:23,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-01-24 15:24:23,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 72 transitions. [2018-01-24 15:24:23,504 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 72 transitions. Word has length 13 [2018-01-24 15:24:23,504 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:23,504 INFO L432 AbstractCegarLoop]: Abstraction has 60 states and 72 transitions. [2018-01-24 15:24:23,504 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 15:24:23,505 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 72 transitions. [2018-01-24 15:24:23,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-01-24 15:24:23,505 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:23,506 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:23,506 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:23,506 INFO L82 PathProgramCache]: Analyzing trace with hash 1794788925, now seen corresponding path program 2 times [2018-01-24 15:24:23,506 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:23,507 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:23,507 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:24:23,507 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:23,507 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:23,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:23,516 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:23,573 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:23,574 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:23,574 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:23,574 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:23,574 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:23,574 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:23,574 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:23,587 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:24:23,588 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:23,592 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:23,594 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:23,595 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:23,596 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:23,622 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:23,622 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:23,715 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:23,734 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:23,735 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:23,738 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:24:23,738 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:23,743 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:23,746 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:23,753 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:23,756 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:23,762 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:23,762 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:23,776 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:23,777 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:23,778 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 7 [2018-01-24 15:24:23,778 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:23,778 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 15:24:23,778 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 15:24:23,778 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 15:24:23,779 INFO L87 Difference]: Start difference. First operand 60 states and 72 transitions. Second operand 5 states. [2018-01-24 15:24:23,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:23,901 INFO L93 Difference]: Finished difference Result 85 states and 104 transitions. [2018-01-24 15:24:23,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 15:24:23,901 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 18 [2018-01-24 15:24:23,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:23,904 INFO L225 Difference]: With dead ends: 85 [2018-01-24 15:24:23,904 INFO L226 Difference]: Without dead ends: 81 [2018-01-24 15:24:23,905 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 66 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 15:24:23,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-01-24 15:24:23,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 74. [2018-01-24 15:24:23,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-24 15:24:23,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 91 transitions. [2018-01-24 15:24:23,918 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 91 transitions. Word has length 18 [2018-01-24 15:24:23,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:23,918 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 91 transitions. [2018-01-24 15:24:23,918 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 15:24:23,918 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 91 transitions. [2018-01-24 15:24:23,920 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-01-24 15:24:23,920 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:23,920 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:23,920 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:23,921 INFO L82 PathProgramCache]: Analyzing trace with hash -424025969, now seen corresponding path program 3 times [2018-01-24 15:24:23,921 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:23,922 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:23,922 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:23,922 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:23,922 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:23,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:23,936 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:24,090 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:24,091 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:24,091 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:24,091 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:24,091 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:24,091 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:24,091 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:24,097 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:24:24,127 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:24:24,131 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:24,132 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:24,146 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:24,159 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:24,160 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:24,161 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:24,169 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:24,169 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:24,254 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:24,283 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:24,283 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:24,286 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:24:24,287 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:24:24,291 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:24,293 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:24,298 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:24,303 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:24,308 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:24,311 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:24,318 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:24,318 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:24,328 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:24,329 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:24,329 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 15:24:24,329 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:24,329 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 15:24:24,329 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 15:24:24,330 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 15:24:24,330 INFO L87 Difference]: Start difference. First operand 74 states and 91 transitions. Second operand 6 states. [2018-01-24 15:24:24,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:24,478 INFO L93 Difference]: Finished difference Result 100 states and 124 transitions. [2018-01-24 15:24:24,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 15:24:24,479 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 23 [2018-01-24 15:24:24,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:24,480 INFO L225 Difference]: With dead ends: 100 [2018-01-24 15:24:24,480 INFO L226 Difference]: Without dead ends: 96 [2018-01-24 15:24:24,480 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 85 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 15:24:24,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-01-24 15:24:24,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 88. [2018-01-24 15:24:24,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-01-24 15:24:24,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 110 transitions. [2018-01-24 15:24:24,488 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 110 transitions. Word has length 23 [2018-01-24 15:24:24,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:24,488 INFO L432 AbstractCegarLoop]: Abstraction has 88 states and 110 transitions. [2018-01-24 15:24:24,488 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 15:24:24,488 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 110 transitions. [2018-01-24 15:24:24,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-01-24 15:24:24,490 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:24,490 INFO L322 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:24,490 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:24,490 INFO L82 PathProgramCache]: Analyzing trace with hash -1714228867, now seen corresponding path program 4 times [2018-01-24 15:24:24,491 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:24,491 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:24,491 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:24,491 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:24,491 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:24,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:24,503 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:24,581 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:24,581 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:24,581 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:24,581 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:24,582 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:24,582 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:24,582 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:24,587 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:24:24,588 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:24:24,605 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:24,607 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:24,614 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:24,614 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:24,685 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:24,705 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:24,705 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:24,708 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:24:24,708 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:24:24,726 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:24,729 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:24,736 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:24,736 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:24,748 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:24,749 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:24,750 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 15:24:24,750 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:24,751 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 15:24:24,751 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 15:24:24,751 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 15:24:24,751 INFO L87 Difference]: Start difference. First operand 88 states and 110 transitions. Second operand 7 states. [2018-01-24 15:24:24,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:24,936 INFO L93 Difference]: Finished difference Result 115 states and 144 transitions. [2018-01-24 15:24:24,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 15:24:24,937 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 28 [2018-01-24 15:24:24,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:24,938 INFO L225 Difference]: With dead ends: 115 [2018-01-24 15:24:24,938 INFO L226 Difference]: Without dead ends: 111 [2018-01-24 15:24:24,939 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 116 GetRequests, 104 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 15:24:24,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-01-24 15:24:24,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 102. [2018-01-24 15:24:24,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-01-24 15:24:24,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 129 transitions. [2018-01-24 15:24:24,956 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 129 transitions. Word has length 28 [2018-01-24 15:24:24,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:24,956 INFO L432 AbstractCegarLoop]: Abstraction has 102 states and 129 transitions. [2018-01-24 15:24:24,956 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 15:24:24,957 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 129 transitions. [2018-01-24 15:24:24,958 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-01-24 15:24:24,958 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:24,958 INFO L322 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:24,958 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:24,959 INFO L82 PathProgramCache]: Analyzing trace with hash -771406513, now seen corresponding path program 5 times [2018-01-24 15:24:24,959 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:24,960 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:24,960 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:24,960 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:24,960 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:24,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:24,974 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:25,084 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:25,084 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:25,084 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:25,085 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:25,085 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:25,085 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:25,085 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:25,091 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:24:25,091 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:25,094 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:25,095 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:25,097 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:25,098 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:25,099 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:25,101 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:25,101 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:25,103 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:25,113 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:25,113 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:25,181 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:25,202 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:25,202 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:25,207 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:24:25,207 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:25,211 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:25,214 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:25,219 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:25,229 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:25,239 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:25,253 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:25,260 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:25,264 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:25,277 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:25,277 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:25,305 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:25,307 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:25,307 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 15:24:25,307 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:25,308 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 15:24:25,308 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 15:24:25,308 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 15:24:25,308 INFO L87 Difference]: Start difference. First operand 102 states and 129 transitions. Second operand 8 states. [2018-01-24 15:24:25,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:25,628 INFO L93 Difference]: Finished difference Result 130 states and 164 transitions. [2018-01-24 15:24:25,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 15:24:25,628 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 33 [2018-01-24 15:24:25,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:25,629 INFO L225 Difference]: With dead ends: 130 [2018-01-24 15:24:25,629 INFO L226 Difference]: Without dead ends: 126 [2018-01-24 15:24:25,630 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 123 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 15:24:25,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-01-24 15:24:25,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 116. [2018-01-24 15:24:25,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 116 states. [2018-01-24 15:24:25,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 148 transitions. [2018-01-24 15:24:25,640 INFO L78 Accepts]: Start accepts. Automaton has 116 states and 148 transitions. Word has length 33 [2018-01-24 15:24:25,640 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:25,640 INFO L432 AbstractCegarLoop]: Abstraction has 116 states and 148 transitions. [2018-01-24 15:24:25,640 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 15:24:25,640 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 148 transitions. [2018-01-24 15:24:25,641 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-01-24 15:24:25,642 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:25,642 INFO L322 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 6, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:25,642 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:25,642 INFO L82 PathProgramCache]: Analyzing trace with hash -240614211, now seen corresponding path program 6 times [2018-01-24 15:24:25,642 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:25,643 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:25,643 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:25,643 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:25,643 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:25,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:25,656 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:25,748 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:25,749 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:25,749 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:25,749 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:25,749 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:25,749 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:25,749 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:25,760 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:24:25,760 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:24:25,764 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:25,765 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:25,767 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:25,768 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:25,770 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:25,772 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:25,774 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:25,774 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:25,776 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:25,797 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:25,797 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:25,959 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:25,979 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:25,979 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:25,985 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:24:25,985 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:24:25,989 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:25,992 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:25,997 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:26,002 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:26,008 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:26,015 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:26,023 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:26,030 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:26,033 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:26,040 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:26,040 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:26,047 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:26,048 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:26,048 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 15:24:26,048 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:26,048 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 15:24:26,049 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 15:24:26,049 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 15:24:26,049 INFO L87 Difference]: Start difference. First operand 116 states and 148 transitions. Second operand 9 states. [2018-01-24 15:24:26,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:26,344 INFO L93 Difference]: Finished difference Result 145 states and 184 transitions. [2018-01-24 15:24:26,344 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 15:24:26,344 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 38 [2018-01-24 15:24:26,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:26,346 INFO L225 Difference]: With dead ends: 145 [2018-01-24 15:24:26,346 INFO L226 Difference]: Without dead ends: 141 [2018-01-24 15:24:26,347 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 142 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 15:24:26,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-01-24 15:24:26,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 130. [2018-01-24 15:24:26,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-01-24 15:24:26,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 167 transitions. [2018-01-24 15:24:26,360 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 167 transitions. Word has length 38 [2018-01-24 15:24:26,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:26,361 INFO L432 AbstractCegarLoop]: Abstraction has 130 states and 167 transitions. [2018-01-24 15:24:26,361 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 15:24:26,361 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 167 transitions. [2018-01-24 15:24:26,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-01-24 15:24:26,363 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:26,363 INFO L322 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 7, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:26,363 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:26,363 INFO L82 PathProgramCache]: Analyzing trace with hash 1558821391, now seen corresponding path program 7 times [2018-01-24 15:24:26,364 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:26,364 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:26,365 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:26,365 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:26,365 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:26,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:26,379 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:26,487 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:26,488 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:26,488 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:26,488 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:26,488 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:26,488 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:26,488 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:26,500 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:24:26,500 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:24:26,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:26,512 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:26,523 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:26,523 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:26,618 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:26,638 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:26,638 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:26,641 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:24:26,641 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:24:26,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:26,659 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:26,666 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:26,667 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:26,679 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:26,681 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:26,681 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 15:24:26,681 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:26,681 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 15:24:26,681 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 15:24:26,682 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 15:24:26,682 INFO L87 Difference]: Start difference. First operand 130 states and 167 transitions. Second operand 10 states. [2018-01-24 15:24:27,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:27,042 INFO L93 Difference]: Finished difference Result 160 states and 204 transitions. [2018-01-24 15:24:27,042 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 15:24:27,042 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 43 [2018-01-24 15:24:27,042 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:27,043 INFO L225 Difference]: With dead ends: 160 [2018-01-24 15:24:27,043 INFO L226 Difference]: Without dead ends: 156 [2018-01-24 15:24:27,044 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 179 GetRequests, 161 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 15:24:27,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-01-24 15:24:27,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 144. [2018-01-24 15:24:27,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-01-24 15:24:27,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 186 transitions. [2018-01-24 15:24:27,055 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 186 transitions. Word has length 43 [2018-01-24 15:24:27,056 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:27,056 INFO L432 AbstractCegarLoop]: Abstraction has 144 states and 186 transitions. [2018-01-24 15:24:27,056 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 15:24:27,056 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 186 transitions. [2018-01-24 15:24:27,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-01-24 15:24:27,058 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:27,058 INFO L322 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 8, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:27,058 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:27,059 INFO L82 PathProgramCache]: Analyzing trace with hash -821098499, now seen corresponding path program 8 times [2018-01-24 15:24:27,059 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:27,059 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:27,060 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:24:27,060 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:27,060 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:27,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:27,071 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:27,173 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:27,173 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:27,173 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:27,173 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:27,173 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:27,173 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:27,174 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:27,178 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:24:27,179 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:27,181 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:27,185 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:27,186 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:27,187 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:27,196 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:27,196 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:27,320 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:27,340 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:27,340 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:27,343 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:24:27,343 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:27,346 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:27,353 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:27,368 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:27,373 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:27,382 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:27,382 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:27,392 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:27,394 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:27,395 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 15:24:27,395 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:27,395 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 15:24:27,395 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 15:24:27,395 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 15:24:27,396 INFO L87 Difference]: Start difference. First operand 144 states and 186 transitions. Second operand 11 states. [2018-01-24 15:24:28,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:28,115 INFO L93 Difference]: Finished difference Result 175 states and 224 transitions. [2018-01-24 15:24:28,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 15:24:28,116 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 48 [2018-01-24 15:24:28,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:28,117 INFO L225 Difference]: With dead ends: 175 [2018-01-24 15:24:28,118 INFO L226 Difference]: Without dead ends: 171 [2018-01-24 15:24:28,118 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 200 GetRequests, 180 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 15:24:28,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-01-24 15:24:28,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 158. [2018-01-24 15:24:28,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-01-24 15:24:28,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 205 transitions. [2018-01-24 15:24:28,134 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 205 transitions. Word has length 48 [2018-01-24 15:24:28,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:28,135 INFO L432 AbstractCegarLoop]: Abstraction has 158 states and 205 transitions. [2018-01-24 15:24:28,135 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 15:24:28,135 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 205 transitions. [2018-01-24 15:24:28,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-01-24 15:24:28,136 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:28,137 INFO L322 BasicCegarLoop]: trace histogram [10, 10, 9, 9, 9, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:28,137 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:28,137 INFO L82 PathProgramCache]: Analyzing trace with hash -413974833, now seen corresponding path program 9 times [2018-01-24 15:24:28,137 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:28,138 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:28,138 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:28,138 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:28,138 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:28,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:28,150 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:28,346 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:28,347 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:28,347 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:28,347 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:28,347 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:28,347 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:28,347 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:28,358 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:24:28,358 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:24:28,363 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,364 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,366 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,368 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,369 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,371 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,374 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,376 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,378 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,381 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,382 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:28,385 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:28,401 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:28,402 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:28,569 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:28,589 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:28,590 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:28,592 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:24:28,593 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:24:28,596 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,598 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,603 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,608 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,615 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,623 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,631 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,641 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,653 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,665 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:28,675 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:28,678 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:28,689 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:28,689 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:28,707 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:28,708 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:28,708 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 15:24:28,708 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:28,709 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 15:24:28,709 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 15:24:28,709 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 15:24:28,710 INFO L87 Difference]: Start difference. First operand 158 states and 205 transitions. Second operand 12 states. [2018-01-24 15:24:29,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:29,214 INFO L93 Difference]: Finished difference Result 190 states and 244 transitions. [2018-01-24 15:24:29,231 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 15:24:29,231 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 53 [2018-01-24 15:24:29,231 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:29,232 INFO L225 Difference]: With dead ends: 190 [2018-01-24 15:24:29,232 INFO L226 Difference]: Without dead ends: 186 [2018-01-24 15:24:29,233 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 221 GetRequests, 199 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 15:24:29,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-01-24 15:24:29,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 172. [2018-01-24 15:24:29,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-01-24 15:24:29,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 224 transitions. [2018-01-24 15:24:29,245 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 224 transitions. Word has length 53 [2018-01-24 15:24:29,246 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:29,246 INFO L432 AbstractCegarLoop]: Abstraction has 172 states and 224 transitions. [2018-01-24 15:24:29,246 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 15:24:29,246 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 224 transitions. [2018-01-24 15:24:29,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-01-24 15:24:29,248 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:29,248 INFO L322 BasicCegarLoop]: trace histogram [11, 11, 10, 10, 10, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:29,248 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:29,248 INFO L82 PathProgramCache]: Analyzing trace with hash -442860739, now seen corresponding path program 10 times [2018-01-24 15:24:29,248 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:29,249 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:29,249 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:29,249 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:29,249 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:29,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:29,264 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:29,447 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:29,448 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:29,448 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:29,448 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:29,448 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:29,448 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:29,448 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:29,453 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:24:29,453 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:24:29,475 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:29,477 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:29,496 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:29,496 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:29,671 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:29,691 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:29,691 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:29,694 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:24:29,694 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:24:29,725 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:29,728 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:29,737 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:29,737 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:29,747 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:29,748 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:29,749 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 15:24:29,749 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:29,749 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 15:24:29,749 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 15:24:29,749 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 15:24:29,750 INFO L87 Difference]: Start difference. First operand 172 states and 224 transitions. Second operand 13 states. [2018-01-24 15:24:30,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:30,278 INFO L93 Difference]: Finished difference Result 205 states and 264 transitions. [2018-01-24 15:24:30,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 15:24:30,278 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 58 [2018-01-24 15:24:30,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:30,279 INFO L225 Difference]: With dead ends: 205 [2018-01-24 15:24:30,279 INFO L226 Difference]: Without dead ends: 201 [2018-01-24 15:24:30,280 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 242 GetRequests, 218 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 15:24:30,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2018-01-24 15:24:30,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 186. [2018-01-24 15:24:30,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-01-24 15:24:30,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 243 transitions. [2018-01-24 15:24:30,289 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 243 transitions. Word has length 58 [2018-01-24 15:24:30,289 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:30,289 INFO L432 AbstractCegarLoop]: Abstraction has 186 states and 243 transitions. [2018-01-24 15:24:30,289 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 15:24:30,289 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 243 transitions. [2018-01-24 15:24:30,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-01-24 15:24:30,291 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:30,291 INFO L322 BasicCegarLoop]: trace histogram [12, 12, 11, 11, 11, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:30,291 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:30,291 INFO L82 PathProgramCache]: Analyzing trace with hash -634530929, now seen corresponding path program 11 times [2018-01-24 15:24:30,291 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:30,292 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:30,292 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:30,292 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:30,292 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:30,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:30,302 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:30,432 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:30,433 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:30,433 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:30,433 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:30,433 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:30,433 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:30,433 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:30,438 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:24:30,438 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:30,441 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,442 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,444 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,445 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,446 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,448 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,449 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,450 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,452 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,453 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,455 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,457 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,457 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:30,459 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:30,472 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:30,472 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:30,640 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:30,659 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:30,659 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:30,662 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:24:30,662 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:30,665 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,668 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,672 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,678 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,684 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,692 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,700 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,710 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,720 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,732 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,745 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,760 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:30,770 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:30,773 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:30,786 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:30,786 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:30,802 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:30,804 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:30,804 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 15:24:30,804 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:30,805 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 15:24:30,805 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 15:24:30,805 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 15:24:30,805 INFO L87 Difference]: Start difference. First operand 186 states and 243 transitions. Second operand 14 states. [2018-01-24 15:24:31,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:31,430 INFO L93 Difference]: Finished difference Result 220 states and 284 transitions. [2018-01-24 15:24:31,430 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 15:24:31,430 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 63 [2018-01-24 15:24:31,430 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:31,431 INFO L225 Difference]: With dead ends: 220 [2018-01-24 15:24:31,431 INFO L226 Difference]: Without dead ends: 216 [2018-01-24 15:24:31,432 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 263 GetRequests, 237 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 15:24:31,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-01-24 15:24:31,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 200. [2018-01-24 15:24:31,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 200 states. [2018-01-24 15:24:31,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200 states to 200 states and 262 transitions. [2018-01-24 15:24:31,443 INFO L78 Accepts]: Start accepts. Automaton has 200 states and 262 transitions. Word has length 63 [2018-01-24 15:24:31,443 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:31,443 INFO L432 AbstractCegarLoop]: Abstraction has 200 states and 262 transitions. [2018-01-24 15:24:31,443 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 15:24:31,443 INFO L276 IsEmpty]: Start isEmpty. Operand 200 states and 262 transitions. [2018-01-24 15:24:31,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-01-24 15:24:31,445 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:31,445 INFO L322 BasicCegarLoop]: trace histogram [13, 13, 12, 12, 12, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:31,445 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:31,446 INFO L82 PathProgramCache]: Analyzing trace with hash 2145312381, now seen corresponding path program 12 times [2018-01-24 15:24:31,446 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:31,447 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:31,447 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:31,447 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:31,447 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:31,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:31,458 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:31,617 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:31,617 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:31,617 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:31,617 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:31,617 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:31,617 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:31,617 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:31,622 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:24:31,622 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:24:31,626 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,627 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,628 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,629 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,630 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,631 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,632 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,633 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,635 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,636 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,638 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,639 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,641 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,642 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:31,643 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:31,657 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:31,658 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:31,862 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:31,881 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:31,882 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:31,884 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:24:31,885 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:24:31,888 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,890 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,894 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,900 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,906 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,913 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,921 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,931 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,941 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,953 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,966 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,979 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:31,994 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:32,005 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:32,009 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:32,025 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:32,025 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:32,040 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:32,041 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:32,041 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 27 [2018-01-24 15:24:32,041 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:32,041 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 15:24:32,042 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 15:24:32,042 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 15:24:32,042 INFO L87 Difference]: Start difference. First operand 200 states and 262 transitions. Second operand 15 states. [2018-01-24 15:24:32,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:32,768 INFO L93 Difference]: Finished difference Result 235 states and 304 transitions. [2018-01-24 15:24:32,768 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 15:24:32,768 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2018-01-24 15:24:32,768 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:32,769 INFO L225 Difference]: With dead ends: 235 [2018-01-24 15:24:32,769 INFO L226 Difference]: Without dead ends: 231 [2018-01-24 15:24:32,770 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 284 GetRequests, 256 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 15:24:32,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states. [2018-01-24 15:24:32,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 214. [2018-01-24 15:24:32,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-01-24 15:24:32,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 281 transitions. [2018-01-24 15:24:32,779 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 281 transitions. Word has length 68 [2018-01-24 15:24:32,779 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:32,779 INFO L432 AbstractCegarLoop]: Abstraction has 214 states and 281 transitions. [2018-01-24 15:24:32,779 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 15:24:32,779 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 281 transitions. [2018-01-24 15:24:32,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-01-24 15:24:32,780 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:32,780 INFO L322 BasicCegarLoop]: trace histogram [14, 14, 13, 13, 13, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:32,780 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:32,780 INFO L82 PathProgramCache]: Analyzing trace with hash 1734703183, now seen corresponding path program 13 times [2018-01-24 15:24:32,780 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:32,781 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:32,781 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:32,781 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:32,781 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:32,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:32,791 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:32,956 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:32,956 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:32,956 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:32,956 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:32,956 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:32,956 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:32,956 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:32,961 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:24:32,961 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:24:32,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:32,974 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:33,023 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:33,023 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:33,347 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:33,368 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:33,368 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:33,374 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:24:33,374 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:24:33,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:33,411 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:33,427 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:33,427 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:33,457 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:33,458 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:33,458 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 29 [2018-01-24 15:24:33,459 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:33,459 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 15:24:33,459 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 15:24:33,460 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 15:24:33,460 INFO L87 Difference]: Start difference. First operand 214 states and 281 transitions. Second operand 16 states. [2018-01-24 15:24:34,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:34,297 INFO L93 Difference]: Finished difference Result 250 states and 324 transitions. [2018-01-24 15:24:34,331 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 15:24:34,331 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 73 [2018-01-24 15:24:34,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:34,333 INFO L225 Difference]: With dead ends: 250 [2018-01-24 15:24:34,333 INFO L226 Difference]: Without dead ends: 246 [2018-01-24 15:24:34,333 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 305 GetRequests, 275 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 15:24:34,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-01-24 15:24:34,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 228. [2018-01-24 15:24:34,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-01-24 15:24:34,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 300 transitions. [2018-01-24 15:24:34,343 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 300 transitions. Word has length 73 [2018-01-24 15:24:34,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:34,343 INFO L432 AbstractCegarLoop]: Abstraction has 228 states and 300 transitions. [2018-01-24 15:24:34,343 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 15:24:34,344 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 300 transitions. [2018-01-24 15:24:34,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-24 15:24:34,344 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:34,345 INFO L322 BasicCegarLoop]: trace histogram [15, 15, 14, 14, 14, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:34,345 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:34,345 INFO L82 PathProgramCache]: Analyzing trace with hash -1083166275, now seen corresponding path program 14 times [2018-01-24 15:24:34,345 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:34,345 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:34,346 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:24:34,346 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:34,346 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:34,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:34,358 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:34,813 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:34,813 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:34,813 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:34,813 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:34,813 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:34,814 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:34,814 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:34,818 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:24:34,819 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:34,822 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:34,827 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:34,828 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:34,830 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:34,842 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:34,842 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:35,086 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:35,106 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:35,106 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:35,109 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:24:35,109 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:35,115 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:35,125 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:35,139 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:35,143 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:35,156 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:35,156 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:35,170 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:35,171 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:35,171 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 31 [2018-01-24 15:24:35,171 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:35,171 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 15:24:35,171 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 15:24:35,172 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 15:24:35,172 INFO L87 Difference]: Start difference. First operand 228 states and 300 transitions. Second operand 17 states. [2018-01-24 15:24:36,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:36,093 INFO L93 Difference]: Finished difference Result 265 states and 344 transitions. [2018-01-24 15:24:36,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 15:24:36,093 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 78 [2018-01-24 15:24:36,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:36,095 INFO L225 Difference]: With dead ends: 265 [2018-01-24 15:24:36,095 INFO L226 Difference]: Without dead ends: 261 [2018-01-24 15:24:36,096 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 326 GetRequests, 294 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 15:24:36,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 261 states. [2018-01-24 15:24:36,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 261 to 242. [2018-01-24 15:24:36,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 242 states. [2018-01-24 15:24:36,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242 states to 242 states and 319 transitions. [2018-01-24 15:24:36,109 INFO L78 Accepts]: Start accepts. Automaton has 242 states and 319 transitions. Word has length 78 [2018-01-24 15:24:36,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:36,110 INFO L432 AbstractCegarLoop]: Abstraction has 242 states and 319 transitions. [2018-01-24 15:24:36,110 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 15:24:36,110 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 319 transitions. [2018-01-24 15:24:36,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-01-24 15:24:36,112 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:36,112 INFO L322 BasicCegarLoop]: trace histogram [16, 16, 15, 15, 15, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:36,112 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:36,112 INFO L82 PathProgramCache]: Analyzing trace with hash 1239821583, now seen corresponding path program 15 times [2018-01-24 15:24:36,112 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:36,113 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:36,113 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:36,113 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:36,113 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:36,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:36,127 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:36,372 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:36,372 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:36,372 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:36,373 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:36,373 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:36,373 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:36,373 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:36,378 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:24:36,378 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:24:36,382 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,383 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,384 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,385 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,386 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,388 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,389 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,391 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,392 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,394 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,395 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,397 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,399 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,401 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,403 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,405 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,406 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:36,408 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:36,428 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:36,428 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:36,794 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:36,814 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:36,814 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:36,817 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:24:36,817 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:24:36,821 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,823 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,827 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,833 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,839 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,846 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,854 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,863 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,873 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,884 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,897 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,910 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,925 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,940 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,957 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,974 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:36,995 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:36,999 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:37,012 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:37,012 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:37,033 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:37,034 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:37,034 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 33 [2018-01-24 15:24:37,034 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:37,035 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 15:24:37,035 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 15:24:37,035 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 15:24:37,035 INFO L87 Difference]: Start difference. First operand 242 states and 319 transitions. Second operand 18 states. [2018-01-24 15:24:38,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:38,122 INFO L93 Difference]: Finished difference Result 280 states and 364 transitions. [2018-01-24 15:24:38,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 15:24:38,122 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 83 [2018-01-24 15:24:38,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:38,123 INFO L225 Difference]: With dead ends: 280 [2018-01-24 15:24:38,123 INFO L226 Difference]: Without dead ends: 276 [2018-01-24 15:24:38,124 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 347 GetRequests, 313 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 15:24:38,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states. [2018-01-24 15:24:38,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 256. [2018-01-24 15:24:38,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 256 states. [2018-01-24 15:24:38,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 256 states to 256 states and 338 transitions. [2018-01-24 15:24:38,132 INFO L78 Accepts]: Start accepts. Automaton has 256 states and 338 transitions. Word has length 83 [2018-01-24 15:24:38,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:38,133 INFO L432 AbstractCegarLoop]: Abstraction has 256 states and 338 transitions. [2018-01-24 15:24:38,133 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 15:24:38,133 INFO L276 IsEmpty]: Start isEmpty. Operand 256 states and 338 transitions. [2018-01-24 15:24:38,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-01-24 15:24:38,134 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:38,134 INFO L322 BasicCegarLoop]: trace histogram [17, 17, 16, 16, 16, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:38,134 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:38,135 INFO L82 PathProgramCache]: Analyzing trace with hash -589138691, now seen corresponding path program 16 times [2018-01-24 15:24:38,135 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:38,135 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:38,135 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:38,136 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:38,136 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:38,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:38,147 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:38,668 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:38,669 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:38,669 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:38,669 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:38,669 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:38,669 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:38,669 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:38,675 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:24:38,675 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:24:38,696 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:38,699 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:38,723 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:38,724 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:39,123 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:39,142 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:39,142 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:39,145 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:24:39,145 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:24:39,194 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:39,198 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:39,212 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:39,213 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:39,229 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:39,230 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:39,230 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 35 [2018-01-24 15:24:39,230 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:39,231 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 15:24:39,231 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 15:24:39,231 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 15:24:39,231 INFO L87 Difference]: Start difference. First operand 256 states and 338 transitions. Second operand 19 states. [2018-01-24 15:24:40,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:40,429 INFO L93 Difference]: Finished difference Result 295 states and 384 transitions. [2018-01-24 15:24:40,430 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 15:24:40,430 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 88 [2018-01-24 15:24:40,430 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:40,432 INFO L225 Difference]: With dead ends: 295 [2018-01-24 15:24:40,432 INFO L226 Difference]: Without dead ends: 291 [2018-01-24 15:24:40,432 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 368 GetRequests, 332 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 15:24:40,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states. [2018-01-24 15:24:40,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 270. [2018-01-24 15:24:40,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2018-01-24 15:24:40,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 357 transitions. [2018-01-24 15:24:40,447 INFO L78 Accepts]: Start accepts. Automaton has 270 states and 357 transitions. Word has length 88 [2018-01-24 15:24:40,447 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:40,447 INFO L432 AbstractCegarLoop]: Abstraction has 270 states and 357 transitions. [2018-01-24 15:24:40,448 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 15:24:40,448 INFO L276 IsEmpty]: Start isEmpty. Operand 270 states and 357 transitions. [2018-01-24 15:24:40,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-01-24 15:24:40,450 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:40,450 INFO L322 BasicCegarLoop]: trace histogram [18, 18, 17, 17, 17, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:40,450 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:40,451 INFO L82 PathProgramCache]: Analyzing trace with hash -2053377585, now seen corresponding path program 17 times [2018-01-24 15:24:40,451 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:40,452 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:40,452 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:40,452 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:40,452 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:40,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:40,469 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:40,785 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:40,785 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:40,785 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:40,786 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:40,786 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:40,786 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:40,786 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:40,791 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:24:40,791 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:40,795 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,796 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,797 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,798 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,799 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,800 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,802 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,803 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,804 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,806 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,808 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,809 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,811 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,813 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,815 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,817 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,819 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,822 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:40,822 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:40,824 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:40,840 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:40,840 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:41,181 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:41,201 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:41,201 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:41,204 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:24:41,204 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:41,208 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,210 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,215 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,221 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,227 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,235 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,244 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,254 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,265 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,277 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,290 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,305 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,320 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,336 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,359 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,378 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,398 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,419 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:41,438 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:41,443 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:41,463 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:41,464 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:41,482 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:41,484 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:41,484 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 37 [2018-01-24 15:24:41,484 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:41,484 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 15:24:41,485 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 15:24:41,485 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 15:24:41,485 INFO L87 Difference]: Start difference. First operand 270 states and 357 transitions. Second operand 20 states. [2018-01-24 15:24:42,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:42,813 INFO L93 Difference]: Finished difference Result 310 states and 404 transitions. [2018-01-24 15:24:42,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 15:24:42,814 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 93 [2018-01-24 15:24:42,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:42,816 INFO L225 Difference]: With dead ends: 310 [2018-01-24 15:24:42,816 INFO L226 Difference]: Without dead ends: 306 [2018-01-24 15:24:42,817 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 389 GetRequests, 351 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 15:24:42,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306 states. [2018-01-24 15:24:42,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306 to 284. [2018-01-24 15:24:42,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 284 states. [2018-01-24 15:24:42,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 376 transitions. [2018-01-24 15:24:42,831 INFO L78 Accepts]: Start accepts. Automaton has 284 states and 376 transitions. Word has length 93 [2018-01-24 15:24:42,831 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:42,831 INFO L432 AbstractCegarLoop]: Abstraction has 284 states and 376 transitions. [2018-01-24 15:24:42,831 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 15:24:42,831 INFO L276 IsEmpty]: Start isEmpty. Operand 284 states and 376 transitions. [2018-01-24 15:24:42,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-01-24 15:24:42,833 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:42,833 INFO L322 BasicCegarLoop]: trace histogram [19, 19, 18, 18, 18, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:42,834 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:42,834 INFO L82 PathProgramCache]: Analyzing trace with hash 1741269053, now seen corresponding path program 18 times [2018-01-24 15:24:42,834 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:42,835 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:42,835 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:42,835 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:42,835 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:42,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:42,850 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:43,124 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:43,124 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:43,124 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:43,124 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:43,124 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:43,124 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:43,124 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:43,129 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:24:43,129 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:24:43,133 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,134 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,135 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,137 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,138 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,140 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,142 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,144 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,146 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,148 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,150 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,153 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,156 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,159 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,162 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,165 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,168 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,171 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,175 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,175 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:43,178 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:43,194 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:43,194 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:43,738 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:43,758 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:43,758 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:43,761 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:24:43,761 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:24:43,767 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,769 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,774 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,779 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,786 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,793 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,802 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,811 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,822 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,834 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,848 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,862 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,878 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,894 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,912 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,938 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,959 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:43,981 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:44,002 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:24:44,027 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:44,032 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:44,048 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:44,048 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:44,073 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:44,075 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:44,075 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 39 [2018-01-24 15:24:44,075 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:44,075 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 15:24:44,075 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 15:24:44,076 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 15:24:44,076 INFO L87 Difference]: Start difference. First operand 284 states and 376 transitions. Second operand 21 states. [2018-01-24 15:24:45,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:45,758 INFO L93 Difference]: Finished difference Result 325 states and 424 transitions. [2018-01-24 15:24:45,787 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 15:24:45,787 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 98 [2018-01-24 15:24:45,787 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:45,789 INFO L225 Difference]: With dead ends: 325 [2018-01-24 15:24:45,789 INFO L226 Difference]: Without dead ends: 321 [2018-01-24 15:24:45,790 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 410 GetRequests, 370 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 15:24:45,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2018-01-24 15:24:45,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 298. [2018-01-24 15:24:45,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 298 states. [2018-01-24 15:24:45,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 395 transitions. [2018-01-24 15:24:45,799 INFO L78 Accepts]: Start accepts. Automaton has 298 states and 395 transitions. Word has length 98 [2018-01-24 15:24:45,799 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:45,799 INFO L432 AbstractCegarLoop]: Abstraction has 298 states and 395 transitions. [2018-01-24 15:24:45,799 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 15:24:45,799 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 395 transitions. [2018-01-24 15:24:45,801 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2018-01-24 15:24:45,801 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:45,801 INFO L322 BasicCegarLoop]: trace histogram [20, 20, 19, 19, 19, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:45,801 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:45,801 INFO L82 PathProgramCache]: Analyzing trace with hash 661833359, now seen corresponding path program 19 times [2018-01-24 15:24:45,801 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:45,802 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:45,802 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:45,802 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:45,802 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:45,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:45,813 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:46,102 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:46,103 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:46,103 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:46,103 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:46,103 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:46,103 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:46,103 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:46,108 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:24:46,108 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:24:46,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:46,121 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:46,139 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:46,139 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:46,584 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:46,603 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:46,603 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:46,606 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:24:46,606 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:24:46,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:46,647 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:46,667 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:46,667 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:46,687 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:46,688 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:46,689 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 41 [2018-01-24 15:24:46,689 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:46,689 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 15:24:46,689 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 15:24:46,690 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 15:24:46,690 INFO L87 Difference]: Start difference. First operand 298 states and 395 transitions. Second operand 22 states. [2018-01-24 15:24:48,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:48,314 INFO L93 Difference]: Finished difference Result 340 states and 444 transitions. [2018-01-24 15:24:48,314 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 15:24:48,314 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 103 [2018-01-24 15:24:48,314 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:48,316 INFO L225 Difference]: With dead ends: 340 [2018-01-24 15:24:48,316 INFO L226 Difference]: Without dead ends: 336 [2018-01-24 15:24:48,317 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 431 GetRequests, 389 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 15:24:48,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 336 states. [2018-01-24 15:24:48,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 336 to 312. [2018-01-24 15:24:48,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 312 states. [2018-01-24 15:24:48,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312 states to 312 states and 414 transitions. [2018-01-24 15:24:48,331 INFO L78 Accepts]: Start accepts. Automaton has 312 states and 414 transitions. Word has length 103 [2018-01-24 15:24:48,332 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:48,332 INFO L432 AbstractCegarLoop]: Abstraction has 312 states and 414 transitions. [2018-01-24 15:24:48,332 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 15:24:48,332 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 414 transitions. [2018-01-24 15:24:48,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-01-24 15:24:48,334 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:48,335 INFO L322 BasicCegarLoop]: trace histogram [21, 21, 20, 20, 20, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:48,335 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:48,335 INFO L82 PathProgramCache]: Analyzing trace with hash -2034644099, now seen corresponding path program 20 times [2018-01-24 15:24:48,335 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:48,336 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:48,336 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:24:48,336 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:48,336 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:48,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:48,355 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:49,061 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:49,062 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:49,062 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:49,062 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:49,062 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:49,062 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:49,062 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:49,067 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:24:49,067 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:49,070 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:49,077 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:49,080 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:49,082 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:49,100 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:49,100 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:49,572 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:49,609 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:49,609 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:49,612 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:24:49,612 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:49,618 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:49,632 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:49,652 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:49,658 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:49,677 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:49,677 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:49,700 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:49,702 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:49,703 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 43 [2018-01-24 15:24:49,703 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:49,703 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 15:24:49,703 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 15:24:49,704 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 15:24:49,704 INFO L87 Difference]: Start difference. First operand 312 states and 414 transitions. Second operand 23 states. [2018-01-24 15:24:51,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:51,565 INFO L93 Difference]: Finished difference Result 355 states and 464 transitions. [2018-01-24 15:24:51,587 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 15:24:51,588 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 108 [2018-01-24 15:24:51,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:51,589 INFO L225 Difference]: With dead ends: 355 [2018-01-24 15:24:51,590 INFO L226 Difference]: Without dead ends: 351 [2018-01-24 15:24:51,590 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 452 GetRequests, 408 SyntacticMatches, 2 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 15:24:51,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 351 states. [2018-01-24 15:24:51,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 351 to 326. [2018-01-24 15:24:51,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 326 states. [2018-01-24 15:24:51,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 326 states to 326 states and 433 transitions. [2018-01-24 15:24:51,599 INFO L78 Accepts]: Start accepts. Automaton has 326 states and 433 transitions. Word has length 108 [2018-01-24 15:24:51,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:51,599 INFO L432 AbstractCegarLoop]: Abstraction has 326 states and 433 transitions. [2018-01-24 15:24:51,599 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 15:24:51,600 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 433 transitions. [2018-01-24 15:24:51,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-01-24 15:24:51,601 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:51,601 INFO L322 BasicCegarLoop]: trace histogram [22, 22, 21, 21, 21, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:51,601 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:51,601 INFO L82 PathProgramCache]: Analyzing trace with hash 89566031, now seen corresponding path program 21 times [2018-01-24 15:24:51,601 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:51,602 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:51,602 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:51,602 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:51,602 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:51,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:51,616 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:51,933 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:51,934 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:51,934 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:51,934 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:51,934 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:51,934 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:51,934 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:51,939 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:24:51,939 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:24:51,943 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,944 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,945 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,946 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,947 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,948 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,950 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,951 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,953 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,954 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,956 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,958 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,960 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,962 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,964 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,966 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,968 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,970 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,973 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,975 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,978 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,980 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:51,981 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:51,983 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:52,003 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:52,003 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:52,496 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:52,515 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:52,515 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:52,518 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:24:52,518 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:24:52,523 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,525 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,529 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,534 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,540 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,548 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,556 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,566 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,576 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,588 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,601 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,615 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,631 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,646 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,664 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,682 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,709 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,730 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,752 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,774 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,806 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,831 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:24:52,851 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:52,865 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:52,898 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:52,898 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:52,949 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:52,951 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:52,951 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 45 [2018-01-24 15:24:52,951 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:52,952 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 15:24:52,952 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 15:24:52,953 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 15:24:52,953 INFO L87 Difference]: Start difference. First operand 326 states and 433 transitions. Second operand 24 states. [2018-01-24 15:24:54,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:54,868 INFO L93 Difference]: Finished difference Result 370 states and 484 transitions. [2018-01-24 15:24:54,869 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 15:24:54,869 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 113 [2018-01-24 15:24:54,869 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:54,871 INFO L225 Difference]: With dead ends: 370 [2018-01-24 15:24:54,871 INFO L226 Difference]: Without dead ends: 366 [2018-01-24 15:24:54,871 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 473 GetRequests, 427 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 15:24:54,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states. [2018-01-24 15:24:54,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 340. [2018-01-24 15:24:54,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 340 states. [2018-01-24 15:24:54,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 452 transitions. [2018-01-24 15:24:54,881 INFO L78 Accepts]: Start accepts. Automaton has 340 states and 452 transitions. Word has length 113 [2018-01-24 15:24:54,881 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:54,881 INFO L432 AbstractCegarLoop]: Abstraction has 340 states and 452 transitions. [2018-01-24 15:24:54,881 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 15:24:54,881 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 452 transitions. [2018-01-24 15:24:54,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-01-24 15:24:54,882 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:54,882 INFO L322 BasicCegarLoop]: trace histogram [23, 23, 22, 22, 22, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:54,882 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:54,883 INFO L82 PathProgramCache]: Analyzing trace with hash 927391421, now seen corresponding path program 22 times [2018-01-24 15:24:54,883 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:54,883 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:54,883 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:54,883 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:54,883 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:54,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:54,893 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:55,456 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:55,457 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:55,457 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:55,457 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:55,457 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:55,457 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:55,457 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:55,462 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:24:55,462 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:24:55,487 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:55,489 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:55,520 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:55,521 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:56,053 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:56,073 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:56,073 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:56,076 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:24:56,076 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:24:56,144 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:56,149 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:56,179 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:56,179 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:56,204 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:56,205 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:56,205 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 47 [2018-01-24 15:24:56,205 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:56,205 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-24 15:24:56,206 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-24 15:24:56,206 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 15:24:56,206 INFO L87 Difference]: Start difference. First operand 340 states and 452 transitions. Second operand 25 states. [2018-01-24 15:24:58,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:24:58,278 INFO L93 Difference]: Finished difference Result 385 states and 504 transitions. [2018-01-24 15:24:58,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 15:24:58,278 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 118 [2018-01-24 15:24:58,279 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:24:58,280 INFO L225 Difference]: With dead ends: 385 [2018-01-24 15:24:58,280 INFO L226 Difference]: Without dead ends: 381 [2018-01-24 15:24:58,281 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 494 GetRequests, 446 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 15:24:58,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 381 states. [2018-01-24 15:24:58,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 381 to 354. [2018-01-24 15:24:58,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354 states. [2018-01-24 15:24:58,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354 states to 354 states and 471 transitions. [2018-01-24 15:24:58,293 INFO L78 Accepts]: Start accepts. Automaton has 354 states and 471 transitions. Word has length 118 [2018-01-24 15:24:58,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:24:58,294 INFO L432 AbstractCegarLoop]: Abstraction has 354 states and 471 transitions. [2018-01-24 15:24:58,294 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-24 15:24:58,294 INFO L276 IsEmpty]: Start isEmpty. Operand 354 states and 471 transitions. [2018-01-24 15:24:58,296 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-01-24 15:24:58,296 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:24:58,296 INFO L322 BasicCegarLoop]: trace histogram [24, 24, 23, 23, 23, 1, 1, 1, 1, 1, 1] [2018-01-24 15:24:58,296 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:24:58,296 INFO L82 PathProgramCache]: Analyzing trace with hash 2117312527, now seen corresponding path program 23 times [2018-01-24 15:24:58,297 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:24:58,297 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:58,297 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:24:58,297 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:24:58,298 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:24:58,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:24:58,312 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:24:58,680 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:58,681 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:58,681 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:24:58,681 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:24:58,681 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:24:58,681 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:58,681 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:24:58,686 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:24:58,686 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:58,689 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,691 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,692 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,693 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,694 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,695 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,696 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,698 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,699 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,701 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,702 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,704 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,706 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,708 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,710 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,712 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,714 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,716 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,718 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,720 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,723 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,725 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,728 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,731 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:58,731 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:58,734 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:58,756 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:58,756 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:59,323 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:59,342 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:24:59,343 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:24:59,345 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:24:59,345 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:24:59,351 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,353 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,359 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,364 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,372 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,380 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,389 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,399 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,409 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,421 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,434 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,449 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,464 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,481 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,506 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,526 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,546 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,567 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,589 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,619 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,643 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,670 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,706 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,735 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:24:59,771 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:24:59,777 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:24:59,831 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:59,831 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:24:59,890 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:24:59,892 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:24:59,892 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 49 [2018-01-24 15:24:59,892 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:24:59,892 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 15:24:59,892 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 15:24:59,893 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 15:24:59,893 INFO L87 Difference]: Start difference. First operand 354 states and 471 transitions. Second operand 26 states. [2018-01-24 15:25:02,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:02,145 INFO L93 Difference]: Finished difference Result 400 states and 524 transitions. [2018-01-24 15:25:02,145 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 15:25:02,145 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 123 [2018-01-24 15:25:02,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:02,147 INFO L225 Difference]: With dead ends: 400 [2018-01-24 15:25:02,147 INFO L226 Difference]: Without dead ends: 396 [2018-01-24 15:25:02,147 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 515 GetRequests, 465 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 15:25:02,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 396 states. [2018-01-24 15:25:02,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 396 to 368. [2018-01-24 15:25:02,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2018-01-24 15:25:02,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 490 transitions. [2018-01-24 15:25:02,163 INFO L78 Accepts]: Start accepts. Automaton has 368 states and 490 transitions. Word has length 123 [2018-01-24 15:25:02,163 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:02,163 INFO L432 AbstractCegarLoop]: Abstraction has 368 states and 490 transitions. [2018-01-24 15:25:02,163 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 15:25:02,163 INFO L276 IsEmpty]: Start isEmpty. Operand 368 states and 490 transitions. [2018-01-24 15:25:02,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-01-24 15:25:02,165 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:02,166 INFO L322 BasicCegarLoop]: trace histogram [25, 25, 24, 24, 24, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:02,166 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:02,166 INFO L82 PathProgramCache]: Analyzing trace with hash -1912282627, now seen corresponding path program 24 times [2018-01-24 15:25:02,166 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:02,167 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:02,167 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:02,167 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:02,167 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:02,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:02,184 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:02,629 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:02,629 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:02,630 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:02,630 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:02,630 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:02,630 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:02,630 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:02,635 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:02,635 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:02,639 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,641 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,642 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,643 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,644 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,645 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,647 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,648 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,650 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,652 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,654 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,655 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,658 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,660 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,662 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,665 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,667 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,671 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,675 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,678 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,681 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,684 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,687 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,690 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,693 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:02,693 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:02,696 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:02,734 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:02,734 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:03,615 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:03,646 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:03,646 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:03,650 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:03,650 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:03,659 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,662 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,669 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,678 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,689 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,701 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,712 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,723 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,735 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,748 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,763 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,779 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,797 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,815 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,836 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,866 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,889 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,912 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,935 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,970 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:03,997 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:04,025 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:04,066 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:04,097 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:04,140 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:04,164 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:04,171 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:04,199 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:04,199 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:04,243 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:04,244 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:04,245 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 51 [2018-01-24 15:25:04,245 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:04,245 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 15:25:04,245 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 15:25:04,246 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 15:25:04,246 INFO L87 Difference]: Start difference. First operand 368 states and 490 transitions. Second operand 27 states. [2018-01-24 15:25:07,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:07,011 INFO L93 Difference]: Finished difference Result 415 states and 544 transitions. [2018-01-24 15:25:07,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 15:25:07,011 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 128 [2018-01-24 15:25:07,011 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:07,013 INFO L225 Difference]: With dead ends: 415 [2018-01-24 15:25:07,013 INFO L226 Difference]: Without dead ends: 411 [2018-01-24 15:25:07,014 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 536 GetRequests, 484 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 15:25:07,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 411 states. [2018-01-24 15:25:07,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 411 to 382. [2018-01-24 15:25:07,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2018-01-24 15:25:07,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 509 transitions. [2018-01-24 15:25:07,030 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 509 transitions. Word has length 128 [2018-01-24 15:25:07,030 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:07,030 INFO L432 AbstractCegarLoop]: Abstraction has 382 states and 509 transitions. [2018-01-24 15:25:07,030 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 15:25:07,030 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 509 transitions. [2018-01-24 15:25:07,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2018-01-24 15:25:07,033 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:07,034 INFO L322 BasicCegarLoop]: trace histogram [26, 26, 25, 25, 25, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:07,034 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:07,034 INFO L82 PathProgramCache]: Analyzing trace with hash 972399823, now seen corresponding path program 25 times [2018-01-24 15:25:07,034 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:07,035 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:07,035 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:07,035 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:07,035 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:07,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:07,054 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:07,638 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:07,639 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:07,639 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:07,639 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:07,639 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:07,639 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:07,639 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:07,644 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:07,644 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:07,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:07,664 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:07,690 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:07,690 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:08,388 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:08,408 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:08,408 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:08,411 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:08,411 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:08,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:08,465 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:08,495 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:08,495 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:08,525 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:08,527 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:08,527 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 53 [2018-01-24 15:25:08,527 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:08,527 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 15:25:08,527 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 15:25:08,528 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 15:25:08,528 INFO L87 Difference]: Start difference. First operand 382 states and 509 transitions. Second operand 28 states. [2018-01-24 15:25:11,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:11,332 INFO L93 Difference]: Finished difference Result 430 states and 564 transitions. [2018-01-24 15:25:11,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 15:25:11,332 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 133 [2018-01-24 15:25:11,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:11,334 INFO L225 Difference]: With dead ends: 430 [2018-01-24 15:25:11,334 INFO L226 Difference]: Without dead ends: 426 [2018-01-24 15:25:11,335 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 557 GetRequests, 503 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 15:25:11,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 426 states. [2018-01-24 15:25:11,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 426 to 396. [2018-01-24 15:25:11,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 396 states. [2018-01-24 15:25:11,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 396 states to 396 states and 528 transitions. [2018-01-24 15:25:11,345 INFO L78 Accepts]: Start accepts. Automaton has 396 states and 528 transitions. Word has length 133 [2018-01-24 15:25:11,345 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:11,345 INFO L432 AbstractCegarLoop]: Abstraction has 396 states and 528 transitions. [2018-01-24 15:25:11,346 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 15:25:11,346 INFO L276 IsEmpty]: Start isEmpty. Operand 396 states and 528 transitions. [2018-01-24 15:25:11,347 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-01-24 15:25:11,347 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:11,347 INFO L322 BasicCegarLoop]: trace histogram [27, 27, 26, 26, 26, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:11,347 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:11,347 INFO L82 PathProgramCache]: Analyzing trace with hash -158870211, now seen corresponding path program 26 times [2018-01-24 15:25:11,347 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:11,348 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:11,348 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:11,348 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:11,348 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:11,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:11,360 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:11,839 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:11,839 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:11,840 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:11,840 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:11,840 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:11,840 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:11,840 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:11,849 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:11,849 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:11,855 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:11,873 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:11,876 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:11,879 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:11,940 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:11,940 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:12,702 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:12,722 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:12,723 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:12,726 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:12,726 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:12,731 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:12,748 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:12,774 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:12,779 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:12,806 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:12,806 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:12,839 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:12,840 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:12,841 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 55 [2018-01-24 15:25:12,841 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:12,841 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 15:25:12,841 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 15:25:12,842 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 15:25:12,842 INFO L87 Difference]: Start difference. First operand 396 states and 528 transitions. Second operand 29 states. Received shutdown request... [2018-01-24 15:25:14,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 15:25:14,472 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 15:25:14,476 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 15:25:14,476 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 03:25:14 BoogieIcfgContainer [2018-01-24 15:25:14,476 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 15:25:14,477 INFO L168 Benchmark]: Toolchain (without parser) took 52344.59 ms. Allocated memory was 302.0 MB in the beginning and 715.1 MB in the end (delta: 413.1 MB). Free memory was 263.0 MB in the beginning and 579.5 MB in the end (delta: -316.5 MB). Peak memory consumption was 96.7 MB. Max. memory is 5.3 GB. [2018-01-24 15:25:14,478 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 302.0 MB. Free memory is still 268.0 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 15:25:14,478 INFO L168 Benchmark]: CACSL2BoogieTranslator took 178.01 ms. Allocated memory is still 302.0 MB. Free memory was 262.0 MB in the beginning and 254.0 MB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 5.3 GB. [2018-01-24 15:25:14,478 INFO L168 Benchmark]: Boogie Preprocessor took 27.60 ms. Allocated memory is still 302.0 MB. Free memory was 254.0 MB in the beginning and 252.0 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 15:25:14,478 INFO L168 Benchmark]: RCFGBuilder took 174.56 ms. Allocated memory is still 302.0 MB. Free memory was 252.0 MB in the beginning and 239.4 MB in the end (delta: 12.6 MB). Peak memory consumption was 12.6 MB. Max. memory is 5.3 GB. [2018-01-24 15:25:14,479 INFO L168 Benchmark]: TraceAbstraction took 51956.21 ms. Allocated memory was 302.0 MB in the beginning and 715.1 MB in the end (delta: 413.1 MB). Free memory was 238.4 MB in the beginning and 579.5 MB in the end (delta: -341.1 MB). Peak memory consumption was 72.1 MB. Max. memory is 5.3 GB. [2018-01-24 15:25:14,480 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 302.0 MB. Free memory is still 268.0 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 178.01 ms. Allocated memory is still 302.0 MB. Free memory was 262.0 MB in the beginning and 254.0 MB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 27.60 ms. Allocated memory is still 302.0 MB. Free memory was 254.0 MB in the beginning and 252.0 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 174.56 ms. Allocated memory is still 302.0 MB. Free memory was 252.0 MB in the beginning and 239.4 MB in the end (delta: 12.6 MB). Peak memory consumption was 12.6 MB. Max. memory is 5.3 GB. * TraceAbstraction took 51956.21 ms. Allocated memory was 302.0 MB in the beginning and 715.1 MB in the end (delta: 413.1 MB). Free memory was 238.4 MB in the beginning and 579.5 MB in the end (delta: -341.1 MB). Peak memory consumption was 72.1 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 10 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 0 LocStat_NO_SUPPORTING_DISEQUALITIES : 1 LocStat_NO_DISJUNCTIONS : -20 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 15 TransStat_MAX_WEQGRAPH_SIZE : 0 TransStat_MAX_SIZEOF_WEQEDGELABEL : 0 TransStat_NO_SUPPORTING_EQUALITIES : 5 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 16 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.168625 RENAME_VARIABLES(MILLISECONDS) : 0.396431 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.105211 PROJECTAWAY(MILLISECONDS) : 0.206448 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.000000 DISJOIN(MILLISECONDS) : 1.733370 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.450015 ADD_EQUALITY(MILLISECONDS) : 0.080417 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.101256 #CONJOIN_DISJUNCTIVE : 18 #RENAME_VARIABLES : 43 #UNFREEZE : 0 #CONJOIN : 29 #PROJECTAWAY : 36 #ADD_WEAK_EQUALITY : 0 #DISJOIN : 1 #RENAME_VARIABLES_DISJUNCTIVE : 41 #ADD_EQUALITY : 5 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 17]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 17). Cancelled while BasicCegarLoop was constructing difference of abstraction (396states) and interpolant automaton (currently 20 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (266 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 24]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 24). Cancelled while BasicCegarLoop was constructing difference of abstraction (396states) and interpolant automaton (currently 20 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (266 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 26]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 26). Cancelled while BasicCegarLoop was constructing difference of abstraction (396states) and interpolant automaton (currently 20 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (266 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 19]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 19). Cancelled while BasicCegarLoop was constructing difference of abstraction (396states) and interpolant automaton (currently 20 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (266 states constructedinput type IntersectNwa). - StatisticsResult: Ultimate Automizer benchmark data CFG has 6 procedures, 42 locations, 4 error locations. TIMEOUT Result, 51.9s OverallTime, 27 OverallIterations, 27 TraceHistogramMax, 28.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4602 SDtfs, 3363 SDslu, 57295 SDs, 0 SdLazy, 79693 SolverSat, 813 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 22.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 8205 GetRequests, 7398 SyntacticMatches, 52 SemanticMatches, 755 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 377 ImplicationChecksByTransitivity, 13.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=396occurred in iteration=26, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.1s AbstIntTime, 1 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.3s AutomataMinimizationTime, 26 MinimizatonAttempts, 455 StatesRemovedByMinimization, 26 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 3.6s SatisfiabilityAnalysisTime, 17.3s InterpolantComputationTime, 5897 NumberOfCodeBlocks, 5897 NumberOfCodeBlocksAsserted, 425 NumberOfCheckSat, 9692 ConstructedInterpolants, 0 QuantifiedInterpolants, 6767390 SizeOfPredicates, 0 NumberOfNonLiveVariables, 5200 ConjunctsInSsa, 1560 ConjunctsInUnsatCore, 131 InterpolantComputations, 1 PerfectInterpolantSequences, 0/78390 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sanfoundry_24_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_15-25-14-489.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sanfoundry_24_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-VPDomainBenchmark-0-2018-01-24_15-25-14-489.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sanfoundry_24_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-0-2018-01-24_15-25-14-489.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sanfoundry_24_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_15-25-14-489.csv Completed graceful shutdown