java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf -i ../../../trunk/examples/svcomp/memsafety/20051113-1.c_false-valid-memtrack.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 20:06:03,311 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 20:06:03,312 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 20:06:03,327 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 20:06:03,327 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 20:06:03,328 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 20:06:03,329 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 20:06:03,331 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 20:06:03,332 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 20:06:03,333 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 20:06:03,334 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 20:06:03,334 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 20:06:03,334 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 20:06:03,335 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 20:06:03,336 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 20:06:03,339 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 20:06:03,341 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 20:06:03,343 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 20:06:03,344 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 20:06:03,346 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 20:06:03,348 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-01-24 20:06:03,354 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 20:06:03,354 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 20:06:03,355 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf [2018-01-24 20:06:03,364 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 20:06:03,365 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 20:06:03,366 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 20:06:03,366 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 20:06:03,366 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 20:06:03,366 INFO L133 SettingsManager]: * Weq Fattening=true [2018-01-24 20:06:03,366 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 20:06:03,367 INFO L133 SettingsManager]: * Precise comparison operator=true [2018-01-24 20:06:03,367 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 20:06:03,368 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 20:06:03,368 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 20:06:03,368 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 20:06:03,368 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 20:06:03,368 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 20:06:03,369 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 20:06:03,369 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 20:06:03,369 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 20:06:03,369 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 20:06:03,369 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 20:06:03,370 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 20:06:03,370 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 20:06:03,370 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 20:06:03,370 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 20:06:03,370 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 20:06:03,371 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 20:06:03,371 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 20:06:03,371 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 20:06:03,371 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 20:06:03,372 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 20:06:03,372 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 20:06:03,372 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 20:06:03,372 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 20:06:03,372 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 20:06:03,372 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 20:06:03,373 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 20:06:03,374 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 20:06:03,374 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 20:06:03,410 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 20:06:03,423 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 20:06:03,427 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 20:06:03,429 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 20:06:03,430 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 20:06:03,430 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/memsafety/20051113-1.c_false-valid-memtrack.i [2018-01-24 20:06:03,615 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 20:06:03,621 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 20:06:03,622 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 20:06:03,622 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 20:06:03,627 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 20:06:03,628 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 08:06:03" (1/1) ... [2018-01-24 20:06:03,632 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7ef7ce9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:06:03, skipping insertion in model container [2018-01-24 20:06:03,632 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 08:06:03" (1/1) ... [2018-01-24 20:06:03,651 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 20:06:03,692 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 20:06:03,814 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 20:06:03,835 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 20:06:03,843 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:06:03 WrapperNode [2018-01-24 20:06:03,843 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 20:06:03,844 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 20:06:03,844 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 20:06:03,844 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 20:06:03,862 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:06:03" (1/1) ... [2018-01-24 20:06:03,862 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:06:03" (1/1) ... [2018-01-24 20:06:03,874 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:06:03" (1/1) ... [2018-01-24 20:06:03,874 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:06:03" (1/1) ... [2018-01-24 20:06:03,878 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:06:03" (1/1) ... [2018-01-24 20:06:03,881 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:06:03" (1/1) ... [2018-01-24 20:06:03,882 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:06:03" (1/1) ... [2018-01-24 20:06:03,883 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 20:06:03,884 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 20:06:03,884 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 20:06:03,884 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 20:06:03,885 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:06:03" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 20:06:03,929 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 20:06:03,929 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 20:06:03,929 INFO L136 BoogieDeclarations]: Found implementation of procedure Sum [2018-01-24 20:06:03,930 INFO L136 BoogieDeclarations]: Found implementation of procedure Sum2 [2018-01-24 20:06:03,930 INFO L136 BoogieDeclarations]: Found implementation of procedure dummy_abort [2018-01-24 20:06:03,930 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 20:06:03,930 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 20:06:03,930 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 20:06:03,931 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 20:06:03,931 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 20:06:03,931 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 20:06:03,931 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-01-24 20:06:03,931 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-01-24 20:06:03,931 INFO L128 BoogieDeclarations]: Found specification of procedure memset [2018-01-24 20:06:03,932 INFO L128 BoogieDeclarations]: Found specification of procedure Sum [2018-01-24 20:06:03,932 INFO L128 BoogieDeclarations]: Found specification of procedure Sum2 [2018-01-24 20:06:03,932 INFO L128 BoogieDeclarations]: Found specification of procedure dummy_abort [2018-01-24 20:06:03,932 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 20:06:03,932 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 20:06:03,932 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 20:06:04,056 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-01-24 20:06:04,223 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 20:06:04,224 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 08:06:04 BoogieIcfgContainer [2018-01-24 20:06:04,224 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 20:06:04,225 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 20:06:04,225 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 20:06:04,226 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 20:06:04,227 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 08:06:03" (1/3) ... [2018-01-24 20:06:04,228 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@50d8c5a9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 08:06:04, skipping insertion in model container [2018-01-24 20:06:04,228 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:06:03" (2/3) ... [2018-01-24 20:06:04,228 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@50d8c5a9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 08:06:04, skipping insertion in model container [2018-01-24 20:06:04,228 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 08:06:04" (3/3) ... [2018-01-24 20:06:04,230 INFO L105 eAbstractionObserver]: Analyzing ICFG 20051113-1.c_false-valid-memtrack.i [2018-01-24 20:06:04,240 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 20:06:04,248 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 25 error locations. [2018-01-24 20:06:04,298 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 20:06:04,298 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 20:06:04,298 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 20:06:04,298 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 20:06:04,299 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 20:06:04,299 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 20:06:04,299 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 20:06:04,299 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 20:06:04,300 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 20:06:04,321 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states. [2018-01-24 20:06:04,328 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 20:06:04,328 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:04,329 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:04,329 INFO L371 AbstractCegarLoop]: === Iteration 1 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:04,334 INFO L82 PathProgramCache]: Analyzing trace with hash -1274877597, now seen corresponding path program 1 times [2018-01-24 20:06:04,337 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:04,395 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:04,395 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:04,395 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:04,395 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:04,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:04,453 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:04,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:06:04,534 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 20:06:04,534 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 20:06:04,534 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 20:06:04,538 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 20:06:04,554 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 20:06:04,555 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 20:06:04,558 INFO L87 Difference]: Start difference. First operand 80 states. Second operand 4 states. [2018-01-24 20:06:04,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:04,831 INFO L93 Difference]: Finished difference Result 111 states and 123 transitions. [2018-01-24 20:06:04,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 20:06:04,832 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 8 [2018-01-24 20:06:04,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:04,841 INFO L225 Difference]: With dead ends: 111 [2018-01-24 20:06:04,841 INFO L226 Difference]: Without dead ends: 69 [2018-01-24 20:06:04,844 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 20:06:04,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-01-24 20:06:04,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2018-01-24 20:06:04,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-01-24 20:06:04,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 74 transitions. [2018-01-24 20:06:04,880 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 74 transitions. Word has length 8 [2018-01-24 20:06:04,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:04,880 INFO L432 AbstractCegarLoop]: Abstraction has 69 states and 74 transitions. [2018-01-24 20:06:04,880 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 20:06:04,880 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 74 transitions. [2018-01-24 20:06:04,881 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 20:06:04,881 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:04,881 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:04,881 INFO L371 AbstractCegarLoop]: === Iteration 2 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:04,882 INFO L82 PathProgramCache]: Analyzing trace with hash -1274877596, now seen corresponding path program 1 times [2018-01-24 20:06:04,882 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:04,883 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:04,883 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:04,883 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:04,883 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:04,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:04,898 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:04,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:06:04,974 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 20:06:04,974 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 20:06:04,974 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 20:06:04,976 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 20:06:04,976 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 20:06:04,976 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 20:06:04,977 INFO L87 Difference]: Start difference. First operand 69 states and 74 transitions. Second operand 4 states. [2018-01-24 20:06:05,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:05,096 INFO L93 Difference]: Finished difference Result 69 states and 74 transitions. [2018-01-24 20:06:05,096 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 20:06:05,097 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 8 [2018-01-24 20:06:05,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:05,098 INFO L225 Difference]: With dead ends: 69 [2018-01-24 20:06:05,098 INFO L226 Difference]: Without dead ends: 61 [2018-01-24 20:06:05,099 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 20:06:05,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-01-24 20:06:05,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2018-01-24 20:06:05,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-01-24 20:06:05,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 66 transitions. [2018-01-24 20:06:05,109 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 66 transitions. Word has length 8 [2018-01-24 20:06:05,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:05,109 INFO L432 AbstractCegarLoop]: Abstraction has 61 states and 66 transitions. [2018-01-24 20:06:05,109 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 20:06:05,110 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 66 transitions. [2018-01-24 20:06:05,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-24 20:06:05,111 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:05,111 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:05,111 INFO L371 AbstractCegarLoop]: === Iteration 3 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:05,111 INFO L82 PathProgramCache]: Analyzing trace with hash -1852712777, now seen corresponding path program 1 times [2018-01-24 20:06:05,111 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:05,112 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:05,112 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:05,113 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:05,113 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:05,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:05,139 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:05,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:06:05,212 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 20:06:05,212 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 20:06:05,212 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 20:06:05,213 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 20:06:05,213 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 20:06:05,213 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 20:06:05,213 INFO L87 Difference]: Start difference. First operand 61 states and 66 transitions. Second operand 5 states. [2018-01-24 20:06:05,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:05,342 INFO L93 Difference]: Finished difference Result 61 states and 66 transitions. [2018-01-24 20:06:05,343 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 20:06:05,343 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 25 [2018-01-24 20:06:05,343 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:05,344 INFO L225 Difference]: With dead ends: 61 [2018-01-24 20:06:05,344 INFO L226 Difference]: Without dead ends: 59 [2018-01-24 20:06:05,345 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 20:06:05,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-01-24 20:06:05,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2018-01-24 20:06:05,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2018-01-24 20:06:05,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 64 transitions. [2018-01-24 20:06:05,352 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 64 transitions. Word has length 25 [2018-01-24 20:06:05,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:05,353 INFO L432 AbstractCegarLoop]: Abstraction has 59 states and 64 transitions. [2018-01-24 20:06:05,353 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 20:06:05,353 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 64 transitions. [2018-01-24 20:06:05,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-24 20:06:05,354 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:05,354 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:05,355 INFO L371 AbstractCegarLoop]: === Iteration 4 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:05,355 INFO L82 PathProgramCache]: Analyzing trace with hash -1852712776, now seen corresponding path program 1 times [2018-01-24 20:06:05,355 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:05,356 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:05,356 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:05,356 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:05,357 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:05,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:05,379 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:05,492 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:06:05,492 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 20:06:05,492 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 20:06:05,492 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 20:06:05,493 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 20:06:05,493 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 20:06:05,493 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 20:06:05,494 INFO L87 Difference]: Start difference. First operand 59 states and 64 transitions. Second operand 6 states. [2018-01-24 20:06:05,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:05,636 INFO L93 Difference]: Finished difference Result 59 states and 64 transitions. [2018-01-24 20:06:05,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 20:06:05,637 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2018-01-24 20:06:05,637 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:05,637 INFO L225 Difference]: With dead ends: 59 [2018-01-24 20:06:05,637 INFO L226 Difference]: Without dead ends: 58 [2018-01-24 20:06:05,638 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-01-24 20:06:05,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-01-24 20:06:05,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 58. [2018-01-24 20:06:05,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-01-24 20:06:05,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 63 transitions. [2018-01-24 20:06:05,646 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 63 transitions. Word has length 25 [2018-01-24 20:06:05,646 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:05,646 INFO L432 AbstractCegarLoop]: Abstraction has 58 states and 63 transitions. [2018-01-24 20:06:05,646 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 20:06:05,646 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 63 transitions. [2018-01-24 20:06:05,647 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 20:06:05,647 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:05,647 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:05,647 INFO L371 AbstractCegarLoop]: === Iteration 5 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:05,647 INFO L82 PathProgramCache]: Analyzing trace with hash 1954449657, now seen corresponding path program 1 times [2018-01-24 20:06:05,647 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:05,648 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:05,648 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:05,648 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:05,649 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:05,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:05,674 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:06,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:06:06,045 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 20:06:06,045 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-01-24 20:06:06,045 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 20:06:06,046 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 20:06:06,046 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 20:06:06,046 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-01-24 20:06:06,046 INFO L87 Difference]: Start difference. First operand 58 states and 63 transitions. Second operand 9 states. [2018-01-24 20:06:06,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:06,285 INFO L93 Difference]: Finished difference Result 93 states and 102 transitions. [2018-01-24 20:06:06,285 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 20:06:06,285 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 27 [2018-01-24 20:06:06,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:06,287 INFO L225 Difference]: With dead ends: 93 [2018-01-24 20:06:06,287 INFO L226 Difference]: Without dead ends: 64 [2018-01-24 20:06:06,287 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 1 SyntacticMatches, 6 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-01-24 20:06:06,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-01-24 20:06:06,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 62. [2018-01-24 20:06:06,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-01-24 20:06:06,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 67 transitions. [2018-01-24 20:06:06,297 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 67 transitions. Word has length 27 [2018-01-24 20:06:06,298 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:06,298 INFO L432 AbstractCegarLoop]: Abstraction has 62 states and 67 transitions. [2018-01-24 20:06:06,298 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 20:06:06,298 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 67 transitions. [2018-01-24 20:06:06,299 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-01-24 20:06:06,299 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:06,299 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:06,299 INFO L371 AbstractCegarLoop]: === Iteration 6 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:06,300 INFO L82 PathProgramCache]: Analyzing trace with hash 1339860797, now seen corresponding path program 1 times [2018-01-24 20:06:06,300 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:06,301 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:06,301 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:06,301 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:06,301 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:06,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:06,322 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:06,484 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:06:06,484 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:06,484 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:06,485 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 34 with the following transitions: [2018-01-24 20:06:06,487 INFO L201 CegarAbsIntRunner]: [24], [25], [31], [32], [34], [38], [39], [46], [47], [49], [50], [52], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [105], [106], [110], [111], [112], [120], [121], [122] [2018-01-24 20:06:06,528 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 20:06:06,529 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 20:06:07,877 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 20:06:07,879 INFO L268 AbstractInterpreter]: Visited 30 different actions 37 times. Merged at 7 different actions 7 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 19 variables. [2018-01-24 20:06:07,900 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 20:06:07,901 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:07,901 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:07,912 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:07,913 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:06:07,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:07,954 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:08,000 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 20:06:08,000 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:08,075 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 20:06:08,110 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 20:06:08,111 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4, 4] imperfect sequences [6] total 11 [2018-01-24 20:06:08,111 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 20:06:08,111 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 20:06:08,112 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 20:06:08,112 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-01-24 20:06:08,112 INFO L87 Difference]: Start difference. First operand 62 states and 67 transitions. Second operand 4 states. [2018-01-24 20:06:08,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:08,134 INFO L93 Difference]: Finished difference Result 114 states and 124 transitions. [2018-01-24 20:06:08,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 20:06:08,135 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 33 [2018-01-24 20:06:08,135 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:08,135 INFO L225 Difference]: With dead ends: 114 [2018-01-24 20:06:08,136 INFO L226 Difference]: Without dead ends: 63 [2018-01-24 20:06:08,136 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 61 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2018-01-24 20:06:08,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-01-24 20:06:08,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2018-01-24 20:06:08,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-01-24 20:06:08,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 68 transitions. [2018-01-24 20:06:08,143 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 68 transitions. Word has length 33 [2018-01-24 20:06:08,143 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:08,144 INFO L432 AbstractCegarLoop]: Abstraction has 63 states and 68 transitions. [2018-01-24 20:06:08,144 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 20:06:08,144 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 68 transitions. [2018-01-24 20:06:08,145 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-24 20:06:08,145 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:08,145 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:08,145 INFO L371 AbstractCegarLoop]: === Iteration 7 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:08,145 INFO L82 PathProgramCache]: Analyzing trace with hash 1619594826, now seen corresponding path program 1 times [2018-01-24 20:06:08,145 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:08,146 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:08,146 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:08,146 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:08,146 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:08,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:08,166 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:08,368 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-01-24 20:06:08,369 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:08,369 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:08,369 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 35 with the following transitions: [2018-01-24 20:06:08,369 INFO L201 CegarAbsIntRunner]: [24], [25], [29], [31], [32], [34], [38], [39], [46], [47], [49], [50], [52], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [105], [106], [110], [111], [112], [120], [121], [122] [2018-01-24 20:06:08,371 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 20:06:08,371 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 20:06:12,844 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 20:06:12,844 INFO L268 AbstractInterpreter]: Visited 31 different actions 46 times. Merged at 10 different actions 13 times. Never widened. Found 4 fixpoints after 3 different actions. Largest state had 19 variables. [2018-01-24 20:06:12,846 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 20:06:12,846 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:12,846 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:12,861 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:12,861 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:06:12,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:12,888 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:12,939 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 20:06:12,940 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:13,029 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 20:06:13,049 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:13,050 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 4 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:13,056 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:13,056 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:06:13,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:13,105 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:13,110 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 20:06:13,110 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:13,136 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 20:06:13,138 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:06:13,138 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5, 5, 5] total 13 [2018-01-24 20:06:13,139 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:06:13,139 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 20:06:13,139 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 20:06:13,140 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=122, Unknown=0, NotChecked=0, Total=156 [2018-01-24 20:06:13,140 INFO L87 Difference]: Start difference. First operand 63 states and 68 transitions. Second operand 10 states. [2018-01-24 20:06:13,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:13,454 INFO L93 Difference]: Finished difference Result 126 states and 138 transitions. [2018-01-24 20:06:13,455 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 20:06:13,455 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 34 [2018-01-24 20:06:13,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:13,457 INFO L225 Difference]: With dead ends: 126 [2018-01-24 20:06:13,458 INFO L226 Difference]: Without dead ends: 75 [2018-01-24 20:06:13,460 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 146 GetRequests, 128 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=53, Invalid=219, Unknown=0, NotChecked=0, Total=272 [2018-01-24 20:06:13,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-01-24 20:06:13,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 70. [2018-01-24 20:06:13,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-01-24 20:06:13,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 76 transitions. [2018-01-24 20:06:13,468 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 76 transitions. Word has length 34 [2018-01-24 20:06:13,469 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:13,469 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 76 transitions. [2018-01-24 20:06:13,469 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 20:06:13,469 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 76 transitions. [2018-01-24 20:06:13,470 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 20:06:13,470 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:13,470 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:13,470 INFO L371 AbstractCegarLoop]: === Iteration 8 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:13,471 INFO L82 PathProgramCache]: Analyzing trace with hash -341936469, now seen corresponding path program 1 times [2018-01-24 20:06:13,471 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:13,472 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:13,472 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:13,472 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:13,472 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:13,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:13,489 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:13,541 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 20:06:13,541 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 20:06:13,542 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 20:06:13,542 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 20:06:13,542 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 20:06:13,542 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 20:06:13,543 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 20:06:13,543 INFO L87 Difference]: Start difference. First operand 70 states and 76 transitions. Second operand 5 states. [2018-01-24 20:06:13,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:13,623 INFO L93 Difference]: Finished difference Result 70 states and 76 transitions. [2018-01-24 20:06:13,623 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 20:06:13,623 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 42 [2018-01-24 20:06:13,624 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:13,625 INFO L225 Difference]: With dead ends: 70 [2018-01-24 20:06:13,625 INFO L226 Difference]: Without dead ends: 68 [2018-01-24 20:06:13,625 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 20:06:13,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2018-01-24 20:06:13,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 68. [2018-01-24 20:06:13,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68 states. [2018-01-24 20:06:13,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 74 transitions. [2018-01-24 20:06:13,632 INFO L78 Accepts]: Start accepts. Automaton has 68 states and 74 transitions. Word has length 42 [2018-01-24 20:06:13,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:13,633 INFO L432 AbstractCegarLoop]: Abstraction has 68 states and 74 transitions. [2018-01-24 20:06:13,633 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 20:06:13,633 INFO L276 IsEmpty]: Start isEmpty. Operand 68 states and 74 transitions. [2018-01-24 20:06:13,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 20:06:13,634 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:13,635 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:13,635 INFO L371 AbstractCegarLoop]: === Iteration 9 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:13,635 INFO L82 PathProgramCache]: Analyzing trace with hash -341936468, now seen corresponding path program 1 times [2018-01-24 20:06:13,635 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:13,636 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:13,636 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:13,636 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:13,636 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:13,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:13,653 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:13,777 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 20:06:13,777 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 20:06:13,777 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 20:06:13,777 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 20:06:13,777 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 20:06:13,778 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 20:06:13,778 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 20:06:13,778 INFO L87 Difference]: Start difference. First operand 68 states and 74 transitions. Second operand 6 states. [2018-01-24 20:06:13,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:13,921 INFO L93 Difference]: Finished difference Result 68 states and 74 transitions. [2018-01-24 20:06:13,921 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 20:06:13,921 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 42 [2018-01-24 20:06:13,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:13,922 INFO L225 Difference]: With dead ends: 68 [2018-01-24 20:06:13,923 INFO L226 Difference]: Without dead ends: 67 [2018-01-24 20:06:13,923 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-01-24 20:06:13,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-01-24 20:06:13,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2018-01-24 20:06:13,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-01-24 20:06:13,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 73 transitions. [2018-01-24 20:06:13,930 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 73 transitions. Word has length 42 [2018-01-24 20:06:13,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:13,931 INFO L432 AbstractCegarLoop]: Abstraction has 67 states and 73 transitions. [2018-01-24 20:06:13,931 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 20:06:13,931 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 73 transitions. [2018-01-24 20:06:13,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-24 20:06:13,933 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:13,933 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:13,933 INFO L371 AbstractCegarLoop]: === Iteration 10 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:13,933 INFO L82 PathProgramCache]: Analyzing trace with hash -614912991, now seen corresponding path program 2 times [2018-01-24 20:06:13,933 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:13,934 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:13,934 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:13,934 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:13,935 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:13,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:13,951 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:14,295 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 20:06:14,295 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:14,295 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:14,295 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:06:14,295 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:06:14,295 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:14,296 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:14,301 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:06:14,301 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:06:14,318 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:14,331 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:14,332 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:14,335 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:14,437 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 20:06:14,437 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:14,513 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 20:06:14,534 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:14,534 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:14,537 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:06:14,537 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:06:14,555 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:14,579 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:14,591 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:14,595 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:14,600 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 20:06:14,600 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:14,627 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 20:06:14,629 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:06:14,630 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6, 6, 6] total 16 [2018-01-24 20:06:14,630 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:06:14,630 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 20:06:14,630 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 20:06:14,631 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=189, Unknown=0, NotChecked=0, Total=240 [2018-01-24 20:06:14,631 INFO L87 Difference]: Start difference. First operand 67 states and 73 transitions. Second operand 12 states. [2018-01-24 20:06:14,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:14,877 INFO L93 Difference]: Finished difference Result 136 states and 150 transitions. [2018-01-24 20:06:14,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 20:06:14,877 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 41 [2018-01-24 20:06:14,877 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:14,878 INFO L225 Difference]: With dead ends: 136 [2018-01-24 20:06:14,878 INFO L226 Difference]: Without dead ends: 82 [2018-01-24 20:06:14,879 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 176 GetRequests, 154 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=75, Invalid=345, Unknown=0, NotChecked=0, Total=420 [2018-01-24 20:06:14,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-01-24 20:06:14,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 74. [2018-01-24 20:06:14,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-24 20:06:14,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 81 transitions. [2018-01-24 20:06:14,887 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 81 transitions. Word has length 41 [2018-01-24 20:06:14,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:14,887 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 81 transitions. [2018-01-24 20:06:14,887 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 20:06:14,887 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 81 transitions. [2018-01-24 20:06:14,888 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-01-24 20:06:14,888 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:14,888 INFO L322 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:14,888 INFO L371 AbstractCegarLoop]: === Iteration 11 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:14,889 INFO L82 PathProgramCache]: Analyzing trace with hash 1732121728, now seen corresponding path program 1 times [2018-01-24 20:06:14,889 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:14,890 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:14,890 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:06:14,890 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:14,890 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:14,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:14,907 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:15,344 WARN L146 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 25 DAG size of output 17 [2018-01-24 20:06:15,540 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-01-24 20:06:15,540 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:15,540 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:15,541 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 46 with the following transitions: [2018-01-24 20:06:15,541 INFO L201 CegarAbsIntRunner]: [0], [4], [5], [12], [15], [24], [25], [29], [31], [32], [34], [38], [39], [44], [46], [47], [50], [52], [56], [57], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [91], [105], [106], [110], [111], [112], [113], [116], [120], [121], [122] [2018-01-24 20:06:15,543 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 20:06:15,543 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 20:06:18,166 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 20:06:18,167 INFO L268 AbstractInterpreter]: Visited 41 different actions 60 times. Merged at 13 different actions 16 times. Never widened. Found 5 fixpoints after 4 different actions. Largest state had 20 variables. [2018-01-24 20:06:18,210 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 20:06:18,210 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:18,210 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:18,217 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:18,218 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:06:18,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:18,248 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:18,305 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 20:06:18,305 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:18,389 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 20:06:18,410 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:18,410 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:18,414 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:18,414 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:06:18,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:18,453 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:18,457 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 20:06:18,457 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:18,478 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 20:06:18,481 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:06:18,481 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 7, 7, 7, 7] total 22 [2018-01-24 20:06:18,481 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:06:18,481 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 20:06:18,481 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 20:06:18,482 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=378, Unknown=0, NotChecked=0, Total=462 [2018-01-24 20:06:18,482 INFO L87 Difference]: Start difference. First operand 74 states and 81 transitions. Second operand 17 states. [2018-01-24 20:06:18,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:18,738 INFO L93 Difference]: Finished difference Result 144 states and 160 transitions. [2018-01-24 20:06:18,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 20:06:18,738 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 45 [2018-01-24 20:06:18,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:18,739 INFO L225 Difference]: With dead ends: 144 [2018-01-24 20:06:18,739 INFO L226 Difference]: Without dead ends: 84 [2018-01-24 20:06:18,740 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 168 SyntacticMatches, 10 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 108 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=116, Invalid=586, Unknown=0, NotChecked=0, Total=702 [2018-01-24 20:06:18,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-01-24 20:06:18,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 79. [2018-01-24 20:06:18,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-01-24 20:06:18,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 87 transitions. [2018-01-24 20:06:18,745 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 87 transitions. Word has length 45 [2018-01-24 20:06:18,746 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:18,746 INFO L432 AbstractCegarLoop]: Abstraction has 79 states and 87 transitions. [2018-01-24 20:06:18,746 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 20:06:18,746 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 87 transitions. [2018-01-24 20:06:18,747 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-01-24 20:06:18,747 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:18,747 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:18,747 INFO L371 AbstractCegarLoop]: === Iteration 12 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:18,747 INFO L82 PathProgramCache]: Analyzing trace with hash -117713403, now seen corresponding path program 3 times [2018-01-24 20:06:18,748 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:18,748 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:18,749 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:18,749 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:18,749 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:18,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:18,765 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:18,999 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 17 proven. 13 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 20:06:18,999 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:18,999 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:18,999 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:06:19,000 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:06:19,000 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:19,000 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:19,009 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:06:19,009 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:06:19,020 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:19,030 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:19,032 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:19,034 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:19,050 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 20:06:19,051 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,054 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,054 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-01-24 20:06:19,110 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 20:06:19,111 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 20:06:19,112 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,113 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,116 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,117 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:20, output treesize:16 [2018-01-24 20:06:19,134 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 20:06:19,137 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,139 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,139 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 20:06:19,140 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,147 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,152 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,153 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:29, output treesize:25 [2018-01-24 20:06:19,187 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 20:06:19,193 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,194 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,194 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,195 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,196 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,196 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,197 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 20:06:19,198 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,208 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,215 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,215 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:38, output treesize:34 [2018-01-24 20:06:19,256 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 20:06:19,259 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,260 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,261 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,261 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,262 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,263 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,264 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,265 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,265 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,267 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,268 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,269 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,270 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 20:06:19,271 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,292 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,300 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,300 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:47, output treesize:43 [2018-01-24 20:06:19,329 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 20:06:19,333 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,334 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,334 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,335 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,336 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,336 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,337 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,338 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,338 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,339 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,340 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,340 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,341 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,342 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,343 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,343 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,344 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 20:06:19,345 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,381 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,389 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,389 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:56, output treesize:52 [2018-01-24 20:06:19,421 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 20:06:19,425 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,426 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,427 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,427 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,428 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,429 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,430 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,430 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,431 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,432 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,432 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,433 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,434 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,437 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,438 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,439 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,440 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,441 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,441 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,442 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,443 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,444 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 20:06:19,444 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,491 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,501 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,501 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:65, output treesize:61 [2018-01-24 20:06:19,535 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 20:06:19,539 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,540 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,540 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,541 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,541 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,542 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,543 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,543 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,544 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,545 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,545 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,546 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,547 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,547 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,548 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,548 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,549 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,550 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,550 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,551 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,552 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,552 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,553 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,554 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,554 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,555 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,556 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,557 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 20:06:19,557 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,608 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,618 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,618 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:74, output treesize:70 [2018-01-24 20:06:19,824 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 53 [2018-01-24 20:06:19,848 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,858 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,864 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,865 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,872 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,873 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,880 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,881 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,882 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,894 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,908 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,909 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,910 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,910 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,919 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,920 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,921 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,922 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,923 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,925 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,926 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,927 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,928 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,928 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,929 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,930 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,931 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:19,931 INFO L303 Elim1Store]: Index analysis took 105 ms [2018-01-24 20:06:19,932 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 7 select indices, 7 select index equivalence classes, 27 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 160 [2018-01-24 20:06:19,933 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,957 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:19,963 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 20:06:19,963 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:90, output treesize:25 [2018-01-24 20:06:20,032 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 10 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 20:06:20,032 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:21,011 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 20:06:21,031 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:21,032 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:21,035 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:06:21,035 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:06:21,053 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:21,074 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:21,096 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:21,101 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:21,106 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 20:06:21,107 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,109 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,109 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-01-24 20:06:21,223 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 20:06:21,224 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 20:06:21,225 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,226 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,230 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,231 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:20, output treesize:16 [2018-01-24 20:06:21,274 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 20:06:21,277 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,277 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,278 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 20:06:21,278 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,283 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,290 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,290 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:29, output treesize:25 [2018-01-24 20:06:21,344 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 20:06:21,347 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,348 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,348 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,349 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,350 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,350 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,351 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 20:06:21,351 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,361 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,367 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,367 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:38, output treesize:34 [2018-01-24 20:06:21,408 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 20:06:21,410 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,411 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,411 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,412 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,412 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,413 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,414 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,414 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,415 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,416 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,416 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,417 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,418 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 20:06:21,418 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,433 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,439 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,440 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:47, output treesize:43 [2018-01-24 20:06:21,483 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 20:06:21,485 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,486 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,487 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,487 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,488 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,488 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,489 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,489 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,490 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,490 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,491 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,491 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,492 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,493 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,493 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,494 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,494 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 20:06:21,495 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,516 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,524 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,524 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:56, output treesize:52 [2018-01-24 20:06:21,584 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 20:06:21,588 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,589 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,590 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,591 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,592 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,593 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,594 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,595 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,596 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,597 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,598 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,599 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,600 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,601 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,602 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,603 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,604 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,605 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,606 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,607 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,608 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,609 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 20:06:21,610 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,655 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,665 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,666 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:65, output treesize:61 [2018-01-24 20:06:21,745 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 20:06:21,749 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,749 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,750 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,751 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,751 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,752 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,753 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,753 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,754 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,755 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,755 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,756 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,756 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,757 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,758 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,758 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,759 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,760 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,760 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,761 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,761 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,762 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,763 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,763 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,764 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,765 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,765 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:21,766 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 20:06:21,767 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,814 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,824 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:21,825 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:74, output treesize:70 [2018-01-24 20:06:22,106 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 41 [2018-01-24 20:06:22,109 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:22,110 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:22,110 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:22,111 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:22,112 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:22,112 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:22,113 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 27 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 43 [2018-01-24 20:06:22,113 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:22,121 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:22,126 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 20:06:22,126 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:78, output treesize:25 [2018-01-24 20:06:22,222 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 10 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 20:06:22,222 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:22,864 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 20:06:22,866 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:06:22,866 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 17, 10, 17, 10] total 54 [2018-01-24 20:06:22,866 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:06:22,867 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 20:06:22,867 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 20:06:22,867 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=2520, Unknown=1, NotChecked=0, Total=2862 [2018-01-24 20:06:22,868 INFO L87 Difference]: Start difference. First operand 79 states and 87 transitions. Second operand 30 states. [2018-01-24 20:06:24,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:24,510 INFO L93 Difference]: Finished difference Result 113 states and 126 transitions. [2018-01-24 20:06:24,510 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 20:06:24,510 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 49 [2018-01-24 20:06:24,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:24,511 INFO L225 Difference]: With dead ends: 113 [2018-01-24 20:06:24,511 INFO L226 Difference]: Without dead ends: 77 [2018-01-24 20:06:24,512 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 235 GetRequests, 136 SyntacticMatches, 28 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2186 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=795, Invalid=4460, Unknown=1, NotChecked=0, Total=5256 [2018-01-24 20:06:24,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2018-01-24 20:06:24,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 77. [2018-01-24 20:06:24,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-01-24 20:06:24,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 84 transitions. [2018-01-24 20:06:24,518 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 84 transitions. Word has length 49 [2018-01-24 20:06:24,519 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:24,519 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 84 transitions. [2018-01-24 20:06:24,519 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 20:06:24,519 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 84 transitions. [2018-01-24 20:06:24,520 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 20:06:24,520 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:24,520 INFO L322 BasicCegarLoop]: trace histogram [4, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:24,520 INFO L371 AbstractCegarLoop]: === Iteration 13 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:24,520 INFO L82 PathProgramCache]: Analyzing trace with hash 2106198684, now seen corresponding path program 1 times [2018-01-24 20:06:24,520 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:24,521 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:24,521 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:06:24,521 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:24,521 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:24,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:24,534 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:24,592 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-01-24 20:06:24,593 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 20:06:24,593 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 20:06:24,593 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 20:06:24,593 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 20:06:24,593 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 20:06:24,594 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 20:06:24,594 INFO L87 Difference]: Start difference. First operand 77 states and 84 transitions. Second operand 5 states. [2018-01-24 20:06:24,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:24,626 INFO L93 Difference]: Finished difference Result 86 states and 93 transitions. [2018-01-24 20:06:24,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 20:06:24,626 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 52 [2018-01-24 20:06:24,626 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:24,627 INFO L225 Difference]: With dead ends: 86 [2018-01-24 20:06:24,627 INFO L226 Difference]: Without dead ends: 83 [2018-01-24 20:06:24,628 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 20:06:24,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-01-24 20:06:24,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 82. [2018-01-24 20:06:24,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-01-24 20:06:24,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 89 transitions. [2018-01-24 20:06:24,635 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 89 transitions. Word has length 52 [2018-01-24 20:06:24,636 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:24,636 INFO L432 AbstractCegarLoop]: Abstraction has 82 states and 89 transitions. [2018-01-24 20:06:24,636 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 20:06:24,636 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 89 transitions. [2018-01-24 20:06:24,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 20:06:24,637 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:24,637 INFO L322 BasicCegarLoop]: trace histogram [4, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:24,637 INFO L371 AbstractCegarLoop]: === Iteration 14 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:24,637 INFO L82 PathProgramCache]: Analyzing trace with hash 1604645521, now seen corresponding path program 1 times [2018-01-24 20:06:24,637 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:24,638 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:24,638 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:24,638 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:24,639 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:24,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:24,652 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:24,996 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-01-24 20:06:24,996 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:24,996 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:24,997 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 53 with the following transitions: [2018-01-24 20:06:24,997 INFO L201 CegarAbsIntRunner]: [0], [4], [5], [12], [13], [15], [16], [18], [24], [25], [29], [31], [32], [34], [38], [39], [44], [46], [47], [50], [52], [56], [57], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [91], [105], [106], [110], [111], [112], [113], [116], [120], [121], [122] [2018-01-24 20:06:24,998 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 20:06:24,998 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 20:06:27,359 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 20:06:27,360 INFO L268 AbstractInterpreter]: Visited 44 different actions 70 times. Merged at 20 different actions 23 times. Never widened. Found 6 fixpoints after 5 different actions. Largest state had 20 variables. [2018-01-24 20:06:27,372 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 20:06:27,372 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:27,372 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:27,378 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:27,378 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:06:27,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:27,405 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:27,494 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 20:06:27,494 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:27,598 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 20:06:27,618 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:27,618 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:27,621 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:27,621 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:06:27,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:27,661 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:27,665 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 20:06:27,665 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:27,686 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 20:06:27,688 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:06:27,688 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8, 8, 8] total 25 [2018-01-24 20:06:27,688 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:06:27,688 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 20:06:27,688 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 20:06:27,689 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=490, Unknown=0, NotChecked=0, Total=600 [2018-01-24 20:06:27,689 INFO L87 Difference]: Start difference. First operand 82 states and 89 transitions. Second operand 19 states. [2018-01-24 20:06:28,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:28,015 INFO L93 Difference]: Finished difference Result 151 states and 166 transitions. [2018-01-24 20:06:28,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 20:06:28,015 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 52 [2018-01-24 20:06:28,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:28,016 INFO L225 Difference]: With dead ends: 151 [2018-01-24 20:06:28,016 INFO L226 Difference]: Without dead ends: 84 [2018-01-24 20:06:28,017 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 233 GetRequests, 194 SyntacticMatches, 8 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 153 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=174, Invalid=882, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 20:06:28,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-01-24 20:06:28,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 81. [2018-01-24 20:06:28,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-01-24 20:06:28,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 88 transitions. [2018-01-24 20:06:28,026 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 88 transitions. Word has length 52 [2018-01-24 20:06:28,027 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:28,027 INFO L432 AbstractCegarLoop]: Abstraction has 81 states and 88 transitions. [2018-01-24 20:06:28,027 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 20:06:28,027 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 88 transitions. [2018-01-24 20:06:28,028 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-01-24 20:06:28,028 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:28,028 INFO L322 BasicCegarLoop]: trace histogram [5, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:28,028 INFO L371 AbstractCegarLoop]: === Iteration 15 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:28,028 INFO L82 PathProgramCache]: Analyzing trace with hash -544800124, now seen corresponding path program 1 times [2018-01-24 20:06:28,028 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:28,029 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:28,029 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:28,029 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:28,029 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:28,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:28,040 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:28,207 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-01-24 20:06:28,207 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:28,207 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:28,207 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 57 with the following transitions: [2018-01-24 20:06:28,207 INFO L201 CegarAbsIntRunner]: [0], [4], [5], [10], [22], [23], [24], [25], [29], [31], [32], [33], [34], [38], [39], [44], [46], [47], [50], [52], [56], [57], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [91], [94], [97], [102], [104], [105], [106], [110], [111], [112], [113], [116], [117], [118], [119], [120], [121], [122] [2018-01-24 20:06:28,209 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 20:06:28,209 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 20:06:30,120 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 20:06:30,120 INFO L268 AbstractInterpreter]: Visited 50 different actions 69 times. Merged at 13 different actions 16 times. Never widened. Found 5 fixpoints after 4 different actions. Largest state had 20 variables. [2018-01-24 20:06:30,132 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 20:06:30,132 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:30,132 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:30,143 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:30,143 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:06:30,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:30,173 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:30,244 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 20:06:30,244 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:30,429 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 20:06:30,454 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:30,454 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:30,457 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:30,457 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:06:30,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:30,500 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:30,505 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 20:06:30,505 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:30,535 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 20:06:30,537 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:06:30,537 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 23 [2018-01-24 20:06:30,537 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:06:30,538 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 20:06:30,538 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 20:06:30,538 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=124, Invalid=382, Unknown=0, NotChecked=0, Total=506 [2018-01-24 20:06:30,538 INFO L87 Difference]: Start difference. First operand 81 states and 88 transitions. Second operand 16 states. [2018-01-24 20:06:30,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:30,699 INFO L93 Difference]: Finished difference Result 148 states and 162 transitions. [2018-01-24 20:06:30,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 20:06:30,700 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 56 [2018-01-24 20:06:30,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:30,700 INFO L225 Difference]: With dead ends: 148 [2018-01-24 20:06:30,700 INFO L226 Difference]: Without dead ends: 80 [2018-01-24 20:06:30,701 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 242 GetRequests, 208 SyntacticMatches, 10 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=143, Invalid=507, Unknown=0, NotChecked=0, Total=650 [2018-01-24 20:06:30,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-24 20:06:30,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 77. [2018-01-24 20:06:30,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-01-24 20:06:30,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 83 transitions. [2018-01-24 20:06:30,707 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 83 transitions. Word has length 56 [2018-01-24 20:06:30,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:30,707 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 83 transitions. [2018-01-24 20:06:30,707 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 20:06:30,707 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 83 transitions. [2018-01-24 20:06:30,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-01-24 20:06:30,708 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:30,708 INFO L322 BasicCegarLoop]: trace histogram [6, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:30,708 INFO L371 AbstractCegarLoop]: === Iteration 16 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:30,708 INFO L82 PathProgramCache]: Analyzing trace with hash -1454707584, now seen corresponding path program 1 times [2018-01-24 20:06:30,708 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:30,709 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:30,709 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:30,709 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:30,709 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:30,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:30,726 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:31,001 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 20:06:31,001 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:31,001 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:31,001 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 61 with the following transitions: [2018-01-24 20:06:31,001 INFO L201 CegarAbsIntRunner]: [0], [4], [5], [10], [12], [13], [16], [18], [22], [23], [24], [25], [29], [31], [32], [34], [38], [39], [44], [46], [47], [50], [52], [56], [57], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [91], [94], [100], [102], [104], [105], [106], [110], [111], [112], [113], [116], [117], [120], [121], [122] [2018-01-24 20:06:31,003 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 20:06:31,003 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 20:06:33,178 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 20:06:33,178 INFO L268 AbstractInterpreter]: Visited 51 different actions 82 times. Merged at 24 different actions 27 times. Never widened. Found 6 fixpoints after 5 different actions. Largest state had 20 variables. [2018-01-24 20:06:33,189 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 20:06:33,189 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:33,189 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:33,197 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:33,198 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:06:33,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:33,223 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:33,289 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 20:06:33,289 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:33,419 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 20:06:33,439 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:33,439 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:33,442 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:33,442 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:06:33,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:33,486 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:33,491 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 20:06:33,491 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:33,520 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 20:06:33,521 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:06:33,521 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 10, 10, 10, 10] total 25 [2018-01-24 20:06:33,521 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:06:33,522 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 20:06:33,522 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 20:06:33,522 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=440, Unknown=0, NotChecked=0, Total=600 [2018-01-24 20:06:33,522 INFO L87 Difference]: Start difference. First operand 77 states and 83 transitions. Second operand 17 states. [2018-01-24 20:06:33,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:33,695 INFO L93 Difference]: Finished difference Result 150 states and 163 transitions. [2018-01-24 20:06:33,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 20:06:33,696 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 60 [2018-01-24 20:06:33,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:33,696 INFO L225 Difference]: With dead ends: 150 [2018-01-24 20:06:33,696 INFO L226 Difference]: Without dead ends: 87 [2018-01-24 20:06:33,697 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 222 SyntacticMatches, 8 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 106 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=191, Invalid=621, Unknown=0, NotChecked=0, Total=812 [2018-01-24 20:06:33,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-01-24 20:06:33,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 84. [2018-01-24 20:06:33,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-01-24 20:06:33,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 90 transitions. [2018-01-24 20:06:33,703 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 90 transitions. Word has length 60 [2018-01-24 20:06:33,703 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:33,703 INFO L432 AbstractCegarLoop]: Abstraction has 84 states and 90 transitions. [2018-01-24 20:06:33,703 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 20:06:33,703 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 90 transitions. [2018-01-24 20:06:33,704 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-01-24 20:06:33,704 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:33,704 INFO L322 BasicCegarLoop]: trace histogram [7, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:33,705 INFO L371 AbstractCegarLoop]: === Iteration 17 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:33,705 INFO L82 PathProgramCache]: Analyzing trace with hash -374403177, now seen corresponding path program 2 times [2018-01-24 20:06:33,705 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:33,706 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:33,706 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:33,706 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:33,706 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:33,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:33,723 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:33,918 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 20:06:33,919 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:33,919 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:33,919 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:06:33,919 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:06:33,919 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:33,919 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:33,930 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:06:33,930 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:06:33,954 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:33,975 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:33,977 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:33,980 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:34,099 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 20:06:34,099 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:34,273 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 20:06:34,293 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:34,293 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:34,296 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:06:34,296 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:06:34,318 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:34,351 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:34,368 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:34,372 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:34,378 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 20:06:34,378 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:34,446 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 20:06:34,447 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:06:34,448 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 11, 11, 11] total 28 [2018-01-24 20:06:34,448 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:06:34,448 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 20:06:34,448 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 20:06:34,448 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=197, Invalid=559, Unknown=0, NotChecked=0, Total=756 [2018-01-24 20:06:34,448 INFO L87 Difference]: Start difference. First operand 84 states and 90 transitions. Second operand 19 states. [2018-01-24 20:06:34,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:34,695 INFO L93 Difference]: Finished difference Result 154 states and 166 transitions. [2018-01-24 20:06:34,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 20:06:34,695 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 67 [2018-01-24 20:06:34,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:34,696 INFO L225 Difference]: With dead ends: 154 [2018-01-24 20:06:34,696 INFO L226 Difference]: Without dead ends: 85 [2018-01-24 20:06:34,697 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 288 GetRequests, 250 SyntacticMatches, 8 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 123 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=229, Invalid=763, Unknown=0, NotChecked=0, Total=992 [2018-01-24 20:06:34,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-01-24 20:06:34,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-01-24 20:06:34,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-01-24 20:06:34,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 90 transitions. [2018-01-24 20:06:34,703 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 90 transitions. Word has length 67 [2018-01-24 20:06:34,703 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:34,703 INFO L432 AbstractCegarLoop]: Abstraction has 85 states and 90 transitions. [2018-01-24 20:06:34,703 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 20:06:34,703 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 90 transitions. [2018-01-24 20:06:34,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-01-24 20:06:34,704 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:34,704 INFO L322 BasicCegarLoop]: trace histogram [8, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:34,704 INFO L371 AbstractCegarLoop]: === Iteration 18 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:34,704 INFO L82 PathProgramCache]: Analyzing trace with hash -1696068192, now seen corresponding path program 3 times [2018-01-24 20:06:34,704 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:34,704 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:34,705 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:06:34,705 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:34,705 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:34,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:34,718 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:34,937 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-01-24 20:06:34,937 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:34,937 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:34,937 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:06:34,938 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:06:34,938 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:34,938 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:34,943 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:06:34,943 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:06:34,958 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:34,971 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:34,982 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:34,984 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:34,986 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:35,006 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 20:06:35,008 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 20:06:35,008 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,009 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,011 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,011 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:15, output treesize:11 [2018-01-24 20:06:35,023 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 20:06:35,025 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,025 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,025 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 20:06:35,026 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,029 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,033 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,033 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:24, output treesize:20 [2018-01-24 20:06:35,048 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 20:06:35,050 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,050 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,051 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,051 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,052 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,053 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,053 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 20:06:35,053 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,063 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,068 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,068 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:33, output treesize:29 [2018-01-24 20:06:35,086 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 20:06:35,088 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,089 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,090 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,090 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,091 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,092 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,092 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,093 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,093 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,094 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,094 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,095 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,096 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 20:06:35,096 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,111 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,117 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,117 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:38 [2018-01-24 20:06:35,146 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 20:06:35,149 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,149 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,150 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,150 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,151 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,152 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,152 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,153 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,153 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,154 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,154 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,155 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,155 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,156 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,157 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,157 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,158 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 20:06:35,158 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,180 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,186 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,187 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:51, output treesize:47 [2018-01-24 20:06:35,210 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 20:06:35,212 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,213 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,213 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,214 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,214 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,215 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,215 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,216 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,217 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,217 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,218 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,218 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,219 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,219 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,220 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,220 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,221 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,221 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,222 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,223 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,223 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,224 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 20:06:35,224 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,252 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,261 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,261 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:60, output treesize:56 [2018-01-24 20:06:35,301 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 20:06:35,304 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,304 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,305 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,305 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,306 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,306 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,307 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,307 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,308 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,308 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,309 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,309 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,310 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,310 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,311 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,311 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,312 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,312 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,313 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,313 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,314 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,315 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,315 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,316 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,316 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,317 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,317 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:35,318 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 20:06:35,318 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,357 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,366 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,366 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:69, output treesize:65 [2018-01-24 20:06:35,603 WARN L307 Elim1Store]: Array PQE input equivalent to false [2018-01-24 20:06:35,603 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,604 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:35,604 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:121, output treesize:1 [2018-01-24 20:06:35,618 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 20:06:35,618 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:36,013 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 20:06:36,033 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:36,033 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:36,036 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:06:36,036 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:06:36,058 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:36,086 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:36,164 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:36,200 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:36,207 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:36,214 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 20:06:36,216 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 20:06:36,216 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,217 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,219 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,219 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:15, output treesize:11 [2018-01-24 20:06:36,222 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 20:06:36,224 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,225 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,225 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 20:06:36,225 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,232 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,236 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,236 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:24, output treesize:20 [2018-01-24 20:06:36,239 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 20:06:36,241 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,241 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,242 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,243 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,243 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,244 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,244 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 20:06:36,245 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,254 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,259 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,260 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:33, output treesize:29 [2018-01-24 20:06:36,263 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 20:06:36,265 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,266 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,267 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,267 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,268 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,269 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,269 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,270 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,271 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,271 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,272 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,272 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,273 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 20:06:36,273 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,295 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,302 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,302 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:38 [2018-01-24 20:06:36,306 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 20:06:36,308 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,309 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,310 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,310 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,311 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,311 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,312 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,313 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,313 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,314 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,315 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,315 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,316 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,317 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,317 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,318 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,318 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 20:06:36,319 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,347 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,355 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,356 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:51, output treesize:47 [2018-01-24 20:06:36,359 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 20:06:36,362 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,363 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,363 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,364 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,365 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,366 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,366 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,367 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,368 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,368 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,369 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,370 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,370 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,371 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,372 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,372 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,373 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,374 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,375 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,375 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,376 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,377 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 20:06:36,377 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,414 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,422 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,422 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:60, output treesize:56 [2018-01-24 20:06:36,426 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 20:06:36,428 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,429 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,429 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,430 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,430 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,431 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,431 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,432 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,432 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,433 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,433 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,434 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,434 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,435 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,435 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,436 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,436 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,437 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,437 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,438 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,438 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,439 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,439 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,440 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,440 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,442 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,443 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 20:06:36,443 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 20:06:36,444 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,483 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,492 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 20:06:36,492 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:69, output treesize:65 [2018-01-24 20:06:37,011 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 20:06:37,011 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:37,254 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 20:06:37,256 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:06:37,256 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 17, 8, 17, 8] total 42 [2018-01-24 20:06:37,256 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:06:37,256 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 20:06:37,257 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 20:06:37,257 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=213, Invalid=1509, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 20:06:37,257 INFO L87 Difference]: Start difference. First operand 85 states and 90 transitions. Second operand 28 states. [2018-01-24 20:06:38,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:38,190 INFO L93 Difference]: Finished difference Result 130 states and 139 transitions. [2018-01-24 20:06:38,190 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 20:06:38,190 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 74 [2018-01-24 20:06:38,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:38,191 INFO L225 Difference]: With dead ends: 130 [2018-01-24 20:06:38,191 INFO L226 Difference]: Without dead ends: 94 [2018-01-24 20:06:38,192 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 248 SyntacticMatches, 28 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1458 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=476, Invalid=3556, Unknown=0, NotChecked=0, Total=4032 [2018-01-24 20:06:38,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-01-24 20:06:38,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 91. [2018-01-24 20:06:38,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-01-24 20:06:38,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 95 transitions. [2018-01-24 20:06:38,199 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 95 transitions. Word has length 74 [2018-01-24 20:06:38,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:38,199 INFO L432 AbstractCegarLoop]: Abstraction has 91 states and 95 transitions. [2018-01-24 20:06:38,199 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 20:06:38,199 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 95 transitions. [2018-01-24 20:06:38,200 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-01-24 20:06:38,200 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:38,200 INFO L322 BasicCegarLoop]: trace histogram [8, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:38,200 INFO L371 AbstractCegarLoop]: === Iteration 19 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:38,200 INFO L82 PathProgramCache]: Analyzing trace with hash 1151371872, now seen corresponding path program 4 times [2018-01-24 20:06:38,201 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:38,201 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:38,201 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:06:38,202 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:38,202 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:38,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:38,220 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:38,324 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:38,324 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:38,324 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:38,324 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:06:38,324 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:06:38,324 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:38,324 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:38,329 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:06:38,329 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:06:38,368 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:38,371 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:38,423 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:38,423 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:38,595 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:38,615 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:38,616 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:38,618 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:06:38,619 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:06:38,705 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:38,710 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:38,716 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:38,716 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:38,760 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:38,761 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:06:38,761 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 32 [2018-01-24 20:06:38,762 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:06:38,762 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 20:06:38,762 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 20:06:38,762 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=357, Invalid=635, Unknown=0, NotChecked=0, Total=992 [2018-01-24 20:06:38,762 INFO L87 Difference]: Start difference. First operand 91 states and 95 transitions. Second operand 22 states. [2018-01-24 20:06:38,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:38,797 INFO L93 Difference]: Finished difference Result 164 states and 172 transitions. [2018-01-24 20:06:38,797 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 20:06:38,797 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 86 [2018-01-24 20:06:38,797 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:38,798 INFO L225 Difference]: With dead ends: 164 [2018-01-24 20:06:38,798 INFO L226 Difference]: Without dead ends: 92 [2018-01-24 20:06:38,798 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 355 GetRequests, 322 SyntacticMatches, 2 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 374 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=380, Invalid=676, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 20:06:38,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states. [2018-01-24 20:06:38,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 92. [2018-01-24 20:06:38,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-01-24 20:06:38,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 96 transitions. [2018-01-24 20:06:38,804 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 96 transitions. Word has length 86 [2018-01-24 20:06:38,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:38,805 INFO L432 AbstractCegarLoop]: Abstraction has 92 states and 96 transitions. [2018-01-24 20:06:38,805 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 20:06:38,805 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 96 transitions. [2018-01-24 20:06:38,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 20:06:38,805 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:38,805 INFO L322 BasicCegarLoop]: trace histogram [9, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:38,806 INFO L371 AbstractCegarLoop]: === Iteration 20 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:38,806 INFO L82 PathProgramCache]: Analyzing trace with hash -1429474957, now seen corresponding path program 5 times [2018-01-24 20:06:38,806 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:38,806 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:38,806 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:06:38,807 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:38,807 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:38,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:38,820 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:38,955 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:38,955 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:38,955 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:38,955 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:06:38,955 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:06:38,955 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:38,955 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:38,961 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:06:38,962 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:06:38,970 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:38,971 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:38,975 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:38,982 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:38,992 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:39,009 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:39,013 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:39,016 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:39,084 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:39,084 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:39,397 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:39,425 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:39,425 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:39,428 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:06:39,429 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:06:39,438 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:39,440 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:39,452 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:39,483 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:39,591 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:40,056 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:40,081 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:40,087 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:40,093 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:40,093 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:40,139 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:40,140 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:06:40,141 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 35 [2018-01-24 20:06:40,141 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:06:40,141 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 20:06:40,141 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 20:06:40,142 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=426, Invalid=764, Unknown=0, NotChecked=0, Total=1190 [2018-01-24 20:06:40,142 INFO L87 Difference]: Start difference. First operand 92 states and 96 transitions. Second operand 24 states. [2018-01-24 20:06:40,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:40,228 INFO L93 Difference]: Finished difference Result 165 states and 173 transitions. [2018-01-24 20:06:40,270 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 20:06:40,271 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 87 [2018-01-24 20:06:40,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:40,271 INFO L225 Difference]: With dead ends: 165 [2018-01-24 20:06:40,271 INFO L226 Difference]: Without dead ends: 93 [2018-01-24 20:06:40,272 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 360 GetRequests, 324 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 457 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=451, Invalid=809, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 20:06:40,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-01-24 20:06:40,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2018-01-24 20:06:40,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-01-24 20:06:40,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 97 transitions. [2018-01-24 20:06:40,281 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 97 transitions. Word has length 87 [2018-01-24 20:06:40,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:40,282 INFO L432 AbstractCegarLoop]: Abstraction has 93 states and 97 transitions. [2018-01-24 20:06:40,282 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 20:06:40,282 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 97 transitions. [2018-01-24 20:06:40,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-01-24 20:06:40,283 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:40,283 INFO L322 BasicCegarLoop]: trace histogram [10, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:40,283 INFO L371 AbstractCegarLoop]: === Iteration 21 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:40,283 INFO L82 PathProgramCache]: Analyzing trace with hash 168651968, now seen corresponding path program 6 times [2018-01-24 20:06:40,283 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:40,284 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:40,284 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:06:40,284 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:40,284 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:40,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:40,304 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:40,475 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:40,475 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:40,475 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:40,475 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:06:40,475 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:06:40,475 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:40,476 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:40,486 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:06:40,487 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:06:40,508 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:06:40,525 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:06:40,541 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:06:40,586 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:06:40,655 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:06:40,803 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:06:40,805 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:40,808 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:40,877 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:40,877 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:41,112 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:41,133 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:41,133 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:41,137 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:06:41,137 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:06:41,164 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:06:41,190 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:06:41,237 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:06:41,492 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:06:42,128 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:06:43,751 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:06:43,783 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:43,789 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:43,795 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:43,795 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:43,839 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:43,840 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:06:43,841 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 38 [2018-01-24 20:06:43,841 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:06:43,841 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 20:06:43,841 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 20:06:43,842 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=501, Invalid=905, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 20:06:43,842 INFO L87 Difference]: Start difference. First operand 93 states and 97 transitions. Second operand 26 states. [2018-01-24 20:06:43,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:43,878 INFO L93 Difference]: Finished difference Result 166 states and 174 transitions. [2018-01-24 20:06:43,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 20:06:43,879 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 88 [2018-01-24 20:06:43,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:43,880 INFO L225 Difference]: With dead ends: 166 [2018-01-24 20:06:43,880 INFO L226 Difference]: Without dead ends: 94 [2018-01-24 20:06:43,881 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 365 GetRequests, 326 SyntacticMatches, 2 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 548 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=528, Invalid=954, Unknown=0, NotChecked=0, Total=1482 [2018-01-24 20:06:43,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-01-24 20:06:43,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 94. [2018-01-24 20:06:43,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-01-24 20:06:43,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 98 transitions. [2018-01-24 20:06:43,887 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 98 transitions. Word has length 88 [2018-01-24 20:06:43,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:43,887 INFO L432 AbstractCegarLoop]: Abstraction has 94 states and 98 transitions. [2018-01-24 20:06:43,887 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 20:06:43,887 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 98 transitions. [2018-01-24 20:06:43,888 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-01-24 20:06:43,888 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:43,888 INFO L322 BasicCegarLoop]: trace histogram [11, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:43,888 INFO L371 AbstractCegarLoop]: === Iteration 22 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:43,888 INFO L82 PathProgramCache]: Analyzing trace with hash -1829020909, now seen corresponding path program 7 times [2018-01-24 20:06:43,888 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:43,889 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:43,889 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:06:43,889 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:43,889 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:43,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:43,902 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:44,120 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:44,120 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:44,120 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:44,120 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:06:44,120 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:06:44,121 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:44,121 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:44,125 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:44,126 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:06:44,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:44,153 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:44,225 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:44,225 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:44,449 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:44,468 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:44,469 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:44,471 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:44,471 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:06:44,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:44,534 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:44,543 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:44,543 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:44,604 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:44,606 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:06:44,606 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 41 [2018-01-24 20:06:44,606 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:06:44,607 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 20:06:44,607 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 20:06:44,607 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=582, Invalid=1058, Unknown=0, NotChecked=0, Total=1640 [2018-01-24 20:06:44,608 INFO L87 Difference]: Start difference. First operand 94 states and 98 transitions. Second operand 28 states. [2018-01-24 20:06:44,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:44,654 INFO L93 Difference]: Finished difference Result 167 states and 175 transitions. [2018-01-24 20:06:44,657 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 20:06:44,657 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 89 [2018-01-24 20:06:44,658 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:44,658 INFO L225 Difference]: With dead ends: 167 [2018-01-24 20:06:44,658 INFO L226 Difference]: Without dead ends: 95 [2018-01-24 20:06:44,659 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 370 GetRequests, 328 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 647 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=611, Invalid=1111, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 20:06:44,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2018-01-24 20:06:44,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2018-01-24 20:06:44,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-01-24 20:06:44,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 99 transitions. [2018-01-24 20:06:44,668 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 99 transitions. Word has length 89 [2018-01-24 20:06:44,669 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:44,669 INFO L432 AbstractCegarLoop]: Abstraction has 95 states and 99 transitions. [2018-01-24 20:06:44,669 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 20:06:44,669 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 99 transitions. [2018-01-24 20:06:44,670 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-01-24 20:06:44,670 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:44,670 INFO L322 BasicCegarLoop]: trace histogram [12, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:44,670 INFO L371 AbstractCegarLoop]: === Iteration 23 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:44,670 INFO L82 PathProgramCache]: Analyzing trace with hash 667629344, now seen corresponding path program 8 times [2018-01-24 20:06:44,671 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:44,671 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:44,671 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:06:44,671 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:44,672 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:44,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:44,691 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:44,876 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:44,877 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:44,877 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:44,877 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:06:44,877 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:06:44,877 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:44,877 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:44,882 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:06:44,882 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:06:44,898 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:44,914 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:44,916 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:44,928 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:45,008 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:45,008 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:45,261 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:45,281 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:45,298 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:45,301 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:06:45,301 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:06:45,322 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:45,362 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:06:45,384 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:45,389 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:45,395 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:45,396 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:45,448 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:45,449 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:06:45,450 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 44 [2018-01-24 20:06:45,450 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:06:45,450 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 20:06:45,450 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 20:06:45,451 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=669, Invalid=1223, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 20:06:45,451 INFO L87 Difference]: Start difference. First operand 95 states and 99 transitions. Second operand 30 states. [2018-01-24 20:06:45,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:06:45,502 INFO L93 Difference]: Finished difference Result 168 states and 176 transitions. [2018-01-24 20:06:45,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 20:06:45,503 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 90 [2018-01-24 20:06:45,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:06:45,503 INFO L225 Difference]: With dead ends: 168 [2018-01-24 20:06:45,503 INFO L226 Difference]: Without dead ends: 96 [2018-01-24 20:06:45,504 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 375 GetRequests, 330 SyntacticMatches, 2 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 754 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=700, Invalid=1280, Unknown=0, NotChecked=0, Total=1980 [2018-01-24 20:06:45,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-01-24 20:06:45,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 96. [2018-01-24 20:06:45,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-01-24 20:06:45,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 100 transitions. [2018-01-24 20:06:45,510 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 100 transitions. Word has length 90 [2018-01-24 20:06:45,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:06:45,510 INFO L432 AbstractCegarLoop]: Abstraction has 96 states and 100 transitions. [2018-01-24 20:06:45,510 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 20:06:45,510 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 100 transitions. [2018-01-24 20:06:45,511 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-01-24 20:06:45,511 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:06:45,511 INFO L322 BasicCegarLoop]: trace histogram [13, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:06:45,511 INFO L371 AbstractCegarLoop]: === Iteration 24 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 20:06:45,511 INFO L82 PathProgramCache]: Analyzing trace with hash 754375859, now seen corresponding path program 9 times [2018-01-24 20:06:45,511 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:06:45,512 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:45,512 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:06:45,512 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:06:45,512 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:06:45,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:06:45,525 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:06:45,695 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:45,695 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:45,695 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:06:45,695 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:06:45,695 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:06:45,696 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:45,696 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:06:45,700 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:06:45,701 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:06:45,725 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:45,746 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:45,772 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:45,787 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:45,818 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:45,854 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:46,019 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:46,102 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:46,103 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:06:46,106 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:06:46,223 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:46,223 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:06:46,589 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:06:46,623 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:06:46,623 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:06:46,627 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:06:46,627 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:06:46,656 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:46,687 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:46,765 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:06:46,924 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command Received shutdown request... Cannot interrupt operation gracefully because timeout expired. Forcing shutdown