java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf -i ../../../trunk/examples/svcomp/array-examples/sanfoundry_24_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 20:01:03,717 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 20:01:03,718 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 20:01:03,734 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 20:01:03,735 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 20:01:03,736 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 20:01:03,737 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 20:01:03,739 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 20:01:03,741 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 20:01:03,742 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 20:01:03,743 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 20:01:03,743 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 20:01:03,744 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 20:01:03,745 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 20:01:03,746 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 20:01:03,749 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 20:01:03,751 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 20:01:03,754 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 20:01:03,755 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 20:01:03,756 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 20:01:03,759 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 20:01:03,759 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 20:01:03,759 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 20:01:03,760 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 20:01:03,761 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 20:01:03,763 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 20:01:03,763 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 20:01:03,764 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 20:01:03,764 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 20:01:03,764 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 20:01:03,765 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 20:01:03,765 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf [2018-01-24 20:01:03,774 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 20:01:03,774 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 20:01:03,775 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 20:01:03,775 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 20:01:03,775 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 20:01:03,775 INFO L133 SettingsManager]: * Weq Fattening=true [2018-01-24 20:01:03,776 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 20:01:03,776 INFO L133 SettingsManager]: * Precise comparison operator=true [2018-01-24 20:01:03,776 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 20:01:03,776 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 20:01:03,776 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 20:01:03,776 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 20:01:03,777 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 20:01:03,777 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 20:01:03,777 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 20:01:03,777 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 20:01:03,777 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 20:01:03,777 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 20:01:03,777 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 20:01:03,778 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 20:01:03,778 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 20:01:03,778 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 20:01:03,778 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 20:01:03,778 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 20:01:03,778 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 20:01:03,779 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 20:01:03,779 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 20:01:03,779 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 20:01:03,779 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 20:01:03,779 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 20:01:03,779 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 20:01:03,779 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 20:01:03,780 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 20:01:03,780 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 20:01:03,780 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 20:01:03,780 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 20:01:03,781 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 20:01:03,815 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 20:01:03,826 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 20:01:03,829 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 20:01:03,831 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 20:01:03,831 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 20:01:03,832 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/sanfoundry_24_false-valid-deref.i [2018-01-24 20:01:03,943 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 20:01:03,948 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 20:01:03,949 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 20:01:03,949 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 20:01:03,955 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 20:01:03,956 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 08:01:03" (1/1) ... [2018-01-24 20:01:03,958 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5823cf82 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:03, skipping insertion in model container [2018-01-24 20:01:03,959 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 08:01:03" (1/1) ... [2018-01-24 20:01:03,974 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 20:01:03,990 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 20:01:04,120 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 20:01:04,134 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 20:01:04,140 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:04 WrapperNode [2018-01-24 20:01:04,140 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 20:01:04,141 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 20:01:04,141 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 20:01:04,141 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 20:01:04,153 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:04" (1/1) ... [2018-01-24 20:01:04,153 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:04" (1/1) ... [2018-01-24 20:01:04,163 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:04" (1/1) ... [2018-01-24 20:01:04,163 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:04" (1/1) ... [2018-01-24 20:01:04,165 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:04" (1/1) ... [2018-01-24 20:01:04,169 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:04" (1/1) ... [2018-01-24 20:01:04,170 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:04" (1/1) ... [2018-01-24 20:01:04,171 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 20:01:04,172 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 20:01:04,172 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 20:01:04,172 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 20:01:04,173 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:04" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 20:01:04,229 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 20:01:04,229 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 20:01:04,229 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 20:01:04,230 INFO L136 BoogieDeclarations]: Found implementation of procedure printEven [2018-01-24 20:01:04,230 INFO L136 BoogieDeclarations]: Found implementation of procedure printOdd [2018-01-24 20:01:04,230 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 20:01:04,230 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 20:01:04,230 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 20:01:04,230 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-24 20:01:04,231 INFO L128 BoogieDeclarations]: Found specification of procedure printEven [2018-01-24 20:01:04,231 INFO L128 BoogieDeclarations]: Found specification of procedure printOdd [2018-01-24 20:01:04,231 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 20:01:04,231 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 20:01:04,231 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 20:01:04,385 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 20:01:04,385 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 08:01:04 BoogieIcfgContainer [2018-01-24 20:01:04,386 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 20:01:04,387 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 20:01:04,387 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 20:01:04,389 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 20:01:04,390 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 08:01:03" (1/3) ... [2018-01-24 20:01:04,391 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@17a17d0d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 08:01:04, skipping insertion in model container [2018-01-24 20:01:04,391 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:04" (2/3) ... [2018-01-24 20:01:04,392 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@17a17d0d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 08:01:04, skipping insertion in model container [2018-01-24 20:01:04,392 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 08:01:04" (3/3) ... [2018-01-24 20:01:04,394 INFO L105 eAbstractionObserver]: Analyzing ICFG sanfoundry_24_false-valid-deref.i [2018-01-24 20:01:04,405 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 20:01:04,415 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 4 error locations. [2018-01-24 20:01:04,467 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 20:01:04,467 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 20:01:04,467 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 20:01:04,467 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 20:01:04,467 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 20:01:04,468 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 20:01:04,468 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 20:01:04,468 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 20:01:04,469 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 20:01:04,491 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states. [2018-01-24 20:01:04,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 20:01:04,499 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:04,500 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:04,501 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:04,505 INFO L82 PathProgramCache]: Analyzing trace with hash 529177341, now seen corresponding path program 1 times [2018-01-24 20:01:04,508 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:04,550 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:04,550 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:04,550 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:04,550 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:04,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:04,592 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:04,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:04,663 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 20:01:04,663 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 20:01:04,664 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 20:01:04,667 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 20:01:04,679 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 20:01:04,680 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 20:01:04,682 INFO L87 Difference]: Start difference. First operand 42 states. Second operand 3 states. [2018-01-24 20:01:04,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:04,788 INFO L93 Difference]: Finished difference Result 97 states and 129 transitions. [2018-01-24 20:01:04,788 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 20:01:04,789 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 8 [2018-01-24 20:01:04,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:04,798 INFO L225 Difference]: With dead ends: 97 [2018-01-24 20:01:04,798 INFO L226 Difference]: Without dead ends: 51 [2018-01-24 20:01:04,803 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 20:01:04,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-01-24 20:01:04,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 46. [2018-01-24 20:01:04,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-01-24 20:01:04,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 53 transitions. [2018-01-24 20:01:04,911 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 53 transitions. Word has length 8 [2018-01-24 20:01:04,911 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:04,911 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 53 transitions. [2018-01-24 20:01:04,911 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 20:01:04,911 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 53 transitions. [2018-01-24 20:01:04,912 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-01-24 20:01:04,913 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:04,913 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:04,913 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:04,913 INFO L82 PathProgramCache]: Analyzing trace with hash -2078569521, now seen corresponding path program 1 times [2018-01-24 20:01:04,913 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:04,915 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:04,915 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:04,915 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:04,915 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:04,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:04,931 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:04,988 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:04,989 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:04,989 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:04,990 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 14 with the following transitions: [2018-01-24 20:01:04,992 INFO L201 CegarAbsIntRunner]: [0], [10], [14], [19], [20], [21], [29], [31], [74], [75], [76] [2018-01-24 20:01:05,047 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 20:01:05,047 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 20:01:05,133 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 20:01:05,135 INFO L268 AbstractInterpreter]: Visited 11 different actions 17 times. Merged at 6 different actions 6 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 5 variables. [2018-01-24 20:01:05,150 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 20:01:05,150 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:05,151 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:05,157 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:05,157 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:01:05,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:05,175 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:05,188 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:05,189 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:05,236 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:05,268 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:05,268 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:05,272 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:05,272 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:01:05,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:05,285 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:05,293 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:05,294 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:05,310 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:05,311 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:05,311 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3, 3, 3] total 5 [2018-01-24 20:01:05,311 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:05,312 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 20:01:05,313 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 20:01:05,313 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 20:01:05,313 INFO L87 Difference]: Start difference. First operand 46 states and 53 transitions. Second operand 4 states. [2018-01-24 20:01:05,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:05,435 INFO L93 Difference]: Finished difference Result 70 states and 84 transitions. [2018-01-24 20:01:05,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 20:01:05,436 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2018-01-24 20:01:05,436 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:05,437 INFO L225 Difference]: With dead ends: 70 [2018-01-24 20:01:05,437 INFO L226 Difference]: Without dead ends: 66 [2018-01-24 20:01:05,438 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 47 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 20:01:05,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-01-24 20:01:05,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 60. [2018-01-24 20:01:05,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-01-24 20:01:05,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 72 transitions. [2018-01-24 20:01:05,446 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 72 transitions. Word has length 13 [2018-01-24 20:01:05,446 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:05,446 INFO L432 AbstractCegarLoop]: Abstraction has 60 states and 72 transitions. [2018-01-24 20:01:05,446 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 20:01:05,446 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 72 transitions. [2018-01-24 20:01:05,447 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-01-24 20:01:05,447 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:05,447 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:05,447 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:05,447 INFO L82 PathProgramCache]: Analyzing trace with hash 1794788925, now seen corresponding path program 2 times [2018-01-24 20:01:05,448 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:05,448 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:05,449 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:05,449 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:05,449 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:05,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:05,457 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:05,539 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:05,539 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:05,539 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:05,539 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:05,540 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:05,540 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:05,540 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:05,553 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:01:05,553 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:05,560 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:05,562 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:05,563 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:05,565 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:05,574 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:05,574 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:05,695 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:05,720 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:05,720 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:05,723 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:01:05,723 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:05,727 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:05,731 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:05,735 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:05,738 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:05,744 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:05,744 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:05,769 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:05,770 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:05,771 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 7 [2018-01-24 20:01:05,771 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:05,771 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 20:01:05,771 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 20:01:05,771 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 20:01:05,771 INFO L87 Difference]: Start difference. First operand 60 states and 72 transitions. Second operand 5 states. [2018-01-24 20:01:05,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:05,914 INFO L93 Difference]: Finished difference Result 85 states and 104 transitions. [2018-01-24 20:01:05,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 20:01:05,914 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 18 [2018-01-24 20:01:05,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:05,916 INFO L225 Difference]: With dead ends: 85 [2018-01-24 20:01:05,916 INFO L226 Difference]: Without dead ends: 81 [2018-01-24 20:01:05,917 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 66 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 20:01:05,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-01-24 20:01:05,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 74. [2018-01-24 20:01:05,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-24 20:01:05,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 91 transitions. [2018-01-24 20:01:05,927 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 91 transitions. Word has length 18 [2018-01-24 20:01:05,927 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:05,927 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 91 transitions. [2018-01-24 20:01:05,927 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 20:01:05,927 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 91 transitions. [2018-01-24 20:01:05,928 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-01-24 20:01:05,929 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:05,929 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:05,929 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:05,929 INFO L82 PathProgramCache]: Analyzing trace with hash -424025969, now seen corresponding path program 3 times [2018-01-24 20:01:05,929 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:05,930 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:05,930 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:05,930 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:05,930 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:05,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:05,943 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:06,018 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:06,018 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:06,018 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:06,019 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:06,019 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:06,019 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:06,019 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:06,032 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:01:06,032 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:01:06,038 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:06,040 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:06,042 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:06,045 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:06,046 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:06,048 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:06,059 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:06,059 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:06,120 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:06,140 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:06,140 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:06,143 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:01:06,144 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:01:06,148 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:06,151 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:06,156 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:06,163 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:06,167 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:06,171 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:06,177 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:06,177 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:06,186 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:06,187 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:06,187 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 20:01:06,187 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:06,188 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 20:01:06,188 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 20:01:06,188 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 20:01:06,189 INFO L87 Difference]: Start difference. First operand 74 states and 91 transitions. Second operand 6 states. [2018-01-24 20:01:06,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:06,344 INFO L93 Difference]: Finished difference Result 100 states and 124 transitions. [2018-01-24 20:01:06,344 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 20:01:06,344 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 23 [2018-01-24 20:01:06,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:06,345 INFO L225 Difference]: With dead ends: 100 [2018-01-24 20:01:06,346 INFO L226 Difference]: Without dead ends: 96 [2018-01-24 20:01:06,346 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 85 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 20:01:06,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-01-24 20:01:06,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 88. [2018-01-24 20:01:06,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-01-24 20:01:06,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 110 transitions. [2018-01-24 20:01:06,354 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 110 transitions. Word has length 23 [2018-01-24 20:01:06,354 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:06,354 INFO L432 AbstractCegarLoop]: Abstraction has 88 states and 110 transitions. [2018-01-24 20:01:06,354 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 20:01:06,354 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 110 transitions. [2018-01-24 20:01:06,355 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-01-24 20:01:06,355 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:06,356 INFO L322 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:06,356 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:06,356 INFO L82 PathProgramCache]: Analyzing trace with hash -1714228867, now seen corresponding path program 4 times [2018-01-24 20:01:06,356 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:06,357 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:06,357 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:06,358 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:06,358 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:06,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:06,368 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:06,469 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:06,469 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:06,469 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:06,469 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:06,470 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:06,470 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:06,470 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:06,475 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:01:06,475 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:01:06,483 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:06,484 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:06,491 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:06,491 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:06,590 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:06,609 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:06,609 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:06,612 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:01:06,612 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:01:06,630 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:06,633 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:06,641 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:06,641 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:06,656 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:06,657 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:06,657 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 20:01:06,658 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:06,658 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 20:01:06,658 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 20:01:06,658 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 20:01:06,658 INFO L87 Difference]: Start difference. First operand 88 states and 110 transitions. Second operand 7 states. [2018-01-24 20:01:06,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:06,856 INFO L93 Difference]: Finished difference Result 115 states and 144 transitions. [2018-01-24 20:01:06,857 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 20:01:06,857 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 28 [2018-01-24 20:01:06,857 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:06,858 INFO L225 Difference]: With dead ends: 115 [2018-01-24 20:01:06,859 INFO L226 Difference]: Without dead ends: 111 [2018-01-24 20:01:06,859 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 116 GetRequests, 104 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 20:01:06,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-01-24 20:01:06,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 102. [2018-01-24 20:01:06,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-01-24 20:01:06,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 129 transitions. [2018-01-24 20:01:06,871 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 129 transitions. Word has length 28 [2018-01-24 20:01:06,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:06,871 INFO L432 AbstractCegarLoop]: Abstraction has 102 states and 129 transitions. [2018-01-24 20:01:06,871 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 20:01:06,872 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 129 transitions. [2018-01-24 20:01:06,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-01-24 20:01:06,874 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:06,874 INFO L322 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:06,874 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:06,874 INFO L82 PathProgramCache]: Analyzing trace with hash -771406513, now seen corresponding path program 5 times [2018-01-24 20:01:06,874 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:06,875 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:06,875 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:06,876 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:06,876 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:06,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:06,889 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:06,981 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:06,981 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:06,981 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:06,981 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:06,982 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:06,982 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:06,982 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:06,990 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:01:06,991 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:06,994 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:06,995 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:06,996 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:06,998 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:06,999 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:07,001 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:07,001 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:07,003 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:07,010 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:07,011 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:07,109 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:07,130 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:07,130 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:07,154 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:01:07,154 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:07,158 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:07,162 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:07,167 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:07,176 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:07,184 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:07,194 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:07,202 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:07,206 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:07,229 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:07,229 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:07,266 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:07,271 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:07,271 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 20:01:07,271 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:07,272 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 20:01:07,272 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 20:01:07,272 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 20:01:07,272 INFO L87 Difference]: Start difference. First operand 102 states and 129 transitions. Second operand 8 states. [2018-01-24 20:01:07,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:07,480 INFO L93 Difference]: Finished difference Result 130 states and 164 transitions. [2018-01-24 20:01:07,517 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 20:01:07,517 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 33 [2018-01-24 20:01:07,517 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:07,518 INFO L225 Difference]: With dead ends: 130 [2018-01-24 20:01:07,518 INFO L226 Difference]: Without dead ends: 126 [2018-01-24 20:01:07,519 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 123 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 20:01:07,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-01-24 20:01:07,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 116. [2018-01-24 20:01:07,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 116 states. [2018-01-24 20:01:07,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 148 transitions. [2018-01-24 20:01:07,531 INFO L78 Accepts]: Start accepts. Automaton has 116 states and 148 transitions. Word has length 33 [2018-01-24 20:01:07,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:07,532 INFO L432 AbstractCegarLoop]: Abstraction has 116 states and 148 transitions. [2018-01-24 20:01:07,532 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 20:01:07,532 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 148 transitions. [2018-01-24 20:01:07,534 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-01-24 20:01:07,534 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:07,534 INFO L322 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 6, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:07,534 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:07,534 INFO L82 PathProgramCache]: Analyzing trace with hash -240614211, now seen corresponding path program 6 times [2018-01-24 20:01:07,534 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:07,535 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:07,535 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:07,536 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:07,536 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:07,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:07,550 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:07,633 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:07,633 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:07,633 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:07,633 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:07,633 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:07,634 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:07,634 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:07,639 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:01:07,639 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:01:07,643 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:07,644 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:07,646 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:07,648 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:07,649 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:07,651 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:07,653 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:07,653 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:07,656 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:07,669 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:07,669 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:07,778 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:07,798 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:07,798 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:07,801 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:01:07,801 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:01:07,805 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:07,807 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:07,812 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:07,818 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:07,825 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:07,832 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:07,841 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:07,848 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:07,851 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:07,860 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:07,860 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:07,869 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:07,871 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:07,871 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 20:01:07,871 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:07,871 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 20:01:07,871 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 20:01:07,872 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 20:01:07,872 INFO L87 Difference]: Start difference. First operand 116 states and 148 transitions. Second operand 9 states. [2018-01-24 20:01:08,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:08,180 INFO L93 Difference]: Finished difference Result 145 states and 184 transitions. [2018-01-24 20:01:08,180 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 20:01:08,180 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 38 [2018-01-24 20:01:08,181 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:08,182 INFO L225 Difference]: With dead ends: 145 [2018-01-24 20:01:08,182 INFO L226 Difference]: Without dead ends: 141 [2018-01-24 20:01:08,182 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 142 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 20:01:08,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-01-24 20:01:08,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 130. [2018-01-24 20:01:08,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-01-24 20:01:08,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 167 transitions. [2018-01-24 20:01:08,194 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 167 transitions. Word has length 38 [2018-01-24 20:01:08,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:08,194 INFO L432 AbstractCegarLoop]: Abstraction has 130 states and 167 transitions. [2018-01-24 20:01:08,194 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 20:01:08,194 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 167 transitions. [2018-01-24 20:01:08,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-01-24 20:01:08,196 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:08,197 INFO L322 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 7, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:08,197 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:08,197 INFO L82 PathProgramCache]: Analyzing trace with hash 1558821391, now seen corresponding path program 7 times [2018-01-24 20:01:08,197 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:08,198 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:08,198 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:08,198 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:08,198 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:08,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:08,211 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:08,326 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:08,327 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:08,327 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:08,327 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:08,327 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:08,327 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:08,327 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:08,339 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:08,339 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:01:08,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:08,351 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:08,362 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:08,362 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:08,455 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:08,475 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:08,476 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:08,479 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:08,479 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:01:08,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:08,498 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:08,507 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:08,507 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:08,517 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:08,518 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:08,518 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 20:01:08,518 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:08,519 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 20:01:08,519 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 20:01:08,519 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 20:01:08,519 INFO L87 Difference]: Start difference. First operand 130 states and 167 transitions. Second operand 10 states. [2018-01-24 20:01:08,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:08,890 INFO L93 Difference]: Finished difference Result 160 states and 204 transitions. [2018-01-24 20:01:08,890 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 20:01:08,890 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 43 [2018-01-24 20:01:08,891 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:08,891 INFO L225 Difference]: With dead ends: 160 [2018-01-24 20:01:08,892 INFO L226 Difference]: Without dead ends: 156 [2018-01-24 20:01:08,892 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 179 GetRequests, 161 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 20:01:08,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-01-24 20:01:08,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 144. [2018-01-24 20:01:08,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-01-24 20:01:08,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 186 transitions. [2018-01-24 20:01:08,903 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 186 transitions. Word has length 43 [2018-01-24 20:01:08,904 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:08,904 INFO L432 AbstractCegarLoop]: Abstraction has 144 states and 186 transitions. [2018-01-24 20:01:08,904 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 20:01:08,904 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 186 transitions. [2018-01-24 20:01:08,906 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-01-24 20:01:08,906 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:08,906 INFO L322 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 8, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:08,906 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:08,906 INFO L82 PathProgramCache]: Analyzing trace with hash -821098499, now seen corresponding path program 8 times [2018-01-24 20:01:08,907 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:08,908 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:08,908 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:08,908 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:08,908 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:08,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:08,921 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:09,043 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:09,044 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:09,044 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:09,044 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:09,044 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:09,044 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:09,044 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:09,050 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:01:09,050 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:09,054 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:09,059 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:09,061 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:09,063 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:09,072 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:09,072 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:09,210 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:09,231 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:09,232 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:09,235 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:01:09,235 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:09,239 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:09,246 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:09,256 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:09,260 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:09,274 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:09,274 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:09,286 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:09,288 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:09,289 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 20:01:09,289 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:09,289 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 20:01:09,290 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 20:01:09,290 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 20:01:09,290 INFO L87 Difference]: Start difference. First operand 144 states and 186 transitions. Second operand 11 states. [2018-01-24 20:01:10,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:10,270 INFO L93 Difference]: Finished difference Result 175 states and 224 transitions. [2018-01-24 20:01:10,270 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 20:01:10,270 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 48 [2018-01-24 20:01:10,270 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:10,272 INFO L225 Difference]: With dead ends: 175 [2018-01-24 20:01:10,272 INFO L226 Difference]: Without dead ends: 171 [2018-01-24 20:01:10,272 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 200 GetRequests, 180 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 20:01:10,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-01-24 20:01:10,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 158. [2018-01-24 20:01:10,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-01-24 20:01:10,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 205 transitions. [2018-01-24 20:01:10,282 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 205 transitions. Word has length 48 [2018-01-24 20:01:10,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:10,283 INFO L432 AbstractCegarLoop]: Abstraction has 158 states and 205 transitions. [2018-01-24 20:01:10,283 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 20:01:10,283 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 205 transitions. [2018-01-24 20:01:10,284 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-01-24 20:01:10,284 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:10,284 INFO L322 BasicCegarLoop]: trace histogram [10, 10, 9, 9, 9, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:10,284 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:10,284 INFO L82 PathProgramCache]: Analyzing trace with hash -413974833, now seen corresponding path program 9 times [2018-01-24 20:01:10,284 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:10,285 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:10,285 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:10,285 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:10,285 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:10,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:10,296 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:10,550 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:10,550 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:10,550 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:10,551 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:10,551 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:10,551 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:10,551 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:10,557 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:01:10,557 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:01:10,560 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,562 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,563 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,564 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,566 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,567 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,569 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,571 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,574 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,576 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,577 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:10,579 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:10,592 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:10,593 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:10,765 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:10,786 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:10,786 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:10,789 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:01:10,789 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:01:10,793 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,795 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,800 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,806 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,813 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,821 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,830 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,840 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,852 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,864 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:10,874 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:10,878 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:10,890 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:10,890 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:10,904 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:10,905 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:10,906 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 20:01:10,906 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:10,906 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 20:01:10,906 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 20:01:10,906 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 20:01:10,907 INFO L87 Difference]: Start difference. First operand 158 states and 205 transitions. Second operand 12 states. [2018-01-24 20:01:11,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:11,406 INFO L93 Difference]: Finished difference Result 190 states and 244 transitions. [2018-01-24 20:01:11,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 20:01:11,406 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 53 [2018-01-24 20:01:11,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:11,407 INFO L225 Difference]: With dead ends: 190 [2018-01-24 20:01:11,407 INFO L226 Difference]: Without dead ends: 186 [2018-01-24 20:01:11,408 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 221 GetRequests, 199 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 20:01:11,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-01-24 20:01:11,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 172. [2018-01-24 20:01:11,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-01-24 20:01:11,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 224 transitions. [2018-01-24 20:01:11,419 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 224 transitions. Word has length 53 [2018-01-24 20:01:11,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:11,419 INFO L432 AbstractCegarLoop]: Abstraction has 172 states and 224 transitions. [2018-01-24 20:01:11,419 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 20:01:11,420 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 224 transitions. [2018-01-24 20:01:11,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-01-24 20:01:11,421 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:11,421 INFO L322 BasicCegarLoop]: trace histogram [11, 11, 10, 10, 10, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:11,422 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:11,422 INFO L82 PathProgramCache]: Analyzing trace with hash -442860739, now seen corresponding path program 10 times [2018-01-24 20:01:11,422 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:11,423 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:11,423 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:11,423 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:11,423 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:11,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:11,436 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:11,566 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:11,566 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:11,566 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:11,566 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:11,566 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:11,566 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:11,566 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:11,572 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:01:11,572 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:01:11,584 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:11,585 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:11,595 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:11,595 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:11,760 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:11,780 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:11,780 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:11,783 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:01:11,783 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:01:11,816 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:11,820 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:11,829 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:11,829 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:11,839 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:11,841 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:11,841 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 20:01:11,841 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:11,841 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 20:01:11,841 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 20:01:11,842 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 20:01:11,842 INFO L87 Difference]: Start difference. First operand 172 states and 224 transitions. Second operand 13 states. [2018-01-24 20:01:12,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:12,393 INFO L93 Difference]: Finished difference Result 205 states and 264 transitions. [2018-01-24 20:01:12,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 20:01:12,393 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 58 [2018-01-24 20:01:12,393 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:12,395 INFO L225 Difference]: With dead ends: 205 [2018-01-24 20:01:12,395 INFO L226 Difference]: Without dead ends: 201 [2018-01-24 20:01:12,395 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 242 GetRequests, 218 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 20:01:12,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2018-01-24 20:01:12,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 186. [2018-01-24 20:01:12,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-01-24 20:01:12,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 243 transitions. [2018-01-24 20:01:12,407 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 243 transitions. Word has length 58 [2018-01-24 20:01:12,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:12,407 INFO L432 AbstractCegarLoop]: Abstraction has 186 states and 243 transitions. [2018-01-24 20:01:12,407 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 20:01:12,407 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 243 transitions. [2018-01-24 20:01:12,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-01-24 20:01:12,409 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:12,409 INFO L322 BasicCegarLoop]: trace histogram [12, 12, 11, 11, 11, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:12,409 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:12,410 INFO L82 PathProgramCache]: Analyzing trace with hash -634530929, now seen corresponding path program 11 times [2018-01-24 20:01:12,410 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:12,411 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:12,411 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:12,411 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:12,411 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:12,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:12,422 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:12,581 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:12,581 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:12,581 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:12,581 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:12,581 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:12,581 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:12,581 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:12,589 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:01:12,589 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:12,592 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,593 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,595 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,596 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,598 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,599 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,601 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,602 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,603 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,605 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,607 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,609 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,609 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:12,611 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:12,624 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:12,624 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:12,796 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:12,817 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:12,817 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:12,820 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:01:12,821 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:12,824 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,826 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,831 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,838 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,845 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,854 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,864 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,875 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,887 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,900 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,914 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,930 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:12,941 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:12,944 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:12,959 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:12,959 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:12,992 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:12,994 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:12,994 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 20:01:12,994 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:12,994 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 20:01:12,994 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 20:01:12,995 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 20:01:12,995 INFO L87 Difference]: Start difference. First operand 186 states and 243 transitions. Second operand 14 states. [2018-01-24 20:01:13,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:13,617 INFO L93 Difference]: Finished difference Result 220 states and 284 transitions. [2018-01-24 20:01:13,618 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 20:01:13,618 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 63 [2018-01-24 20:01:13,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:13,619 INFO L225 Difference]: With dead ends: 220 [2018-01-24 20:01:13,620 INFO L226 Difference]: Without dead ends: 216 [2018-01-24 20:01:13,620 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 263 GetRequests, 237 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 20:01:13,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-01-24 20:01:13,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 200. [2018-01-24 20:01:13,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 200 states. [2018-01-24 20:01:13,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200 states to 200 states and 262 transitions. [2018-01-24 20:01:13,633 INFO L78 Accepts]: Start accepts. Automaton has 200 states and 262 transitions. Word has length 63 [2018-01-24 20:01:13,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:13,633 INFO L432 AbstractCegarLoop]: Abstraction has 200 states and 262 transitions. [2018-01-24 20:01:13,633 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 20:01:13,633 INFO L276 IsEmpty]: Start isEmpty. Operand 200 states and 262 transitions. [2018-01-24 20:01:13,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-01-24 20:01:13,635 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:13,635 INFO L322 BasicCegarLoop]: trace histogram [13, 13, 12, 12, 12, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:13,635 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:13,635 INFO L82 PathProgramCache]: Analyzing trace with hash 2145312381, now seen corresponding path program 12 times [2018-01-24 20:01:13,636 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:13,636 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:13,636 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:13,637 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:13,637 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:13,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:13,650 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:13,805 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:13,805 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:13,805 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:13,805 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:13,805 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:13,806 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:13,806 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:13,811 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:01:13,811 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:01:13,814 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:13,815 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:13,816 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:13,818 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:13,819 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:13,820 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:13,821 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:13,823 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:13,824 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:13,826 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:13,828 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:13,829 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:13,831 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:13,832 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:13,833 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:13,847 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:13,847 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:14,054 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:14,073 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:14,074 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:14,076 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:01:14,077 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:01:14,081 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:14,083 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:14,087 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:14,093 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:14,099 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:14,107 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:14,116 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:14,126 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:14,137 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:14,149 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:14,163 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:14,177 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:14,193 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:14,205 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:14,209 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:14,220 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:14,220 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:14,239 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:14,241 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:14,241 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 27 [2018-01-24 20:01:14,241 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:14,241 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 20:01:14,242 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 20:01:14,242 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 20:01:14,242 INFO L87 Difference]: Start difference. First operand 200 states and 262 transitions. Second operand 15 states. [2018-01-24 20:01:14,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:14,977 INFO L93 Difference]: Finished difference Result 235 states and 304 transitions. [2018-01-24 20:01:14,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 20:01:14,977 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2018-01-24 20:01:14,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:14,978 INFO L225 Difference]: With dead ends: 235 [2018-01-24 20:01:14,979 INFO L226 Difference]: Without dead ends: 231 [2018-01-24 20:01:14,979 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 284 GetRequests, 256 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 20:01:14,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states. [2018-01-24 20:01:14,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 214. [2018-01-24 20:01:14,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-01-24 20:01:14,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 281 transitions. [2018-01-24 20:01:14,992 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 281 transitions. Word has length 68 [2018-01-24 20:01:14,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:14,992 INFO L432 AbstractCegarLoop]: Abstraction has 214 states and 281 transitions. [2018-01-24 20:01:14,992 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 20:01:14,992 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 281 transitions. [2018-01-24 20:01:14,994 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-01-24 20:01:14,994 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:14,994 INFO L322 BasicCegarLoop]: trace histogram [14, 14, 13, 13, 13, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:14,994 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:14,994 INFO L82 PathProgramCache]: Analyzing trace with hash 1734703183, now seen corresponding path program 13 times [2018-01-24 20:01:14,994 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:14,995 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:14,995 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:14,995 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:14,995 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:15,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:15,010 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:15,249 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:15,250 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:15,250 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:15,250 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:15,250 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:15,250 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:15,250 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:15,257 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:15,258 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:01:15,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:15,270 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:15,286 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:15,287 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:15,537 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:15,557 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:15,557 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:15,560 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:15,560 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:01:15,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:15,587 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:15,603 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:15,603 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:15,626 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:15,628 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:15,628 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 29 [2018-01-24 20:01:15,628 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:15,628 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 20:01:15,629 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 20:01:15,629 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 20:01:15,629 INFO L87 Difference]: Start difference. First operand 214 states and 281 transitions. Second operand 16 states. [2018-01-24 20:01:16,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:16,475 INFO L93 Difference]: Finished difference Result 250 states and 324 transitions. [2018-01-24 20:01:16,475 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 20:01:16,475 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 73 [2018-01-24 20:01:16,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:16,476 INFO L225 Difference]: With dead ends: 250 [2018-01-24 20:01:16,477 INFO L226 Difference]: Without dead ends: 246 [2018-01-24 20:01:16,477 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 305 GetRequests, 275 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 20:01:16,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-01-24 20:01:16,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 228. [2018-01-24 20:01:16,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-01-24 20:01:16,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 300 transitions. [2018-01-24 20:01:16,489 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 300 transitions. Word has length 73 [2018-01-24 20:01:16,489 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:16,490 INFO L432 AbstractCegarLoop]: Abstraction has 228 states and 300 transitions. [2018-01-24 20:01:16,490 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 20:01:16,490 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 300 transitions. [2018-01-24 20:01:16,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-24 20:01:16,491 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:16,492 INFO L322 BasicCegarLoop]: trace histogram [15, 15, 14, 14, 14, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:16,492 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:16,492 INFO L82 PathProgramCache]: Analyzing trace with hash -1083166275, now seen corresponding path program 14 times [2018-01-24 20:01:16,492 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:16,493 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:16,493 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:16,493 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:16,493 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:16,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:16,508 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:16,827 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:16,827 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:16,827 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:16,827 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:16,827 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:16,827 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:16,828 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:16,834 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:01:16,834 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:16,838 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:16,857 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:16,870 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:16,872 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:16,908 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:16,908 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:17,323 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:17,343 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:17,343 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:17,347 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:01:17,347 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:17,353 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:17,366 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:17,388 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:17,393 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:17,415 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:17,415 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:17,431 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:17,432 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:17,432 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 31 [2018-01-24 20:01:17,432 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:17,432 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 20:01:17,432 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 20:01:17,433 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 20:01:17,433 INFO L87 Difference]: Start difference. First operand 228 states and 300 transitions. Second operand 17 states. [2018-01-24 20:01:18,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:18,352 INFO L93 Difference]: Finished difference Result 265 states and 344 transitions. [2018-01-24 20:01:18,352 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 20:01:18,352 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 78 [2018-01-24 20:01:18,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:18,353 INFO L225 Difference]: With dead ends: 265 [2018-01-24 20:01:18,354 INFO L226 Difference]: Without dead ends: 261 [2018-01-24 20:01:18,354 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 326 GetRequests, 294 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 20:01:18,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 261 states. [2018-01-24 20:01:18,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 261 to 242. [2018-01-24 20:01:18,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 242 states. [2018-01-24 20:01:18,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242 states to 242 states and 319 transitions. [2018-01-24 20:01:18,368 INFO L78 Accepts]: Start accepts. Automaton has 242 states and 319 transitions. Word has length 78 [2018-01-24 20:01:18,368 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:18,369 INFO L432 AbstractCegarLoop]: Abstraction has 242 states and 319 transitions. [2018-01-24 20:01:18,369 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 20:01:18,369 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 319 transitions. [2018-01-24 20:01:18,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-01-24 20:01:18,371 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:18,371 INFO L322 BasicCegarLoop]: trace histogram [16, 16, 15, 15, 15, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:18,371 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:18,371 INFO L82 PathProgramCache]: Analyzing trace with hash 1239821583, now seen corresponding path program 15 times [2018-01-24 20:01:18,371 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:18,372 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:18,372 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:18,372 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:18,372 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:18,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:18,385 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:18,592 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:18,592 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:18,592 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:18,593 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:18,593 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:18,593 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:18,593 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:18,604 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:01:18,604 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:01:18,608 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,610 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,611 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,612 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,614 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,616 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,617 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,619 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,622 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,624 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,626 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,629 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,631 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,634 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,636 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,638 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,639 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:18,641 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:18,654 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:18,654 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:18,961 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:18,981 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:18,981 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:18,984 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:01:18,984 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:01:18,988 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,990 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:18,995 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:19,000 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:19,007 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:19,014 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:19,023 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:19,033 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:19,044 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:19,056 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:19,068 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:19,083 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:19,099 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:19,115 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:19,132 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:19,151 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:19,174 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:19,178 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:19,195 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:19,196 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:19,215 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:19,216 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:19,217 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 33 [2018-01-24 20:01:19,217 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:19,217 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 20:01:19,217 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 20:01:19,217 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 20:01:19,217 INFO L87 Difference]: Start difference. First operand 242 states and 319 transitions. Second operand 18 states. [2018-01-24 20:01:20,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:20,322 INFO L93 Difference]: Finished difference Result 280 states and 364 transitions. [2018-01-24 20:01:20,322 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 20:01:20,322 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 83 [2018-01-24 20:01:20,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:20,324 INFO L225 Difference]: With dead ends: 280 [2018-01-24 20:01:20,324 INFO L226 Difference]: Without dead ends: 276 [2018-01-24 20:01:20,325 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 347 GetRequests, 313 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 20:01:20,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states. [2018-01-24 20:01:20,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 256. [2018-01-24 20:01:20,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 256 states. [2018-01-24 20:01:20,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 256 states to 256 states and 338 transitions. [2018-01-24 20:01:20,344 INFO L78 Accepts]: Start accepts. Automaton has 256 states and 338 transitions. Word has length 83 [2018-01-24 20:01:20,345 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:20,345 INFO L432 AbstractCegarLoop]: Abstraction has 256 states and 338 transitions. [2018-01-24 20:01:20,345 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 20:01:20,346 INFO L276 IsEmpty]: Start isEmpty. Operand 256 states and 338 transitions. [2018-01-24 20:01:20,347 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-01-24 20:01:20,348 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:20,348 INFO L322 BasicCegarLoop]: trace histogram [17, 17, 16, 16, 16, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:20,348 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:20,348 INFO L82 PathProgramCache]: Analyzing trace with hash -589138691, now seen corresponding path program 16 times [2018-01-24 20:01:20,348 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:20,350 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:20,351 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:20,351 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:20,351 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:20,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:20,370 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:20,634 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:20,635 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:20,635 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:20,635 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:20,635 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:20,635 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:20,635 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:20,640 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:01:20,641 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:01:20,658 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:20,660 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:20,682 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:20,682 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:21,087 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:21,107 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:21,107 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:21,111 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:01:21,111 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:01:21,162 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:21,167 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:21,188 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:21,188 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:21,207 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:21,209 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:21,209 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 35 [2018-01-24 20:01:21,209 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:21,209 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 20:01:21,210 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 20:01:21,210 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 20:01:21,210 INFO L87 Difference]: Start difference. First operand 256 states and 338 transitions. Second operand 19 states. [2018-01-24 20:01:22,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:22,415 INFO L93 Difference]: Finished difference Result 295 states and 384 transitions. [2018-01-24 20:01:22,415 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 20:01:22,415 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 88 [2018-01-24 20:01:22,415 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:22,416 INFO L225 Difference]: With dead ends: 295 [2018-01-24 20:01:22,417 INFO L226 Difference]: Without dead ends: 291 [2018-01-24 20:01:22,417 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 368 GetRequests, 332 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 20:01:22,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states. [2018-01-24 20:01:22,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 270. [2018-01-24 20:01:22,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2018-01-24 20:01:22,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 357 transitions. [2018-01-24 20:01:22,427 INFO L78 Accepts]: Start accepts. Automaton has 270 states and 357 transitions. Word has length 88 [2018-01-24 20:01:22,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:22,428 INFO L432 AbstractCegarLoop]: Abstraction has 270 states and 357 transitions. [2018-01-24 20:01:22,428 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 20:01:22,428 INFO L276 IsEmpty]: Start isEmpty. Operand 270 states and 357 transitions. [2018-01-24 20:01:22,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-01-24 20:01:22,430 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:22,430 INFO L322 BasicCegarLoop]: trace histogram [18, 18, 17, 17, 17, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:22,430 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:22,430 INFO L82 PathProgramCache]: Analyzing trace with hash -2053377585, now seen corresponding path program 17 times [2018-01-24 20:01:22,431 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:22,431 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:22,431 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:22,431 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:22,431 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:22,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:22,443 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:22,662 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:22,663 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:22,663 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:22,663 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:22,663 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:22,663 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:22,663 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:22,668 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:01:22,668 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:22,672 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,673 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,674 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,675 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,676 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,678 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,679 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,681 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,682 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,684 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,685 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,687 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,689 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,691 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,693 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,695 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,698 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,700 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:22,701 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:22,703 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:22,718 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:22,718 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:23,062 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:23,082 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:23,082 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:23,085 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:01:23,085 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:23,089 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,091 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,096 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,102 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,109 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,117 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,126 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,136 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,147 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,160 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,173 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,188 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,204 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,221 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,246 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,266 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,286 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,308 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:23,328 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:23,332 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:23,348 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:23,348 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:23,366 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:23,367 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:23,396 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 37 [2018-01-24 20:01:23,396 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:23,396 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 20:01:23,396 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 20:01:23,397 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 20:01:23,397 INFO L87 Difference]: Start difference. First operand 270 states and 357 transitions. Second operand 20 states. [2018-01-24 20:01:24,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:24,768 INFO L93 Difference]: Finished difference Result 310 states and 404 transitions. [2018-01-24 20:01:24,768 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 20:01:24,768 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 93 [2018-01-24 20:01:24,768 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:24,770 INFO L225 Difference]: With dead ends: 310 [2018-01-24 20:01:24,770 INFO L226 Difference]: Without dead ends: 306 [2018-01-24 20:01:24,770 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 389 GetRequests, 351 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 20:01:24,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306 states. [2018-01-24 20:01:24,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306 to 284. [2018-01-24 20:01:24,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 284 states. [2018-01-24 20:01:24,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 376 transitions. [2018-01-24 20:01:24,780 INFO L78 Accepts]: Start accepts. Automaton has 284 states and 376 transitions. Word has length 93 [2018-01-24 20:01:24,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:24,780 INFO L432 AbstractCegarLoop]: Abstraction has 284 states and 376 transitions. [2018-01-24 20:01:24,780 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 20:01:24,781 INFO L276 IsEmpty]: Start isEmpty. Operand 284 states and 376 transitions. [2018-01-24 20:01:24,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-01-24 20:01:24,782 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:24,782 INFO L322 BasicCegarLoop]: trace histogram [19, 19, 18, 18, 18, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:24,782 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:24,782 INFO L82 PathProgramCache]: Analyzing trace with hash 1741269053, now seen corresponding path program 18 times [2018-01-24 20:01:24,782 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:24,783 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:24,783 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:24,783 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:24,783 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:24,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:24,793 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:25,141 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:25,142 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:25,142 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:25,142 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:25,142 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:25,142 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:25,142 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:25,147 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:01:25,147 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:01:25,152 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,156 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,157 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,158 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,160 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,161 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,162 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,164 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,166 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,167 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,169 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,172 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,174 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,177 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,180 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,183 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,186 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,190 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,194 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,194 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:25,196 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:25,213 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:25,214 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:25,969 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:25,989 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:25,989 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:25,992 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:01:25,992 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:01:25,997 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:25,999 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,003 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,009 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,016 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,024 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,033 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,043 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,054 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,066 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,080 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,095 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,111 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,128 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,146 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,173 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,194 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,217 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,240 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:26,266 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:26,271 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:26,287 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:26,287 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:26,309 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:26,310 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:26,310 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 39 [2018-01-24 20:01:26,310 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:26,311 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 20:01:26,311 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 20:01:26,311 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 20:01:26,311 INFO L87 Difference]: Start difference. First operand 284 states and 376 transitions. Second operand 21 states. [2018-01-24 20:01:28,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:28,066 INFO L93 Difference]: Finished difference Result 325 states and 424 transitions. [2018-01-24 20:01:28,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 20:01:28,066 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 98 [2018-01-24 20:01:28,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:28,068 INFO L225 Difference]: With dead ends: 325 [2018-01-24 20:01:28,068 INFO L226 Difference]: Without dead ends: 321 [2018-01-24 20:01:28,069 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 410 GetRequests, 370 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 20:01:28,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2018-01-24 20:01:28,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 298. [2018-01-24 20:01:28,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 298 states. [2018-01-24 20:01:28,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 395 transitions. [2018-01-24 20:01:28,079 INFO L78 Accepts]: Start accepts. Automaton has 298 states and 395 transitions. Word has length 98 [2018-01-24 20:01:28,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:28,079 INFO L432 AbstractCegarLoop]: Abstraction has 298 states and 395 transitions. [2018-01-24 20:01:28,080 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 20:01:28,080 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 395 transitions. [2018-01-24 20:01:28,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2018-01-24 20:01:28,081 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:28,081 INFO L322 BasicCegarLoop]: trace histogram [20, 20, 19, 19, 19, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:28,081 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:28,081 INFO L82 PathProgramCache]: Analyzing trace with hash 661833359, now seen corresponding path program 19 times [2018-01-24 20:01:28,081 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:28,082 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:28,082 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:28,082 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:28,082 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:28,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:28,093 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:28,342 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:28,342 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:28,342 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:28,342 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:28,343 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:28,343 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:28,343 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:28,347 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:28,348 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:01:28,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:28,361 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:28,383 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:28,383 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:28,870 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:28,890 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:28,890 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:28,893 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:28,893 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:01:28,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:28,932 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:28,952 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:28,952 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:28,974 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:28,975 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:28,975 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 41 [2018-01-24 20:01:28,975 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:28,975 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 20:01:28,976 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 20:01:28,976 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 20:01:28,976 INFO L87 Difference]: Start difference. First operand 298 states and 395 transitions. Second operand 22 states. [2018-01-24 20:01:30,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:30,587 INFO L93 Difference]: Finished difference Result 340 states and 444 transitions. [2018-01-24 20:01:30,587 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 20:01:30,587 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 103 [2018-01-24 20:01:30,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:30,589 INFO L225 Difference]: With dead ends: 340 [2018-01-24 20:01:30,589 INFO L226 Difference]: Without dead ends: 336 [2018-01-24 20:01:30,590 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 431 GetRequests, 389 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 20:01:30,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 336 states. [2018-01-24 20:01:30,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 336 to 312. [2018-01-24 20:01:30,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 312 states. [2018-01-24 20:01:30,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312 states to 312 states and 414 transitions. [2018-01-24 20:01:30,599 INFO L78 Accepts]: Start accepts. Automaton has 312 states and 414 transitions. Word has length 103 [2018-01-24 20:01:30,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:30,600 INFO L432 AbstractCegarLoop]: Abstraction has 312 states and 414 transitions. [2018-01-24 20:01:30,600 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 20:01:30,600 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 414 transitions. [2018-01-24 20:01:30,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-01-24 20:01:30,601 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:30,601 INFO L322 BasicCegarLoop]: trace histogram [21, 21, 20, 20, 20, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:30,601 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:30,601 INFO L82 PathProgramCache]: Analyzing trace with hash -2034644099, now seen corresponding path program 20 times [2018-01-24 20:01:30,601 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:30,602 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:30,602 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:30,602 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:30,602 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:30,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:30,614 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:31,310 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:31,310 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:31,310 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:31,310 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:31,310 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:31,310 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:31,310 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:31,315 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:01:31,315 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:31,320 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:31,328 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:31,330 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:31,332 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:31,352 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:31,352 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:31,817 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:31,847 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:31,847 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:31,850 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:01:31,850 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:31,856 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:31,873 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:31,902 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:31,907 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:31,936 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:31,936 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:31,982 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:31,983 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:31,984 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 43 [2018-01-24 20:01:31,984 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:31,984 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 20:01:31,984 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 20:01:31,985 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 20:01:31,985 INFO L87 Difference]: Start difference. First operand 312 states and 414 transitions. Second operand 23 states. [2018-01-24 20:01:33,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:33,878 INFO L93 Difference]: Finished difference Result 355 states and 464 transitions. [2018-01-24 20:01:33,878 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 20:01:33,879 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 108 [2018-01-24 20:01:33,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:33,880 INFO L225 Difference]: With dead ends: 355 [2018-01-24 20:01:33,880 INFO L226 Difference]: Without dead ends: 351 [2018-01-24 20:01:33,881 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 452 GetRequests, 408 SyntacticMatches, 2 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 20:01:33,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 351 states. [2018-01-24 20:01:33,895 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 351 to 326. [2018-01-24 20:01:33,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 326 states. [2018-01-24 20:01:33,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 326 states to 326 states and 433 transitions. [2018-01-24 20:01:33,897 INFO L78 Accepts]: Start accepts. Automaton has 326 states and 433 transitions. Word has length 108 [2018-01-24 20:01:33,897 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:33,897 INFO L432 AbstractCegarLoop]: Abstraction has 326 states and 433 transitions. [2018-01-24 20:01:33,898 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 20:01:33,898 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 433 transitions. [2018-01-24 20:01:33,900 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-01-24 20:01:33,900 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:33,900 INFO L322 BasicCegarLoop]: trace histogram [22, 22, 21, 21, 21, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:33,900 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:33,900 INFO L82 PathProgramCache]: Analyzing trace with hash 89566031, now seen corresponding path program 21 times [2018-01-24 20:01:33,901 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:33,901 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:33,901 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:33,902 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:33,902 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:33,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:33,919 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:34,405 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:34,405 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:34,405 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:34,405 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:34,406 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:34,406 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:34,406 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:34,410 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:01:34,411 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:01:34,414 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,416 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,416 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,417 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,419 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,420 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,421 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,423 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,424 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,425 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,427 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,429 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,430 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,432 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,434 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,436 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,438 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,441 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,443 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,445 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,448 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,450 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:34,451 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:34,453 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:34,477 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:34,477 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:34,973 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:34,992 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:34,993 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:34,996 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:01:34,996 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:01:35,001 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,003 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,007 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,013 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,020 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,027 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,036 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,046 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,057 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,069 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,082 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,097 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,112 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,129 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,146 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,165 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,193 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,215 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,237 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,260 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,294 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,321 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:01:35,342 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:35,356 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:35,389 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:35,389 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:35,419 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:35,421 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:35,421 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 45 [2018-01-24 20:01:35,421 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:35,422 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 20:01:35,422 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 20:01:35,423 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 20:01:35,423 INFO L87 Difference]: Start difference. First operand 326 states and 433 transitions. Second operand 24 states. [2018-01-24 20:01:37,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:37,346 INFO L93 Difference]: Finished difference Result 370 states and 484 transitions. [2018-01-24 20:01:37,346 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 20:01:37,346 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 113 [2018-01-24 20:01:37,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:37,348 INFO L225 Difference]: With dead ends: 370 [2018-01-24 20:01:37,348 INFO L226 Difference]: Without dead ends: 366 [2018-01-24 20:01:37,349 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 473 GetRequests, 427 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 20:01:37,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states. [2018-01-24 20:01:37,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 340. [2018-01-24 20:01:37,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 340 states. [2018-01-24 20:01:37,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 452 transitions. [2018-01-24 20:01:37,362 INFO L78 Accepts]: Start accepts. Automaton has 340 states and 452 transitions. Word has length 113 [2018-01-24 20:01:37,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:37,363 INFO L432 AbstractCegarLoop]: Abstraction has 340 states and 452 transitions. [2018-01-24 20:01:37,363 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 20:01:37,363 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 452 transitions. [2018-01-24 20:01:37,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-01-24 20:01:37,365 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:37,365 INFO L322 BasicCegarLoop]: trace histogram [23, 23, 22, 22, 22, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:37,365 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:37,365 INFO L82 PathProgramCache]: Analyzing trace with hash 927391421, now seen corresponding path program 22 times [2018-01-24 20:01:37,366 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:37,366 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:37,366 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:37,367 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:37,367 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:37,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:37,384 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:37,806 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:37,806 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:37,807 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:37,807 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:37,807 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:37,807 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:37,807 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:37,814 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:01:37,814 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:01:37,842 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:37,845 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:37,893 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:37,894 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:38,461 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:38,480 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:38,480 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:38,483 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:01:38,484 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:01:38,551 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:38,556 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:38,586 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:38,587 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:38,612 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:38,614 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:38,614 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 47 [2018-01-24 20:01:38,614 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:38,614 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-24 20:01:38,614 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-24 20:01:38,615 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 20:01:38,615 INFO L87 Difference]: Start difference. First operand 340 states and 452 transitions. Second operand 25 states. [2018-01-24 20:01:40,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:40,716 INFO L93 Difference]: Finished difference Result 385 states and 504 transitions. [2018-01-24 20:01:40,716 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 20:01:40,716 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 118 [2018-01-24 20:01:40,717 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:40,718 INFO L225 Difference]: With dead ends: 385 [2018-01-24 20:01:40,719 INFO L226 Difference]: Without dead ends: 381 [2018-01-24 20:01:40,720 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 494 GetRequests, 446 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 20:01:40,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 381 states. [2018-01-24 20:01:40,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 381 to 354. [2018-01-24 20:01:40,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354 states. [2018-01-24 20:01:40,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354 states to 354 states and 471 transitions. [2018-01-24 20:01:40,734 INFO L78 Accepts]: Start accepts. Automaton has 354 states and 471 transitions. Word has length 118 [2018-01-24 20:01:40,734 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:40,734 INFO L432 AbstractCegarLoop]: Abstraction has 354 states and 471 transitions. [2018-01-24 20:01:40,734 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-24 20:01:40,734 INFO L276 IsEmpty]: Start isEmpty. Operand 354 states and 471 transitions. [2018-01-24 20:01:40,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-01-24 20:01:40,737 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:40,737 INFO L322 BasicCegarLoop]: trace histogram [24, 24, 23, 23, 23, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:40,737 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:40,737 INFO L82 PathProgramCache]: Analyzing trace with hash 2117312527, now seen corresponding path program 23 times [2018-01-24 20:01:40,737 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:40,738 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:40,738 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:40,738 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:40,738 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:40,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:40,756 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:41,177 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:41,177 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:41,177 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:41,177 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:41,177 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:41,177 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:41,177 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:41,182 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:01:41,182 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:41,186 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,187 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,188 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,189 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,190 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,191 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,192 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,194 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,195 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,197 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,198 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,200 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,203 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,205 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,207 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,209 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,211 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,213 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,215 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,218 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,220 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,223 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,225 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,229 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,229 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:41,231 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:41,254 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:41,254 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:41,825 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:41,845 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:41,845 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:41,847 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:01:41,848 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:41,852 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,855 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,860 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,866 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,873 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,881 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,890 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,901 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,912 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,924 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,938 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,953 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,969 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:41,986 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:42,011 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:42,031 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:42,052 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:42,073 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:42,095 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:42,128 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:42,152 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:42,180 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:42,217 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:42,247 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:42,284 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:42,290 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:42,322 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:42,322 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:42,365 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:42,367 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:42,367 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 49 [2018-01-24 20:01:42,367 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:42,368 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 20:01:42,368 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 20:01:42,368 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 20:01:42,368 INFO L87 Difference]: Start difference. First operand 354 states and 471 transitions. Second operand 26 states. [2018-01-24 20:01:44,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:44,657 INFO L93 Difference]: Finished difference Result 400 states and 524 transitions. [2018-01-24 20:01:44,657 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 20:01:44,657 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 123 [2018-01-24 20:01:44,658 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:44,659 INFO L225 Difference]: With dead ends: 400 [2018-01-24 20:01:44,659 INFO L226 Difference]: Without dead ends: 396 [2018-01-24 20:01:44,660 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 515 GetRequests, 465 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 20:01:44,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 396 states. [2018-01-24 20:01:44,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 396 to 368. [2018-01-24 20:01:44,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2018-01-24 20:01:44,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 490 transitions. [2018-01-24 20:01:44,675 INFO L78 Accepts]: Start accepts. Automaton has 368 states and 490 transitions. Word has length 123 [2018-01-24 20:01:44,676 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:44,676 INFO L432 AbstractCegarLoop]: Abstraction has 368 states and 490 transitions. [2018-01-24 20:01:44,676 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 20:01:44,676 INFO L276 IsEmpty]: Start isEmpty. Operand 368 states and 490 transitions. [2018-01-24 20:01:44,678 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-01-24 20:01:44,678 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:44,678 INFO L322 BasicCegarLoop]: trace histogram [25, 25, 24, 24, 24, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:44,678 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:44,679 INFO L82 PathProgramCache]: Analyzing trace with hash -1912282627, now seen corresponding path program 24 times [2018-01-24 20:01:44,679 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:44,679 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:44,680 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:44,680 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:44,680 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:44,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:44,698 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:45,145 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:45,146 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:45,146 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:45,146 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:45,146 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:45,146 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:45,146 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:45,151 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:01:45,151 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:01:45,155 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,156 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,157 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,158 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,160 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,161 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,162 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,164 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,165 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,167 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,168 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,170 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,172 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,174 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,176 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,178 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,180 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,182 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,185 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,187 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,190 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,192 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,195 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,198 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,201 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:45,202 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:45,204 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:45,228 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:45,228 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:46,035 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:46,055 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:46,056 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:46,059 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:01:46,059 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:01:46,066 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,068 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,075 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,084 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,094 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,105 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,114 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,124 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,136 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,149 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,164 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,181 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,198 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,216 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,234 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,262 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,283 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,305 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,328 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,361 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,387 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,413 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,451 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,480 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,519 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:01:46,542 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:46,548 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:46,576 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:46,576 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:46,610 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:46,611 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:46,612 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 51 [2018-01-24 20:01:46,612 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:46,612 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 20:01:46,612 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 20:01:46,613 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 20:01:46,613 INFO L87 Difference]: Start difference. First operand 368 states and 490 transitions. Second operand 27 states. [2018-01-24 20:01:49,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:49,064 INFO L93 Difference]: Finished difference Result 415 states and 544 transitions. [2018-01-24 20:01:49,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 20:01:49,064 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 128 [2018-01-24 20:01:49,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:49,066 INFO L225 Difference]: With dead ends: 415 [2018-01-24 20:01:49,066 INFO L226 Difference]: Without dead ends: 411 [2018-01-24 20:01:49,070 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 536 GetRequests, 484 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 20:01:49,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 411 states. [2018-01-24 20:01:49,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 411 to 382. [2018-01-24 20:01:49,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2018-01-24 20:01:49,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 509 transitions. [2018-01-24 20:01:49,080 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 509 transitions. Word has length 128 [2018-01-24 20:01:49,080 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:49,080 INFO L432 AbstractCegarLoop]: Abstraction has 382 states and 509 transitions. [2018-01-24 20:01:49,080 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 20:01:49,080 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 509 transitions. [2018-01-24 20:01:49,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2018-01-24 20:01:49,081 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:49,082 INFO L322 BasicCegarLoop]: trace histogram [26, 26, 25, 25, 25, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:49,082 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:49,082 INFO L82 PathProgramCache]: Analyzing trace with hash 972399823, now seen corresponding path program 25 times [2018-01-24 20:01:49,082 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:49,082 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:49,082 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:01:49,083 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:49,083 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:49,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:49,094 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:49,511 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:49,512 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:49,512 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:49,512 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:49,512 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:49,512 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:49,512 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:49,517 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:49,517 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:01:49,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:49,534 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:49,559 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:49,560 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:50,226 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:50,245 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:50,246 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:50,248 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:50,249 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:01:50,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:50,298 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:50,324 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:50,325 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:50,356 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:50,357 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:50,357 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 53 [2018-01-24 20:01:50,357 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:50,358 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 20:01:50,358 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 20:01:50,359 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 20:01:50,359 INFO L87 Difference]: Start difference. First operand 382 states and 509 transitions. Second operand 28 states. [2018-01-24 20:01:53,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:53,014 INFO L93 Difference]: Finished difference Result 430 states and 564 transitions. [2018-01-24 20:01:53,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 20:01:53,014 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 133 [2018-01-24 20:01:53,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:53,016 INFO L225 Difference]: With dead ends: 430 [2018-01-24 20:01:53,016 INFO L226 Difference]: Without dead ends: 426 [2018-01-24 20:01:53,017 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 557 GetRequests, 503 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 20:01:53,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 426 states. [2018-01-24 20:01:53,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 426 to 396. [2018-01-24 20:01:53,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 396 states. [2018-01-24 20:01:53,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 396 states to 396 states and 528 transitions. [2018-01-24 20:01:53,033 INFO L78 Accepts]: Start accepts. Automaton has 396 states and 528 transitions. Word has length 133 [2018-01-24 20:01:53,033 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:53,033 INFO L432 AbstractCegarLoop]: Abstraction has 396 states and 528 transitions. [2018-01-24 20:01:53,033 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 20:01:53,033 INFO L276 IsEmpty]: Start isEmpty. Operand 396 states and 528 transitions. [2018-01-24 20:01:53,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-01-24 20:01:53,035 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:53,036 INFO L322 BasicCegarLoop]: trace histogram [27, 27, 26, 26, 26, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:53,036 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:53,036 INFO L82 PathProgramCache]: Analyzing trace with hash -158870211, now seen corresponding path program 26 times [2018-01-24 20:01:53,036 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:53,037 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:53,037 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:53,037 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:53,037 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:53,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:53,054 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:53,501 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:53,501 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:53,501 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:53,501 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:01:53,501 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:01:53,501 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:53,501 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:53,507 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:01:53,507 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:53,513 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:53,525 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:53,528 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:53,531 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:53,559 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:53,559 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:54,279 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:54,298 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:54,299 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:01:54,302 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:01:54,302 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:01:54,307 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:54,325 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:01:54,349 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:01:54,354 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:54,381 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:54,381 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:01:54,437 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:54,438 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:01:54,439 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 55 [2018-01-24 20:01:54,439 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:01:54,439 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 20:01:54,440 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 20:01:54,440 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 20:01:54,441 INFO L87 Difference]: Start difference. First operand 396 states and 528 transitions. Second operand 29 states. Received shutdown request... [2018-01-24 20:01:55,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 20:01:55,887 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 20:01:55,891 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 20:01:55,892 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 08:01:55 BoogieIcfgContainer [2018-01-24 20:01:55,892 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 20:01:55,893 INFO L168 Benchmark]: Toolchain (without parser) took 51949.10 ms. Allocated memory was 301.5 MB in the beginning and 725.6 MB in the end (delta: 424.1 MB). Free memory was 262.4 MB in the beginning and 492.9 MB in the end (delta: -230.5 MB). Peak memory consumption was 193.7 MB. Max. memory is 5.3 GB. [2018-01-24 20:01:55,893 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 301.5 MB. Free memory is still 266.4 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 20:01:55,893 INFO L168 Benchmark]: CACSL2BoogieTranslator took 191.66 ms. Allocated memory is still 301.5 MB. Free memory was 260.4 MB in the beginning and 252.4 MB in the end (delta: 8.0 MB). Peak memory consumption was 8.0 MB. Max. memory is 5.3 GB. [2018-01-24 20:01:55,894 INFO L168 Benchmark]: Boogie Preprocessor took 30.15 ms. Allocated memory is still 301.5 MB. Free memory was 252.4 MB in the beginning and 250.4 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 20:01:55,894 INFO L168 Benchmark]: RCFGBuilder took 214.23 ms. Allocated memory is still 301.5 MB. Free memory was 250.4 MB in the beginning and 237.4 MB in the end (delta: 13.0 MB). Peak memory consumption was 13.0 MB. Max. memory is 5.3 GB. [2018-01-24 20:01:55,894 INFO L168 Benchmark]: TraceAbstraction took 51505.34 ms. Allocated memory was 301.5 MB in the beginning and 725.6 MB in the end (delta: 424.1 MB). Free memory was 237.4 MB in the beginning and 492.9 MB in the end (delta: -255.5 MB). Peak memory consumption was 168.6 MB. Max. memory is 5.3 GB. [2018-01-24 20:01:55,895 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 301.5 MB. Free memory is still 266.4 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 191.66 ms. Allocated memory is still 301.5 MB. Free memory was 260.4 MB in the beginning and 252.4 MB in the end (delta: 8.0 MB). Peak memory consumption was 8.0 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 30.15 ms. Allocated memory is still 301.5 MB. Free memory was 252.4 MB in the beginning and 250.4 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 214.23 ms. Allocated memory is still 301.5 MB. Free memory was 250.4 MB in the beginning and 237.4 MB in the end (delta: 13.0 MB). Peak memory consumption was 13.0 MB. Max. memory is 5.3 GB. * TraceAbstraction took 51505.34 ms. Allocated memory was 301.5 MB in the beginning and 725.6 MB in the end (delta: 424.1 MB). Free memory was 237.4 MB in the beginning and 492.9 MB in the end (delta: -255.5 MB). Peak memory consumption was 168.6 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 10 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 0 LocStat_NO_SUPPORTING_DISEQUALITIES : 1 LocStat_NO_DISJUNCTIONS : -20 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 15 TransStat_MAX_WEQGRAPH_SIZE : 0 TransStat_MAX_SIZEOF_WEQEDGELABEL : 0 TransStat_NO_SUPPORTING_EQUALITIES : 5 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 16 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.177890 RENAME_VARIABLES(MILLISECONDS) : 0.382761 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.116066 PROJECTAWAY(MILLISECONDS) : 0.221488 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.000000 DISJOIN(MILLISECONDS) : 2.446562 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.438271 ADD_EQUALITY(MILLISECONDS) : 0.066063 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.077586 #CONJOIN_DISJUNCTIVE : 18 #RENAME_VARIABLES : 43 #UNFREEZE : 0 #CONJOIN : 29 #PROJECTAWAY : 36 #ADD_WEAK_EQUALITY : 0 #DISJOIN : 1 #RENAME_VARIABLES_DISJUNCTIVE : 41 #ADD_EQUALITY : 5 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 17]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 17). Cancelled while BasicCegarLoop was constructing difference of abstraction (396states) and interpolant automaton (currently 19 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (254 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 24]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 24). Cancelled while BasicCegarLoop was constructing difference of abstraction (396states) and interpolant automaton (currently 19 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (254 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 26]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 26). Cancelled while BasicCegarLoop was constructing difference of abstraction (396states) and interpolant automaton (currently 19 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (254 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 19]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 19). Cancelled while BasicCegarLoop was constructing difference of abstraction (396states) and interpolant automaton (currently 19 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (254 states constructedinput type IntersectNwa). - StatisticsResult: Ultimate Automizer benchmark data CFG has 6 procedures, 42 locations, 4 error locations. TIMEOUT Result, 51.4s OverallTime, 27 OverallIterations, 27 TraceHistogramMax, 28.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4596 SDtfs, 3357 SDslu, 57164 SDs, 0 SdLazy, 79478 SolverSat, 811 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 22.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 8205 GetRequests, 7398 SyntacticMatches, 52 SemanticMatches, 755 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 377 ImplicationChecksByTransitivity, 13.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=396occurred in iteration=26, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.1s AbstIntTime, 1 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.3s AutomataMinimizationTime, 26 MinimizatonAttempts, 455 StatesRemovedByMinimization, 26 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 3.6s SatisfiabilityAnalysisTime, 16.9s InterpolantComputationTime, 5897 NumberOfCodeBlocks, 5897 NumberOfCodeBlocksAsserted, 425 NumberOfCheckSat, 9692 ConstructedInterpolants, 0 QuantifiedInterpolants, 6767390 SizeOfPredicates, 0 NumberOfNonLiveVariables, 5200 ConjunctsInSsa, 1560 ConjunctsInUnsatCore, 131 InterpolantComputations, 1 PerfectInterpolantSequences, 0/78390 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sanfoundry_24_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_20-01-55-904.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sanfoundry_24_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-0-2018-01-24_20-01-55-904.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sanfoundry_24_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-0-2018-01-24_20-01-55-904.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sanfoundry_24_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_20-01-55-904.csv Completed graceful shutdown