java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/array-examples/sorting_bubblesort_false-unreach-call2_ground.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-1cceb4a-m [2018-01-29 22:37:18,199 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-29 22:37:18,200 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-29 22:37:18,209 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-29 22:37:18,209 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-29 22:37:18,210 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-29 22:37:18,211 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-29 22:37:18,212 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-29 22:37:18,213 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-29 22:37:18,213 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-29 22:37:18,214 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-29 22:37:18,214 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-29 22:37:18,214 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-29 22:37:18,215 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-29 22:37:18,215 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-29 22:37:18,217 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-29 22:37:18,218 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-29 22:37:18,219 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-29 22:37:18,219 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-29 22:37:18,220 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-29 22:37:18,231 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-01-29 22:37:18,233 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-29 22:37:18,234 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-29 22:37:18,234 INFO L98 SettingsManager]: Beginning loading settings from /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf [2018-01-29 22:37:18,239 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-29 22:37:18,239 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-29 22:37:18,239 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-29 22:37:18,240 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-29 22:37:18,240 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-29 22:37:18,240 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-29 22:37:18,240 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-29 22:37:18,240 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-29 22:37:18,240 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-29 22:37:18,240 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-29 22:37:18,240 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-29 22:37:18,241 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-29 22:37:18,241 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-01-29 22:37:18,241 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-29 22:37:18,241 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-01-29 22:37:18,241 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-29 22:37:18,241 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-01-29 22:37:18,241 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-01-29 22:37:18,241 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-29 22:37:18,241 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-01-29 22:37:18,241 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-29 22:37:18,241 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-29 22:37:18,242 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-29 22:37:18,242 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-29 22:37:18,242 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-29 22:37:18,242 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-29 22:37:18,242 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-29 22:37:18,242 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-29 22:37:18,242 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-29 22:37:18,242 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-29 22:37:18,242 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-29 22:37:18,242 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-29 22:37:18,243 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-29 22:37:18,243 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-29 22:37:18,262 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-29 22:37:18,271 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-29 22:37:18,273 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-29 22:37:18,274 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-29 22:37:18,274 INFO L276 PluginConnector]: CDTParser initialized [2018-01-29 22:37:18,274 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/sorting_bubblesort_false-unreach-call2_ground.i [2018-01-29 22:37:18,346 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-29 22:37:18,347 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-29 22:37:18,348 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-29 22:37:18,348 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-29 22:37:18,353 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-29 22:37:18,353 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.01 10:37:18" (1/1) ... [2018-01-29 22:37:18,355 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@78080993 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:37:18, skipping insertion in model container [2018-01-29 22:37:18,355 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.01 10:37:18" (1/1) ... [2018-01-29 22:37:18,366 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-29 22:37:18,375 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-29 22:37:18,445 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-29 22:37:18,453 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-29 22:37:18,456 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:37:18 WrapperNode [2018-01-29 22:37:18,456 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-29 22:37:18,457 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-29 22:37:18,457 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-29 22:37:18,457 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-29 22:37:18,465 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:37:18" (1/1) ... [2018-01-29 22:37:18,465 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:37:18" (1/1) ... [2018-01-29 22:37:18,469 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:37:18" (1/1) ... [2018-01-29 22:37:18,470 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:37:18" (1/1) ... [2018-01-29 22:37:18,470 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:37:18" (1/1) ... [2018-01-29 22:37:18,473 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:37:18" (1/1) ... [2018-01-29 22:37:18,473 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:37:18" (1/1) ... [2018-01-29 22:37:18,474 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-29 22:37:18,474 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-29 22:37:18,475 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-29 22:37:18,475 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-29 22:37:18,475 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:37:18" (1/1) ... No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-29 22:37:18,531 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-29 22:37:18,531 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-29 22:37:18,531 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-29 22:37:18,531 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-29 22:37:18,531 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-29 22:37:18,532 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-29 22:37:18,532 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-29 22:37:18,532 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-29 22:37:18,532 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-29 22:37:18,782 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-29 22:37:18,783 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.01 10:37:18 BoogieIcfgContainer [2018-01-29 22:37:18,783 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-29 22:37:18,783 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-29 22:37:18,783 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-29 22:37:18,785 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-29 22:37:18,785 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 29.01 10:37:18" (1/3) ... [2018-01-29 22:37:18,786 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@16a95ac3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 29.01 10:37:18, skipping insertion in model container [2018-01-29 22:37:18,786 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:37:18" (2/3) ... [2018-01-29 22:37:18,786 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@16a95ac3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 29.01 10:37:18, skipping insertion in model container [2018-01-29 22:37:18,786 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.01 10:37:18" (3/3) ... [2018-01-29 22:37:18,787 INFO L107 eAbstractionObserver]: Analyzing ICFG sorting_bubblesort_false-unreach-call2_ground.i [2018-01-29 22:37:18,792 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-29 22:37:18,796 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-01-29 22:37:18,821 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-29 22:37:18,821 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-29 22:37:18,821 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-29 22:37:18,821 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-29 22:37:18,821 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-29 22:37:18,821 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-29 22:37:18,821 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-29 22:37:18,821 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-29 22:37:18,822 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-29 22:37:18,831 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states. [2018-01-29 22:37:18,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-01-29 22:37:18,834 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:18,835 INFO L350 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:18,835 INFO L371 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:18,838 INFO L82 PathProgramCache]: Analyzing trace with hash 1032819300, now seen corresponding path program 1 times [2018-01-29 22:37:18,839 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:18,839 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:18,868 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:18,868 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:18,868 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:18,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:18,888 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:18,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:18,905 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-29 22:37:18,905 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-29 22:37:18,906 INFO L409 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-01-29 22:37:18,913 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-01-29 22:37:18,913 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-29 22:37:18,915 INFO L87 Difference]: Start difference. First operand 44 states. Second operand 2 states. [2018-01-29 22:37:18,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:18,929 INFO L93 Difference]: Finished difference Result 82 states and 100 transitions. [2018-01-29 22:37:18,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-01-29 22:37:18,929 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 19 [2018-01-29 22:37:18,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:18,935 INFO L225 Difference]: With dead ends: 82 [2018-01-29 22:37:18,935 INFO L226 Difference]: Without dead ends: 39 [2018-01-29 22:37:18,937 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-29 22:37:18,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2018-01-29 22:37:18,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2018-01-29 22:37:18,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-01-29 22:37:18,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 44 transitions. [2018-01-29 22:37:18,958 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 44 transitions. Word has length 19 [2018-01-29 22:37:18,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:18,959 INFO L432 AbstractCegarLoop]: Abstraction has 39 states and 44 transitions. [2018-01-29 22:37:18,959 INFO L433 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-01-29 22:37:18,959 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 44 transitions. [2018-01-29 22:37:18,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-01-29 22:37:18,959 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:18,960 INFO L350 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:18,960 INFO L371 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:18,960 INFO L82 PathProgramCache]: Analyzing trace with hash 196893831, now seen corresponding path program 1 times [2018-01-29 22:37:18,960 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:18,960 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:18,961 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:18,961 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:18,961 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:18,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:18,965 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:19,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:19,026 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-29 22:37:19,026 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-29 22:37:19,027 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-29 22:37:19,027 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-29 22:37:19,027 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-29 22:37:19,027 INFO L87 Difference]: Start difference. First operand 39 states and 44 transitions. Second operand 3 states. [2018-01-29 22:37:19,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:19,083 INFO L93 Difference]: Finished difference Result 71 states and 81 transitions. [2018-01-29 22:37:19,083 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-29 22:37:19,083 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 20 [2018-01-29 22:37:19,083 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:19,084 INFO L225 Difference]: With dead ends: 71 [2018-01-29 22:37:19,084 INFO L226 Difference]: Without dead ends: 50 [2018-01-29 22:37:19,085 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-29 22:37:19,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-01-29 22:37:19,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 45. [2018-01-29 22:37:19,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-01-29 22:37:19,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 52 transitions. [2018-01-29 22:37:19,089 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 52 transitions. Word has length 20 [2018-01-29 22:37:19,089 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:19,089 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 52 transitions. [2018-01-29 22:37:19,089 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-29 22:37:19,089 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 52 transitions. [2018-01-29 22:37:19,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-01-29 22:37:19,089 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:19,090 INFO L350 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:19,090 INFO L371 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:19,090 INFO L82 PathProgramCache]: Analyzing trace with hash 757431314, now seen corresponding path program 1 times [2018-01-29 22:37:19,090 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:19,090 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:19,091 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:19,091 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:19,091 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:19,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:19,099 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:19,148 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:19,148 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-29 22:37:19,148 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-29 22:37:19,149 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-29 22:37:19,149 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-29 22:37:19,149 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-29 22:37:19,149 INFO L87 Difference]: Start difference. First operand 45 states and 52 transitions. Second operand 3 states. [2018-01-29 22:37:19,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:19,261 INFO L93 Difference]: Finished difference Result 93 states and 109 transitions. [2018-01-29 22:37:19,261 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-29 22:37:19,262 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 26 [2018-01-29 22:37:19,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:19,263 INFO L225 Difference]: With dead ends: 93 [2018-01-29 22:37:19,263 INFO L226 Difference]: Without dead ends: 54 [2018-01-29 22:37:19,264 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-29 22:37:19,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-01-29 22:37:19,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 47. [2018-01-29 22:37:19,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-01-29 22:37:19,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 54 transitions. [2018-01-29 22:37:19,268 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 54 transitions. Word has length 26 [2018-01-29 22:37:19,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:19,268 INFO L432 AbstractCegarLoop]: Abstraction has 47 states and 54 transitions. [2018-01-29 22:37:19,268 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-29 22:37:19,268 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 54 transitions. [2018-01-29 22:37:19,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-01-29 22:37:19,269 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:19,269 INFO L350 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:19,269 INFO L371 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:19,269 INFO L82 PathProgramCache]: Analyzing trace with hash 1321651130, now seen corresponding path program 1 times [2018-01-29 22:37:19,269 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:19,269 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:19,270 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:19,270 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:19,270 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:19,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:19,275 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:19,403 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:19,403 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:19,403 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-29 22:37:19,417 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:19,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:19,431 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:19,443 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:19,460 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:19,460 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2018-01-29 22:37:19,460 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-29 22:37:19,460 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-29 22:37:19,460 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-29 22:37:19,460 INFO L87 Difference]: Start difference. First operand 47 states and 54 transitions. Second operand 4 states. [2018-01-29 22:37:19,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:19,543 INFO L93 Difference]: Finished difference Result 107 states and 126 transitions. [2018-01-29 22:37:19,543 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-29 22:37:19,543 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 30 [2018-01-29 22:37:19,544 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:19,544 INFO L225 Difference]: With dead ends: 107 [2018-01-29 22:37:19,544 INFO L226 Difference]: Without dead ends: 66 [2018-01-29 22:37:19,544 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-29 22:37:19,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-01-29 22:37:19,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 58. [2018-01-29 22:37:19,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-01-29 22:37:19,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 66 transitions. [2018-01-29 22:37:19,549 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 66 transitions. Word has length 30 [2018-01-29 22:37:19,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:19,549 INFO L432 AbstractCegarLoop]: Abstraction has 58 states and 66 transitions. [2018-01-29 22:37:19,549 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-29 22:37:19,549 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 66 transitions. [2018-01-29 22:37:19,550 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-29 22:37:19,550 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:19,550 INFO L350 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:19,550 INFO L371 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:19,550 INFO L82 PathProgramCache]: Analyzing trace with hash 443025250, now seen corresponding path program 2 times [2018-01-29 22:37:19,550 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:19,550 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:19,551 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:19,551 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:19,551 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:19,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:19,558 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:19,631 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 2 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:19,631 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:19,631 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:19,641 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:37:19,648 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:19,655 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:19,659 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:19,663 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:19,667 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 2 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:19,683 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:19,683 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-01-29 22:37:19,683 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-29 22:37:19,683 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-29 22:37:19,684 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-01-29 22:37:19,684 INFO L87 Difference]: Start difference. First operand 58 states and 66 transitions. Second operand 5 states. [2018-01-29 22:37:19,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:19,848 INFO L93 Difference]: Finished difference Result 130 states and 152 transitions. [2018-01-29 22:37:19,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-29 22:37:19,848 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 34 [2018-01-29 22:37:19,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:19,850 INFO L225 Difference]: With dead ends: 130 [2018-01-29 22:37:19,850 INFO L226 Difference]: Without dead ends: 78 [2018-01-29 22:37:19,850 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 35 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-01-29 22:37:19,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2018-01-29 22:37:19,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 70. [2018-01-29 22:37:19,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-01-29 22:37:19,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 80 transitions. [2018-01-29 22:37:19,856 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 80 transitions. Word has length 34 [2018-01-29 22:37:19,856 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:19,856 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 80 transitions. [2018-01-29 22:37:19,856 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-29 22:37:19,857 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 80 transitions. [2018-01-29 22:37:19,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-01-29 22:37:19,857 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:19,857 INFO L350 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:19,857 INFO L371 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:19,857 INFO L82 PathProgramCache]: Analyzing trace with hash 1983065866, now seen corresponding path program 3 times [2018-01-29 22:37:19,857 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:19,857 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:19,858 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:19,858 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:19,858 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:19,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:19,864 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:19,950 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 2 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:19,950 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:19,950 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-29 22:37:19,956 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:19,964 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:19,967 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:19,968 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:19,970 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:19,971 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:19,971 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:19,972 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:19,976 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 2 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:19,993 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:19,993 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-01-29 22:37:19,993 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-29 22:37:19,993 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-29 22:37:19,994 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-29 22:37:19,994 INFO L87 Difference]: Start difference. First operand 70 states and 80 transitions. Second operand 6 states. [2018-01-29 22:37:20,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:20,063 INFO L93 Difference]: Finished difference Result 154 states and 180 transitions. [2018-01-29 22:37:20,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-29 22:37:20,063 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 38 [2018-01-29 22:37:20,063 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:20,063 INFO L225 Difference]: With dead ends: 154 [2018-01-29 22:37:20,063 INFO L226 Difference]: Without dead ends: 90 [2018-01-29 22:37:20,064 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-29 22:37:20,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-01-29 22:37:20,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 82. [2018-01-29 22:37:20,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-01-29 22:37:20,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 94 transitions. [2018-01-29 22:37:20,067 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 94 transitions. Word has length 38 [2018-01-29 22:37:20,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:20,067 INFO L432 AbstractCegarLoop]: Abstraction has 82 states and 94 transitions. [2018-01-29 22:37:20,068 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-29 22:37:20,068 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 94 transitions. [2018-01-29 22:37:20,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-29 22:37:20,068 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:20,068 INFO L350 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:20,068 INFO L371 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:20,068 INFO L82 PathProgramCache]: Analyzing trace with hash 592593586, now seen corresponding path program 4 times [2018-01-29 22:37:20,069 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:20,069 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:20,069 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:20,069 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:20,069 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:20,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:20,075 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:20,142 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:20,142 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:20,142 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:20,147 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:37:20,160 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:20,161 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:20,165 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:20,181 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:20,181 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2018-01-29 22:37:20,182 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-29 22:37:20,182 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-29 22:37:20,182 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-01-29 22:37:20,182 INFO L87 Difference]: Start difference. First operand 82 states and 94 transitions. Second operand 7 states. [2018-01-29 22:37:20,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:20,334 INFO L93 Difference]: Finished difference Result 178 states and 208 transitions. [2018-01-29 22:37:20,336 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-29 22:37:20,336 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 42 [2018-01-29 22:37:20,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:20,338 INFO L225 Difference]: With dead ends: 178 [2018-01-29 22:37:20,338 INFO L226 Difference]: Without dead ends: 102 [2018-01-29 22:37:20,338 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-01-29 22:37:20,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-01-29 22:37:20,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 94. [2018-01-29 22:37:20,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-01-29 22:37:20,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 108 transitions. [2018-01-29 22:37:20,342 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 108 transitions. Word has length 42 [2018-01-29 22:37:20,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:20,342 INFO L432 AbstractCegarLoop]: Abstraction has 94 states and 108 transitions. [2018-01-29 22:37:20,342 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-29 22:37:20,342 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 108 transitions. [2018-01-29 22:37:20,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-01-29 22:37:20,343 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:20,343 INFO L350 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:20,343 INFO L371 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:20,343 INFO L82 PathProgramCache]: Analyzing trace with hash 1039090266, now seen corresponding path program 5 times [2018-01-29 22:37:20,345 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:20,345 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:20,346 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:20,346 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:20,346 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:20,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:20,355 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:20,443 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 2 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:20,443 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:20,443 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:20,454 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:37:20,457 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:20,474 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:20,487 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:20,497 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:20,502 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:20,503 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:20,504 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:20,505 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:20,510 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 2 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:20,526 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:20,526 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2018-01-29 22:37:20,526 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-29 22:37:20,526 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-29 22:37:20,527 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-29 22:37:20,527 INFO L87 Difference]: Start difference. First operand 94 states and 108 transitions. Second operand 8 states. [2018-01-29 22:37:20,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:20,731 INFO L93 Difference]: Finished difference Result 202 states and 236 transitions. [2018-01-29 22:37:20,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-29 22:37:20,731 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 46 [2018-01-29 22:37:20,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:20,732 INFO L225 Difference]: With dead ends: 202 [2018-01-29 22:37:20,732 INFO L226 Difference]: Without dead ends: 114 [2018-01-29 22:37:20,732 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 47 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-29 22:37:20,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-01-29 22:37:20,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 106. [2018-01-29 22:37:20,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-01-29 22:37:20,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 122 transitions. [2018-01-29 22:37:20,736 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 122 transitions. Word has length 46 [2018-01-29 22:37:20,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:20,737 INFO L432 AbstractCegarLoop]: Abstraction has 106 states and 122 transitions. [2018-01-29 22:37:20,737 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-29 22:37:20,737 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 122 transitions. [2018-01-29 22:37:20,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-01-29 22:37:20,737 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:20,738 INFO L350 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:20,738 INFO L371 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:20,738 INFO L82 PathProgramCache]: Analyzing trace with hash -1120653822, now seen corresponding path program 6 times [2018-01-29 22:37:20,738 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:20,738 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:20,738 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:20,738 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:20,739 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:20,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:20,744 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:20,905 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 2 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:20,905 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:20,905 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:20,911 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:37:20,923 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:20,924 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:20,925 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:20,926 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:20,927 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:20,930 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:20,933 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:20,940 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:20,947 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:20,948 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:20,952 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 2 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:20,971 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:20,971 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2018-01-29 22:37:20,972 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-29 22:37:20,972 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-29 22:37:20,972 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-01-29 22:37:20,972 INFO L87 Difference]: Start difference. First operand 106 states and 122 transitions. Second operand 9 states. [2018-01-29 22:37:21,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:21,055 INFO L93 Difference]: Finished difference Result 226 states and 264 transitions. [2018-01-29 22:37:21,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-29 22:37:21,055 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 50 [2018-01-29 22:37:21,055 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:21,056 INFO L225 Difference]: With dead ends: 226 [2018-01-29 22:37:21,056 INFO L226 Difference]: Without dead ends: 126 [2018-01-29 22:37:21,056 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 51 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-01-29 22:37:21,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-01-29 22:37:21,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 118. [2018-01-29 22:37:21,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-29 22:37:21,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 136 transitions. [2018-01-29 22:37:21,062 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 136 transitions. Word has length 50 [2018-01-29 22:37:21,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:21,062 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 136 transitions. [2018-01-29 22:37:21,063 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-29 22:37:21,063 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 136 transitions. [2018-01-29 22:37:21,063 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-01-29 22:37:21,063 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:21,063 INFO L350 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:21,063 INFO L371 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:21,064 INFO L82 PathProgramCache]: Analyzing trace with hash -213187158, now seen corresponding path program 7 times [2018-01-29 22:37:21,064 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:21,064 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:21,064 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:21,064 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:21,064 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:21,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:21,073 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:21,236 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 98 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:21,236 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:21,236 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:21,241 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:21,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:21,264 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:21,275 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 98 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:21,291 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:21,292 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2018-01-29 22:37:21,292 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-29 22:37:21,292 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-29 22:37:21,292 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-29 22:37:21,292 INFO L87 Difference]: Start difference. First operand 118 states and 136 transitions. Second operand 10 states. [2018-01-29 22:37:21,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:21,528 INFO L93 Difference]: Finished difference Result 250 states and 292 transitions. [2018-01-29 22:37:21,533 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-29 22:37:21,533 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 54 [2018-01-29 22:37:21,533 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:21,534 INFO L225 Difference]: With dead ends: 250 [2018-01-29 22:37:21,534 INFO L226 Difference]: Without dead ends: 138 [2018-01-29 22:37:21,535 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-29 22:37:21,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-01-29 22:37:21,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 130. [2018-01-29 22:37:21,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-01-29 22:37:21,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 150 transitions. [2018-01-29 22:37:21,541 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 150 transitions. Word has length 54 [2018-01-29 22:37:21,541 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:21,542 INFO L432 AbstractCegarLoop]: Abstraction has 130 states and 150 transitions. [2018-01-29 22:37:21,542 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-29 22:37:21,542 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 150 transitions. [2018-01-29 22:37:21,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-01-29 22:37:21,542 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:21,542 INFO L350 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:21,543 INFO L371 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:21,543 INFO L82 PathProgramCache]: Analyzing trace with hash 224250194, now seen corresponding path program 8 times [2018-01-29 22:37:21,543 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:21,543 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:21,543 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:21,543 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:21,543 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:21,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:21,550 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:21,886 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 2 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:21,886 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:21,886 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:21,891 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:37:21,894 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:21,910 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:21,910 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:21,912 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:21,917 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 2 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:21,933 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:21,934 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2018-01-29 22:37:21,934 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-29 22:37:21,934 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-29 22:37:21,934 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-01-29 22:37:21,934 INFO L87 Difference]: Start difference. First operand 130 states and 150 transitions. Second operand 11 states. [2018-01-29 22:37:22,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:22,001 INFO L93 Difference]: Finished difference Result 274 states and 320 transitions. [2018-01-29 22:37:22,001 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-29 22:37:22,001 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 58 [2018-01-29 22:37:22,001 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:22,002 INFO L225 Difference]: With dead ends: 274 [2018-01-29 22:37:22,002 INFO L226 Difference]: Without dead ends: 150 [2018-01-29 22:37:22,002 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 59 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-01-29 22:37:22,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-01-29 22:37:22,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 142. [2018-01-29 22:37:22,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-01-29 22:37:22,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 164 transitions. [2018-01-29 22:37:22,005 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 164 transitions. Word has length 58 [2018-01-29 22:37:22,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:22,006 INFO L432 AbstractCegarLoop]: Abstraction has 142 states and 164 transitions. [2018-01-29 22:37:22,006 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-29 22:37:22,006 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 164 transitions. [2018-01-29 22:37:22,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-29 22:37:22,006 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:22,007 INFO L350 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:22,007 INFO L371 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:22,007 INFO L82 PathProgramCache]: Analyzing trace with hash -1818855174, now seen corresponding path program 9 times [2018-01-29 22:37:22,007 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:22,007 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:22,007 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:22,007 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:22,007 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:22,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:22,013 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:22,103 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 2 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:22,103 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:22,103 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:22,108 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:37:22,112 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:22,118 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:22,127 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:22,127 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:22,128 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:22,129 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:22,130 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:22,131 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:22,131 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:22,132 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:22,133 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:22,133 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:22,136 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:22,142 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 2 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:22,159 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:22,159 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2018-01-29 22:37:22,159 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-29 22:37:22,159 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-29 22:37:22,159 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-01-29 22:37:22,159 INFO L87 Difference]: Start difference. First operand 142 states and 164 transitions. Second operand 12 states. [2018-01-29 22:37:22,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:22,279 INFO L93 Difference]: Finished difference Result 298 states and 348 transitions. [2018-01-29 22:37:22,279 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-29 22:37:22,279 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 62 [2018-01-29 22:37:22,279 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:22,279 INFO L225 Difference]: With dead ends: 298 [2018-01-29 22:37:22,279 INFO L226 Difference]: Without dead ends: 162 [2018-01-29 22:37:22,280 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 63 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-01-29 22:37:22,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-01-29 22:37:22,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 154. [2018-01-29 22:37:22,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-01-29 22:37:22,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 178 transitions. [2018-01-29 22:37:22,283 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 178 transitions. Word has length 62 [2018-01-29 22:37:22,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:22,283 INFO L432 AbstractCegarLoop]: Abstraction has 154 states and 178 transitions. [2018-01-29 22:37:22,283 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-29 22:37:22,283 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 178 transitions. [2018-01-29 22:37:22,284 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-01-29 22:37:22,284 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:22,284 INFO L350 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:22,284 INFO L371 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:22,284 INFO L82 PathProgramCache]: Analyzing trace with hash -383839070, now seen corresponding path program 10 times [2018-01-29 22:37:22,284 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:22,284 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:22,285 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:22,285 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:22,285 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:22,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:22,293 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:22,373 INFO L134 CoverageAnalysis]: Checked inductivity of 202 backedges. 2 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:22,373 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:22,373 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:22,378 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:37:22,389 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:22,390 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:22,404 INFO L134 CoverageAnalysis]: Checked inductivity of 202 backedges. 2 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:22,421 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:22,421 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2018-01-29 22:37:22,422 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-29 22:37:22,422 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-29 22:37:22,422 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-01-29 22:37:22,422 INFO L87 Difference]: Start difference. First operand 154 states and 178 transitions. Second operand 13 states. [2018-01-29 22:37:22,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:22,510 INFO L93 Difference]: Finished difference Result 322 states and 376 transitions. [2018-01-29 22:37:22,510 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-29 22:37:22,510 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 66 [2018-01-29 22:37:22,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:22,510 INFO L225 Difference]: With dead ends: 322 [2018-01-29 22:37:22,510 INFO L226 Difference]: Without dead ends: 174 [2018-01-29 22:37:22,511 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-01-29 22:37:22,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-01-29 22:37:22,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 166. [2018-01-29 22:37:22,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-01-29 22:37:22,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 192 transitions. [2018-01-29 22:37:22,513 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 192 transitions. Word has length 66 [2018-01-29 22:37:22,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:22,514 INFO L432 AbstractCegarLoop]: Abstraction has 166 states and 192 transitions. [2018-01-29 22:37:22,514 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-29 22:37:22,514 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 192 transitions. [2018-01-29 22:37:22,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-01-29 22:37:22,514 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:22,514 INFO L350 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:22,514 INFO L371 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:22,515 INFO L82 PathProgramCache]: Analyzing trace with hash -870212534, now seen corresponding path program 11 times [2018-01-29 22:37:22,515 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:22,515 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:22,515 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:22,515 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:22,515 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:22,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:22,521 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:22,628 INFO L134 CoverageAnalysis]: Checked inductivity of 244 backedges. 2 proven. 242 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:22,628 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:22,628 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:22,633 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:37:22,637 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:22,643 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:22,653 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:22,662 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:22,671 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:22,680 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:22,690 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:22,699 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:22,708 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:22,718 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:22,727 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:22,736 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:22,745 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:22,746 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:22,760 INFO L134 CoverageAnalysis]: Checked inductivity of 244 backedges. 2 proven. 242 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:22,783 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:22,783 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 14 [2018-01-29 22:37:22,783 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-29 22:37:22,784 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-29 22:37:22,784 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-29 22:37:22,784 INFO L87 Difference]: Start difference. First operand 166 states and 192 transitions. Second operand 14 states. [2018-01-29 22:37:22,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:22,934 INFO L93 Difference]: Finished difference Result 346 states and 404 transitions. [2018-01-29 22:37:22,934 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-29 22:37:22,934 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 70 [2018-01-29 22:37:22,934 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:22,935 INFO L225 Difference]: With dead ends: 346 [2018-01-29 22:37:22,935 INFO L226 Difference]: Without dead ends: 186 [2018-01-29 22:37:22,935 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 71 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-29 22:37:22,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-01-29 22:37:22,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 178. [2018-01-29 22:37:22,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178 states. [2018-01-29 22:37:22,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 206 transitions. [2018-01-29 22:37:22,938 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 206 transitions. Word has length 70 [2018-01-29 22:37:22,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:22,939 INFO L432 AbstractCegarLoop]: Abstraction has 178 states and 206 transitions. [2018-01-29 22:37:22,939 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-29 22:37:22,939 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 206 transitions. [2018-01-29 22:37:22,939 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-01-29 22:37:22,939 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:22,939 INFO L350 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:22,939 INFO L371 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:22,940 INFO L82 PathProgramCache]: Analyzing trace with hash -708309006, now seen corresponding path program 12 times [2018-01-29 22:37:22,940 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:22,940 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:22,940 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:22,940 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:22,940 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:22,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:22,946 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:23,059 INFO L134 CoverageAnalysis]: Checked inductivity of 290 backedges. 2 proven. 288 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:23,059 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:23,059 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:23,064 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:37:23,067 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:23,070 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:23,071 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:23,077 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:23,078 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:23,079 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:23,085 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:23,086 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:23,087 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:23,088 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:23,089 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:23,090 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:23,091 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:23,092 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:23,092 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:23,093 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:23,107 INFO L134 CoverageAnalysis]: Checked inductivity of 290 backedges. 2 proven. 288 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:23,124 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:23,124 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 15 [2018-01-29 22:37:23,124 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-29 22:37:23,124 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-29 22:37:23,124 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2018-01-29 22:37:23,125 INFO L87 Difference]: Start difference. First operand 178 states and 206 transitions. Second operand 15 states. [2018-01-29 22:37:23,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:23,211 INFO L93 Difference]: Finished difference Result 370 states and 432 transitions. [2018-01-29 22:37:23,214 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-29 22:37:23,214 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 74 [2018-01-29 22:37:23,214 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:23,215 INFO L225 Difference]: With dead ends: 370 [2018-01-29 22:37:23,215 INFO L226 Difference]: Without dead ends: 198 [2018-01-29 22:37:23,215 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 75 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2018-01-29 22:37:23,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states. [2018-01-29 22:37:23,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 190. [2018-01-29 22:37:23,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-01-29 22:37:23,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 220 transitions. [2018-01-29 22:37:23,218 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 220 transitions. Word has length 74 [2018-01-29 22:37:23,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:23,219 INFO L432 AbstractCegarLoop]: Abstraction has 190 states and 220 transitions. [2018-01-29 22:37:23,219 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-29 22:37:23,219 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 220 transitions. [2018-01-29 22:37:23,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-29 22:37:23,219 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:23,219 INFO L350 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:23,219 INFO L371 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:23,219 INFO L82 PathProgramCache]: Analyzing trace with hash -96702566, now seen corresponding path program 13 times [2018-01-29 22:37:23,220 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:23,220 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:23,220 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:23,220 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:23,220 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:23,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:23,225 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:23,392 INFO L134 CoverageAnalysis]: Checked inductivity of 340 backedges. 2 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:23,392 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:23,392 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:23,398 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:23,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:23,406 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:23,422 INFO L134 CoverageAnalysis]: Checked inductivity of 340 backedges. 2 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:23,440 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:23,440 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 16 [2018-01-29 22:37:23,440 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-29 22:37:23,440 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-29 22:37:23,440 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-29 22:37:23,441 INFO L87 Difference]: Start difference. First operand 190 states and 220 transitions. Second operand 16 states. [2018-01-29 22:37:23,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:23,545 INFO L93 Difference]: Finished difference Result 394 states and 460 transitions. [2018-01-29 22:37:23,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-29 22:37:23,560 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 78 [2018-01-29 22:37:23,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:23,561 INFO L225 Difference]: With dead ends: 394 [2018-01-29 22:37:23,561 INFO L226 Difference]: Without dead ends: 210 [2018-01-29 22:37:23,561 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-29 22:37:23,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states. [2018-01-29 22:37:23,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 202. [2018-01-29 22:37:23,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202 states. [2018-01-29 22:37:23,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202 states to 202 states and 234 transitions. [2018-01-29 22:37:23,564 INFO L78 Accepts]: Start accepts. Automaton has 202 states and 234 transitions. Word has length 78 [2018-01-29 22:37:23,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:23,564 INFO L432 AbstractCegarLoop]: Abstraction has 202 states and 234 transitions. [2018-01-29 22:37:23,564 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-29 22:37:23,564 INFO L276 IsEmpty]: Start isEmpty. Operand 202 states and 234 transitions. [2018-01-29 22:37:23,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-01-29 22:37:23,565 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:23,565 INFO L350 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:23,565 INFO L371 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:23,565 INFO L82 PathProgramCache]: Analyzing trace with hash 145275714, now seen corresponding path program 14 times [2018-01-29 22:37:23,565 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:23,565 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:23,566 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:23,566 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:23,566 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:23,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:23,573 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:23,741 INFO L134 CoverageAnalysis]: Checked inductivity of 394 backedges. 2 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:23,741 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:23,741 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:23,747 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:37:23,751 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:23,755 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:23,756 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:23,757 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:23,768 INFO L134 CoverageAnalysis]: Checked inductivity of 394 backedges. 2 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:23,785 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:23,786 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 17 [2018-01-29 22:37:23,786 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-29 22:37:23,786 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-29 22:37:23,786 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2018-01-29 22:37:23,786 INFO L87 Difference]: Start difference. First operand 202 states and 234 transitions. Second operand 17 states. [2018-01-29 22:37:24,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:24,063 INFO L93 Difference]: Finished difference Result 418 states and 488 transitions. [2018-01-29 22:37:24,076 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-29 22:37:24,076 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 82 [2018-01-29 22:37:24,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:24,077 INFO L225 Difference]: With dead ends: 418 [2018-01-29 22:37:24,077 INFO L226 Difference]: Without dead ends: 222 [2018-01-29 22:37:24,078 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2018-01-29 22:37:24,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states. [2018-01-29 22:37:24,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 214. [2018-01-29 22:37:24,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-01-29 22:37:24,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 248 transitions. [2018-01-29 22:37:24,081 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 248 transitions. Word has length 82 [2018-01-29 22:37:24,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:24,081 INFO L432 AbstractCegarLoop]: Abstraction has 214 states and 248 transitions. [2018-01-29 22:37:24,081 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-29 22:37:24,081 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 248 transitions. [2018-01-29 22:37:24,082 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-01-29 22:37:24,082 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:24,082 INFO L350 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:24,082 INFO L371 AbstractCegarLoop]: === Iteration 18 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:24,082 INFO L82 PathProgramCache]: Analyzing trace with hash 725021418, now seen corresponding path program 15 times [2018-01-29 22:37:24,082 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:24,082 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:24,082 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:24,083 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:24,083 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:24,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:24,087 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:24,263 INFO L134 CoverageAnalysis]: Checked inductivity of 452 backedges. 2 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:24,263 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:24,263 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:24,268 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:37:24,272 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,283 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,297 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,303 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,313 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,323 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,337 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,347 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,353 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,363 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,373 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,383 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,394 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,403 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,413 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,424 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,425 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:24,425 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:24,426 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:24,434 INFO L134 CoverageAnalysis]: Checked inductivity of 452 backedges. 2 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:24,451 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:24,451 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2018-01-29 22:37:24,451 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-29 22:37:24,452 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-29 22:37:24,452 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-01-29 22:37:24,452 INFO L87 Difference]: Start difference. First operand 214 states and 248 transitions. Second operand 18 states. [2018-01-29 22:37:24,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:24,957 INFO L93 Difference]: Finished difference Result 442 states and 516 transitions. [2018-01-29 22:37:24,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-29 22:37:24,957 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 86 [2018-01-29 22:37:24,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:24,958 INFO L225 Difference]: With dead ends: 442 [2018-01-29 22:37:24,958 INFO L226 Difference]: Without dead ends: 234 [2018-01-29 22:37:24,958 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-01-29 22:37:24,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states. [2018-01-29 22:37:24,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 226. [2018-01-29 22:37:24,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-01-29 22:37:24,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 262 transitions. [2018-01-29 22:37:24,961 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 262 transitions. Word has length 86 [2018-01-29 22:37:24,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:24,961 INFO L432 AbstractCegarLoop]: Abstraction has 226 states and 262 transitions. [2018-01-29 22:37:24,962 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-29 22:37:24,962 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 262 transitions. [2018-01-29 22:37:24,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-01-29 22:37:24,962 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:24,962 INFO L350 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:24,962 INFO L371 AbstractCegarLoop]: === Iteration 19 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:24,962 INFO L82 PathProgramCache]: Analyzing trace with hash 1729173138, now seen corresponding path program 16 times [2018-01-29 22:37:24,962 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:24,962 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:24,963 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:24,963 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:24,963 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:24,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:24,967 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:25,678 INFO L134 CoverageAnalysis]: Checked inductivity of 514 backedges. 2 proven. 512 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:25,678 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:25,679 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:25,683 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:37:25,695 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:25,696 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:25,708 INFO L134 CoverageAnalysis]: Checked inductivity of 514 backedges. 2 proven. 512 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:25,730 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:25,730 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 19 [2018-01-29 22:37:25,731 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-29 22:37:25,731 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-29 22:37:25,731 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-01-29 22:37:25,731 INFO L87 Difference]: Start difference. First operand 226 states and 262 transitions. Second operand 19 states. [2018-01-29 22:37:25,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:25,829 INFO L93 Difference]: Finished difference Result 466 states and 544 transitions. [2018-01-29 22:37:25,830 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-29 22:37:25,830 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 90 [2018-01-29 22:37:25,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:25,831 INFO L225 Difference]: With dead ends: 466 [2018-01-29 22:37:25,831 INFO L226 Difference]: Without dead ends: 246 [2018-01-29 22:37:25,831 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-01-29 22:37:25,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-01-29 22:37:25,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 238. [2018-01-29 22:37:25,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-01-29 22:37:25,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 276 transitions. [2018-01-29 22:37:25,834 INFO L78 Accepts]: Start accepts. Automaton has 238 states and 276 transitions. Word has length 90 [2018-01-29 22:37:25,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:25,835 INFO L432 AbstractCegarLoop]: Abstraction has 238 states and 276 transitions. [2018-01-29 22:37:25,835 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-29 22:37:25,835 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 276 transitions. [2018-01-29 22:37:25,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-01-29 22:37:25,835 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:25,835 INFO L350 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:25,835 INFO L371 AbstractCegarLoop]: === Iteration 20 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:25,835 INFO L82 PathProgramCache]: Analyzing trace with hash 476128826, now seen corresponding path program 17 times [2018-01-29 22:37:25,836 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:25,836 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:25,836 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:25,836 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:25,836 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:25,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:25,840 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:25,994 INFO L134 CoverageAnalysis]: Checked inductivity of 580 backedges. 2 proven. 578 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:25,994 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:25,994 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:26,000 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:37:26,002 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,003 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,004 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,005 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,005 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,006 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,013 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,017 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,026 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,036 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,047 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,057 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,061 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,062 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,063 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,064 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,065 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,066 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:26,066 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:26,068 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:26,076 INFO L134 CoverageAnalysis]: Checked inductivity of 580 backedges. 2 proven. 578 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:26,093 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:26,093 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 20 [2018-01-29 22:37:26,093 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-29 22:37:26,094 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-29 22:37:26,094 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-29 22:37:26,094 INFO L87 Difference]: Start difference. First operand 238 states and 276 transitions. Second operand 20 states. [2018-01-29 22:37:26,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:26,328 INFO L93 Difference]: Finished difference Result 490 states and 572 transitions. [2018-01-29 22:37:26,328 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-29 22:37:26,328 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 94 [2018-01-29 22:37:26,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:26,329 INFO L225 Difference]: With dead ends: 490 [2018-01-29 22:37:26,329 INFO L226 Difference]: Without dead ends: 258 [2018-01-29 22:37:26,329 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 95 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-29 22:37:26,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 258 states. [2018-01-29 22:37:26,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 258 to 250. [2018-01-29 22:37:26,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-01-29 22:37:26,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 290 transitions. [2018-01-29 22:37:26,332 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 290 transitions. Word has length 94 [2018-01-29 22:37:26,333 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:26,333 INFO L432 AbstractCegarLoop]: Abstraction has 250 states and 290 transitions. [2018-01-29 22:37:26,333 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-29 22:37:26,333 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 290 transitions. [2018-01-29 22:37:26,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-01-29 22:37:26,334 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:26,334 INFO L350 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:26,334 INFO L371 AbstractCegarLoop]: === Iteration 21 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:26,334 INFO L82 PathProgramCache]: Analyzing trace with hash -2041503262, now seen corresponding path program 18 times [2018-01-29 22:37:26,334 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:26,335 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:26,335 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:26,335 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:26,335 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:26,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:26,341 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:26,502 INFO L134 CoverageAnalysis]: Checked inductivity of 650 backedges. 2 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:26,502 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:26,502 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:26,506 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:37:26,510 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,516 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,527 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,529 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,530 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,531 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,532 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,533 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,533 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,534 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,535 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,536 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,537 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,538 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,539 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,540 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,541 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,542 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,543 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,544 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:26,544 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:26,545 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:26,554 INFO L134 CoverageAnalysis]: Checked inductivity of 650 backedges. 2 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:26,573 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:26,573 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 21 [2018-01-29 22:37:26,574 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-29 22:37:26,574 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-29 22:37:26,574 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2018-01-29 22:37:26,574 INFO L87 Difference]: Start difference. First operand 250 states and 290 transitions. Second operand 21 states. [2018-01-29 22:37:26,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:26,734 INFO L93 Difference]: Finished difference Result 514 states and 600 transitions. [2018-01-29 22:37:26,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-29 22:37:26,734 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 98 [2018-01-29 22:37:26,734 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:26,734 INFO L225 Difference]: With dead ends: 514 [2018-01-29 22:37:26,735 INFO L226 Difference]: Without dead ends: 270 [2018-01-29 22:37:26,735 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 99 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2018-01-29 22:37:26,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states. [2018-01-29 22:37:26,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 262. [2018-01-29 22:37:26,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 262 states. [2018-01-29 22:37:26,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 304 transitions. [2018-01-29 22:37:26,738 INFO L78 Accepts]: Start accepts. Automaton has 262 states and 304 transitions. Word has length 98 [2018-01-29 22:37:26,738 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:26,738 INFO L432 AbstractCegarLoop]: Abstraction has 262 states and 304 transitions. [2018-01-29 22:37:26,738 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-29 22:37:26,738 INFO L276 IsEmpty]: Start isEmpty. Operand 262 states and 304 transitions. [2018-01-29 22:37:26,739 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-01-29 22:37:26,739 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:26,739 INFO L350 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:26,739 INFO L371 AbstractCegarLoop]: === Iteration 22 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:26,739 INFO L82 PathProgramCache]: Analyzing trace with hash 990579082, now seen corresponding path program 19 times [2018-01-29 22:37:26,739 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:26,739 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:26,740 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:26,740 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:26,740 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:26,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:26,744 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:27,212 INFO L134 CoverageAnalysis]: Checked inductivity of 724 backedges. 2 proven. 722 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:27,212 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:27,213 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:27,217 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:27,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:27,227 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:27,236 INFO L134 CoverageAnalysis]: Checked inductivity of 724 backedges. 2 proven. 722 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:27,253 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:27,253 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 22 [2018-01-29 22:37:27,253 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-29 22:37:27,253 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-29 22:37:27,254 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-29 22:37:27,254 INFO L87 Difference]: Start difference. First operand 262 states and 304 transitions. Second operand 22 states. [2018-01-29 22:37:27,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:27,346 INFO L93 Difference]: Finished difference Result 538 states and 628 transitions. [2018-01-29 22:37:27,346 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-29 22:37:27,346 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 102 [2018-01-29 22:37:27,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:27,347 INFO L225 Difference]: With dead ends: 538 [2018-01-29 22:37:27,347 INFO L226 Difference]: Without dead ends: 282 [2018-01-29 22:37:27,348 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 103 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-29 22:37:27,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2018-01-29 22:37:27,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 274. [2018-01-29 22:37:27,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 274 states. [2018-01-29 22:37:27,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 274 states to 274 states and 318 transitions. [2018-01-29 22:37:27,351 INFO L78 Accepts]: Start accepts. Automaton has 274 states and 318 transitions. Word has length 102 [2018-01-29 22:37:27,351 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:27,351 INFO L432 AbstractCegarLoop]: Abstraction has 274 states and 318 transitions. [2018-01-29 22:37:27,351 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-29 22:37:27,351 INFO L276 IsEmpty]: Start isEmpty. Operand 274 states and 318 transitions. [2018-01-29 22:37:27,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-01-29 22:37:27,352 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:27,352 INFO L350 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:27,352 INFO L371 AbstractCegarLoop]: === Iteration 23 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:27,352 INFO L82 PathProgramCache]: Analyzing trace with hash -1413948110, now seen corresponding path program 20 times [2018-01-29 22:37:27,352 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:27,352 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:27,352 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:27,352 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:27,352 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:27,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:27,357 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:27,782 INFO L134 CoverageAnalysis]: Checked inductivity of 802 backedges. 2 proven. 800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:27,782 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:27,783 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:27,799 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:37:27,804 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:27,809 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:27,810 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:27,811 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:27,822 INFO L134 CoverageAnalysis]: Checked inductivity of 802 backedges. 2 proven. 800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:27,839 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:27,839 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 23 [2018-01-29 22:37:27,839 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-29 22:37:27,839 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-29 22:37:27,839 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2018-01-29 22:37:27,839 INFO L87 Difference]: Start difference. First operand 274 states and 318 transitions. Second operand 23 states. [2018-01-29 22:37:27,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:27,957 INFO L93 Difference]: Finished difference Result 562 states and 656 transitions. [2018-01-29 22:37:27,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-29 22:37:27,957 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 106 [2018-01-29 22:37:27,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:27,958 INFO L225 Difference]: With dead ends: 562 [2018-01-29 22:37:27,958 INFO L226 Difference]: Without dead ends: 294 [2018-01-29 22:37:27,958 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 128 GetRequests, 107 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2018-01-29 22:37:27,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 294 states. [2018-01-29 22:37:27,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 294 to 286. [2018-01-29 22:37:27,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 286 states. [2018-01-29 22:37:27,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 286 states to 286 states and 332 transitions. [2018-01-29 22:37:27,961 INFO L78 Accepts]: Start accepts. Automaton has 286 states and 332 transitions. Word has length 106 [2018-01-29 22:37:27,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:27,961 INFO L432 AbstractCegarLoop]: Abstraction has 286 states and 332 transitions. [2018-01-29 22:37:27,961 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-29 22:37:27,961 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 332 transitions. [2018-01-29 22:37:27,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-01-29 22:37:27,962 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:27,962 INFO L350 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:27,962 INFO L371 AbstractCegarLoop]: === Iteration 24 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:27,962 INFO L82 PathProgramCache]: Analyzing trace with hash -1534812966, now seen corresponding path program 21 times [2018-01-29 22:37:27,962 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:27,962 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:27,963 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:27,963 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:27,963 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:27,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:27,967 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:28,268 INFO L134 CoverageAnalysis]: Checked inductivity of 884 backedges. 2 proven. 882 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:28,268 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:28,269 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:28,276 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:37:28,279 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,280 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,281 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,281 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,282 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,283 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,283 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,284 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,285 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,286 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,287 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,288 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,288 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,289 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,290 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,291 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,293 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,294 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,295 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,296 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,297 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,298 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,300 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:28,300 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:28,301 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:28,310 INFO L134 CoverageAnalysis]: Checked inductivity of 884 backedges. 2 proven. 882 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:28,328 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:28,329 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 24 [2018-01-29 22:37:28,329 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-29 22:37:28,329 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-29 22:37:28,329 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-01-29 22:37:28,329 INFO L87 Difference]: Start difference. First operand 286 states and 332 transitions. Second operand 24 states. [2018-01-29 22:37:28,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:28,466 INFO L93 Difference]: Finished difference Result 586 states and 684 transitions. [2018-01-29 22:37:28,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-29 22:37:28,467 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 110 [2018-01-29 22:37:28,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:28,468 INFO L225 Difference]: With dead ends: 586 [2018-01-29 22:37:28,468 INFO L226 Difference]: Without dead ends: 306 [2018-01-29 22:37:28,468 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 111 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-01-29 22:37:28,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306 states. [2018-01-29 22:37:28,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306 to 298. [2018-01-29 22:37:28,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 298 states. [2018-01-29 22:37:28,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 346 transitions. [2018-01-29 22:37:28,471 INFO L78 Accepts]: Start accepts. Automaton has 298 states and 346 transitions. Word has length 110 [2018-01-29 22:37:28,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:28,472 INFO L432 AbstractCegarLoop]: Abstraction has 298 states and 346 transitions. [2018-01-29 22:37:28,472 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-29 22:37:28,472 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 346 transitions. [2018-01-29 22:37:28,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-01-29 22:37:28,472 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:28,472 INFO L350 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:28,473 INFO L371 AbstractCegarLoop]: === Iteration 25 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:28,473 INFO L82 PathProgramCache]: Analyzing trace with hash -862435198, now seen corresponding path program 22 times [2018-01-29 22:37:28,473 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:28,473 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:28,473 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:28,473 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:28,473 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:28,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:28,478 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:28,742 INFO L134 CoverageAnalysis]: Checked inductivity of 970 backedges. 2 proven. 968 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:28,742 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:28,742 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:28,747 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:37:28,758 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:28,760 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:28,769 INFO L134 CoverageAnalysis]: Checked inductivity of 970 backedges. 2 proven. 968 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:28,786 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:28,786 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 25 [2018-01-29 22:37:28,786 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-29 22:37:28,786 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-29 22:37:28,787 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-01-29 22:37:28,787 INFO L87 Difference]: Start difference. First operand 298 states and 346 transitions. Second operand 25 states. [2018-01-29 22:37:28,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:28,901 INFO L93 Difference]: Finished difference Result 610 states and 712 transitions. [2018-01-29 22:37:28,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-29 22:37:28,901 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 114 [2018-01-29 22:37:28,901 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:28,902 INFO L225 Difference]: With dead ends: 610 [2018-01-29 22:37:28,902 INFO L226 Difference]: Without dead ends: 318 [2018-01-29 22:37:28,902 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 138 GetRequests, 115 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-01-29 22:37:28,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 318 states. [2018-01-29 22:37:28,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 318 to 310. [2018-01-29 22:37:28,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 310 states. [2018-01-29 22:37:28,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 310 states to 310 states and 360 transitions. [2018-01-29 22:37:28,905 INFO L78 Accepts]: Start accepts. Automaton has 310 states and 360 transitions. Word has length 114 [2018-01-29 22:37:28,905 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:28,905 INFO L432 AbstractCegarLoop]: Abstraction has 310 states and 360 transitions. [2018-01-29 22:37:28,905 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-29 22:37:28,905 INFO L276 IsEmpty]: Start isEmpty. Operand 310 states and 360 transitions. [2018-01-29 22:37:28,906 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-01-29 22:37:28,906 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:28,906 INFO L350 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:28,906 INFO L371 AbstractCegarLoop]: === Iteration 26 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:28,906 INFO L82 PathProgramCache]: Analyzing trace with hash 639492138, now seen corresponding path program 23 times [2018-01-29 22:37:28,906 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:28,906 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:28,907 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:28,907 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:28,907 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:28,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:28,912 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:29,104 INFO L134 CoverageAnalysis]: Checked inductivity of 1060 backedges. 2 proven. 1058 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:29,104 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:29,104 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:29,109 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:37:29,112 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,114 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,115 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,115 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,116 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,117 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,120 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,121 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,122 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,123 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,124 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,124 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,125 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,126 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,127 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,128 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,129 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,130 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,131 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,132 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,133 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,134 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,135 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,137 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:29,137 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:29,138 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:29,148 INFO L134 CoverageAnalysis]: Checked inductivity of 1060 backedges. 2 proven. 1058 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:29,165 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:29,165 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 26 [2018-01-29 22:37:29,165 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-29 22:37:29,165 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-29 22:37:29,165 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-29 22:37:29,165 INFO L87 Difference]: Start difference. First operand 310 states and 360 transitions. Second operand 26 states. [2018-01-29 22:37:29,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:29,281 INFO L93 Difference]: Finished difference Result 634 states and 740 transitions. [2018-01-29 22:37:29,281 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-29 22:37:29,281 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 118 [2018-01-29 22:37:29,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:29,282 INFO L225 Difference]: With dead ends: 634 [2018-01-29 22:37:29,282 INFO L226 Difference]: Without dead ends: 330 [2018-01-29 22:37:29,282 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 143 GetRequests, 119 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-29 22:37:29,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330 states. [2018-01-29 22:37:29,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330 to 322. [2018-01-29 22:37:29,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 322 states. [2018-01-29 22:37:29,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 374 transitions. [2018-01-29 22:37:29,285 INFO L78 Accepts]: Start accepts. Automaton has 322 states and 374 transitions. Word has length 118 [2018-01-29 22:37:29,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:29,285 INFO L432 AbstractCegarLoop]: Abstraction has 322 states and 374 transitions. [2018-01-29 22:37:29,285 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-29 22:37:29,285 INFO L276 IsEmpty]: Start isEmpty. Operand 322 states and 374 transitions. [2018-01-29 22:37:29,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-29 22:37:29,286 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:29,286 INFO L350 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:29,286 INFO L371 AbstractCegarLoop]: === Iteration 27 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:29,286 INFO L82 PathProgramCache]: Analyzing trace with hash -1908448302, now seen corresponding path program 24 times [2018-01-29 22:37:29,286 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:29,286 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:29,287 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:29,287 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:29,287 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:29,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:29,291 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:29,601 INFO L134 CoverageAnalysis]: Checked inductivity of 1154 backedges. 2 proven. 1152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:29,602 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:29,602 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:29,606 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:37:29,609 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,610 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,611 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,612 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,613 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,613 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,614 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,615 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,616 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,616 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,617 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,618 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,619 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,620 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,621 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,622 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,623 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,624 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,625 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,626 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,627 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,628 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,629 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,630 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,631 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,633 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:29,633 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:29,634 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:29,645 INFO L134 CoverageAnalysis]: Checked inductivity of 1154 backedges. 2 proven. 1152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:29,661 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:29,662 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 27 [2018-01-29 22:37:29,662 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-29 22:37:29,662 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-29 22:37:29,662 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2018-01-29 22:37:29,662 INFO L87 Difference]: Start difference. First operand 322 states and 374 transitions. Second operand 27 states. [2018-01-29 22:37:29,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:29,778 INFO L93 Difference]: Finished difference Result 658 states and 768 transitions. [2018-01-29 22:37:29,779 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-29 22:37:29,779 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 122 [2018-01-29 22:37:29,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:29,779 INFO L225 Difference]: With dead ends: 658 [2018-01-29 22:37:29,779 INFO L226 Difference]: Without dead ends: 342 [2018-01-29 22:37:29,780 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 123 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2018-01-29 22:37:29,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states. [2018-01-29 22:37:29,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 334. [2018-01-29 22:37:29,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 334 states. [2018-01-29 22:37:29,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 334 states to 334 states and 388 transitions. [2018-01-29 22:37:29,783 INFO L78 Accepts]: Start accepts. Automaton has 334 states and 388 transitions. Word has length 122 [2018-01-29 22:37:29,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:29,783 INFO L432 AbstractCegarLoop]: Abstraction has 334 states and 388 transitions. [2018-01-29 22:37:29,783 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-29 22:37:29,783 INFO L276 IsEmpty]: Start isEmpty. Operand 334 states and 388 transitions. [2018-01-29 22:37:29,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-01-29 22:37:29,784 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:29,784 INFO L350 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:29,784 INFO L371 AbstractCegarLoop]: === Iteration 28 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:29,784 INFO L82 PathProgramCache]: Analyzing trace with hash 1025954682, now seen corresponding path program 25 times [2018-01-29 22:37:29,784 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:29,784 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:29,785 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:29,785 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:29,785 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:29,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:29,790 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:30,173 INFO L134 CoverageAnalysis]: Checked inductivity of 1252 backedges. 2 proven. 1250 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:30,174 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:30,174 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:30,178 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:30,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:30,190 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:30,201 INFO L134 CoverageAnalysis]: Checked inductivity of 1252 backedges. 2 proven. 1250 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:30,217 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:30,217 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 28 [2018-01-29 22:37:30,217 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-29 22:37:30,218 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-29 22:37:30,218 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-29 22:37:30,218 INFO L87 Difference]: Start difference. First operand 334 states and 388 transitions. Second operand 28 states. [2018-01-29 22:37:30,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:30,335 INFO L93 Difference]: Finished difference Result 682 states and 796 transitions. [2018-01-29 22:37:30,335 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-29 22:37:30,335 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 126 [2018-01-29 22:37:30,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:30,336 INFO L225 Difference]: With dead ends: 682 [2018-01-29 22:37:30,336 INFO L226 Difference]: Without dead ends: 354 [2018-01-29 22:37:30,337 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 153 GetRequests, 127 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-29 22:37:30,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354 states. [2018-01-29 22:37:30,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354 to 346. [2018-01-29 22:37:30,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 346 states. [2018-01-29 22:37:30,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 346 states to 346 states and 402 transitions. [2018-01-29 22:37:30,340 INFO L78 Accepts]: Start accepts. Automaton has 346 states and 402 transitions. Word has length 126 [2018-01-29 22:37:30,340 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:30,340 INFO L432 AbstractCegarLoop]: Abstraction has 346 states and 402 transitions. [2018-01-29 22:37:30,340 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-29 22:37:30,340 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 402 transitions. [2018-01-29 22:37:30,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-01-29 22:37:30,341 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:30,341 INFO L350 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:30,341 INFO L371 AbstractCegarLoop]: === Iteration 29 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:30,341 INFO L82 PathProgramCache]: Analyzing trace with hash 1174286114, now seen corresponding path program 26 times [2018-01-29 22:37:30,341 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:30,341 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:30,341 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:30,342 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:30,342 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:30,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:30,346 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:30,971 INFO L134 CoverageAnalysis]: Checked inductivity of 1354 backedges. 2 proven. 1352 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:30,971 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:30,971 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:30,982 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:37:30,986 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:30,992 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:30,994 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:30,996 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:31,008 INFO L134 CoverageAnalysis]: Checked inductivity of 1354 backedges. 2 proven. 1352 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:31,025 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:31,025 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 29 [2018-01-29 22:37:31,025 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-29 22:37:31,026 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-29 22:37:31,026 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2018-01-29 22:37:31,026 INFO L87 Difference]: Start difference. First operand 346 states and 402 transitions. Second operand 29 states. [2018-01-29 22:37:31,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:31,182 INFO L93 Difference]: Finished difference Result 706 states and 824 transitions. [2018-01-29 22:37:31,183 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-29 22:37:31,183 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 130 [2018-01-29 22:37:31,183 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:31,184 INFO L225 Difference]: With dead ends: 706 [2018-01-29 22:37:31,184 INFO L226 Difference]: Without dead ends: 366 [2018-01-29 22:37:31,185 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 131 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2018-01-29 22:37:31,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states. [2018-01-29 22:37:31,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 358. [2018-01-29 22:37:31,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 358 states. [2018-01-29 22:37:31,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 358 states to 358 states and 416 transitions. [2018-01-29 22:37:31,189 INFO L78 Accepts]: Start accepts. Automaton has 358 states and 416 transitions. Word has length 130 [2018-01-29 22:37:31,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:31,189 INFO L432 AbstractCegarLoop]: Abstraction has 358 states and 416 transitions. [2018-01-29 22:37:31,189 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-29 22:37:31,189 INFO L276 IsEmpty]: Start isEmpty. Operand 358 states and 416 transitions. [2018-01-29 22:37:31,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-01-29 22:37:31,189 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:31,189 INFO L350 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:31,190 INFO L371 AbstractCegarLoop]: === Iteration 30 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:31,190 INFO L82 PathProgramCache]: Analyzing trace with hash 384792266, now seen corresponding path program 27 times [2018-01-29 22:37:31,190 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:31,190 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:31,190 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:31,190 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:31,190 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:31,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:31,195 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:31,832 INFO L134 CoverageAnalysis]: Checked inductivity of 1460 backedges. 2 proven. 1458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:31,833 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:31,833 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:31,839 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:37:31,843 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,843 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,844 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,845 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,846 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,847 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,848 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,849 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,849 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,850 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,851 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,852 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,854 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,855 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,856 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,857 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,858 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,859 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,860 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,861 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,863 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,864 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,866 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,867 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,869 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,870 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,871 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,873 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,874 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:31,875 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:31,876 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:31,888 INFO L134 CoverageAnalysis]: Checked inductivity of 1460 backedges. 2 proven. 1458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:31,905 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:31,905 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 30 [2018-01-29 22:37:31,905 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-29 22:37:31,905 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-29 22:37:31,905 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-01-29 22:37:31,906 INFO L87 Difference]: Start difference. First operand 358 states and 416 transitions. Second operand 30 states. [2018-01-29 22:37:32,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:32,046 INFO L93 Difference]: Finished difference Result 730 states and 852 transitions. [2018-01-29 22:37:32,046 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-29 22:37:32,046 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 134 [2018-01-29 22:37:32,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:32,047 INFO L225 Difference]: With dead ends: 730 [2018-01-29 22:37:32,047 INFO L226 Difference]: Without dead ends: 378 [2018-01-29 22:37:32,047 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 135 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-01-29 22:37:32,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 378 states. [2018-01-29 22:37:32,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 378 to 370. [2018-01-29 22:37:32,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 370 states. [2018-01-29 22:37:32,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 370 states to 370 states and 430 transitions. [2018-01-29 22:37:32,050 INFO L78 Accepts]: Start accepts. Automaton has 370 states and 430 transitions. Word has length 134 [2018-01-29 22:37:32,051 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:32,051 INFO L432 AbstractCegarLoop]: Abstraction has 370 states and 430 transitions. [2018-01-29 22:37:32,051 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-29 22:37:32,051 INFO L276 IsEmpty]: Start isEmpty. Operand 370 states and 430 transitions. [2018-01-29 22:37:32,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-01-29 22:37:32,051 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:32,051 INFO L350 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:32,051 INFO L371 AbstractCegarLoop]: === Iteration 31 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:32,051 INFO L82 PathProgramCache]: Analyzing trace with hash -115037582, now seen corresponding path program 28 times [2018-01-29 22:37:32,052 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:32,052 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:32,052 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:32,052 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:32,052 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:32,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:32,057 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:32,370 INFO L134 CoverageAnalysis]: Checked inductivity of 1570 backedges. 2 proven. 1568 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:32,371 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:32,371 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:32,376 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:37:32,388 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:32,390 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:32,409 INFO L134 CoverageAnalysis]: Checked inductivity of 1570 backedges. 2 proven. 1568 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:32,425 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:32,425 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 31 [2018-01-29 22:37:32,426 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-01-29 22:37:32,426 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-01-29 22:37:32,426 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2018-01-29 22:37:32,426 INFO L87 Difference]: Start difference. First operand 370 states and 430 transitions. Second operand 31 states. [2018-01-29 22:37:32,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:32,607 INFO L93 Difference]: Finished difference Result 754 states and 880 transitions. [2018-01-29 22:37:32,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-29 22:37:32,607 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 138 [2018-01-29 22:37:32,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:32,608 INFO L225 Difference]: With dead ends: 754 [2018-01-29 22:37:32,608 INFO L226 Difference]: Without dead ends: 390 [2018-01-29 22:37:32,609 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 168 GetRequests, 139 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2018-01-29 22:37:32,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 390 states. [2018-01-29 22:37:32,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 390 to 382. [2018-01-29 22:37:32,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2018-01-29 22:37:32,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 444 transitions. [2018-01-29 22:37:32,613 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 444 transitions. Word has length 138 [2018-01-29 22:37:32,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:32,613 INFO L432 AbstractCegarLoop]: Abstraction has 382 states and 444 transitions. [2018-01-29 22:37:32,613 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-01-29 22:37:32,613 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 444 transitions. [2018-01-29 22:37:32,614 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-01-29 22:37:32,614 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:32,614 INFO L350 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:32,614 INFO L371 AbstractCegarLoop]: === Iteration 32 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:32,614 INFO L82 PathProgramCache]: Analyzing trace with hash -1865954790, now seen corresponding path program 29 times [2018-01-29 22:37:32,614 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:32,614 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:32,615 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:32,615 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:32,615 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:32,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:32,620 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:32,950 INFO L134 CoverageAnalysis]: Checked inductivity of 1684 backedges. 2 proven. 1682 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:32,950 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:32,950 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:32,954 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:37:32,957 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,958 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,958 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,959 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,960 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,960 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,961 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,962 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,963 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,964 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,965 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,965 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,967 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,968 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,969 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,970 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,971 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,972 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,973 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,975 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,976 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,977 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,978 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,980 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,981 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,983 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,984 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,986 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,988 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,990 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:32,990 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:32,992 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:33,005 INFO L134 CoverageAnalysis]: Checked inductivity of 1684 backedges. 2 proven. 1682 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:33,021 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:33,021 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 32 [2018-01-29 22:37:33,022 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-01-29 22:37:33,022 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-01-29 22:37:33,022 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-29 22:37:33,022 INFO L87 Difference]: Start difference. First operand 382 states and 444 transitions. Second operand 32 states. [2018-01-29 22:37:33,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:33,161 INFO L93 Difference]: Finished difference Result 778 states and 908 transitions. [2018-01-29 22:37:33,162 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-01-29 22:37:33,162 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 142 [2018-01-29 22:37:33,162 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:33,162 INFO L225 Difference]: With dead ends: 778 [2018-01-29 22:37:33,162 INFO L226 Difference]: Without dead ends: 402 [2018-01-29 22:37:33,163 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 173 GetRequests, 143 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-29 22:37:33,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 402 states. [2018-01-29 22:37:33,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 402 to 394. [2018-01-29 22:37:33,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 394 states. [2018-01-29 22:37:33,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 394 states to 394 states and 458 transitions. [2018-01-29 22:37:33,166 INFO L78 Accepts]: Start accepts. Automaton has 394 states and 458 transitions. Word has length 142 [2018-01-29 22:37:33,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:33,166 INFO L432 AbstractCegarLoop]: Abstraction has 394 states and 458 transitions. [2018-01-29 22:37:33,167 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-01-29 22:37:33,167 INFO L276 IsEmpty]: Start isEmpty. Operand 394 states and 458 transitions. [2018-01-29 22:37:33,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-01-29 22:37:33,167 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:33,167 INFO L350 BasicCegarLoop]: trace histogram [31, 30, 30, 30, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:33,167 INFO L371 AbstractCegarLoop]: === Iteration 33 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:33,167 INFO L82 PathProgramCache]: Analyzing trace with hash 1560466882, now seen corresponding path program 30 times [2018-01-29 22:37:33,168 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:33,168 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:33,168 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:33,168 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:33,168 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:33,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:33,173 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:33,864 INFO L134 CoverageAnalysis]: Checked inductivity of 1802 backedges. 2 proven. 1800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:33,864 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:33,864 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:33,868 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:37:33,872 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,873 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,874 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,874 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,875 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,876 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,877 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,877 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,878 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,879 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,880 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,881 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,882 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,882 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,884 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,885 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,886 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,887 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,888 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,889 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,890 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,891 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,893 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,894 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,895 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,896 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,897 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,898 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,900 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,901 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,902 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,904 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:33,904 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:33,905 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:33,919 INFO L134 CoverageAnalysis]: Checked inductivity of 1802 backedges. 2 proven. 1800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:33,936 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:33,936 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 33 [2018-01-29 22:37:33,936 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-29 22:37:33,936 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-29 22:37:33,936 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-01-29 22:37:33,937 INFO L87 Difference]: Start difference. First operand 394 states and 458 transitions. Second operand 33 states. [2018-01-29 22:37:34,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:34,199 INFO L93 Difference]: Finished difference Result 802 states and 936 transitions. [2018-01-29 22:37:34,202 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-01-29 22:37:34,202 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 146 [2018-01-29 22:37:34,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:34,203 INFO L225 Difference]: With dead ends: 802 [2018-01-29 22:37:34,203 INFO L226 Difference]: Without dead ends: 414 [2018-01-29 22:37:34,203 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 178 GetRequests, 147 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-01-29 22:37:34,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 414 states. [2018-01-29 22:37:34,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 414 to 406. [2018-01-29 22:37:34,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 406 states. [2018-01-29 22:37:34,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 406 states to 406 states and 472 transitions. [2018-01-29 22:37:34,207 INFO L78 Accepts]: Start accepts. Automaton has 406 states and 472 transitions. Word has length 146 [2018-01-29 22:37:34,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:34,207 INFO L432 AbstractCegarLoop]: Abstraction has 406 states and 472 transitions. [2018-01-29 22:37:34,207 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-29 22:37:34,207 INFO L276 IsEmpty]: Start isEmpty. Operand 406 states and 472 transitions. [2018-01-29 22:37:34,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-01-29 22:37:34,208 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:34,208 INFO L350 BasicCegarLoop]: trace histogram [32, 31, 31, 31, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:34,208 INFO L371 AbstractCegarLoop]: === Iteration 34 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:34,208 INFO L82 PathProgramCache]: Analyzing trace with hash 939511146, now seen corresponding path program 31 times [2018-01-29 22:37:34,208 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:34,208 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:34,209 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:34,209 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:34,209 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:34,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:34,214 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:34,589 INFO L134 CoverageAnalysis]: Checked inductivity of 1924 backedges. 2 proven. 1922 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:34,589 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:34,589 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:34,594 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:34,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:34,609 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:34,623 INFO L134 CoverageAnalysis]: Checked inductivity of 1924 backedges. 2 proven. 1922 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:34,640 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:34,640 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 34 [2018-01-29 22:37:34,640 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-01-29 22:37:34,640 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-01-29 22:37:34,640 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-29 22:37:34,640 INFO L87 Difference]: Start difference. First operand 406 states and 472 transitions. Second operand 34 states. [2018-01-29 22:37:34,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:34,824 INFO L93 Difference]: Finished difference Result 826 states and 964 transitions. [2018-01-29 22:37:34,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-01-29 22:37:34,824 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 150 [2018-01-29 22:37:34,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:34,826 INFO L225 Difference]: With dead ends: 826 [2018-01-29 22:37:34,826 INFO L226 Difference]: Without dead ends: 426 [2018-01-29 22:37:34,827 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 151 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-29 22:37:34,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 426 states. [2018-01-29 22:37:34,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 426 to 418. [2018-01-29 22:37:34,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 418 states. [2018-01-29 22:37:34,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 418 states to 418 states and 486 transitions. [2018-01-29 22:37:34,831 INFO L78 Accepts]: Start accepts. Automaton has 418 states and 486 transitions. Word has length 150 [2018-01-29 22:37:34,831 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:34,831 INFO L432 AbstractCegarLoop]: Abstraction has 418 states and 486 transitions. [2018-01-29 22:37:34,832 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-01-29 22:37:34,832 INFO L276 IsEmpty]: Start isEmpty. Operand 418 states and 486 transitions. [2018-01-29 22:37:34,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2018-01-29 22:37:34,833 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:34,833 INFO L350 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:34,833 INFO L371 AbstractCegarLoop]: === Iteration 35 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:34,833 INFO L82 PathProgramCache]: Analyzing trace with hash -689393390, now seen corresponding path program 32 times [2018-01-29 22:37:34,833 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:34,833 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:34,833 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:34,834 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:34,834 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:34,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:34,839 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:35,535 INFO L134 CoverageAnalysis]: Checked inductivity of 2050 backedges. 2 proven. 2048 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:35,535 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:35,535 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:35,540 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:37:35,544 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:35,552 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:35,554 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:35,556 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:35,581 INFO L134 CoverageAnalysis]: Checked inductivity of 2050 backedges. 2 proven. 2048 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:35,597 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:35,598 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 35 [2018-01-29 22:37:35,598 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-01-29 22:37:35,598 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-01-29 22:37:35,598 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2018-01-29 22:37:35,598 INFO L87 Difference]: Start difference. First operand 418 states and 486 transitions. Second operand 35 states. [2018-01-29 22:37:35,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:35,778 INFO L93 Difference]: Finished difference Result 850 states and 992 transitions. [2018-01-29 22:37:35,786 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-01-29 22:37:35,786 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 154 [2018-01-29 22:37:35,787 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:35,787 INFO L225 Difference]: With dead ends: 850 [2018-01-29 22:37:35,788 INFO L226 Difference]: Without dead ends: 438 [2018-01-29 22:37:35,788 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 188 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2018-01-29 22:37:35,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 438 states. [2018-01-29 22:37:35,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 438 to 430. [2018-01-29 22:37:35,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 430 states. [2018-01-29 22:37:35,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 500 transitions. [2018-01-29 22:37:35,792 INFO L78 Accepts]: Start accepts. Automaton has 430 states and 500 transitions. Word has length 154 [2018-01-29 22:37:35,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:35,792 INFO L432 AbstractCegarLoop]: Abstraction has 430 states and 500 transitions. [2018-01-29 22:37:35,792 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-01-29 22:37:35,792 INFO L276 IsEmpty]: Start isEmpty. Operand 430 states and 500 transitions. [2018-01-29 22:37:35,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-01-29 22:37:35,793 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:35,793 INFO L350 BasicCegarLoop]: trace histogram [34, 33, 33, 33, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:35,793 INFO L371 AbstractCegarLoop]: === Iteration 36 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:35,793 INFO L82 PathProgramCache]: Analyzing trace with hash 1239908538, now seen corresponding path program 33 times [2018-01-29 22:37:35,793 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:35,793 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:35,794 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:35,794 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:35,794 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:35,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:35,799 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:36,194 INFO L134 CoverageAnalysis]: Checked inductivity of 2180 backedges. 2 proven. 2178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:36,195 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:36,195 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:36,200 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:37:36,204 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,217 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,223 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,233 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,240 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,250 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,260 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,266 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,267 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,268 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,269 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,270 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,271 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,272 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,273 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,274 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,275 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,276 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,277 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,278 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,279 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,280 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,281 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,282 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,283 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,285 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,286 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,287 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,288 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,290 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,291 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,293 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,295 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,296 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,298 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:36,298 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:36,300 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:36,315 INFO L134 CoverageAnalysis]: Checked inductivity of 2180 backedges. 2 proven. 2178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:36,331 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:36,332 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 36 [2018-01-29 22:37:36,332 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-01-29 22:37:36,332 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-01-29 22:37:36,332 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-01-29 22:37:36,332 INFO L87 Difference]: Start difference. First operand 430 states and 500 transitions. Second operand 36 states. [2018-01-29 22:37:36,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:36,506 INFO L93 Difference]: Finished difference Result 874 states and 1020 transitions. [2018-01-29 22:37:36,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-01-29 22:37:36,506 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 158 [2018-01-29 22:37:36,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:36,507 INFO L225 Difference]: With dead ends: 874 [2018-01-29 22:37:36,508 INFO L226 Difference]: Without dead ends: 450 [2018-01-29 22:37:36,508 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 193 GetRequests, 159 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-01-29 22:37:36,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 450 states. [2018-01-29 22:37:36,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 450 to 442. [2018-01-29 22:37:36,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 442 states. [2018-01-29 22:37:36,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 442 states to 442 states and 514 transitions. [2018-01-29 22:37:36,512 INFO L78 Accepts]: Start accepts. Automaton has 442 states and 514 transitions. Word has length 158 [2018-01-29 22:37:36,512 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:36,513 INFO L432 AbstractCegarLoop]: Abstraction has 442 states and 514 transitions. [2018-01-29 22:37:36,513 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-01-29 22:37:36,513 INFO L276 IsEmpty]: Start isEmpty. Operand 442 states and 514 transitions. [2018-01-29 22:37:36,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2018-01-29 22:37:36,513 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:36,513 INFO L350 BasicCegarLoop]: trace histogram [35, 34, 34, 34, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:36,513 INFO L371 AbstractCegarLoop]: === Iteration 37 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:36,514 INFO L82 PathProgramCache]: Analyzing trace with hash 2082880610, now seen corresponding path program 34 times [2018-01-29 22:37:36,514 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:36,514 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:36,514 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:36,514 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:36,514 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:36,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:36,519 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:37,568 INFO L134 CoverageAnalysis]: Checked inductivity of 2314 backedges. 2 proven. 2312 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:37,568 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:37,569 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:37,573 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:37:37,613 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:37,615 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:37,631 INFO L134 CoverageAnalysis]: Checked inductivity of 2314 backedges. 2 proven. 2312 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:37,649 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:37,649 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 37 [2018-01-29 22:37:37,649 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-01-29 22:37:37,650 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-01-29 22:37:37,650 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2018-01-29 22:37:37,650 INFO L87 Difference]: Start difference. First operand 442 states and 514 transitions. Second operand 37 states. [2018-01-29 22:37:38,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:38,999 INFO L93 Difference]: Finished difference Result 898 states and 1048 transitions. [2018-01-29 22:37:39,000 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-01-29 22:37:39,000 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 162 [2018-01-29 22:37:39,000 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:39,001 INFO L225 Difference]: With dead ends: 898 [2018-01-29 22:37:39,001 INFO L226 Difference]: Without dead ends: 462 [2018-01-29 22:37:39,002 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 163 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2018-01-29 22:37:39,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-01-29 22:37:39,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 454. [2018-01-29 22:37:39,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. [2018-01-29 22:37:39,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 528 transitions. [2018-01-29 22:37:39,005 INFO L78 Accepts]: Start accepts. Automaton has 454 states and 528 transitions. Word has length 162 [2018-01-29 22:37:39,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:39,005 INFO L432 AbstractCegarLoop]: Abstraction has 454 states and 528 transitions. [2018-01-29 22:37:39,005 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-01-29 22:37:39,005 INFO L276 IsEmpty]: Start isEmpty. Operand 454 states and 528 transitions. [2018-01-29 22:37:39,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2018-01-29 22:37:39,006 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:39,006 INFO L350 BasicCegarLoop]: trace histogram [36, 35, 35, 35, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:39,006 INFO L371 AbstractCegarLoop]: === Iteration 38 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:39,006 INFO L82 PathProgramCache]: Analyzing trace with hash -1278286838, now seen corresponding path program 35 times [2018-01-29 22:37:39,006 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:39,006 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:39,007 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:39,007 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:39,007 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:39,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:39,012 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:39,516 INFO L134 CoverageAnalysis]: Checked inductivity of 2452 backedges. 2 proven. 2450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:39,517 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:39,517 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:39,522 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:37:39,525 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,526 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,526 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,527 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,528 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,529 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,530 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,531 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,532 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,533 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,534 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,535 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,536 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,537 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,538 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,539 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,540 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,541 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,542 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,543 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,544 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,545 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,547 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,548 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,549 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,550 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,552 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,553 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,554 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,555 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,558 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,559 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,561 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,563 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,570 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,580 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:39,585 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:39,587 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:39,607 INFO L134 CoverageAnalysis]: Checked inductivity of 2452 backedges. 2 proven. 2450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:39,624 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:39,624 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 38 [2018-01-29 22:37:39,624 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-01-29 22:37:39,625 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-01-29 22:37:39,625 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-29 22:37:39,625 INFO L87 Difference]: Start difference. First operand 454 states and 528 transitions. Second operand 38 states. [2018-01-29 22:37:40,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:40,006 INFO L93 Difference]: Finished difference Result 922 states and 1076 transitions. [2018-01-29 22:37:40,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-01-29 22:37:40,006 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 166 [2018-01-29 22:37:40,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:40,007 INFO L225 Difference]: With dead ends: 922 [2018-01-29 22:37:40,007 INFO L226 Difference]: Without dead ends: 474 [2018-01-29 22:37:40,008 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 167 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-29 22:37:40,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 474 states. [2018-01-29 22:37:40,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 474 to 466. [2018-01-29 22:37:40,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 466 states. [2018-01-29 22:37:40,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 466 states to 466 states and 542 transitions. [2018-01-29 22:37:40,011 INFO L78 Accepts]: Start accepts. Automaton has 466 states and 542 transitions. Word has length 166 [2018-01-29 22:37:40,011 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:40,011 INFO L432 AbstractCegarLoop]: Abstraction has 466 states and 542 transitions. [2018-01-29 22:37:40,011 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-01-29 22:37:40,012 INFO L276 IsEmpty]: Start isEmpty. Operand 466 states and 542 transitions. [2018-01-29 22:37:40,012 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2018-01-29 22:37:40,012 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:40,012 INFO L350 BasicCegarLoop]: trace histogram [37, 36, 36, 36, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:40,012 INFO L371 AbstractCegarLoop]: === Iteration 39 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:40,012 INFO L82 PathProgramCache]: Analyzing trace with hash 302741426, now seen corresponding path program 36 times [2018-01-29 22:37:40,013 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:40,013 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:40,013 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:40,013 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:40,013 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:40,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:40,019 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:41,408 INFO L134 CoverageAnalysis]: Checked inductivity of 2594 backedges. 2 proven. 2592 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:41,408 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:41,408 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:41,413 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:37:41,419 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,422 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,423 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,423 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,424 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,425 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,426 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,426 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,427 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,428 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,429 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,430 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,430 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,431 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,432 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,433 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,440 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,441 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,442 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,443 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,444 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,445 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,446 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,447 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,448 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,450 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,451 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,452 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,453 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,455 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,456 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,457 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,459 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,460 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,461 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,463 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,465 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,466 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:41,467 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:41,468 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:41,484 INFO L134 CoverageAnalysis]: Checked inductivity of 2594 backedges. 2 proven. 2592 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:41,501 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:41,501 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 39 [2018-01-29 22:37:41,501 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-01-29 22:37:41,502 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-01-29 22:37:41,502 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2018-01-29 22:37:41,502 INFO L87 Difference]: Start difference. First operand 466 states and 542 transitions. Second operand 39 states. [2018-01-29 22:37:41,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:41,721 INFO L93 Difference]: Finished difference Result 946 states and 1104 transitions. [2018-01-29 22:37:41,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-01-29 22:37:41,721 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 170 [2018-01-29 22:37:41,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:41,722 INFO L225 Difference]: With dead ends: 946 [2018-01-29 22:37:41,722 INFO L226 Difference]: Without dead ends: 486 [2018-01-29 22:37:41,722 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 208 GetRequests, 171 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2018-01-29 22:37:41,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 486 states. [2018-01-29 22:37:41,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 486 to 478. [2018-01-29 22:37:41,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 478 states. [2018-01-29 22:37:41,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 478 states to 478 states and 556 transitions. [2018-01-29 22:37:41,726 INFO L78 Accepts]: Start accepts. Automaton has 478 states and 556 transitions. Word has length 170 [2018-01-29 22:37:41,726 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:41,726 INFO L432 AbstractCegarLoop]: Abstraction has 478 states and 556 transitions. [2018-01-29 22:37:41,726 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-01-29 22:37:41,726 INFO L276 IsEmpty]: Start isEmpty. Operand 478 states and 556 transitions. [2018-01-29 22:37:41,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-01-29 22:37:41,727 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:41,727 INFO L350 BasicCegarLoop]: trace histogram [38, 37, 37, 37, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:41,727 INFO L371 AbstractCegarLoop]: === Iteration 40 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:41,727 INFO L82 PathProgramCache]: Analyzing trace with hash 319158106, now seen corresponding path program 37 times [2018-01-29 22:37:41,727 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:41,727 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:41,728 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:41,728 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:41,728 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:41,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:41,733 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:42,271 INFO L134 CoverageAnalysis]: Checked inductivity of 2740 backedges. 2 proven. 2738 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:42,271 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:42,271 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:42,276 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:42,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:42,291 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:42,308 INFO L134 CoverageAnalysis]: Checked inductivity of 2740 backedges. 2 proven. 2738 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:42,325 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:42,325 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 40 [2018-01-29 22:37:42,325 INFO L409 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-01-29 22:37:42,325 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-01-29 22:37:42,326 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-29 22:37:42,326 INFO L87 Difference]: Start difference. First operand 478 states and 556 transitions. Second operand 40 states. [2018-01-29 22:37:42,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:42,619 INFO L93 Difference]: Finished difference Result 970 states and 1132 transitions. [2018-01-29 22:37:42,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-01-29 22:37:42,619 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 174 [2018-01-29 22:37:42,620 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:42,621 INFO L225 Difference]: With dead ends: 970 [2018-01-29 22:37:42,621 INFO L226 Difference]: Without dead ends: 498 [2018-01-29 22:37:42,621 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 213 GetRequests, 175 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-29 22:37:42,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states. [2018-01-29 22:37:42,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 490. [2018-01-29 22:37:42,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 490 states. [2018-01-29 22:37:42,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 490 states to 490 states and 570 transitions. [2018-01-29 22:37:42,625 INFO L78 Accepts]: Start accepts. Automaton has 490 states and 570 transitions. Word has length 174 [2018-01-29 22:37:42,625 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:42,625 INFO L432 AbstractCegarLoop]: Abstraction has 490 states and 570 transitions. [2018-01-29 22:37:42,625 INFO L433 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-01-29 22:37:42,625 INFO L276 IsEmpty]: Start isEmpty. Operand 490 states and 570 transitions. [2018-01-29 22:37:42,626 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2018-01-29 22:37:42,626 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:42,626 INFO L350 BasicCegarLoop]: trace histogram [39, 38, 38, 38, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:42,626 INFO L371 AbstractCegarLoop]: === Iteration 41 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:42,626 INFO L82 PathProgramCache]: Analyzing trace with hash 233333506, now seen corresponding path program 38 times [2018-01-29 22:37:42,626 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:42,626 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:42,627 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:42,627 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:42,627 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:42,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:42,632 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:43,352 INFO L134 CoverageAnalysis]: Checked inductivity of 2890 backedges. 2 proven. 2888 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:43,353 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:43,353 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:43,357 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:37:43,360 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:43,368 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:43,371 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:43,373 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:43,392 INFO L134 CoverageAnalysis]: Checked inductivity of 2890 backedges. 2 proven. 2888 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:43,410 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:43,410 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41] total 41 [2018-01-29 22:37:43,410 INFO L409 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-01-29 22:37:43,411 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-01-29 22:37:43,411 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2018-01-29 22:37:43,411 INFO L87 Difference]: Start difference. First operand 490 states and 570 transitions. Second operand 41 states. [2018-01-29 22:37:43,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:43,617 INFO L93 Difference]: Finished difference Result 994 states and 1160 transitions. [2018-01-29 22:37:43,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-01-29 22:37:43,619 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 178 [2018-01-29 22:37:43,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:43,620 INFO L225 Difference]: With dead ends: 994 [2018-01-29 22:37:43,620 INFO L226 Difference]: Without dead ends: 510 [2018-01-29 22:37:43,621 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 218 GetRequests, 179 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2018-01-29 22:37:43,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 510 states. [2018-01-29 22:37:43,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 510 to 502. [2018-01-29 22:37:43,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 502 states. [2018-01-29 22:37:43,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 502 states to 502 states and 584 transitions. [2018-01-29 22:37:43,624 INFO L78 Accepts]: Start accepts. Automaton has 502 states and 584 transitions. Word has length 178 [2018-01-29 22:37:43,624 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:43,624 INFO L432 AbstractCegarLoop]: Abstraction has 502 states and 584 transitions. [2018-01-29 22:37:43,624 INFO L433 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-01-29 22:37:43,624 INFO L276 IsEmpty]: Start isEmpty. Operand 502 states and 584 transitions. [2018-01-29 22:37:43,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-01-29 22:37:43,625 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:43,625 INFO L350 BasicCegarLoop]: trace histogram [40, 39, 39, 39, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:43,625 INFO L371 AbstractCegarLoop]: === Iteration 42 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:43,625 INFO L82 PathProgramCache]: Analyzing trace with hash -1260602710, now seen corresponding path program 39 times [2018-01-29 22:37:43,625 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:43,625 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:43,630 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:43,630 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:43,630 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:43,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:43,635 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:44,659 INFO L134 CoverageAnalysis]: Checked inductivity of 3044 backedges. 2 proven. 3042 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:44,659 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:44,659 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:44,664 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:37:44,668 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,669 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,670 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,670 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,671 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,672 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,672 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,673 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,674 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,675 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,676 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,676 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,677 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,678 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,679 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,680 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,681 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,682 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,683 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,684 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,685 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,687 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,688 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,689 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,691 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,692 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,693 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,695 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,696 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,698 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,699 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,701 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,702 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,704 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,706 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,707 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,709 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,711 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,713 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,715 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,716 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:44,717 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:44,719 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:44,737 INFO L134 CoverageAnalysis]: Checked inductivity of 3044 backedges. 2 proven. 3042 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:44,757 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:44,757 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 42 [2018-01-29 22:37:44,757 INFO L409 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-01-29 22:37:44,757 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-01-29 22:37:44,758 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-01-29 22:37:44,758 INFO L87 Difference]: Start difference. First operand 502 states and 584 transitions. Second operand 42 states. [2018-01-29 22:37:45,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:45,962 INFO L93 Difference]: Finished difference Result 1018 states and 1188 transitions. [2018-01-29 22:37:45,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-01-29 22:37:45,962 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 182 [2018-01-29 22:37:45,962 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:45,963 INFO L225 Difference]: With dead ends: 1018 [2018-01-29 22:37:45,963 INFO L226 Difference]: Without dead ends: 522 [2018-01-29 22:37:45,964 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 223 GetRequests, 183 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-01-29 22:37:45,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states. [2018-01-29 22:37:45,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 514. [2018-01-29 22:37:45,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 514 states. [2018-01-29 22:37:45,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 514 states to 514 states and 598 transitions. [2018-01-29 22:37:45,967 INFO L78 Accepts]: Start accepts. Automaton has 514 states and 598 transitions. Word has length 182 [2018-01-29 22:37:45,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:45,967 INFO L432 AbstractCegarLoop]: Abstraction has 514 states and 598 transitions. [2018-01-29 22:37:45,968 INFO L433 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-01-29 22:37:45,968 INFO L276 IsEmpty]: Start isEmpty. Operand 514 states and 598 transitions. [2018-01-29 22:37:45,968 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2018-01-29 22:37:45,968 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:45,968 INFO L350 BasicCegarLoop]: trace histogram [41, 40, 40, 40, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:45,968 INFO L371 AbstractCegarLoop]: === Iteration 43 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:45,969 INFO L82 PathProgramCache]: Analyzing trace with hash -1794310574, now seen corresponding path program 40 times [2018-01-29 22:37:45,969 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:45,969 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:45,969 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:45,969 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:45,969 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:45,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:45,975 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:46,532 INFO L134 CoverageAnalysis]: Checked inductivity of 3202 backedges. 2 proven. 3200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:46,532 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:46,533 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:46,542 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:37:46,558 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:46,560 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:46,579 INFO L134 CoverageAnalysis]: Checked inductivity of 3202 backedges. 2 proven. 3200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:46,596 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:46,597 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 43 [2018-01-29 22:37:46,597 INFO L409 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-01-29 22:37:46,597 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-01-29 22:37:46,597 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2018-01-29 22:37:46,597 INFO L87 Difference]: Start difference. First operand 514 states and 598 transitions. Second operand 43 states. [2018-01-29 22:37:46,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:46,871 INFO L93 Difference]: Finished difference Result 1042 states and 1216 transitions. [2018-01-29 22:37:46,871 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-01-29 22:37:46,871 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 186 [2018-01-29 22:37:46,871 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:46,872 INFO L225 Difference]: With dead ends: 1042 [2018-01-29 22:37:46,872 INFO L226 Difference]: Without dead ends: 534 [2018-01-29 22:37:46,873 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 228 GetRequests, 187 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2018-01-29 22:37:46,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 534 states. [2018-01-29 22:37:46,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 534 to 526. [2018-01-29 22:37:46,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 526 states. [2018-01-29 22:37:46,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 526 states to 526 states and 612 transitions. [2018-01-29 22:37:46,877 INFO L78 Accepts]: Start accepts. Automaton has 526 states and 612 transitions. Word has length 186 [2018-01-29 22:37:46,877 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:46,877 INFO L432 AbstractCegarLoop]: Abstraction has 526 states and 612 transitions. [2018-01-29 22:37:46,877 INFO L433 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-01-29 22:37:46,877 INFO L276 IsEmpty]: Start isEmpty. Operand 526 states and 612 transitions. [2018-01-29 22:37:46,878 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2018-01-29 22:37:46,878 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:46,878 INFO L350 BasicCegarLoop]: trace histogram [42, 41, 41, 41, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:46,878 INFO L371 AbstractCegarLoop]: === Iteration 44 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:46,878 INFO L82 PathProgramCache]: Analyzing trace with hash -1767690758, now seen corresponding path program 41 times [2018-01-29 22:37:46,878 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:46,878 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:46,878 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:46,878 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:46,879 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:46,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:46,884 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:47,411 INFO L134 CoverageAnalysis]: Checked inductivity of 3364 backedges. 2 proven. 3362 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:47,411 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:47,411 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:47,431 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:37:47,434 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,441 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,450 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,459 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,469 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,470 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,470 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,471 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,472 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,473 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,480 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,481 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,482 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,483 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,484 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,485 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,486 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,487 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,488 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,489 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,491 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,492 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,493 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,494 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,495 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,497 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,498 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,499 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,501 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,502 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,503 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,505 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,506 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,508 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,509 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,511 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,512 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,514 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,515 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,517 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,519 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,521 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:47,521 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:47,523 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:47,542 INFO L134 CoverageAnalysis]: Checked inductivity of 3364 backedges. 2 proven. 3362 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:47,559 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:47,559 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 44 [2018-01-29 22:37:47,560 INFO L409 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-01-29 22:37:47,560 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-01-29 22:37:47,560 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-29 22:37:47,560 INFO L87 Difference]: Start difference. First operand 526 states and 612 transitions. Second operand 44 states. [2018-01-29 22:37:47,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:47,847 INFO L93 Difference]: Finished difference Result 1066 states and 1244 transitions. [2018-01-29 22:37:47,847 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-01-29 22:37:47,847 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 190 [2018-01-29 22:37:47,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:47,848 INFO L225 Difference]: With dead ends: 1066 [2018-01-29 22:37:47,848 INFO L226 Difference]: Without dead ends: 546 [2018-01-29 22:37:47,849 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 233 GetRequests, 191 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-29 22:37:47,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states. [2018-01-29 22:37:47,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 538. [2018-01-29 22:37:47,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-01-29 22:37:47,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 626 transitions. [2018-01-29 22:37:47,853 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 626 transitions. Word has length 190 [2018-01-29 22:37:47,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:47,853 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 626 transitions. [2018-01-29 22:37:47,853 INFO L433 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-01-29 22:37:47,853 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 626 transitions. [2018-01-29 22:37:47,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2018-01-29 22:37:47,854 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:47,854 INFO L350 BasicCegarLoop]: trace histogram [43, 42, 42, 42, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:47,854 INFO L371 AbstractCegarLoop]: === Iteration 45 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:47,854 INFO L82 PathProgramCache]: Analyzing trace with hash 2093566370, now seen corresponding path program 42 times [2018-01-29 22:37:47,854 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:47,854 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:47,854 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:47,854 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:47,854 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:47,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:47,860 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:48,481 INFO L134 CoverageAnalysis]: Checked inductivity of 3530 backedges. 2 proven. 3528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:48,481 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:48,482 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:48,486 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:37:48,489 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,490 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,491 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,492 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,492 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,493 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,494 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,494 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,495 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,496 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,497 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,498 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,499 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,500 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,501 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,502 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,503 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,504 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,505 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,506 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,507 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,509 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,510 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,511 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,512 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,513 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,514 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,516 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,517 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,518 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,519 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,521 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,522 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,524 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,525 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,527 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,528 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,530 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,532 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,533 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,535 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,537 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,539 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,541 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:48,541 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:48,543 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:48,564 INFO L134 CoverageAnalysis]: Checked inductivity of 3530 backedges. 2 proven. 3528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:48,580 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:48,581 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45] total 45 [2018-01-29 22:37:48,581 INFO L409 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-01-29 22:37:48,581 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-01-29 22:37:48,581 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2018-01-29 22:37:48,581 INFO L87 Difference]: Start difference. First operand 538 states and 626 transitions. Second operand 45 states. [2018-01-29 22:37:48,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:48,966 INFO L93 Difference]: Finished difference Result 1090 states and 1272 transitions. [2018-01-29 22:37:48,966 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-01-29 22:37:48,966 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 194 [2018-01-29 22:37:48,967 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:48,967 INFO L225 Difference]: With dead ends: 1090 [2018-01-29 22:37:48,967 INFO L226 Difference]: Without dead ends: 558 [2018-01-29 22:37:48,968 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 195 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2018-01-29 22:37:48,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 558 states. [2018-01-29 22:37:48,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 558 to 550. [2018-01-29 22:37:48,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 550 states. [2018-01-29 22:37:48,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 550 states to 550 states and 640 transitions. [2018-01-29 22:37:48,972 INFO L78 Accepts]: Start accepts. Automaton has 550 states and 640 transitions. Word has length 194 [2018-01-29 22:37:48,972 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:48,972 INFO L432 AbstractCegarLoop]: Abstraction has 550 states and 640 transitions. [2018-01-29 22:37:48,972 INFO L433 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-01-29 22:37:48,973 INFO L276 IsEmpty]: Start isEmpty. Operand 550 states and 640 transitions. [2018-01-29 22:37:48,973 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-01-29 22:37:48,973 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:48,973 INFO L350 BasicCegarLoop]: trace histogram [44, 43, 43, 43, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:48,973 INFO L371 AbstractCegarLoop]: === Iteration 46 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:48,973 INFO L82 PathProgramCache]: Analyzing trace with hash 1705595210, now seen corresponding path program 43 times [2018-01-29 22:37:48,974 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:48,974 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:48,974 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:48,974 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:48,974 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:48,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:48,984 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:49,538 INFO L134 CoverageAnalysis]: Checked inductivity of 3700 backedges. 2 proven. 3698 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:49,539 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:49,539 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:49,543 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:49,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:49,559 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:49,582 INFO L134 CoverageAnalysis]: Checked inductivity of 3700 backedges. 2 proven. 3698 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:49,599 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:49,599 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 46 [2018-01-29 22:37:49,599 INFO L409 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-01-29 22:37:49,600 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-01-29 22:37:49,600 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-29 22:37:49,600 INFO L87 Difference]: Start difference. First operand 550 states and 640 transitions. Second operand 46 states. [2018-01-29 22:37:49,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:49,935 INFO L93 Difference]: Finished difference Result 1114 states and 1300 transitions. [2018-01-29 22:37:49,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-01-29 22:37:49,937 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 198 [2018-01-29 22:37:49,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:49,938 INFO L225 Difference]: With dead ends: 1114 [2018-01-29 22:37:49,938 INFO L226 Difference]: Without dead ends: 570 [2018-01-29 22:37:49,939 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 243 GetRequests, 199 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-29 22:37:49,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 570 states. [2018-01-29 22:37:49,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 570 to 562. [2018-01-29 22:37:49,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 562 states. [2018-01-29 22:37:49,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 562 states to 562 states and 654 transitions. [2018-01-29 22:37:49,943 INFO L78 Accepts]: Start accepts. Automaton has 562 states and 654 transitions. Word has length 198 [2018-01-29 22:37:49,943 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:49,943 INFO L432 AbstractCegarLoop]: Abstraction has 562 states and 654 transitions. [2018-01-29 22:37:49,943 INFO L433 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-01-29 22:37:49,943 INFO L276 IsEmpty]: Start isEmpty. Operand 562 states and 654 transitions. [2018-01-29 22:37:49,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 203 [2018-01-29 22:37:49,944 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:49,944 INFO L350 BasicCegarLoop]: trace histogram [45, 44, 44, 44, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:49,944 INFO L371 AbstractCegarLoop]: === Iteration 47 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:49,944 INFO L82 PathProgramCache]: Analyzing trace with hash 1248675058, now seen corresponding path program 44 times [2018-01-29 22:37:49,944 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:49,944 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:49,944 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:49,944 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:49,944 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:49,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:49,950 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:50,616 INFO L134 CoverageAnalysis]: Checked inductivity of 3874 backedges. 2 proven. 3872 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:50,616 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:50,616 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-29 22:37:50,620 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:50,626 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:50,634 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:50,637 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:50,639 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:50,662 INFO L134 CoverageAnalysis]: Checked inductivity of 3874 backedges. 2 proven. 3872 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:50,678 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:50,678 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47] total 47 [2018-01-29 22:37:50,679 INFO L409 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-01-29 22:37:50,679 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-01-29 22:37:50,679 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2018-01-29 22:37:50,679 INFO L87 Difference]: Start difference. First operand 562 states and 654 transitions. Second operand 47 states. [2018-01-29 22:37:50,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:50,933 INFO L93 Difference]: Finished difference Result 1138 states and 1328 transitions. [2018-01-29 22:37:50,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-01-29 22:37:50,933 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 202 [2018-01-29 22:37:50,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:50,934 INFO L225 Difference]: With dead ends: 1138 [2018-01-29 22:37:50,934 INFO L226 Difference]: Without dead ends: 582 [2018-01-29 22:37:50,934 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 248 GetRequests, 203 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2018-01-29 22:37:50,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 582 states. [2018-01-29 22:37:50,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 582 to 574. [2018-01-29 22:37:50,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 574 states. [2018-01-29 22:37:50,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 574 states to 574 states and 668 transitions. [2018-01-29 22:37:50,938 INFO L78 Accepts]: Start accepts. Automaton has 574 states and 668 transitions. Word has length 202 [2018-01-29 22:37:50,938 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:50,938 INFO L432 AbstractCegarLoop]: Abstraction has 574 states and 668 transitions. [2018-01-29 22:37:50,938 INFO L433 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-01-29 22:37:50,938 INFO L276 IsEmpty]: Start isEmpty. Operand 574 states and 668 transitions. [2018-01-29 22:37:50,939 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 207 [2018-01-29 22:37:50,939 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:50,939 INFO L350 BasicCegarLoop]: trace histogram [46, 45, 45, 45, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:50,939 INFO L371 AbstractCegarLoop]: === Iteration 48 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:50,939 INFO L82 PathProgramCache]: Analyzing trace with hash 2134844570, now seen corresponding path program 45 times [2018-01-29 22:37:50,939 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:50,939 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:50,940 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:50,940 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:50,940 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:50,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:50,949 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:51,809 INFO L134 CoverageAnalysis]: Checked inductivity of 4052 backedges. 2 proven. 4050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:51,810 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:51,810 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:51,814 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:37:51,819 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,821 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,821 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,822 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,823 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,823 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,824 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,825 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,826 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,826 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,827 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,828 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,829 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,830 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,831 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,832 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,833 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,834 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,835 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,836 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,837 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,838 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,839 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,840 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,841 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,843 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,845 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,847 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,848 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,849 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,853 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,863 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,873 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,883 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,897 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,907 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,917 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,927 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,937 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,947 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,957 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,967 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,977 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,987 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:51,997 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:52,010 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:52,017 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:52,026 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:52,028 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:52,051 INFO L134 CoverageAnalysis]: Checked inductivity of 4052 backedges. 2 proven. 4050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:52,068 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:52,068 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48] total 48 [2018-01-29 22:37:52,068 INFO L409 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-01-29 22:37:52,068 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-01-29 22:37:52,069 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-01-29 22:37:52,069 INFO L87 Difference]: Start difference. First operand 574 states and 668 transitions. Second operand 48 states. [2018-01-29 22:37:52,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:52,508 INFO L93 Difference]: Finished difference Result 1162 states and 1356 transitions. [2018-01-29 22:37:52,508 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-01-29 22:37:52,508 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 206 [2018-01-29 22:37:52,508 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:52,509 INFO L225 Difference]: With dead ends: 1162 [2018-01-29 22:37:52,509 INFO L226 Difference]: Without dead ends: 594 [2018-01-29 22:37:52,509 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 253 GetRequests, 207 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-01-29 22:37:52,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 594 states. [2018-01-29 22:37:52,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 594 to 586. [2018-01-29 22:37:52,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 586 states. [2018-01-29 22:37:52,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 586 states to 586 states and 682 transitions. [2018-01-29 22:37:52,513 INFO L78 Accepts]: Start accepts. Automaton has 586 states and 682 transitions. Word has length 206 [2018-01-29 22:37:52,513 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:52,513 INFO L432 AbstractCegarLoop]: Abstraction has 586 states and 682 transitions. [2018-01-29 22:37:52,513 INFO L433 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-01-29 22:37:52,513 INFO L276 IsEmpty]: Start isEmpty. Operand 586 states and 682 transitions. [2018-01-29 22:37:52,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 211 [2018-01-29 22:37:52,514 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:52,514 INFO L350 BasicCegarLoop]: trace histogram [47, 46, 46, 46, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:52,514 INFO L371 AbstractCegarLoop]: === Iteration 49 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:52,514 INFO L82 PathProgramCache]: Analyzing trace with hash 860418114, now seen corresponding path program 46 times [2018-01-29 22:37:52,514 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:52,514 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:52,515 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:52,515 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:52,515 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:52,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:52,520 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:53,176 INFO L134 CoverageAnalysis]: Checked inductivity of 4234 backedges. 2 proven. 4232 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:53,176 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:53,176 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:53,181 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:37:53,200 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:53,202 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:53,225 INFO L134 CoverageAnalysis]: Checked inductivity of 4234 backedges. 2 proven. 4232 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:53,241 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:53,242 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 49 [2018-01-29 22:37:53,242 INFO L409 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-01-29 22:37:53,242 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-01-29 22:37:53,242 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2018-01-29 22:37:53,242 INFO L87 Difference]: Start difference. First operand 586 states and 682 transitions. Second operand 49 states. [2018-01-29 22:37:53,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:53,481 INFO L93 Difference]: Finished difference Result 1186 states and 1384 transitions. [2018-01-29 22:37:53,490 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-01-29 22:37:53,490 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 210 [2018-01-29 22:37:53,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:53,491 INFO L225 Difference]: With dead ends: 1186 [2018-01-29 22:37:53,491 INFO L226 Difference]: Without dead ends: 606 [2018-01-29 22:37:53,492 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 258 GetRequests, 211 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2018-01-29 22:37:53,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states. [2018-01-29 22:37:53,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 598. [2018-01-29 22:37:53,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 598 states. [2018-01-29 22:37:53,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 598 states to 598 states and 696 transitions. [2018-01-29 22:37:53,496 INFO L78 Accepts]: Start accepts. Automaton has 598 states and 696 transitions. Word has length 210 [2018-01-29 22:37:53,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:53,496 INFO L432 AbstractCegarLoop]: Abstraction has 598 states and 696 transitions. [2018-01-29 22:37:53,496 INFO L433 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-01-29 22:37:53,496 INFO L276 IsEmpty]: Start isEmpty. Operand 598 states and 696 transitions. [2018-01-29 22:37:53,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 215 [2018-01-29 22:37:53,497 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:53,497 INFO L350 BasicCegarLoop]: trace histogram [48, 47, 47, 47, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:53,497 INFO L371 AbstractCegarLoop]: === Iteration 50 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:53,497 INFO L82 PathProgramCache]: Analyzing trace with hash -256595990, now seen corresponding path program 47 times [2018-01-29 22:37:53,497 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:53,497 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:53,498 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:53,498 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:53,498 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:53,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:53,503 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:54,234 INFO L134 CoverageAnalysis]: Checked inductivity of 4420 backedges. 2 proven. 4418 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:54,234 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:54,234 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:54,238 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:37:54,241 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,242 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,243 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,243 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,244 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,245 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,245 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,246 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,247 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,248 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,249 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,249 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,250 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,251 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,252 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,253 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,254 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,255 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,256 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,257 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,258 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,259 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,260 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,261 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,263 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,264 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,265 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,266 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,268 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,273 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,274 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,276 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,277 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,279 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,280 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,282 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,283 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,285 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,287 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,288 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,290 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,292 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,294 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,296 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,298 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,300 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,302 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,304 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:54,304 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:54,306 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:54,343 INFO L134 CoverageAnalysis]: Checked inductivity of 4420 backedges. 2 proven. 4418 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:54,360 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:54,360 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 50 [2018-01-29 22:37:54,360 INFO L409 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-01-29 22:37:54,361 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-01-29 22:37:54,361 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-29 22:37:54,361 INFO L87 Difference]: Start difference. First operand 598 states and 696 transitions. Second operand 50 states. [2018-01-29 22:37:54,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:54,656 INFO L93 Difference]: Finished difference Result 1210 states and 1412 transitions. [2018-01-29 22:37:54,657 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-01-29 22:37:54,657 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 214 [2018-01-29 22:37:54,657 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:54,658 INFO L225 Difference]: With dead ends: 1210 [2018-01-29 22:37:54,658 INFO L226 Difference]: Without dead ends: 618 [2018-01-29 22:37:54,659 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 263 GetRequests, 215 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-29 22:37:54,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 618 states. [2018-01-29 22:37:54,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 618 to 610. [2018-01-29 22:37:54,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 610 states. [2018-01-29 22:37:54,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 610 states to 610 states and 710 transitions. [2018-01-29 22:37:54,663 INFO L78 Accepts]: Start accepts. Automaton has 610 states and 710 transitions. Word has length 214 [2018-01-29 22:37:54,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:54,663 INFO L432 AbstractCegarLoop]: Abstraction has 610 states and 710 transitions. [2018-01-29 22:37:54,663 INFO L433 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-01-29 22:37:54,663 INFO L276 IsEmpty]: Start isEmpty. Operand 610 states and 710 transitions. [2018-01-29 22:37:54,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 219 [2018-01-29 22:37:54,664 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:54,664 INFO L350 BasicCegarLoop]: trace histogram [49, 48, 48, 48, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:54,664 INFO L371 AbstractCegarLoop]: === Iteration 51 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:54,664 INFO L82 PathProgramCache]: Analyzing trace with hash 481053586, now seen corresponding path program 48 times [2018-01-29 22:37:54,664 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:54,664 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:54,664 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:54,664 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:54,664 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:54,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:54,670 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:55,476 INFO L134 CoverageAnalysis]: Checked inductivity of 4610 backedges. 2 proven. 4608 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:55,476 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:55,476 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:55,482 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:37:55,486 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,486 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,487 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,488 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,489 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,490 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,491 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,491 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,492 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,493 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,494 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,496 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,497 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,498 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,499 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,500 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,501 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,502 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,503 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,504 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,505 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,506 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,507 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,508 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,509 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,511 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,512 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,513 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,514 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,515 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,516 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,518 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,519 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,520 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,522 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,523 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,524 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,526 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,527 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,529 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,531 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,533 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,534 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,536 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,538 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,540 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,542 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,544 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,546 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,548 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:37:55,548 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:55,550 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:55,576 INFO L134 CoverageAnalysis]: Checked inductivity of 4610 backedges. 2 proven. 4608 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:55,593 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:55,593 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51] total 51 [2018-01-29 22:37:55,593 INFO L409 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-01-29 22:37:55,593 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-01-29 22:37:55,594 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2018-01-29 22:37:55,594 INFO L87 Difference]: Start difference. First operand 610 states and 710 transitions. Second operand 51 states. [2018-01-29 22:37:55,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:55,946 INFO L93 Difference]: Finished difference Result 1234 states and 1440 transitions. [2018-01-29 22:37:55,947 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-01-29 22:37:55,947 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 218 [2018-01-29 22:37:55,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:55,948 INFO L225 Difference]: With dead ends: 1234 [2018-01-29 22:37:55,948 INFO L226 Difference]: Without dead ends: 630 [2018-01-29 22:37:55,949 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 268 GetRequests, 219 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2018-01-29 22:37:55,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 630 states. [2018-01-29 22:37:55,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 630 to 622. [2018-01-29 22:37:55,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2018-01-29 22:37:55,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 724 transitions. [2018-01-29 22:37:55,954 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 724 transitions. Word has length 218 [2018-01-29 22:37:55,954 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:55,954 INFO L432 AbstractCegarLoop]: Abstraction has 622 states and 724 transitions. [2018-01-29 22:37:55,954 INFO L433 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-01-29 22:37:55,954 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 724 transitions. [2018-01-29 22:37:55,955 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 223 [2018-01-29 22:37:55,955 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:55,955 INFO L350 BasicCegarLoop]: trace histogram [50, 49, 49, 49, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:55,955 INFO L371 AbstractCegarLoop]: === Iteration 52 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:55,955 INFO L82 PathProgramCache]: Analyzing trace with hash 2002377530, now seen corresponding path program 49 times [2018-01-29 22:37:55,955 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:55,955 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:55,956 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:55,956 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:55,956 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:55,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:55,963 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:56,700 INFO L134 CoverageAnalysis]: Checked inductivity of 4804 backedges. 2 proven. 4802 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:56,700 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:56,701 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:56,705 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:56,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:56,723 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:56,749 INFO L134 CoverageAnalysis]: Checked inductivity of 4804 backedges. 2 proven. 4802 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:56,765 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:56,765 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52] total 52 [2018-01-29 22:37:56,766 INFO L409 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-01-29 22:37:56,766 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-01-29 22:37:56,766 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-29 22:37:56,766 INFO L87 Difference]: Start difference. First operand 622 states and 724 transitions. Second operand 52 states. [2018-01-29 22:37:57,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:57,105 INFO L93 Difference]: Finished difference Result 1258 states and 1468 transitions. [2018-01-29 22:37:57,105 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-01-29 22:37:57,105 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 222 [2018-01-29 22:37:57,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:57,106 INFO L225 Difference]: With dead ends: 1258 [2018-01-29 22:37:57,106 INFO L226 Difference]: Without dead ends: 642 [2018-01-29 22:37:57,107 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 273 GetRequests, 223 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-29 22:37:57,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 642 states. [2018-01-29 22:37:57,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 642 to 634. [2018-01-29 22:37:57,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 634 states. [2018-01-29 22:37:57,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 634 states to 634 states and 738 transitions. [2018-01-29 22:37:57,111 INFO L78 Accepts]: Start accepts. Automaton has 634 states and 738 transitions. Word has length 222 [2018-01-29 22:37:57,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:57,111 INFO L432 AbstractCegarLoop]: Abstraction has 634 states and 738 transitions. [2018-01-29 22:37:57,111 INFO L433 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-01-29 22:37:57,111 INFO L276 IsEmpty]: Start isEmpty. Operand 634 states and 738 transitions. [2018-01-29 22:37:57,112 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2018-01-29 22:37:57,112 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:57,112 INFO L350 BasicCegarLoop]: trace histogram [51, 50, 50, 50, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:57,112 INFO L371 AbstractCegarLoop]: === Iteration 53 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:57,112 INFO L82 PathProgramCache]: Analyzing trace with hash -1679337758, now seen corresponding path program 50 times [2018-01-29 22:37:57,112 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:57,112 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:57,113 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:57,113 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:37:57,113 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:57,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:57,119 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:57,924 INFO L134 CoverageAnalysis]: Checked inductivity of 5002 backedges. 2 proven. 5000 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:57,924 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:57,924 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:57,930 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:37:57,934 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:57,945 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:37:57,947 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:57,949 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:57,985 INFO L134 CoverageAnalysis]: Checked inductivity of 5002 backedges. 2 proven. 5000 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:58,002 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:58,003 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53] total 53 [2018-01-29 22:37:58,003 INFO L409 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-01-29 22:37:58,003 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-01-29 22:37:58,003 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1378, Invalid=1378, Unknown=0, NotChecked=0, Total=2756 [2018-01-29 22:37:58,003 INFO L87 Difference]: Start difference. First operand 634 states and 738 transitions. Second operand 53 states. [2018-01-29 22:37:58,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:58,371 INFO L93 Difference]: Finished difference Result 1282 states and 1496 transitions. [2018-01-29 22:37:58,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-01-29 22:37:58,372 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 226 [2018-01-29 22:37:58,372 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:58,373 INFO L225 Difference]: With dead ends: 1282 [2018-01-29 22:37:58,373 INFO L226 Difference]: Without dead ends: 654 [2018-01-29 22:37:58,374 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 278 GetRequests, 227 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1378, Invalid=1378, Unknown=0, NotChecked=0, Total=2756 [2018-01-29 22:37:58,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 654 states. [2018-01-29 22:37:58,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 654 to 646. [2018-01-29 22:37:58,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 646 states. [2018-01-29 22:37:58,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 646 states to 646 states and 752 transitions. [2018-01-29 22:37:58,378 INFO L78 Accepts]: Start accepts. Automaton has 646 states and 752 transitions. Word has length 226 [2018-01-29 22:37:58,378 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:58,378 INFO L432 AbstractCegarLoop]: Abstraction has 646 states and 752 transitions. [2018-01-29 22:37:58,378 INFO L433 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-01-29 22:37:58,378 INFO L276 IsEmpty]: Start isEmpty. Operand 646 states and 752 transitions. [2018-01-29 22:37:58,378 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 231 [2018-01-29 22:37:58,379 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:58,379 INFO L350 BasicCegarLoop]: trace histogram [52, 51, 51, 51, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:58,379 INFO L371 AbstractCegarLoop]: === Iteration 54 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:58,379 INFO L82 PathProgramCache]: Analyzing trace with hash -2139177334, now seen corresponding path program 51 times [2018-01-29 22:37:58,379 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:58,379 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:58,379 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:58,379 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:58,379 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:58,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:58,385 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:37:59,123 INFO L134 CoverageAnalysis]: Checked inductivity of 5204 backedges. 2 proven. 5202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:59,123 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:37:59,124 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:37:59,135 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:37:59,139 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,140 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,140 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,141 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,142 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,142 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,143 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,144 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,145 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,145 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,146 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,147 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,148 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,149 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,150 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,151 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,152 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,153 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,154 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,155 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,156 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,157 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,159 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,160 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,161 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,163 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,164 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,165 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,167 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,168 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,170 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,171 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,173 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,174 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,176 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,178 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,179 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,181 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,183 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,185 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,187 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,188 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,190 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,192 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,194 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,196 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,198 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,200 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,202 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,204 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,207 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,209 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,212 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:37:59,213 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:37:59,215 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:37:59,242 INFO L134 CoverageAnalysis]: Checked inductivity of 5204 backedges. 2 proven. 5202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:37:59,260 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:37:59,260 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54] total 54 [2018-01-29 22:37:59,260 INFO L409 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-01-29 22:37:59,261 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-01-29 22:37:59,261 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-01-29 22:37:59,261 INFO L87 Difference]: Start difference. First operand 646 states and 752 transitions. Second operand 54 states. [2018-01-29 22:37:59,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:37:59,594 INFO L93 Difference]: Finished difference Result 1306 states and 1524 transitions. [2018-01-29 22:37:59,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-01-29 22:37:59,594 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 230 [2018-01-29 22:37:59,594 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:37:59,595 INFO L225 Difference]: With dead ends: 1306 [2018-01-29 22:37:59,595 INFO L226 Difference]: Without dead ends: 666 [2018-01-29 22:37:59,596 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 283 GetRequests, 231 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-01-29 22:37:59,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 666 states. [2018-01-29 22:37:59,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 666 to 658. [2018-01-29 22:37:59,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 658 states. [2018-01-29 22:37:59,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 658 states to 658 states and 766 transitions. [2018-01-29 22:37:59,600 INFO L78 Accepts]: Start accepts. Automaton has 658 states and 766 transitions. Word has length 230 [2018-01-29 22:37:59,600 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:37:59,600 INFO L432 AbstractCegarLoop]: Abstraction has 658 states and 766 transitions. [2018-01-29 22:37:59,600 INFO L433 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-01-29 22:37:59,600 INFO L276 IsEmpty]: Start isEmpty. Operand 658 states and 766 transitions. [2018-01-29 22:37:59,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 235 [2018-01-29 22:37:59,601 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:37:59,601 INFO L350 BasicCegarLoop]: trace histogram [53, 52, 52, 52, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:37:59,601 INFO L371 AbstractCegarLoop]: === Iteration 55 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:37:59,602 INFO L82 PathProgramCache]: Analyzing trace with hash -162917838, now seen corresponding path program 52 times [2018-01-29 22:37:59,602 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:37:59,602 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:37:59,602 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:59,602 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:37:59,602 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:37:59,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:37:59,608 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:00,405 INFO L134 CoverageAnalysis]: Checked inductivity of 5410 backedges. 2 proven. 5408 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:00,405 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:00,405 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:00,410 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:38:00,436 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:00,438 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:00,468 INFO L134 CoverageAnalysis]: Checked inductivity of 5410 backedges. 2 proven. 5408 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:00,484 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:00,485 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55] total 55 [2018-01-29 22:38:00,485 INFO L409 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-01-29 22:38:00,485 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-01-29 22:38:00,485 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1485, Invalid=1485, Unknown=0, NotChecked=0, Total=2970 [2018-01-29 22:38:00,485 INFO L87 Difference]: Start difference. First operand 658 states and 766 transitions. Second operand 55 states. [2018-01-29 22:38:01,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:01,121 INFO L93 Difference]: Finished difference Result 1330 states and 1552 transitions. [2018-01-29 22:38:01,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-01-29 22:38:01,122 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 234 [2018-01-29 22:38:01,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:01,123 INFO L225 Difference]: With dead ends: 1330 [2018-01-29 22:38:01,123 INFO L226 Difference]: Without dead ends: 678 [2018-01-29 22:38:01,124 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 288 GetRequests, 235 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1485, Invalid=1485, Unknown=0, NotChecked=0, Total=2970 [2018-01-29 22:38:01,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 678 states. [2018-01-29 22:38:01,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 678 to 670. [2018-01-29 22:38:01,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 670 states. [2018-01-29 22:38:01,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 670 states to 670 states and 780 transitions. [2018-01-29 22:38:01,128 INFO L78 Accepts]: Start accepts. Automaton has 670 states and 780 transitions. Word has length 234 [2018-01-29 22:38:01,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:01,129 INFO L432 AbstractCegarLoop]: Abstraction has 670 states and 780 transitions. [2018-01-29 22:38:01,129 INFO L433 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-01-29 22:38:01,129 INFO L276 IsEmpty]: Start isEmpty. Operand 670 states and 780 transitions. [2018-01-29 22:38:01,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 239 [2018-01-29 22:38:01,129 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:01,129 INFO L350 BasicCegarLoop]: trace histogram [54, 53, 53, 53, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:01,130 INFO L371 AbstractCegarLoop]: === Iteration 56 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:01,130 INFO L82 PathProgramCache]: Analyzing trace with hash 695423450, now seen corresponding path program 53 times [2018-01-29 22:38:01,130 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:01,130 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:01,130 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:01,130 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:01,130 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:01,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:01,137 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:01,910 INFO L134 CoverageAnalysis]: Checked inductivity of 5620 backedges. 2 proven. 5618 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:01,910 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:01,910 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:01,915 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:38:01,918 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,919 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,919 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,920 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,921 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,922 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,923 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,924 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,925 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,926 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,927 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,927 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,928 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,929 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,930 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,931 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,932 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,933 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,934 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,936 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,937 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,938 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,939 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,940 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,942 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,943 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,944 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,946 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,947 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,949 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,950 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,952 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,953 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,956 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,957 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,960 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,962 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,964 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,967 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,969 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,971 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,973 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,975 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,977 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,980 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,982 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,984 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,987 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,989 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,992 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,994 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:01,997 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:02,000 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:02,003 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:02,003 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:02,005 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:02,039 INFO L134 CoverageAnalysis]: Checked inductivity of 5620 backedges. 2 proven. 5618 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:02,056 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:02,056 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 56] total 56 [2018-01-29 22:38:02,056 INFO L409 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-01-29 22:38:02,057 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-01-29 22:38:02,057 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-29 22:38:02,057 INFO L87 Difference]: Start difference. First operand 670 states and 780 transitions. Second operand 56 states. [2018-01-29 22:38:02,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:02,389 INFO L93 Difference]: Finished difference Result 1354 states and 1580 transitions. [2018-01-29 22:38:02,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-01-29 22:38:02,390 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 238 [2018-01-29 22:38:02,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:02,391 INFO L225 Difference]: With dead ends: 1354 [2018-01-29 22:38:02,391 INFO L226 Difference]: Without dead ends: 690 [2018-01-29 22:38:02,392 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 293 GetRequests, 239 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-29 22:38:02,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 690 states. [2018-01-29 22:38:02,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 690 to 682. [2018-01-29 22:38:02,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 682 states. [2018-01-29 22:38:02,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 682 states to 682 states and 794 transitions. [2018-01-29 22:38:02,396 INFO L78 Accepts]: Start accepts. Automaton has 682 states and 794 transitions. Word has length 238 [2018-01-29 22:38:02,396 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:02,396 INFO L432 AbstractCegarLoop]: Abstraction has 682 states and 794 transitions. [2018-01-29 22:38:02,396 INFO L433 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-01-29 22:38:02,396 INFO L276 IsEmpty]: Start isEmpty. Operand 682 states and 794 transitions. [2018-01-29 22:38:02,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 243 [2018-01-29 22:38:02,397 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:02,397 INFO L350 BasicCegarLoop]: trace histogram [55, 54, 54, 54, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:02,397 INFO L371 AbstractCegarLoop]: === Iteration 57 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:02,397 INFO L82 PathProgramCache]: Analyzing trace with hash 556039554, now seen corresponding path program 54 times [2018-01-29 22:38:02,397 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:02,397 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:02,397 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:02,397 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:02,398 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:02,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:02,404 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:03,249 INFO L134 CoverageAnalysis]: Checked inductivity of 5834 backedges. 2 proven. 5832 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:03,249 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:03,249 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-29 22:38:03,266 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:03,271 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,283 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,290 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,300 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,301 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,302 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,302 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,303 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,304 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,305 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,306 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,306 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,307 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,308 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,309 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,310 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,311 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,312 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,313 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,314 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,315 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,316 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,317 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,318 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,319 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,321 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,322 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,323 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,324 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,326 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,327 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,328 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,330 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,331 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,332 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,334 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,335 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,337 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,338 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,340 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,342 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,343 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,345 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,346 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,348 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,350 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,352 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,353 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,355 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,357 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,359 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,361 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,363 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,365 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,368 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,370 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:03,371 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:03,373 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:03,402 INFO L134 CoverageAnalysis]: Checked inductivity of 5834 backedges. 2 proven. 5832 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:03,419 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:03,419 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57] total 57 [2018-01-29 22:38:03,419 INFO L409 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-01-29 22:38:03,420 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-01-29 22:38:03,420 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1596, Invalid=1596, Unknown=0, NotChecked=0, Total=3192 [2018-01-29 22:38:03,420 INFO L87 Difference]: Start difference. First operand 682 states and 794 transitions. Second operand 57 states. [2018-01-29 22:38:03,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:03,829 INFO L93 Difference]: Finished difference Result 1378 states and 1608 transitions. [2018-01-29 22:38:03,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-01-29 22:38:03,830 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 242 [2018-01-29 22:38:03,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:03,831 INFO L225 Difference]: With dead ends: 1378 [2018-01-29 22:38:03,831 INFO L226 Difference]: Without dead ends: 702 [2018-01-29 22:38:03,832 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 298 GetRequests, 243 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1596, Invalid=1596, Unknown=0, NotChecked=0, Total=3192 [2018-01-29 22:38:03,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 702 states. [2018-01-29 22:38:03,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 702 to 694. [2018-01-29 22:38:03,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 694 states. [2018-01-29 22:38:03,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 694 states to 694 states and 808 transitions. [2018-01-29 22:38:03,836 INFO L78 Accepts]: Start accepts. Automaton has 694 states and 808 transitions. Word has length 242 [2018-01-29 22:38:03,836 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:03,836 INFO L432 AbstractCegarLoop]: Abstraction has 694 states and 808 transitions. [2018-01-29 22:38:03,836 INFO L433 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-01-29 22:38:03,836 INFO L276 IsEmpty]: Start isEmpty. Operand 694 states and 808 transitions. [2018-01-29 22:38:03,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 247 [2018-01-29 22:38:03,843 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:03,844 INFO L350 BasicCegarLoop]: trace histogram [56, 55, 55, 55, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:03,844 INFO L371 AbstractCegarLoop]: === Iteration 58 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:03,844 INFO L82 PathProgramCache]: Analyzing trace with hash 1065850154, now seen corresponding path program 55 times [2018-01-29 22:38:03,844 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:03,844 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:03,844 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:03,844 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:03,844 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:03,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:03,851 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:04,713 INFO L134 CoverageAnalysis]: Checked inductivity of 6052 backedges. 2 proven. 6050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:04,714 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:04,714 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:04,718 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:04,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:04,738 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:04,767 INFO L134 CoverageAnalysis]: Checked inductivity of 6052 backedges. 2 proven. 6050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:04,784 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:04,784 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 58] total 58 [2018-01-29 22:38:04,784 INFO L409 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-01-29 22:38:04,784 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-01-29 22:38:04,784 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-29 22:38:04,784 INFO L87 Difference]: Start difference. First operand 694 states and 808 transitions. Second operand 58 states. [2018-01-29 22:38:05,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:05,222 INFO L93 Difference]: Finished difference Result 1402 states and 1636 transitions. [2018-01-29 22:38:05,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-01-29 22:38:05,222 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 246 [2018-01-29 22:38:05,222 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:05,223 INFO L225 Difference]: With dead ends: 1402 [2018-01-29 22:38:05,223 INFO L226 Difference]: Without dead ends: 714 [2018-01-29 22:38:05,224 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 303 GetRequests, 247 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-29 22:38:05,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 714 states. [2018-01-29 22:38:05,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 714 to 706. [2018-01-29 22:38:05,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 706 states. [2018-01-29 22:38:05,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 706 states to 706 states and 822 transitions. [2018-01-29 22:38:05,228 INFO L78 Accepts]: Start accepts. Automaton has 706 states and 822 transitions. Word has length 246 [2018-01-29 22:38:05,228 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:05,228 INFO L432 AbstractCegarLoop]: Abstraction has 706 states and 822 transitions. [2018-01-29 22:38:05,228 INFO L433 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-01-29 22:38:05,228 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 822 transitions. [2018-01-29 22:38:05,229 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 251 [2018-01-29 22:38:05,229 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:05,229 INFO L350 BasicCegarLoop]: trace histogram [57, 56, 56, 56, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:05,229 INFO L371 AbstractCegarLoop]: === Iteration 59 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:05,229 INFO L82 PathProgramCache]: Analyzing trace with hash -1043949358, now seen corresponding path program 56 times [2018-01-29 22:38:05,229 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:05,229 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:05,230 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:05,230 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:05,230 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:05,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:05,237 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:06,114 INFO L134 CoverageAnalysis]: Checked inductivity of 6274 backedges. 2 proven. 6272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:06,114 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:06,115 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:06,121 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:38:06,125 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:06,137 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:06,140 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:06,142 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:06,187 INFO L134 CoverageAnalysis]: Checked inductivity of 6274 backedges. 2 proven. 6272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:06,206 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:06,207 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59] total 59 [2018-01-29 22:38:06,207 INFO L409 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-01-29 22:38:06,207 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-01-29 22:38:06,207 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1711, Invalid=1711, Unknown=0, NotChecked=0, Total=3422 [2018-01-29 22:38:06,207 INFO L87 Difference]: Start difference. First operand 706 states and 822 transitions. Second operand 59 states. [2018-01-29 22:38:06,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:06,680 INFO L93 Difference]: Finished difference Result 1426 states and 1664 transitions. [2018-01-29 22:38:06,680 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-01-29 22:38:06,680 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 250 [2018-01-29 22:38:06,680 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:06,682 INFO L225 Difference]: With dead ends: 1426 [2018-01-29 22:38:06,682 INFO L226 Difference]: Without dead ends: 726 [2018-01-29 22:38:06,682 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 308 GetRequests, 251 SyntacticMatches, 0 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1711, Invalid=1711, Unknown=0, NotChecked=0, Total=3422 [2018-01-29 22:38:06,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 726 states. [2018-01-29 22:38:06,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 726 to 718. [2018-01-29 22:38:06,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 718 states. [2018-01-29 22:38:06,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 718 states to 718 states and 836 transitions. [2018-01-29 22:38:06,687 INFO L78 Accepts]: Start accepts. Automaton has 718 states and 836 transitions. Word has length 250 [2018-01-29 22:38:06,687 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:06,687 INFO L432 AbstractCegarLoop]: Abstraction has 718 states and 836 transitions. [2018-01-29 22:38:06,687 INFO L433 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-01-29 22:38:06,687 INFO L276 IsEmpty]: Start isEmpty. Operand 718 states and 836 transitions. [2018-01-29 22:38:06,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2018-01-29 22:38:06,688 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:06,688 INFO L350 BasicCegarLoop]: trace histogram [58, 57, 57, 57, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:06,688 INFO L371 AbstractCegarLoop]: === Iteration 60 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:06,688 INFO L82 PathProgramCache]: Analyzing trace with hash 1074497658, now seen corresponding path program 57 times [2018-01-29 22:38:06,688 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:06,688 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:06,689 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:06,689 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:06,689 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:06,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:06,696 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:07,628 INFO L134 CoverageAnalysis]: Checked inductivity of 6500 backedges. 2 proven. 6498 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:07,629 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:07,629 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:07,634 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:38:07,638 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,639 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,640 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,640 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,641 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,642 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,643 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,643 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,644 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,645 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,646 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,647 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,648 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,649 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,650 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,651 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,652 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,653 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,654 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,655 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,656 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,657 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,658 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,659 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,660 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,661 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,662 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,664 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,665 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,666 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,667 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,669 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,671 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,672 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,674 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,675 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,678 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,679 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,681 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,683 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,685 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,687 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,689 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,691 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,693 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,695 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,697 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,699 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,702 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,704 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,706 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,709 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,711 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,714 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,716 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,719 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,721 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,724 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,727 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:07,727 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:07,729 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:07,761 INFO L134 CoverageAnalysis]: Checked inductivity of 6500 backedges. 2 proven. 6498 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:07,778 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:07,779 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 60] total 60 [2018-01-29 22:38:07,779 INFO L409 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-01-29 22:38:07,779 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-01-29 22:38:07,779 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-01-29 22:38:07,779 INFO L87 Difference]: Start difference. First operand 718 states and 836 transitions. Second operand 60 states. [2018-01-29 22:38:08,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:08,312 INFO L93 Difference]: Finished difference Result 1450 states and 1692 transitions. [2018-01-29 22:38:08,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-01-29 22:38:08,312 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 254 [2018-01-29 22:38:08,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:08,313 INFO L225 Difference]: With dead ends: 1450 [2018-01-29 22:38:08,313 INFO L226 Difference]: Without dead ends: 738 [2018-01-29 22:38:08,314 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 313 GetRequests, 255 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-01-29 22:38:08,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 738 states. [2018-01-29 22:38:08,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 738 to 730. [2018-01-29 22:38:08,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 730 states. [2018-01-29 22:38:08,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 730 states to 730 states and 850 transitions. [2018-01-29 22:38:08,318 INFO L78 Accepts]: Start accepts. Automaton has 730 states and 850 transitions. Word has length 254 [2018-01-29 22:38:08,319 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:08,319 INFO L432 AbstractCegarLoop]: Abstraction has 730 states and 850 transitions. [2018-01-29 22:38:08,319 INFO L433 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-01-29 22:38:08,319 INFO L276 IsEmpty]: Start isEmpty. Operand 730 states and 850 transitions. [2018-01-29 22:38:08,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 259 [2018-01-29 22:38:08,319 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:08,320 INFO L350 BasicCegarLoop]: trace histogram [59, 58, 58, 58, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:08,320 INFO L371 AbstractCegarLoop]: === Iteration 61 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:08,320 INFO L82 PathProgramCache]: Analyzing trace with hash 763388962, now seen corresponding path program 58 times [2018-01-29 22:38:08,320 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:08,320 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:08,320 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:08,320 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:08,320 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:08,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:08,328 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:09,317 INFO L134 CoverageAnalysis]: Checked inductivity of 6730 backedges. 2 proven. 6728 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:09,317 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:09,317 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:09,323 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:38:09,345 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:09,347 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:09,379 INFO L134 CoverageAnalysis]: Checked inductivity of 6730 backedges. 2 proven. 6728 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:09,396 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:09,396 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61] total 61 [2018-01-29 22:38:09,396 INFO L409 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-01-29 22:38:09,397 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-01-29 22:38:09,397 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1830, Invalid=1830, Unknown=0, NotChecked=0, Total=3660 [2018-01-29 22:38:09,397 INFO L87 Difference]: Start difference. First operand 730 states and 850 transitions. Second operand 61 states. [2018-01-29 22:38:09,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:09,775 INFO L93 Difference]: Finished difference Result 1474 states and 1720 transitions. [2018-01-29 22:38:09,775 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-01-29 22:38:09,775 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 258 [2018-01-29 22:38:09,776 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:09,777 INFO L225 Difference]: With dead ends: 1474 [2018-01-29 22:38:09,777 INFO L226 Difference]: Without dead ends: 750 [2018-01-29 22:38:09,777 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 318 GetRequests, 259 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1830, Invalid=1830, Unknown=0, NotChecked=0, Total=3660 [2018-01-29 22:38:09,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 750 states. [2018-01-29 22:38:09,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 750 to 742. [2018-01-29 22:38:09,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 742 states. [2018-01-29 22:38:09,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 742 states to 742 states and 864 transitions. [2018-01-29 22:38:09,782 INFO L78 Accepts]: Start accepts. Automaton has 742 states and 864 transitions. Word has length 258 [2018-01-29 22:38:09,782 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:09,782 INFO L432 AbstractCegarLoop]: Abstraction has 742 states and 864 transitions. [2018-01-29 22:38:09,782 INFO L433 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-01-29 22:38:09,782 INFO L276 IsEmpty]: Start isEmpty. Operand 742 states and 864 transitions. [2018-01-29 22:38:09,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 263 [2018-01-29 22:38:09,783 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:09,783 INFO L350 BasicCegarLoop]: trace histogram [60, 59, 59, 59, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:09,783 INFO L371 AbstractCegarLoop]: === Iteration 62 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:09,783 INFO L82 PathProgramCache]: Analyzing trace with hash 1481583562, now seen corresponding path program 59 times [2018-01-29 22:38:09,783 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:09,783 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:09,784 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:09,784 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:09,784 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:09,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:09,791 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:10,799 INFO L134 CoverageAnalysis]: Checked inductivity of 6964 backedges. 2 proven. 6962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:10,799 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:10,799 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:10,803 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:38:10,807 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,807 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,808 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,809 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,809 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,810 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,811 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,812 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,812 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,813 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,814 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,815 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,816 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,817 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,818 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,819 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,820 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,821 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,822 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,823 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,824 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,825 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,826 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,827 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,828 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,830 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,831 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,832 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,833 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,835 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,836 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,838 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,839 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,840 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,842 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,844 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,845 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,847 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,848 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,850 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,852 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,854 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,856 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,858 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,859 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,861 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,863 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,865 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,867 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,869 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,871 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,873 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,875 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,877 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,879 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,882 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,884 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,886 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,889 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,891 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:10,892 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:10,894 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:10,926 INFO L134 CoverageAnalysis]: Checked inductivity of 6964 backedges. 2 proven. 6962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:10,943 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:10,943 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 62] total 62 [2018-01-29 22:38:10,943 INFO L409 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-01-29 22:38:10,944 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-01-29 22:38:10,944 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-29 22:38:10,944 INFO L87 Difference]: Start difference. First operand 742 states and 864 transitions. Second operand 62 states. [2018-01-29 22:38:11,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:11,401 INFO L93 Difference]: Finished difference Result 1498 states and 1748 transitions. [2018-01-29 22:38:11,401 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-01-29 22:38:11,401 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 262 [2018-01-29 22:38:11,401 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:11,402 INFO L225 Difference]: With dead ends: 1498 [2018-01-29 22:38:11,402 INFO L226 Difference]: Without dead ends: 762 [2018-01-29 22:38:11,403 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 323 GetRequests, 263 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-29 22:38:11,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 762 states. [2018-01-29 22:38:11,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 762 to 754. [2018-01-29 22:38:11,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 754 states. [2018-01-29 22:38:11,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 754 states to 754 states and 878 transitions. [2018-01-29 22:38:11,408 INFO L78 Accepts]: Start accepts. Automaton has 754 states and 878 transitions. Word has length 262 [2018-01-29 22:38:11,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:11,408 INFO L432 AbstractCegarLoop]: Abstraction has 754 states and 878 transitions. [2018-01-29 22:38:11,408 INFO L433 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-01-29 22:38:11,408 INFO L276 IsEmpty]: Start isEmpty. Operand 754 states and 878 transitions. [2018-01-29 22:38:11,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 267 [2018-01-29 22:38:11,409 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:11,409 INFO L350 BasicCegarLoop]: trace histogram [61, 60, 60, 60, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:11,409 INFO L371 AbstractCegarLoop]: === Iteration 63 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:11,409 INFO L82 PathProgramCache]: Analyzing trace with hash 1772216178, now seen corresponding path program 60 times [2018-01-29 22:38:11,409 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:11,409 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:11,410 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:11,410 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:11,410 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:11,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:11,418 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:12,404 INFO L134 CoverageAnalysis]: Checked inductivity of 7202 backedges. 2 proven. 7200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:12,404 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:12,404 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:12,409 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:38:12,413 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,414 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,415 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,415 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,416 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,417 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,418 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,418 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,419 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,420 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,421 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,422 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,422 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,423 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,424 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,425 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,426 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,427 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,428 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,429 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,430 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,431 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,432 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,434 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,435 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,436 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,437 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,438 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,440 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,441 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,443 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,444 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,445 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,447 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,448 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,450 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,451 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,453 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,455 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,456 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,458 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,460 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,462 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,464 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,466 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,468 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,470 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,472 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,474 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,476 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,478 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,480 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,483 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,485 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,487 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,489 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,491 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,494 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,496 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,498 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,502 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,505 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:12,505 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:12,507 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:12,541 INFO L134 CoverageAnalysis]: Checked inductivity of 7202 backedges. 2 proven. 7200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:12,557 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:12,558 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 63] total 63 [2018-01-29 22:38:12,558 INFO L409 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-01-29 22:38:12,558 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-01-29 22:38:12,558 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1953, Invalid=1953, Unknown=0, NotChecked=0, Total=3906 [2018-01-29 22:38:12,559 INFO L87 Difference]: Start difference. First operand 754 states and 878 transitions. Second operand 63 states. [2018-01-29 22:38:12,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:12,947 INFO L93 Difference]: Finished difference Result 1522 states and 1776 transitions. [2018-01-29 22:38:12,947 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-01-29 22:38:12,947 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 266 [2018-01-29 22:38:12,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:12,949 INFO L225 Difference]: With dead ends: 1522 [2018-01-29 22:38:12,949 INFO L226 Difference]: Without dead ends: 774 [2018-01-29 22:38:12,949 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 328 GetRequests, 267 SyntacticMatches, 0 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1953, Invalid=1953, Unknown=0, NotChecked=0, Total=3906 [2018-01-29 22:38:12,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 774 states. [2018-01-29 22:38:12,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 774 to 766. [2018-01-29 22:38:12,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 766 states. [2018-01-29 22:38:12,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 766 states to 766 states and 892 transitions. [2018-01-29 22:38:12,954 INFO L78 Accepts]: Start accepts. Automaton has 766 states and 892 transitions. Word has length 266 [2018-01-29 22:38:12,954 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:12,954 INFO L432 AbstractCegarLoop]: Abstraction has 766 states and 892 transitions. [2018-01-29 22:38:12,954 INFO L433 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-01-29 22:38:12,954 INFO L276 IsEmpty]: Start isEmpty. Operand 766 states and 892 transitions. [2018-01-29 22:38:12,955 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 271 [2018-01-29 22:38:12,955 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:12,955 INFO L350 BasicCegarLoop]: trace histogram [62, 61, 61, 61, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:12,955 INFO L371 AbstractCegarLoop]: === Iteration 64 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:12,955 INFO L82 PathProgramCache]: Analyzing trace with hash 1705148186, now seen corresponding path program 61 times [2018-01-29 22:38:12,955 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:12,955 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:12,956 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:12,956 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:12,956 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:12,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:12,963 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:14,033 INFO L134 CoverageAnalysis]: Checked inductivity of 7444 backedges. 2 proven. 7442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:14,033 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:14,033 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:14,039 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:14,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:14,061 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:14,100 INFO L134 CoverageAnalysis]: Checked inductivity of 7444 backedges. 2 proven. 7442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:14,117 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:14,117 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 64] total 64 [2018-01-29 22:38:14,117 INFO L409 AbstractCegarLoop]: Interpolant automaton has 64 states [2018-01-29 22:38:14,117 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2018-01-29 22:38:14,117 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-29 22:38:14,118 INFO L87 Difference]: Start difference. First operand 766 states and 892 transitions. Second operand 64 states. [2018-01-29 22:38:14,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:14,745 INFO L93 Difference]: Finished difference Result 1546 states and 1804 transitions. [2018-01-29 22:38:14,745 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2018-01-29 22:38:14,745 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 270 [2018-01-29 22:38:14,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:14,747 INFO L225 Difference]: With dead ends: 1546 [2018-01-29 22:38:14,747 INFO L226 Difference]: Without dead ends: 786 [2018-01-29 22:38:14,748 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 333 GetRequests, 271 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-29 22:38:14,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 786 states. [2018-01-29 22:38:14,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 786 to 778. [2018-01-29 22:38:14,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 778 states. [2018-01-29 22:38:14,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 778 states to 778 states and 906 transitions. [2018-01-29 22:38:14,753 INFO L78 Accepts]: Start accepts. Automaton has 778 states and 906 transitions. Word has length 270 [2018-01-29 22:38:14,753 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:14,753 INFO L432 AbstractCegarLoop]: Abstraction has 778 states and 906 transitions. [2018-01-29 22:38:14,753 INFO L433 AbstractCegarLoop]: Interpolant automaton has 64 states. [2018-01-29 22:38:14,753 INFO L276 IsEmpty]: Start isEmpty. Operand 778 states and 906 transitions. [2018-01-29 22:38:14,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 275 [2018-01-29 22:38:14,754 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:14,754 INFO L350 BasicCegarLoop]: trace histogram [63, 62, 62, 62, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:14,754 INFO L371 AbstractCegarLoop]: === Iteration 65 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:14,754 INFO L82 PathProgramCache]: Analyzing trace with hash 729483970, now seen corresponding path program 62 times [2018-01-29 22:38:14,754 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:14,754 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:14,755 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:14,755 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:14,755 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:14,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:14,763 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:15,896 INFO L134 CoverageAnalysis]: Checked inductivity of 7690 backedges. 2 proven. 7688 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:15,896 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:15,896 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:15,902 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:38:15,906 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:15,918 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:15,922 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:15,924 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:15,962 INFO L134 CoverageAnalysis]: Checked inductivity of 7690 backedges. 2 proven. 7688 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:15,979 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:15,979 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 65] total 65 [2018-01-29 22:38:15,979 INFO L409 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-01-29 22:38:15,979 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-01-29 22:38:15,979 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2080, Invalid=2080, Unknown=0, NotChecked=0, Total=4160 [2018-01-29 22:38:15,980 INFO L87 Difference]: Start difference. First operand 778 states and 906 transitions. Second operand 65 states. [2018-01-29 22:38:16,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:16,587 INFO L93 Difference]: Finished difference Result 1570 states and 1832 transitions. [2018-01-29 22:38:16,588 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-01-29 22:38:16,588 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 274 [2018-01-29 22:38:16,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:16,589 INFO L225 Difference]: With dead ends: 1570 [2018-01-29 22:38:16,589 INFO L226 Difference]: Without dead ends: 798 [2018-01-29 22:38:16,590 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 275 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=2080, Invalid=2080, Unknown=0, NotChecked=0, Total=4160 [2018-01-29 22:38:16,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 798 states. [2018-01-29 22:38:16,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 798 to 790. [2018-01-29 22:38:16,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 790 states. [2018-01-29 22:38:16,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 790 states and 920 transitions. [2018-01-29 22:38:16,595 INFO L78 Accepts]: Start accepts. Automaton has 790 states and 920 transitions. Word has length 274 [2018-01-29 22:38:16,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:16,595 INFO L432 AbstractCegarLoop]: Abstraction has 790 states and 920 transitions. [2018-01-29 22:38:16,595 INFO L433 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-01-29 22:38:16,595 INFO L276 IsEmpty]: Start isEmpty. Operand 790 states and 920 transitions. [2018-01-29 22:38:16,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 279 [2018-01-29 22:38:16,596 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:16,596 INFO L350 BasicCegarLoop]: trace histogram [64, 63, 63, 63, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:16,597 INFO L371 AbstractCegarLoop]: === Iteration 66 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:16,597 INFO L82 PathProgramCache]: Analyzing trace with hash -178945430, now seen corresponding path program 63 times [2018-01-29 22:38:16,597 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:16,597 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:16,597 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:16,597 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:16,597 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:16,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:16,605 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:17,746 INFO L134 CoverageAnalysis]: Checked inductivity of 7940 backedges. 2 proven. 7938 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:17,746 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:17,746 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:17,751 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:38:17,755 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,756 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,756 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,757 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,757 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,758 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,759 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,760 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,761 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,761 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,762 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,763 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,764 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,765 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,766 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,767 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,768 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,769 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,770 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,772 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,773 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,774 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,775 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,777 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,778 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,779 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,781 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,782 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,783 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,785 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,786 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,788 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,789 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,791 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,792 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,794 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,795 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,797 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,799 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,801 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,803 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,804 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,806 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,808 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,810 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,812 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,814 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,816 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,818 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,820 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,822 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,824 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,826 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,829 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,831 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,833 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,835 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,838 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,840 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,842 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,845 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,847 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,850 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,853 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,855 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:17,856 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:17,858 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:17,918 INFO L134 CoverageAnalysis]: Checked inductivity of 7940 backedges. 2 proven. 7938 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:17,936 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:17,936 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 66] total 66 [2018-01-29 22:38:17,936 INFO L409 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-01-29 22:38:17,936 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-01-29 22:38:17,937 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-01-29 22:38:17,937 INFO L87 Difference]: Start difference. First operand 790 states and 920 transitions. Second operand 66 states. [2018-01-29 22:38:18,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:18,564 INFO L93 Difference]: Finished difference Result 1594 states and 1860 transitions. [2018-01-29 22:38:18,564 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-01-29 22:38:18,564 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 278 [2018-01-29 22:38:18,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:18,566 INFO L225 Difference]: With dead ends: 1594 [2018-01-29 22:38:18,566 INFO L226 Difference]: Without dead ends: 810 [2018-01-29 22:38:18,566 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 279 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-01-29 22:38:18,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 810 states. [2018-01-29 22:38:18,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 810 to 802. [2018-01-29 22:38:18,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 802 states. [2018-01-29 22:38:18,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 802 states to 802 states and 934 transitions. [2018-01-29 22:38:18,571 INFO L78 Accepts]: Start accepts. Automaton has 802 states and 934 transitions. Word has length 278 [2018-01-29 22:38:18,572 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:18,572 INFO L432 AbstractCegarLoop]: Abstraction has 802 states and 934 transitions. [2018-01-29 22:38:18,572 INFO L433 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-01-29 22:38:18,572 INFO L276 IsEmpty]: Start isEmpty. Operand 802 states and 934 transitions. [2018-01-29 22:38:18,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 283 [2018-01-29 22:38:18,573 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:18,573 INFO L350 BasicCegarLoop]: trace histogram [65, 64, 64, 64, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:18,573 INFO L371 AbstractCegarLoop]: === Iteration 67 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:18,573 INFO L82 PathProgramCache]: Analyzing trace with hash -665065966, now seen corresponding path program 64 times [2018-01-29 22:38:18,573 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:18,573 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:18,573 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:18,574 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:18,574 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:18,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:18,582 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:19,730 INFO L134 CoverageAnalysis]: Checked inductivity of 8194 backedges. 2 proven. 8192 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:19,730 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:19,730 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:19,736 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:38:19,760 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:19,762 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:19,801 INFO L134 CoverageAnalysis]: Checked inductivity of 8194 backedges. 2 proven. 8192 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:19,817 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:19,817 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [67, 67] total 67 [2018-01-29 22:38:19,818 INFO L409 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-01-29 22:38:19,818 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-01-29 22:38:19,818 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2211, Invalid=2211, Unknown=0, NotChecked=0, Total=4422 [2018-01-29 22:38:19,818 INFO L87 Difference]: Start difference. First operand 802 states and 934 transitions. Second operand 67 states. [2018-01-29 22:38:20,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:20,461 INFO L93 Difference]: Finished difference Result 1618 states and 1888 transitions. [2018-01-29 22:38:20,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-01-29 22:38:20,462 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 282 [2018-01-29 22:38:20,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:20,463 INFO L225 Difference]: With dead ends: 1618 [2018-01-29 22:38:20,463 INFO L226 Difference]: Without dead ends: 822 [2018-01-29 22:38:20,464 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 348 GetRequests, 283 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=2211, Invalid=2211, Unknown=0, NotChecked=0, Total=4422 [2018-01-29 22:38:20,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 822 states. [2018-01-29 22:38:20,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 822 to 814. [2018-01-29 22:38:20,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 814 states. [2018-01-29 22:38:20,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 814 states to 814 states and 948 transitions. [2018-01-29 22:38:20,470 INFO L78 Accepts]: Start accepts. Automaton has 814 states and 948 transitions. Word has length 282 [2018-01-29 22:38:20,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:20,470 INFO L432 AbstractCegarLoop]: Abstraction has 814 states and 948 transitions. [2018-01-29 22:38:20,470 INFO L433 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-01-29 22:38:20,470 INFO L276 IsEmpty]: Start isEmpty. Operand 814 states and 948 transitions. [2018-01-29 22:38:20,471 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 287 [2018-01-29 22:38:20,471 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:20,471 INFO L350 BasicCegarLoop]: trace histogram [66, 65, 65, 65, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:20,471 INFO L371 AbstractCegarLoop]: === Iteration 68 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:20,471 INFO L82 PathProgramCache]: Analyzing trace with hash 1152923066, now seen corresponding path program 65 times [2018-01-29 22:38:20,471 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:20,471 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:20,472 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:20,472 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:20,472 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:20,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:20,480 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:21,723 INFO L134 CoverageAnalysis]: Checked inductivity of 8452 backedges. 2 proven. 8450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:21,723 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:21,723 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:21,728 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:38:21,741 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,742 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,743 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,743 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,744 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,745 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,746 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,746 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,747 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,748 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,749 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,749 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,750 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,751 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,752 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,753 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,754 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,755 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,757 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,758 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,759 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,760 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,761 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,762 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,764 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,765 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,766 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,767 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,769 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,770 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,772 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,773 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,775 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,776 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,778 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,779 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,781 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,782 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,784 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,786 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,788 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,789 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,791 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,793 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,795 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,797 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,799 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,801 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,803 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,805 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,807 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,809 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,811 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,813 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,815 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,818 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,820 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,823 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,825 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,827 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,830 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,832 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,835 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,838 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,841 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,845 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:21,845 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:21,848 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:21,890 INFO L134 CoverageAnalysis]: Checked inductivity of 8452 backedges. 2 proven. 8450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:21,908 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:21,908 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 68] total 68 [2018-01-29 22:38:21,908 INFO L409 AbstractCegarLoop]: Interpolant automaton has 68 states [2018-01-29 22:38:21,909 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2018-01-29 22:38:21,909 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-01-29 22:38:21,909 INFO L87 Difference]: Start difference. First operand 814 states and 948 transitions. Second operand 68 states. [2018-01-29 22:38:22,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:22,571 INFO L93 Difference]: Finished difference Result 1642 states and 1916 transitions. [2018-01-29 22:38:22,571 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-01-29 22:38:22,571 INFO L78 Accepts]: Start accepts. Automaton has 68 states. Word has length 286 [2018-01-29 22:38:22,571 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:22,573 INFO L225 Difference]: With dead ends: 1642 [2018-01-29 22:38:22,573 INFO L226 Difference]: Without dead ends: 834 [2018-01-29 22:38:22,574 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 353 GetRequests, 287 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-01-29 22:38:22,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 834 states. [2018-01-29 22:38:22,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 834 to 826. [2018-01-29 22:38:22,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 826 states. [2018-01-29 22:38:22,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 826 states to 826 states and 962 transitions. [2018-01-29 22:38:22,579 INFO L78 Accepts]: Start accepts. Automaton has 826 states and 962 transitions. Word has length 286 [2018-01-29 22:38:22,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:22,579 INFO L432 AbstractCegarLoop]: Abstraction has 826 states and 962 transitions. [2018-01-29 22:38:22,579 INFO L433 AbstractCegarLoop]: Interpolant automaton has 68 states. [2018-01-29 22:38:22,579 INFO L276 IsEmpty]: Start isEmpty. Operand 826 states and 962 transitions. [2018-01-29 22:38:22,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 291 [2018-01-29 22:38:22,580 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:22,580 INFO L350 BasicCegarLoop]: trace histogram [67, 66, 66, 66, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:22,580 INFO L371 AbstractCegarLoop]: === Iteration 69 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:22,580 INFO L82 PathProgramCache]: Analyzing trace with hash -2053869214, now seen corresponding path program 66 times [2018-01-29 22:38:22,580 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:22,580 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:22,581 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:22,581 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:22,581 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:22,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:22,589 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:23,818 INFO L134 CoverageAnalysis]: Checked inductivity of 8714 backedges. 2 proven. 8712 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:23,818 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:23,819 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:23,823 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:38:23,828 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,829 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,830 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,831 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,831 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,832 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,833 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,833 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,834 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,835 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,836 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,837 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,838 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,839 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,839 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,840 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,841 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,842 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,843 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,845 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,846 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,847 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,848 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,849 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,850 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,851 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,852 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,854 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,855 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,856 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,858 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,859 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,860 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,862 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,863 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,864 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,866 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,867 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,869 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,870 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,872 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,874 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,875 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,877 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,879 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,880 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,882 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,884 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,886 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,888 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,890 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,892 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,894 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,896 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,898 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,900 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,902 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,904 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,906 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,908 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,910 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,913 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,915 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,917 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,919 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,922 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,924 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,928 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:23,928 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:23,931 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:23,970 INFO L134 CoverageAnalysis]: Checked inductivity of 8714 backedges. 2 proven. 8712 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:23,987 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:23,987 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [69, 69] total 69 [2018-01-29 22:38:23,987 INFO L409 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-01-29 22:38:23,987 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-01-29 22:38:23,988 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2346, Invalid=2346, Unknown=0, NotChecked=0, Total=4692 [2018-01-29 22:38:23,988 INFO L87 Difference]: Start difference. First operand 826 states and 962 transitions. Second operand 69 states. [2018-01-29 22:38:24,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:24,709 INFO L93 Difference]: Finished difference Result 1666 states and 1944 transitions. [2018-01-29 22:38:24,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-01-29 22:38:24,709 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 290 [2018-01-29 22:38:24,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:24,711 INFO L225 Difference]: With dead ends: 1666 [2018-01-29 22:38:24,711 INFO L226 Difference]: Without dead ends: 846 [2018-01-29 22:38:24,712 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 358 GetRequests, 291 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2346, Invalid=2346, Unknown=0, NotChecked=0, Total=4692 [2018-01-29 22:38:24,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 846 states. [2018-01-29 22:38:24,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 846 to 838. [2018-01-29 22:38:24,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 838 states. [2018-01-29 22:38:24,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 976 transitions. [2018-01-29 22:38:24,717 INFO L78 Accepts]: Start accepts. Automaton has 838 states and 976 transitions. Word has length 290 [2018-01-29 22:38:24,717 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:24,717 INFO L432 AbstractCegarLoop]: Abstraction has 838 states and 976 transitions. [2018-01-29 22:38:24,717 INFO L433 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-01-29 22:38:24,718 INFO L276 IsEmpty]: Start isEmpty. Operand 838 states and 976 transitions. [2018-01-29 22:38:24,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 295 [2018-01-29 22:38:24,719 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:24,719 INFO L350 BasicCegarLoop]: trace histogram [68, 67, 67, 67, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:24,719 INFO L371 AbstractCegarLoop]: === Iteration 70 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:24,719 INFO L82 PathProgramCache]: Analyzing trace with hash 1092262154, now seen corresponding path program 67 times [2018-01-29 22:38:24,719 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:24,719 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:24,719 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:24,719 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:24,719 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:24,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:24,728 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. Received shutdown request... [2018-01-29 22:38:24,978 FATAL L265 ToolchainWalker]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: Timeout exceeded at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.walkLeafNode(Interpolator.java:265) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.access$1(Interpolator.java:263) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator$ProofTreeWalker.walk(Interpolator.java:132) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:122) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:113) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.interpolate(Interpolator.java:220) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.getInterpolants(Interpolator.java:201) at de.uni_freiburg.informatik.ultimate.smtinterpol.smtlib2.SMTInterpol.getInterpolants(SMTInterpol.java:915) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.managedscript.ManagedScript.getInterpolants(ManagedScript.java:192) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.NestedInterpolantsBuilder.computeCraigInterpolants(NestedInterpolantsBuilder.java:281) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.NestedInterpolantsBuilder.(NestedInterpolantsBuilder.java:164) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.computeInterpolantsTree(InterpolatingTraceCheckCraig.java:263) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.computeInterpolants(InterpolatingTraceCheckCraig.java:199) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.(InterpolatingTraceCheckCraig.java:106) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructCraig(TraceCheckConstructor.java:222) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.get(TraceCheckConstructor.java:179) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.MultiTrackTraceAbstractionRefinementStrategy.getTraceCheck(MultiTrackTraceAbstractionRefinementStrategy.java:218) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.checkFeasibility(BaseRefinementStrategy.java:231) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.executeStrategy(BaseRefinementStrategy.java:205) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:68) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:396) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:381) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:316) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:292) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:147) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:115) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:119) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:324) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.runToolchainDefault(DefaultToolchainJob.java:221) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.BasicToolchainJob.run(BasicToolchainJob.java:134) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) [2018-01-29 22:38:24,980 INFO L168 Benchmark]: Toolchain (without parser) took 66634.50 ms. Allocated memory was 151.0 MB in the beginning and 1.1 GB in the end (delta: 921.2 MB). Free memory was 114.6 MB in the beginning and 727.1 MB in the end (delta: -612.5 MB). Peak memory consumption was 938.6 MB. Max. memory is 5.3 GB. [2018-01-29 22:38:24,981 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 151.0 MB. Free memory is still 120.8 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-29 22:38:24,981 INFO L168 Benchmark]: CACSL2BoogieTranslator took 108.71 ms. Allocated memory is still 151.0 MB. Free memory was 114.6 MB in the beginning and 106.1 MB in the end (delta: 8.5 MB). Peak memory consumption was 8.5 MB. Max. memory is 5.3 GB. [2018-01-29 22:38:24,982 INFO L168 Benchmark]: Boogie Preprocessor took 17.76 ms. Allocated memory is still 151.0 MB. Free memory was 106.1 MB in the beginning and 104.7 MB in the end (delta: 1.4 MB). Peak memory consumption was 1.4 MB. Max. memory is 5.3 GB. [2018-01-29 22:38:24,982 INFO L168 Benchmark]: RCFGBuilder took 308.42 ms. Allocated memory is still 151.0 MB. Free memory was 104.7 MB in the beginning and 92.0 MB in the end (delta: 12.7 MB). Peak memory consumption was 12.7 MB. Max. memory is 5.3 GB. [2018-01-29 22:38:24,982 INFO L168 Benchmark]: TraceAbstraction took 66196.66 ms. Allocated memory was 151.0 MB in the beginning and 1.1 GB in the end (delta: 921.2 MB). Free memory was 91.6 MB in the beginning and 727.1 MB in the end (delta: -635.5 MB). Peak memory consumption was 915.6 MB. Max. memory is 5.3 GB. [2018-01-29 22:38:24,983 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 151.0 MB. Free memory is still 120.8 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 108.71 ms. Allocated memory is still 151.0 MB. Free memory was 114.6 MB in the beginning and 106.1 MB in the end (delta: 8.5 MB). Peak memory consumption was 8.5 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 17.76 ms. Allocated memory is still 151.0 MB. Free memory was 106.1 MB in the beginning and 104.7 MB in the end (delta: 1.4 MB). Peak memory consumption was 1.4 MB. Max. memory is 5.3 GB. * RCFGBuilder took 308.42 ms. Allocated memory is still 151.0 MB. Free memory was 104.7 MB in the beginning and 92.0 MB in the end (delta: 12.7 MB). Peak memory consumption was 12.7 MB. Max. memory is 5.3 GB. * TraceAbstraction took 66196.66 ms. Allocated memory was 151.0 MB in the beginning and 1.1 GB in the end (delta: 921.2 MB). Free memory was 91.6 MB in the beginning and 727.1 MB in the end (delta: -635.5 MB). Peak memory consumption was 915.6 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: Timeout exceeded de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: Timeout exceeded: de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.walkLeafNode(Interpolator.java:265) RESULT: Ultimate could not prove your program: Toolchain returned no result. Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sorting_bubblesort_false-unreach-call2_ground.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-29_22-38-24-986.csv Completed graceful shutdown