java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/array-examples/sorting_bubblesort_false-unreach-call_ground.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-1cceb4a-m [2018-01-29 22:38:26,242 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-29 22:38:26,244 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-29 22:38:26,255 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-29 22:38:26,256 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-29 22:38:26,256 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-29 22:38:26,257 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-29 22:38:26,258 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-29 22:38:26,259 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-29 22:38:26,259 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-29 22:38:26,260 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-29 22:38:26,260 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-29 22:38:26,261 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-29 22:38:26,261 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-29 22:38:26,262 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-29 22:38:26,263 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-29 22:38:26,264 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-29 22:38:26,265 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-29 22:38:26,266 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-29 22:38:26,266 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-29 22:38:26,267 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-01-29 22:38:26,270 INFO L98 SettingsManager]: Beginning loading settings from /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf [2018-01-29 22:38:26,275 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-29 22:38:26,275 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-29 22:38:26,276 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-29 22:38:26,276 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-29 22:38:26,276 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-29 22:38:26,276 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-29 22:38:26,276 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-29 22:38:26,277 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-29 22:38:26,277 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-29 22:38:26,277 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-29 22:38:26,277 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-29 22:38:26,277 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-29 22:38:26,277 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-01-29 22:38:26,277 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-29 22:38:26,277 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-01-29 22:38:26,277 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-29 22:38:26,277 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-01-29 22:38:26,278 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-01-29 22:38:26,278 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-29 22:38:26,278 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-01-29 22:38:26,278 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-29 22:38:26,278 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-29 22:38:26,278 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-29 22:38:26,278 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-29 22:38:26,278 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-29 22:38:26,278 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-29 22:38:26,278 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-29 22:38:26,279 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-29 22:38:26,279 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-29 22:38:26,279 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-29 22:38:26,279 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-29 22:38:26,279 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-29 22:38:26,279 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-29 22:38:26,279 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-29 22:38:26,308 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-29 22:38:26,315 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-29 22:38:26,319 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-29 22:38:26,319 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-29 22:38:26,320 INFO L276 PluginConnector]: CDTParser initialized [2018-01-29 22:38:26,320 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/sorting_bubblesort_false-unreach-call_ground.i [2018-01-29 22:38:26,384 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-29 22:38:26,385 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-29 22:38:26,386 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-29 22:38:26,386 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-29 22:38:26,389 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-29 22:38:26,390 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.01 10:38:26" (1/1) ... [2018-01-29 22:38:26,392 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@74663061 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:38:26, skipping insertion in model container [2018-01-29 22:38:26,392 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.01 10:38:26" (1/1) ... [2018-01-29 22:38:26,401 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-29 22:38:26,409 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-29 22:38:26,478 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-29 22:38:26,486 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-29 22:38:26,489 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:38:26 WrapperNode [2018-01-29 22:38:26,489 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-29 22:38:26,490 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-29 22:38:26,490 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-29 22:38:26,490 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-29 22:38:26,498 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:38:26" (1/1) ... [2018-01-29 22:38:26,498 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:38:26" (1/1) ... [2018-01-29 22:38:26,503 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:38:26" (1/1) ... [2018-01-29 22:38:26,503 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:38:26" (1/1) ... [2018-01-29 22:38:26,504 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:38:26" (1/1) ... [2018-01-29 22:38:26,506 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:38:26" (1/1) ... [2018-01-29 22:38:26,507 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:38:26" (1/1) ... [2018-01-29 22:38:26,507 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-29 22:38:26,508 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-29 22:38:26,508 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-29 22:38:26,508 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-29 22:38:26,508 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:38:26" (1/1) ... No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-29 22:38:26,548 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-29 22:38:26,548 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-29 22:38:26,548 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-29 22:38:26,549 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-29 22:38:26,549 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-29 22:38:26,549 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-29 22:38:26,549 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-29 22:38:26,549 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-29 22:38:26,549 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-29 22:38:26,924 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-29 22:38:26,925 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.01 10:38:26 BoogieIcfgContainer [2018-01-29 22:38:26,925 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-29 22:38:26,925 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-29 22:38:26,925 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-29 22:38:26,927 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-29 22:38:26,927 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 29.01 10:38:26" (1/3) ... [2018-01-29 22:38:26,928 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1a881a75 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 29.01 10:38:26, skipping insertion in model container [2018-01-29 22:38:26,928 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 10:38:26" (2/3) ... [2018-01-29 22:38:26,928 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1a881a75 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 29.01 10:38:26, skipping insertion in model container [2018-01-29 22:38:26,928 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.01 10:38:26" (3/3) ... [2018-01-29 22:38:26,929 INFO L107 eAbstractionObserver]: Analyzing ICFG sorting_bubblesort_false-unreach-call_ground.i [2018-01-29 22:38:26,934 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-29 22:38:26,938 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-01-29 22:38:26,962 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-29 22:38:26,962 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-29 22:38:26,962 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-29 22:38:26,962 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-29 22:38:26,962 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-29 22:38:26,962 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-29 22:38:26,962 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-29 22:38:26,962 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-29 22:38:26,963 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-29 22:38:26,972 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states. [2018-01-29 22:38:26,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-01-29 22:38:26,975 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:26,976 INFO L350 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:26,976 INFO L371 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:26,978 INFO L82 PathProgramCache]: Analyzing trace with hash 1032819300, now seen corresponding path program 1 times [2018-01-29 22:38:26,979 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:26,980 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:27,008 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:27,008 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:27,008 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:27,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:27,028 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:27,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:27,045 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-29 22:38:27,045 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-29 22:38:27,046 INFO L409 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-01-29 22:38:27,053 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-01-29 22:38:27,053 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-29 22:38:27,054 INFO L87 Difference]: Start difference. First operand 44 states. Second operand 2 states. [2018-01-29 22:38:27,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:27,068 INFO L93 Difference]: Finished difference Result 82 states and 100 transitions. [2018-01-29 22:38:27,068 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-01-29 22:38:27,068 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 19 [2018-01-29 22:38:27,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:27,073 INFO L225 Difference]: With dead ends: 82 [2018-01-29 22:38:27,074 INFO L226 Difference]: Without dead ends: 39 [2018-01-29 22:38:27,075 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-29 22:38:27,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2018-01-29 22:38:27,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2018-01-29 22:38:27,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-01-29 22:38:27,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 44 transitions. [2018-01-29 22:38:27,096 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 44 transitions. Word has length 19 [2018-01-29 22:38:27,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:27,096 INFO L432 AbstractCegarLoop]: Abstraction has 39 states and 44 transitions. [2018-01-29 22:38:27,096 INFO L433 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-01-29 22:38:27,096 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 44 transitions. [2018-01-29 22:38:27,097 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-01-29 22:38:27,097 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:27,097 INFO L350 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:27,097 INFO L371 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:27,097 INFO L82 PathProgramCache]: Analyzing trace with hash 196893831, now seen corresponding path program 1 times [2018-01-29 22:38:27,097 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:27,097 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:27,098 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:27,098 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:27,098 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:27,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:27,102 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:27,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:27,135 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-29 22:38:27,135 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-29 22:38:27,136 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-29 22:38:27,136 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-29 22:38:27,136 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-29 22:38:27,146 INFO L87 Difference]: Start difference. First operand 39 states and 44 transitions. Second operand 3 states. [2018-01-29 22:38:27,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:27,188 INFO L93 Difference]: Finished difference Result 71 states and 81 transitions. [2018-01-29 22:38:27,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-29 22:38:27,189 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 20 [2018-01-29 22:38:27,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:27,189 INFO L225 Difference]: With dead ends: 71 [2018-01-29 22:38:27,189 INFO L226 Difference]: Without dead ends: 50 [2018-01-29 22:38:27,190 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-29 22:38:27,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-01-29 22:38:27,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 45. [2018-01-29 22:38:27,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-01-29 22:38:27,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 52 transitions. [2018-01-29 22:38:27,194 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 52 transitions. Word has length 20 [2018-01-29 22:38:27,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:27,194 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 52 transitions. [2018-01-29 22:38:27,194 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-29 22:38:27,194 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 52 transitions. [2018-01-29 22:38:27,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-01-29 22:38:27,194 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:27,195 INFO L350 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:27,195 INFO L371 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:27,195 INFO L82 PathProgramCache]: Analyzing trace with hash 757431314, now seen corresponding path program 1 times [2018-01-29 22:38:27,195 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:27,195 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:27,196 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:27,196 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:27,196 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:27,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:27,203 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:27,234 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:27,234 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-29 22:38:27,234 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-29 22:38:27,235 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-29 22:38:27,235 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-29 22:38:27,235 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-29 22:38:27,235 INFO L87 Difference]: Start difference. First operand 45 states and 52 transitions. Second operand 3 states. [2018-01-29 22:38:27,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:27,371 INFO L93 Difference]: Finished difference Result 93 states and 109 transitions. [2018-01-29 22:38:27,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-29 22:38:27,372 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 26 [2018-01-29 22:38:27,372 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:27,372 INFO L225 Difference]: With dead ends: 93 [2018-01-29 22:38:27,372 INFO L226 Difference]: Without dead ends: 54 [2018-01-29 22:38:27,373 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-29 22:38:27,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-01-29 22:38:27,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 47. [2018-01-29 22:38:27,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-01-29 22:38:27,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 54 transitions. [2018-01-29 22:38:27,376 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 54 transitions. Word has length 26 [2018-01-29 22:38:27,377 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:27,377 INFO L432 AbstractCegarLoop]: Abstraction has 47 states and 54 transitions. [2018-01-29 22:38:27,377 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-29 22:38:27,377 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 54 transitions. [2018-01-29 22:38:27,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-01-29 22:38:27,377 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:27,377 INFO L350 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:27,377 INFO L371 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:27,377 INFO L82 PathProgramCache]: Analyzing trace with hash 1321651130, now seen corresponding path program 1 times [2018-01-29 22:38:27,378 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:27,378 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:27,378 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:27,378 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:27,378 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:27,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:27,383 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:27,427 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:27,427 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:27,427 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:27,441 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:27,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:27,464 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:27,476 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:27,492 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:27,492 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2018-01-29 22:38:27,493 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-29 22:38:27,493 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-29 22:38:27,493 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-29 22:38:27,493 INFO L87 Difference]: Start difference. First operand 47 states and 54 transitions. Second operand 4 states. [2018-01-29 22:38:27,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:27,608 INFO L93 Difference]: Finished difference Result 107 states and 126 transitions. [2018-01-29 22:38:27,608 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-29 22:38:27,608 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 30 [2018-01-29 22:38:27,608 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:27,609 INFO L225 Difference]: With dead ends: 107 [2018-01-29 22:38:27,609 INFO L226 Difference]: Without dead ends: 66 [2018-01-29 22:38:27,609 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-29 22:38:27,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-01-29 22:38:27,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 58. [2018-01-29 22:38:27,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-01-29 22:38:27,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 66 transitions. [2018-01-29 22:38:27,613 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 66 transitions. Word has length 30 [2018-01-29 22:38:27,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:27,613 INFO L432 AbstractCegarLoop]: Abstraction has 58 states and 66 transitions. [2018-01-29 22:38:27,613 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-29 22:38:27,613 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 66 transitions. [2018-01-29 22:38:27,614 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-29 22:38:27,614 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:27,614 INFO L350 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:27,614 INFO L371 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:27,614 INFO L82 PathProgramCache]: Analyzing trace with hash 443025250, now seen corresponding path program 2 times [2018-01-29 22:38:27,614 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:27,614 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:27,615 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:27,615 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:27,615 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:27,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:27,622 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:27,731 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 2 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:27,731 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:27,731 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:27,739 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:38:27,744 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:27,754 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:27,766 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:27,768 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:27,771 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 2 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:27,787 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:27,787 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-01-29 22:38:27,788 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-29 22:38:27,788 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-29 22:38:27,788 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-01-29 22:38:27,788 INFO L87 Difference]: Start difference. First operand 58 states and 66 transitions. Second operand 5 states. [2018-01-29 22:38:27,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:27,844 INFO L93 Difference]: Finished difference Result 130 states and 152 transitions. [2018-01-29 22:38:27,844 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-29 22:38:27,844 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 34 [2018-01-29 22:38:27,845 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:27,845 INFO L225 Difference]: With dead ends: 130 [2018-01-29 22:38:27,845 INFO L226 Difference]: Without dead ends: 78 [2018-01-29 22:38:27,845 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 35 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-01-29 22:38:27,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2018-01-29 22:38:27,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 70. [2018-01-29 22:38:27,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-01-29 22:38:27,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 80 transitions. [2018-01-29 22:38:27,849 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 80 transitions. Word has length 34 [2018-01-29 22:38:27,849 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:27,849 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 80 transitions. [2018-01-29 22:38:27,849 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-29 22:38:27,849 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 80 transitions. [2018-01-29 22:38:27,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-01-29 22:38:27,851 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:27,851 INFO L350 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:27,851 INFO L371 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:27,851 INFO L82 PathProgramCache]: Analyzing trace with hash 1983065866, now seen corresponding path program 3 times [2018-01-29 22:38:27,851 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:27,851 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:27,852 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:27,853 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:27,853 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:27,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:27,859 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:27,950 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 2 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:27,950 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:27,950 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:27,963 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:38:27,968 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:27,969 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:27,970 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:27,971 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:27,972 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:27,978 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:27,979 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:27,983 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 2 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:27,999 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:27,999 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-01-29 22:38:27,999 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-29 22:38:28,000 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-29 22:38:28,000 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-29 22:38:28,000 INFO L87 Difference]: Start difference. First operand 70 states and 80 transitions. Second operand 6 states. [2018-01-29 22:38:28,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:28,082 INFO L93 Difference]: Finished difference Result 154 states and 180 transitions. [2018-01-29 22:38:28,084 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-29 22:38:28,084 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 38 [2018-01-29 22:38:28,084 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:28,085 INFO L225 Difference]: With dead ends: 154 [2018-01-29 22:38:28,085 INFO L226 Difference]: Without dead ends: 90 [2018-01-29 22:38:28,085 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-29 22:38:28,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-01-29 22:38:28,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 82. [2018-01-29 22:38:28,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-01-29 22:38:28,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 94 transitions. [2018-01-29 22:38:28,092 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 94 transitions. Word has length 38 [2018-01-29 22:38:28,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:28,092 INFO L432 AbstractCegarLoop]: Abstraction has 82 states and 94 transitions. [2018-01-29 22:38:28,092 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-29 22:38:28,092 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 94 transitions. [2018-01-29 22:38:28,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-29 22:38:28,092 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:28,093 INFO L350 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:28,093 INFO L371 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:28,093 INFO L82 PathProgramCache]: Analyzing trace with hash 592593586, now seen corresponding path program 4 times [2018-01-29 22:38:28,093 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:28,093 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:28,093 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:28,094 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:28,094 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:28,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:28,100 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:28,144 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:28,144 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:28,144 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-29 22:38:28,156 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:28,165 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:28,166 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:28,170 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:28,187 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:28,187 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2018-01-29 22:38:28,187 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-29 22:38:28,187 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-29 22:38:28,187 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-01-29 22:38:28,188 INFO L87 Difference]: Start difference. First operand 82 states and 94 transitions. Second operand 7 states. [2018-01-29 22:38:28,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:28,473 INFO L93 Difference]: Finished difference Result 178 states and 208 transitions. [2018-01-29 22:38:28,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-29 22:38:28,473 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 42 [2018-01-29 22:38:28,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:28,474 INFO L225 Difference]: With dead ends: 178 [2018-01-29 22:38:28,474 INFO L226 Difference]: Without dead ends: 102 [2018-01-29 22:38:28,474 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-01-29 22:38:28,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-01-29 22:38:28,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 94. [2018-01-29 22:38:28,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-01-29 22:38:28,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 108 transitions. [2018-01-29 22:38:28,478 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 108 transitions. Word has length 42 [2018-01-29 22:38:28,478 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:28,478 INFO L432 AbstractCegarLoop]: Abstraction has 94 states and 108 transitions. [2018-01-29 22:38:28,478 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-29 22:38:28,478 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 108 transitions. [2018-01-29 22:38:28,479 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-01-29 22:38:28,479 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:28,479 INFO L350 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:28,479 INFO L371 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:28,479 INFO L82 PathProgramCache]: Analyzing trace with hash 1039090266, now seen corresponding path program 5 times [2018-01-29 22:38:28,479 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:28,479 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:28,480 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:28,480 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:28,480 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:28,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:28,486 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:28,532 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 2 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:28,532 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:28,532 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:28,543 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:38:28,548 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:28,561 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:28,574 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:28,583 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:28,584 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:28,585 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:28,585 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:28,586 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:28,591 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 2 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:28,607 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:28,607 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2018-01-29 22:38:28,607 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-29 22:38:28,607 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-29 22:38:28,608 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-29 22:38:28,608 INFO L87 Difference]: Start difference. First operand 94 states and 108 transitions. Second operand 8 states. [2018-01-29 22:38:28,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:28,791 INFO L93 Difference]: Finished difference Result 202 states and 236 transitions. [2018-01-29 22:38:28,792 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-29 22:38:28,792 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 46 [2018-01-29 22:38:28,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:28,792 INFO L225 Difference]: With dead ends: 202 [2018-01-29 22:38:28,793 INFO L226 Difference]: Without dead ends: 114 [2018-01-29 22:38:28,793 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 47 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-29 22:38:28,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-01-29 22:38:28,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 106. [2018-01-29 22:38:28,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-01-29 22:38:28,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 122 transitions. [2018-01-29 22:38:28,797 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 122 transitions. Word has length 46 [2018-01-29 22:38:28,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:28,798 INFO L432 AbstractCegarLoop]: Abstraction has 106 states and 122 transitions. [2018-01-29 22:38:28,798 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-29 22:38:28,798 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 122 transitions. [2018-01-29 22:38:28,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-01-29 22:38:28,799 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:28,799 INFO L350 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:28,799 INFO L371 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:28,799 INFO L82 PathProgramCache]: Analyzing trace with hash -1120653822, now seen corresponding path program 6 times [2018-01-29 22:38:28,799 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:28,799 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:28,799 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:28,800 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:28,800 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:28,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:28,806 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:28,875 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 2 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:28,876 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:28,876 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:28,881 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:38:28,888 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:28,892 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:28,897 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:28,898 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:28,899 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:28,900 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:28,900 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:28,909 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:28,910 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:28,911 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:28,921 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 2 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:28,937 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:28,937 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2018-01-29 22:38:28,937 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-29 22:38:28,937 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-29 22:38:28,937 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-01-29 22:38:28,938 INFO L87 Difference]: Start difference. First operand 106 states and 122 transitions. Second operand 9 states. [2018-01-29 22:38:29,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:29,074 INFO L93 Difference]: Finished difference Result 226 states and 264 transitions. [2018-01-29 22:38:29,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-29 22:38:29,074 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 50 [2018-01-29 22:38:29,074 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:29,075 INFO L225 Difference]: With dead ends: 226 [2018-01-29 22:38:29,075 INFO L226 Difference]: Without dead ends: 126 [2018-01-29 22:38:29,075 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 51 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-01-29 22:38:29,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-01-29 22:38:29,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 118. [2018-01-29 22:38:29,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-29 22:38:29,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 136 transitions. [2018-01-29 22:38:29,079 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 136 transitions. Word has length 50 [2018-01-29 22:38:29,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:29,080 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 136 transitions. [2018-01-29 22:38:29,080 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-29 22:38:29,080 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 136 transitions. [2018-01-29 22:38:29,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-01-29 22:38:29,080 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:29,081 INFO L350 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:29,081 INFO L371 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:29,081 INFO L82 PathProgramCache]: Analyzing trace with hash -213187158, now seen corresponding path program 7 times [2018-01-29 22:38:29,081 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:29,081 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:29,081 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:29,081 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:29,082 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:29,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:29,087 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:29,191 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 98 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:29,191 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:29,191 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:29,196 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:29,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:29,214 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:29,219 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 98 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:29,235 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:29,236 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2018-01-29 22:38:29,236 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-29 22:38:29,236 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-29 22:38:29,236 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-29 22:38:29,236 INFO L87 Difference]: Start difference. First operand 118 states and 136 transitions. Second operand 10 states. [2018-01-29 22:38:29,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:29,442 INFO L93 Difference]: Finished difference Result 250 states and 292 transitions. [2018-01-29 22:38:29,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-29 22:38:29,442 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 54 [2018-01-29 22:38:29,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:29,443 INFO L225 Difference]: With dead ends: 250 [2018-01-29 22:38:29,443 INFO L226 Difference]: Without dead ends: 138 [2018-01-29 22:38:29,443 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-29 22:38:29,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-01-29 22:38:29,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 130. [2018-01-29 22:38:29,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-01-29 22:38:29,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 150 transitions. [2018-01-29 22:38:29,446 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 150 transitions. Word has length 54 [2018-01-29 22:38:29,447 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:29,447 INFO L432 AbstractCegarLoop]: Abstraction has 130 states and 150 transitions. [2018-01-29 22:38:29,447 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-29 22:38:29,447 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 150 transitions. [2018-01-29 22:38:29,448 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-01-29 22:38:29,448 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:29,448 INFO L350 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:29,448 INFO L371 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:29,448 INFO L82 PathProgramCache]: Analyzing trace with hash 224250194, now seen corresponding path program 8 times [2018-01-29 22:38:29,448 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:29,448 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:29,449 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:29,449 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:29,449 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:29,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:29,455 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:29,782 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 2 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:29,782 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:29,782 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:29,786 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:38:29,790 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:29,806 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:29,806 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:29,808 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:29,816 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 2 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:29,833 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:29,833 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2018-01-29 22:38:29,833 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-29 22:38:29,833 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-29 22:38:29,833 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-01-29 22:38:29,834 INFO L87 Difference]: Start difference. First operand 130 states and 150 transitions. Second operand 11 states. [2018-01-29 22:38:29,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:29,925 INFO L93 Difference]: Finished difference Result 274 states and 320 transitions. [2018-01-29 22:38:29,926 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-29 22:38:29,926 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 58 [2018-01-29 22:38:29,926 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:29,926 INFO L225 Difference]: With dead ends: 274 [2018-01-29 22:38:29,926 INFO L226 Difference]: Without dead ends: 150 [2018-01-29 22:38:29,927 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 59 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-01-29 22:38:29,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-01-29 22:38:29,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 142. [2018-01-29 22:38:29,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-01-29 22:38:29,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 164 transitions. [2018-01-29 22:38:29,930 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 164 transitions. Word has length 58 [2018-01-29 22:38:29,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:29,930 INFO L432 AbstractCegarLoop]: Abstraction has 142 states and 164 transitions. [2018-01-29 22:38:29,930 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-29 22:38:29,930 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 164 transitions. [2018-01-29 22:38:29,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-29 22:38:29,931 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:29,931 INFO L350 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:29,931 INFO L371 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:29,931 INFO L82 PathProgramCache]: Analyzing trace with hash -1818855174, now seen corresponding path program 9 times [2018-01-29 22:38:29,931 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:29,931 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:29,932 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:29,932 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:29,932 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:29,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:29,938 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:30,022 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 2 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:30,022 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:30,022 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:30,027 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:38:30,030 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:30,032 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:30,033 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:30,034 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:30,034 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:30,035 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:30,036 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:30,037 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:30,038 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:30,038 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:30,039 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:30,040 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:30,041 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:30,047 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 2 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:30,063 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:30,063 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2018-01-29 22:38:30,063 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-29 22:38:30,064 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-29 22:38:30,064 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-01-29 22:38:30,064 INFO L87 Difference]: Start difference. First operand 142 states and 164 transitions. Second operand 12 states. [2018-01-29 22:38:30,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:30,178 INFO L93 Difference]: Finished difference Result 298 states and 348 transitions. [2018-01-29 22:38:30,179 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-29 22:38:30,179 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 62 [2018-01-29 22:38:30,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:30,179 INFO L225 Difference]: With dead ends: 298 [2018-01-29 22:38:30,179 INFO L226 Difference]: Without dead ends: 162 [2018-01-29 22:38:30,180 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 63 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-01-29 22:38:30,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-01-29 22:38:30,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 154. [2018-01-29 22:38:30,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-01-29 22:38:30,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 178 transitions. [2018-01-29 22:38:30,185 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 178 transitions. Word has length 62 [2018-01-29 22:38:30,185 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:30,185 INFO L432 AbstractCegarLoop]: Abstraction has 154 states and 178 transitions. [2018-01-29 22:38:30,185 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-29 22:38:30,185 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 178 transitions. [2018-01-29 22:38:30,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-01-29 22:38:30,186 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:30,186 INFO L350 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:30,186 INFO L371 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:30,186 INFO L82 PathProgramCache]: Analyzing trace with hash -383839070, now seen corresponding path program 10 times [2018-01-29 22:38:30,186 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:30,186 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:30,187 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:30,187 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:30,187 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:30,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:30,197 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:30,289 INFO L134 CoverageAnalysis]: Checked inductivity of 202 backedges. 2 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:30,290 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:30,290 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:30,295 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:38:30,303 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:30,305 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:30,314 INFO L134 CoverageAnalysis]: Checked inductivity of 202 backedges. 2 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:30,331 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:30,331 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2018-01-29 22:38:30,331 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-29 22:38:30,331 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-29 22:38:30,332 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-01-29 22:38:30,332 INFO L87 Difference]: Start difference. First operand 154 states and 178 transitions. Second operand 13 states. [2018-01-29 22:38:30,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:30,406 INFO L93 Difference]: Finished difference Result 322 states and 376 transitions. [2018-01-29 22:38:30,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-29 22:38:30,406 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 66 [2018-01-29 22:38:30,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:30,407 INFO L225 Difference]: With dead ends: 322 [2018-01-29 22:38:30,407 INFO L226 Difference]: Without dead ends: 174 [2018-01-29 22:38:30,407 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-01-29 22:38:30,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-01-29 22:38:30,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 166. [2018-01-29 22:38:30,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-01-29 22:38:30,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 192 transitions. [2018-01-29 22:38:30,410 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 192 transitions. Word has length 66 [2018-01-29 22:38:30,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:30,410 INFO L432 AbstractCegarLoop]: Abstraction has 166 states and 192 transitions. [2018-01-29 22:38:30,410 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-29 22:38:30,410 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 192 transitions. [2018-01-29 22:38:30,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-01-29 22:38:30,411 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:30,411 INFO L350 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:30,411 INFO L371 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:30,411 INFO L82 PathProgramCache]: Analyzing trace with hash -870212534, now seen corresponding path program 11 times [2018-01-29 22:38:30,411 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:30,411 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:30,412 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:30,412 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:30,412 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:30,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:30,417 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:30,514 INFO L134 CoverageAnalysis]: Checked inductivity of 244 backedges. 2 proven. 242 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:30,515 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:30,515 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:30,519 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:38:30,522 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:30,537 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:30,547 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:30,560 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:30,570 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:30,583 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:30,593 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:30,603 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:30,613 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:30,623 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:30,630 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:30,640 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:30,650 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:30,651 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:30,657 INFO L134 CoverageAnalysis]: Checked inductivity of 244 backedges. 2 proven. 242 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:30,674 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:30,674 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 14 [2018-01-29 22:38:30,674 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-29 22:38:30,675 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-29 22:38:30,675 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-29 22:38:30,675 INFO L87 Difference]: Start difference. First operand 166 states and 192 transitions. Second operand 14 states. [2018-01-29 22:38:30,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:30,835 INFO L93 Difference]: Finished difference Result 346 states and 404 transitions. [2018-01-29 22:38:30,836 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-29 22:38:30,836 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 70 [2018-01-29 22:38:30,837 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:30,837 INFO L225 Difference]: With dead ends: 346 [2018-01-29 22:38:30,837 INFO L226 Difference]: Without dead ends: 186 [2018-01-29 22:38:30,838 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 71 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-29 22:38:30,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-01-29 22:38:30,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 178. [2018-01-29 22:38:30,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178 states. [2018-01-29 22:38:30,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 206 transitions. [2018-01-29 22:38:30,842 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 206 transitions. Word has length 70 [2018-01-29 22:38:30,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:30,842 INFO L432 AbstractCegarLoop]: Abstraction has 178 states and 206 transitions. [2018-01-29 22:38:30,842 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-29 22:38:30,842 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 206 transitions. [2018-01-29 22:38:30,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-01-29 22:38:30,843 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:30,843 INFO L350 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:30,843 INFO L371 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:30,843 INFO L82 PathProgramCache]: Analyzing trace with hash -708309006, now seen corresponding path program 12 times [2018-01-29 22:38:30,843 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:30,843 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:30,844 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:30,844 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:30,844 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:30,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:30,852 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:31,002 INFO L134 CoverageAnalysis]: Checked inductivity of 290 backedges. 2 proven. 288 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:31,002 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:31,002 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:31,010 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:38:31,014 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:31,015 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:31,015 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:31,017 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:31,018 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:31,019 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:31,020 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:31,020 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:31,021 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:31,022 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:31,023 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:31,024 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:31,025 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:31,026 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:31,026 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:31,027 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:31,042 INFO L134 CoverageAnalysis]: Checked inductivity of 290 backedges. 2 proven. 288 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:31,058 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:31,058 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 15 [2018-01-29 22:38:31,059 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-29 22:38:31,059 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-29 22:38:31,059 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2018-01-29 22:38:31,059 INFO L87 Difference]: Start difference. First operand 178 states and 206 transitions. Second operand 15 states. [2018-01-29 22:38:31,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:31,179 INFO L93 Difference]: Finished difference Result 370 states and 432 transitions. [2018-01-29 22:38:31,182 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-29 22:38:31,182 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 74 [2018-01-29 22:38:31,183 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:31,183 INFO L225 Difference]: With dead ends: 370 [2018-01-29 22:38:31,183 INFO L226 Difference]: Without dead ends: 198 [2018-01-29 22:38:31,184 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 75 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2018-01-29 22:38:31,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states. [2018-01-29 22:38:31,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 190. [2018-01-29 22:38:31,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-01-29 22:38:31,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 220 transitions. [2018-01-29 22:38:31,189 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 220 transitions. Word has length 74 [2018-01-29 22:38:31,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:31,189 INFO L432 AbstractCegarLoop]: Abstraction has 190 states and 220 transitions. [2018-01-29 22:38:31,189 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-29 22:38:31,189 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 220 transitions. [2018-01-29 22:38:31,190 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-29 22:38:31,190 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:31,190 INFO L350 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:31,190 INFO L371 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:31,190 INFO L82 PathProgramCache]: Analyzing trace with hash -96702566, now seen corresponding path program 13 times [2018-01-29 22:38:31,190 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:31,190 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:31,191 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:31,191 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:31,191 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:31,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:31,195 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:31,303 INFO L134 CoverageAnalysis]: Checked inductivity of 340 backedges. 2 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:31,303 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:31,303 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:31,317 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:31,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:31,326 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:31,335 INFO L134 CoverageAnalysis]: Checked inductivity of 340 backedges. 2 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:31,354 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:31,354 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 16 [2018-01-29 22:38:31,355 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-29 22:38:31,355 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-29 22:38:31,355 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-29 22:38:31,355 INFO L87 Difference]: Start difference. First operand 190 states and 220 transitions. Second operand 16 states. [2018-01-29 22:38:31,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:31,481 INFO L93 Difference]: Finished difference Result 394 states and 460 transitions. [2018-01-29 22:38:31,486 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-29 22:38:31,486 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 78 [2018-01-29 22:38:31,486 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:31,487 INFO L225 Difference]: With dead ends: 394 [2018-01-29 22:38:31,487 INFO L226 Difference]: Without dead ends: 210 [2018-01-29 22:38:31,487 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-29 22:38:31,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states. [2018-01-29 22:38:31,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 202. [2018-01-29 22:38:31,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202 states. [2018-01-29 22:38:31,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202 states to 202 states and 234 transitions. [2018-01-29 22:38:31,491 INFO L78 Accepts]: Start accepts. Automaton has 202 states and 234 transitions. Word has length 78 [2018-01-29 22:38:31,491 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:31,491 INFO L432 AbstractCegarLoop]: Abstraction has 202 states and 234 transitions. [2018-01-29 22:38:31,491 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-29 22:38:31,491 INFO L276 IsEmpty]: Start isEmpty. Operand 202 states and 234 transitions. [2018-01-29 22:38:31,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-01-29 22:38:31,492 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:31,492 INFO L350 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:31,492 INFO L371 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:31,492 INFO L82 PathProgramCache]: Analyzing trace with hash 145275714, now seen corresponding path program 14 times [2018-01-29 22:38:31,492 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:31,492 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:31,492 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:31,493 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:31,493 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:31,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:31,497 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:31,675 INFO L134 CoverageAnalysis]: Checked inductivity of 394 backedges. 2 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:31,676 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:31,676 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:31,681 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:38:31,688 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:31,692 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:31,693 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:31,694 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:31,705 INFO L134 CoverageAnalysis]: Checked inductivity of 394 backedges. 2 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:31,724 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:31,724 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 17 [2018-01-29 22:38:31,724 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-29 22:38:31,725 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-29 22:38:31,725 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2018-01-29 22:38:31,725 INFO L87 Difference]: Start difference. First operand 202 states and 234 transitions. Second operand 17 states. [2018-01-29 22:38:32,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:32,120 INFO L93 Difference]: Finished difference Result 418 states and 488 transitions. [2018-01-29 22:38:32,121 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-29 22:38:32,121 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 82 [2018-01-29 22:38:32,121 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:32,121 INFO L225 Difference]: With dead ends: 418 [2018-01-29 22:38:32,121 INFO L226 Difference]: Without dead ends: 222 [2018-01-29 22:38:32,122 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2018-01-29 22:38:32,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states. [2018-01-29 22:38:32,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 214. [2018-01-29 22:38:32,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-01-29 22:38:32,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 248 transitions. [2018-01-29 22:38:32,124 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 248 transitions. Word has length 82 [2018-01-29 22:38:32,125 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:32,125 INFO L432 AbstractCegarLoop]: Abstraction has 214 states and 248 transitions. [2018-01-29 22:38:32,125 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-29 22:38:32,125 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 248 transitions. [2018-01-29 22:38:32,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-01-29 22:38:32,125 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:32,125 INFO L350 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:32,125 INFO L371 AbstractCegarLoop]: === Iteration 18 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:32,125 INFO L82 PathProgramCache]: Analyzing trace with hash 725021418, now seen corresponding path program 15 times [2018-01-29 22:38:32,125 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:32,126 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:32,126 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:32,126 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:32,126 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:32,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:32,130 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:32,852 INFO L134 CoverageAnalysis]: Checked inductivity of 452 backedges. 2 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:32,852 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:32,852 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:32,857 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:38:32,864 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,865 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,872 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,887 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,893 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,903 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,910 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,920 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,930 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,943 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,946 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,946 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,947 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,948 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,949 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,950 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,951 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:32,952 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:32,953 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:32,962 INFO L134 CoverageAnalysis]: Checked inductivity of 452 backedges. 2 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:32,979 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:32,979 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2018-01-29 22:38:32,979 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-29 22:38:32,979 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-29 22:38:32,980 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-01-29 22:38:32,980 INFO L87 Difference]: Start difference. First operand 214 states and 248 transitions. Second operand 18 states. [2018-01-29 22:38:33,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:33,207 INFO L93 Difference]: Finished difference Result 442 states and 516 transitions. [2018-01-29 22:38:33,207 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-29 22:38:33,207 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 86 [2018-01-29 22:38:33,207 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:33,208 INFO L225 Difference]: With dead ends: 442 [2018-01-29 22:38:33,208 INFO L226 Difference]: Without dead ends: 234 [2018-01-29 22:38:33,208 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-01-29 22:38:33,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states. [2018-01-29 22:38:33,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 226. [2018-01-29 22:38:33,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-01-29 22:38:33,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 262 transitions. [2018-01-29 22:38:33,216 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 262 transitions. Word has length 86 [2018-01-29 22:38:33,216 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:33,216 INFO L432 AbstractCegarLoop]: Abstraction has 226 states and 262 transitions. [2018-01-29 22:38:33,216 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-29 22:38:33,216 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 262 transitions. [2018-01-29 22:38:33,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-01-29 22:38:33,220 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:33,220 INFO L350 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:33,220 INFO L371 AbstractCegarLoop]: === Iteration 19 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:33,220 INFO L82 PathProgramCache]: Analyzing trace with hash 1729173138, now seen corresponding path program 16 times [2018-01-29 22:38:33,220 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:33,220 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:33,221 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:33,221 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:33,221 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:33,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:33,232 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:33,387 INFO L134 CoverageAnalysis]: Checked inductivity of 514 backedges. 2 proven. 512 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:33,387 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:33,387 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:33,392 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:38:33,402 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:33,403 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:33,414 INFO L134 CoverageAnalysis]: Checked inductivity of 514 backedges. 2 proven. 512 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:33,431 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:33,431 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 19 [2018-01-29 22:38:33,432 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-29 22:38:33,432 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-29 22:38:33,432 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-01-29 22:38:33,432 INFO L87 Difference]: Start difference. First operand 226 states and 262 transitions. Second operand 19 states. [2018-01-29 22:38:33,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:33,581 INFO L93 Difference]: Finished difference Result 466 states and 544 transitions. [2018-01-29 22:38:33,582 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-29 22:38:33,582 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 90 [2018-01-29 22:38:33,583 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:33,583 INFO L225 Difference]: With dead ends: 466 [2018-01-29 22:38:33,583 INFO L226 Difference]: Without dead ends: 246 [2018-01-29 22:38:33,584 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-01-29 22:38:33,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-01-29 22:38:33,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 238. [2018-01-29 22:38:33,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-01-29 22:38:33,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 276 transitions. [2018-01-29 22:38:33,587 INFO L78 Accepts]: Start accepts. Automaton has 238 states and 276 transitions. Word has length 90 [2018-01-29 22:38:33,587 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:33,588 INFO L432 AbstractCegarLoop]: Abstraction has 238 states and 276 transitions. [2018-01-29 22:38:33,588 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-29 22:38:33,588 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 276 transitions. [2018-01-29 22:38:33,588 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-01-29 22:38:33,588 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:33,588 INFO L350 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:33,588 INFO L371 AbstractCegarLoop]: === Iteration 20 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:33,588 INFO L82 PathProgramCache]: Analyzing trace with hash 476128826, now seen corresponding path program 17 times [2018-01-29 22:38:33,589 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:33,589 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:33,589 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:33,589 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:33,589 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:33,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:33,593 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:33,728 INFO L134 CoverageAnalysis]: Checked inductivity of 580 backedges. 2 proven. 578 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:33,728 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:33,728 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:33,733 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:38:33,735 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,735 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,736 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,737 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,737 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,738 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,739 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,740 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,740 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,741 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,742 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,743 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,744 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,757 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,767 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,777 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,787 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,793 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:33,796 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:33,798 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:33,806 INFO L134 CoverageAnalysis]: Checked inductivity of 580 backedges. 2 proven. 578 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:33,822 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:33,823 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 20 [2018-01-29 22:38:33,823 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-29 22:38:33,823 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-29 22:38:33,823 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-29 22:38:33,823 INFO L87 Difference]: Start difference. First operand 238 states and 276 transitions. Second operand 20 states. [2018-01-29 22:38:33,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:33,955 INFO L93 Difference]: Finished difference Result 490 states and 572 transitions. [2018-01-29 22:38:33,955 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-29 22:38:33,955 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 94 [2018-01-29 22:38:33,955 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:33,956 INFO L225 Difference]: With dead ends: 490 [2018-01-29 22:38:33,956 INFO L226 Difference]: Without dead ends: 258 [2018-01-29 22:38:33,956 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 95 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-29 22:38:33,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 258 states. [2018-01-29 22:38:33,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 258 to 250. [2018-01-29 22:38:33,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-01-29 22:38:33,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 290 transitions. [2018-01-29 22:38:33,959 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 290 transitions. Word has length 94 [2018-01-29 22:38:33,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:33,960 INFO L432 AbstractCegarLoop]: Abstraction has 250 states and 290 transitions. [2018-01-29 22:38:33,960 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-29 22:38:33,960 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 290 transitions. [2018-01-29 22:38:33,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-01-29 22:38:33,960 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:33,960 INFO L350 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:33,960 INFO L371 AbstractCegarLoop]: === Iteration 21 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:33,960 INFO L82 PathProgramCache]: Analyzing trace with hash -2041503262, now seen corresponding path program 18 times [2018-01-29 22:38:33,961 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:33,961 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:33,961 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:33,961 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:33,961 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:33,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:33,966 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:34,391 INFO L134 CoverageAnalysis]: Checked inductivity of 650 backedges. 2 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:34,391 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:34,391 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:34,396 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:38:34,399 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,400 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,400 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,401 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,402 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,402 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,403 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,404 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,405 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,406 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,406 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,407 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,408 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,409 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,410 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,411 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,412 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,419 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,428 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,437 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:34,438 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:34,439 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:34,447 INFO L134 CoverageAnalysis]: Checked inductivity of 650 backedges. 2 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:34,464 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:34,464 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 21 [2018-01-29 22:38:34,464 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-29 22:38:34,464 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-29 22:38:34,464 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2018-01-29 22:38:34,465 INFO L87 Difference]: Start difference. First operand 250 states and 290 transitions. Second operand 21 states. [2018-01-29 22:38:34,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:34,602 INFO L93 Difference]: Finished difference Result 514 states and 600 transitions. [2018-01-29 22:38:34,616 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-29 22:38:34,617 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 98 [2018-01-29 22:38:34,617 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:34,617 INFO L225 Difference]: With dead ends: 514 [2018-01-29 22:38:34,617 INFO L226 Difference]: Without dead ends: 270 [2018-01-29 22:38:34,618 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 99 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2018-01-29 22:38:34,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states. [2018-01-29 22:38:34,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 262. [2018-01-29 22:38:34,620 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 262 states. [2018-01-29 22:38:34,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 304 transitions. [2018-01-29 22:38:34,621 INFO L78 Accepts]: Start accepts. Automaton has 262 states and 304 transitions. Word has length 98 [2018-01-29 22:38:34,621 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:34,621 INFO L432 AbstractCegarLoop]: Abstraction has 262 states and 304 transitions. [2018-01-29 22:38:34,621 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-29 22:38:34,621 INFO L276 IsEmpty]: Start isEmpty. Operand 262 states and 304 transitions. [2018-01-29 22:38:34,621 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-01-29 22:38:34,621 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:34,621 INFO L350 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:34,621 INFO L371 AbstractCegarLoop]: === Iteration 22 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:34,622 INFO L82 PathProgramCache]: Analyzing trace with hash 990579082, now seen corresponding path program 19 times [2018-01-29 22:38:34,622 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:34,622 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:34,622 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:34,622 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:34,622 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:34,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:34,627 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:35,144 INFO L134 CoverageAnalysis]: Checked inductivity of 724 backedges. 2 proven. 722 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:35,144 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:35,144 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:35,149 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:35,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:35,159 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:35,170 INFO L134 CoverageAnalysis]: Checked inductivity of 724 backedges. 2 proven. 722 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:35,189 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:35,189 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 22 [2018-01-29 22:38:35,189 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-29 22:38:35,190 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-29 22:38:35,190 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-29 22:38:35,190 INFO L87 Difference]: Start difference. First operand 262 states and 304 transitions. Second operand 22 states. [2018-01-29 22:38:35,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:35,311 INFO L93 Difference]: Finished difference Result 538 states and 628 transitions. [2018-01-29 22:38:35,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-29 22:38:35,312 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 102 [2018-01-29 22:38:35,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:35,313 INFO L225 Difference]: With dead ends: 538 [2018-01-29 22:38:35,313 INFO L226 Difference]: Without dead ends: 282 [2018-01-29 22:38:35,314 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 103 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-29 22:38:35,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2018-01-29 22:38:35,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 274. [2018-01-29 22:38:35,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 274 states. [2018-01-29 22:38:35,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 274 states to 274 states and 318 transitions. [2018-01-29 22:38:35,317 INFO L78 Accepts]: Start accepts. Automaton has 274 states and 318 transitions. Word has length 102 [2018-01-29 22:38:35,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:35,317 INFO L432 AbstractCegarLoop]: Abstraction has 274 states and 318 transitions. [2018-01-29 22:38:35,317 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-29 22:38:35,317 INFO L276 IsEmpty]: Start isEmpty. Operand 274 states and 318 transitions. [2018-01-29 22:38:35,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-01-29 22:38:35,318 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:35,318 INFO L350 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:35,318 INFO L371 AbstractCegarLoop]: === Iteration 23 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:35,318 INFO L82 PathProgramCache]: Analyzing trace with hash -1413948110, now seen corresponding path program 20 times [2018-01-29 22:38:35,318 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:35,318 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:35,319 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:35,319 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:35,319 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:35,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:35,324 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:35,537 INFO L134 CoverageAnalysis]: Checked inductivity of 802 backedges. 2 proven. 800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:35,537 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:35,537 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:35,547 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:38:35,551 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:35,555 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:35,557 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:35,558 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:35,570 INFO L134 CoverageAnalysis]: Checked inductivity of 802 backedges. 2 proven. 800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:35,586 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:35,586 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 23 [2018-01-29 22:38:35,587 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-29 22:38:35,587 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-29 22:38:35,587 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2018-01-29 22:38:35,587 INFO L87 Difference]: Start difference. First operand 274 states and 318 transitions. Second operand 23 states. [2018-01-29 22:38:35,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:35,705 INFO L93 Difference]: Finished difference Result 562 states and 656 transitions. [2018-01-29 22:38:35,705 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-29 22:38:35,706 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 106 [2018-01-29 22:38:35,706 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:35,706 INFO L225 Difference]: With dead ends: 562 [2018-01-29 22:38:35,706 INFO L226 Difference]: Without dead ends: 294 [2018-01-29 22:38:35,707 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 128 GetRequests, 107 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2018-01-29 22:38:35,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 294 states. [2018-01-29 22:38:35,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 294 to 286. [2018-01-29 22:38:35,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 286 states. [2018-01-29 22:38:35,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 286 states to 286 states and 332 transitions. [2018-01-29 22:38:35,711 INFO L78 Accepts]: Start accepts. Automaton has 286 states and 332 transitions. Word has length 106 [2018-01-29 22:38:35,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:35,711 INFO L432 AbstractCegarLoop]: Abstraction has 286 states and 332 transitions. [2018-01-29 22:38:35,711 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-29 22:38:35,711 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 332 transitions. [2018-01-29 22:38:35,711 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-01-29 22:38:35,711 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:35,712 INFO L350 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:35,712 INFO L371 AbstractCegarLoop]: === Iteration 24 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:35,712 INFO L82 PathProgramCache]: Analyzing trace with hash -1534812966, now seen corresponding path program 21 times [2018-01-29 22:38:35,712 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:35,712 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:35,712 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:35,712 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:35,712 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:35,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:35,717 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:36,128 INFO L134 CoverageAnalysis]: Checked inductivity of 884 backedges. 2 proven. 882 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:36,128 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:36,128 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:36,134 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:38:36,137 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,138 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,139 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,140 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,140 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,141 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,142 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,142 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,143 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,144 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,145 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,146 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,147 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,148 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,148 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,149 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,150 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,151 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,152 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,154 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,155 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,156 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,157 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:36,157 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:36,158 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:36,168 INFO L134 CoverageAnalysis]: Checked inductivity of 884 backedges. 2 proven. 882 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:36,185 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:36,185 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 24 [2018-01-29 22:38:36,185 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-29 22:38:36,185 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-29 22:38:36,185 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-01-29 22:38:36,186 INFO L87 Difference]: Start difference. First operand 286 states and 332 transitions. Second operand 24 states. [2018-01-29 22:38:36,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:36,301 INFO L93 Difference]: Finished difference Result 586 states and 684 transitions. [2018-01-29 22:38:36,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-29 22:38:36,301 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 110 [2018-01-29 22:38:36,301 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:36,302 INFO L225 Difference]: With dead ends: 586 [2018-01-29 22:38:36,302 INFO L226 Difference]: Without dead ends: 306 [2018-01-29 22:38:36,302 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 111 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-01-29 22:38:36,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306 states. [2018-01-29 22:38:36,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306 to 298. [2018-01-29 22:38:36,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 298 states. [2018-01-29 22:38:36,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 346 transitions. [2018-01-29 22:38:36,306 INFO L78 Accepts]: Start accepts. Automaton has 298 states and 346 transitions. Word has length 110 [2018-01-29 22:38:36,306 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:36,306 INFO L432 AbstractCegarLoop]: Abstraction has 298 states and 346 transitions. [2018-01-29 22:38:36,306 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-29 22:38:36,306 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 346 transitions. [2018-01-29 22:38:36,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-01-29 22:38:36,306 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:36,307 INFO L350 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:36,307 INFO L371 AbstractCegarLoop]: === Iteration 25 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:36,307 INFO L82 PathProgramCache]: Analyzing trace with hash -862435198, now seen corresponding path program 22 times [2018-01-29 22:38:36,307 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:36,307 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:36,307 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:36,307 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:36,308 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:36,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:36,313 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:36,763 INFO L134 CoverageAnalysis]: Checked inductivity of 970 backedges. 2 proven. 968 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:36,763 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:36,764 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:36,769 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:38:36,780 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:36,781 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:36,792 INFO L134 CoverageAnalysis]: Checked inductivity of 970 backedges. 2 proven. 968 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:36,809 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:36,809 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 25 [2018-01-29 22:38:36,809 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-29 22:38:36,809 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-29 22:38:36,809 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-01-29 22:38:36,809 INFO L87 Difference]: Start difference. First operand 298 states and 346 transitions. Second operand 25 states. [2018-01-29 22:38:36,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:36,966 INFO L93 Difference]: Finished difference Result 610 states and 712 transitions. [2018-01-29 22:38:36,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-29 22:38:36,971 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 114 [2018-01-29 22:38:36,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:36,972 INFO L225 Difference]: With dead ends: 610 [2018-01-29 22:38:36,972 INFO L226 Difference]: Without dead ends: 318 [2018-01-29 22:38:36,973 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 138 GetRequests, 115 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-01-29 22:38:36,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 318 states. [2018-01-29 22:38:36,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 318 to 310. [2018-01-29 22:38:36,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 310 states. [2018-01-29 22:38:36,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 310 states to 310 states and 360 transitions. [2018-01-29 22:38:36,986 INFO L78 Accepts]: Start accepts. Automaton has 310 states and 360 transitions. Word has length 114 [2018-01-29 22:38:36,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:36,986 INFO L432 AbstractCegarLoop]: Abstraction has 310 states and 360 transitions. [2018-01-29 22:38:36,986 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-29 22:38:36,987 INFO L276 IsEmpty]: Start isEmpty. Operand 310 states and 360 transitions. [2018-01-29 22:38:36,987 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-01-29 22:38:36,987 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:36,987 INFO L350 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:36,987 INFO L371 AbstractCegarLoop]: === Iteration 26 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:36,987 INFO L82 PathProgramCache]: Analyzing trace with hash 639492138, now seen corresponding path program 23 times [2018-01-29 22:38:36,987 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:36,987 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:36,988 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:36,988 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:36,988 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:36,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:36,992 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:37,223 INFO L134 CoverageAnalysis]: Checked inductivity of 1060 backedges. 2 proven. 1058 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:37,223 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:37,223 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:37,227 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:38:37,230 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,230 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,237 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,238 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,239 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,239 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,240 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,241 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,242 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,243 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,244 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,245 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,246 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,250 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,251 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,252 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,253 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,254 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,255 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,256 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,257 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,258 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,259 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,260 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:37,261 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:37,262 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:37,272 INFO L134 CoverageAnalysis]: Checked inductivity of 1060 backedges. 2 proven. 1058 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:37,288 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:37,289 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 26 [2018-01-29 22:38:37,289 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-29 22:38:37,289 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-29 22:38:37,289 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-29 22:38:37,289 INFO L87 Difference]: Start difference. First operand 310 states and 360 transitions. Second operand 26 states. [2018-01-29 22:38:37,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:37,403 INFO L93 Difference]: Finished difference Result 634 states and 740 transitions. [2018-01-29 22:38:37,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-29 22:38:37,403 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 118 [2018-01-29 22:38:37,403 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:37,404 INFO L225 Difference]: With dead ends: 634 [2018-01-29 22:38:37,404 INFO L226 Difference]: Without dead ends: 330 [2018-01-29 22:38:37,405 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 143 GetRequests, 119 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-29 22:38:37,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330 states. [2018-01-29 22:38:37,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330 to 322. [2018-01-29 22:38:37,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 322 states. [2018-01-29 22:38:37,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 374 transitions. [2018-01-29 22:38:37,407 INFO L78 Accepts]: Start accepts. Automaton has 322 states and 374 transitions. Word has length 118 [2018-01-29 22:38:37,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:37,408 INFO L432 AbstractCegarLoop]: Abstraction has 322 states and 374 transitions. [2018-01-29 22:38:37,408 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-29 22:38:37,408 INFO L276 IsEmpty]: Start isEmpty. Operand 322 states and 374 transitions. [2018-01-29 22:38:37,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-29 22:38:37,408 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:37,408 INFO L350 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:37,408 INFO L371 AbstractCegarLoop]: === Iteration 27 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:37,408 INFO L82 PathProgramCache]: Analyzing trace with hash -1908448302, now seen corresponding path program 24 times [2018-01-29 22:38:37,408 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:37,409 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:37,409 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:37,409 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:37,409 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:37,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:37,414 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:37,724 INFO L134 CoverageAnalysis]: Checked inductivity of 1154 backedges. 2 proven. 1152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:37,724 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:37,724 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:37,729 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:38:37,733 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,734 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,735 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,735 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,736 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,737 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,738 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,738 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,739 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,740 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,741 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,742 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,743 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,744 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,745 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,746 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,747 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,749 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,750 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,751 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,752 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,754 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,755 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,756 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,758 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,759 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:37,759 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:37,761 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:37,772 INFO L134 CoverageAnalysis]: Checked inductivity of 1154 backedges. 2 proven. 1152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:37,792 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:37,792 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 27 [2018-01-29 22:38:37,792 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-29 22:38:37,792 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-29 22:38:37,792 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2018-01-29 22:38:37,792 INFO L87 Difference]: Start difference. First operand 322 states and 374 transitions. Second operand 27 states. [2018-01-29 22:38:37,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:37,916 INFO L93 Difference]: Finished difference Result 658 states and 768 transitions. [2018-01-29 22:38:37,916 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-29 22:38:37,916 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 122 [2018-01-29 22:38:37,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:37,917 INFO L225 Difference]: With dead ends: 658 [2018-01-29 22:38:37,920 INFO L226 Difference]: Without dead ends: 342 [2018-01-29 22:38:37,920 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 123 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2018-01-29 22:38:37,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states. [2018-01-29 22:38:37,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 334. [2018-01-29 22:38:37,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 334 states. [2018-01-29 22:38:37,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 334 states to 334 states and 388 transitions. [2018-01-29 22:38:37,924 INFO L78 Accepts]: Start accepts. Automaton has 334 states and 388 transitions. Word has length 122 [2018-01-29 22:38:37,924 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:37,924 INFO L432 AbstractCegarLoop]: Abstraction has 334 states and 388 transitions. [2018-01-29 22:38:37,924 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-29 22:38:37,924 INFO L276 IsEmpty]: Start isEmpty. Operand 334 states and 388 transitions. [2018-01-29 22:38:37,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-01-29 22:38:37,925 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:37,925 INFO L350 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:37,925 INFO L371 AbstractCegarLoop]: === Iteration 28 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:37,925 INFO L82 PathProgramCache]: Analyzing trace with hash 1025954682, now seen corresponding path program 25 times [2018-01-29 22:38:37,925 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:37,925 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:37,926 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:37,926 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:37,926 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:37,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:37,932 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:38,217 INFO L134 CoverageAnalysis]: Checked inductivity of 1252 backedges. 2 proven. 1250 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:38,217 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:38,217 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:38,222 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:38,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:38,233 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:38,244 INFO L134 CoverageAnalysis]: Checked inductivity of 1252 backedges. 2 proven. 1250 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:38,261 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:38,261 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 28 [2018-01-29 22:38:38,261 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-29 22:38:38,261 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-29 22:38:38,261 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-29 22:38:38,262 INFO L87 Difference]: Start difference. First operand 334 states and 388 transitions. Second operand 28 states. [2018-01-29 22:38:38,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:38,380 INFO L93 Difference]: Finished difference Result 682 states and 796 transitions. [2018-01-29 22:38:38,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-29 22:38:38,382 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 126 [2018-01-29 22:38:38,382 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:38,383 INFO L225 Difference]: With dead ends: 682 [2018-01-29 22:38:38,383 INFO L226 Difference]: Without dead ends: 354 [2018-01-29 22:38:38,383 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 153 GetRequests, 127 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-29 22:38:38,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354 states. [2018-01-29 22:38:38,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354 to 346. [2018-01-29 22:38:38,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 346 states. [2018-01-29 22:38:38,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 346 states to 346 states and 402 transitions. [2018-01-29 22:38:38,387 INFO L78 Accepts]: Start accepts. Automaton has 346 states and 402 transitions. Word has length 126 [2018-01-29 22:38:38,387 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:38,387 INFO L432 AbstractCegarLoop]: Abstraction has 346 states and 402 transitions. [2018-01-29 22:38:38,387 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-29 22:38:38,387 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 402 transitions. [2018-01-29 22:38:38,387 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-01-29 22:38:38,388 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:38,388 INFO L350 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:38,388 INFO L371 AbstractCegarLoop]: === Iteration 29 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:38,388 INFO L82 PathProgramCache]: Analyzing trace with hash 1174286114, now seen corresponding path program 26 times [2018-01-29 22:38:38,388 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:38,388 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:38,388 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:38,388 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:38,388 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:38,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:38,393 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:38,757 INFO L134 CoverageAnalysis]: Checked inductivity of 1354 backedges. 2 proven. 1352 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:38,757 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:38,757 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:38,762 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:38:38,767 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:38,774 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:38,775 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:38,777 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:38,788 INFO L134 CoverageAnalysis]: Checked inductivity of 1354 backedges. 2 proven. 1352 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:38,805 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:38,805 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 29 [2018-01-29 22:38:38,805 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-29 22:38:38,805 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-29 22:38:38,806 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2018-01-29 22:38:38,806 INFO L87 Difference]: Start difference. First operand 346 states and 402 transitions. Second operand 29 states. [2018-01-29 22:38:38,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:38,932 INFO L93 Difference]: Finished difference Result 706 states and 824 transitions. [2018-01-29 22:38:38,932 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-29 22:38:38,932 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 130 [2018-01-29 22:38:38,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:38,933 INFO L225 Difference]: With dead ends: 706 [2018-01-29 22:38:38,933 INFO L226 Difference]: Without dead ends: 366 [2018-01-29 22:38:38,934 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 131 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2018-01-29 22:38:38,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states. [2018-01-29 22:38:38,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 358. [2018-01-29 22:38:38,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 358 states. [2018-01-29 22:38:38,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 358 states to 358 states and 416 transitions. [2018-01-29 22:38:38,937 INFO L78 Accepts]: Start accepts. Automaton has 358 states and 416 transitions. Word has length 130 [2018-01-29 22:38:38,937 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:38,937 INFO L432 AbstractCegarLoop]: Abstraction has 358 states and 416 transitions. [2018-01-29 22:38:38,937 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-29 22:38:38,937 INFO L276 IsEmpty]: Start isEmpty. Operand 358 states and 416 transitions. [2018-01-29 22:38:38,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-01-29 22:38:38,938 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:38,938 INFO L350 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:38,938 INFO L371 AbstractCegarLoop]: === Iteration 30 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:38,938 INFO L82 PathProgramCache]: Analyzing trace with hash 384792266, now seen corresponding path program 27 times [2018-01-29 22:38:38,938 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:38,938 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:38,939 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:38,939 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:38,939 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:38,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:38,943 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:39,598 INFO L134 CoverageAnalysis]: Checked inductivity of 1460 backedges. 2 proven. 1458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:39,599 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:39,599 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:39,605 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:38:39,609 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,610 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,610 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,611 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,612 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,612 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,613 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,614 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,615 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,615 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,616 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,617 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,618 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,619 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,620 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,621 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,626 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,627 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,628 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,629 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,630 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,631 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,633 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,634 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,635 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,637 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,638 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,640 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,641 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:39,641 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:39,643 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:39,660 INFO L134 CoverageAnalysis]: Checked inductivity of 1460 backedges. 2 proven. 1458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:39,677 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:39,677 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 30 [2018-01-29 22:38:39,678 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-29 22:38:39,678 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-29 22:38:39,678 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-01-29 22:38:39,678 INFO L87 Difference]: Start difference. First operand 358 states and 416 transitions. Second operand 30 states. [2018-01-29 22:38:39,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:39,840 INFO L93 Difference]: Finished difference Result 730 states and 852 transitions. [2018-01-29 22:38:39,840 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-29 22:38:39,840 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 134 [2018-01-29 22:38:39,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:39,841 INFO L225 Difference]: With dead ends: 730 [2018-01-29 22:38:39,841 INFO L226 Difference]: Without dead ends: 378 [2018-01-29 22:38:39,842 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 135 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-01-29 22:38:39,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 378 states. [2018-01-29 22:38:39,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 378 to 370. [2018-01-29 22:38:39,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 370 states. [2018-01-29 22:38:39,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 370 states to 370 states and 430 transitions. [2018-01-29 22:38:39,845 INFO L78 Accepts]: Start accepts. Automaton has 370 states and 430 transitions. Word has length 134 [2018-01-29 22:38:39,845 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:39,845 INFO L432 AbstractCegarLoop]: Abstraction has 370 states and 430 transitions. [2018-01-29 22:38:39,845 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-29 22:38:39,845 INFO L276 IsEmpty]: Start isEmpty. Operand 370 states and 430 transitions. [2018-01-29 22:38:39,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-01-29 22:38:39,846 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:39,846 INFO L350 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:39,846 INFO L371 AbstractCegarLoop]: === Iteration 31 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:39,846 INFO L82 PathProgramCache]: Analyzing trace with hash -115037582, now seen corresponding path program 28 times [2018-01-29 22:38:39,846 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:39,846 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:39,847 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:39,847 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:39,847 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:39,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:39,853 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:40,372 INFO L134 CoverageAnalysis]: Checked inductivity of 1570 backedges. 2 proven. 1568 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:40,372 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:40,372 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:40,377 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:38:40,392 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:40,394 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:40,409 INFO L134 CoverageAnalysis]: Checked inductivity of 1570 backedges. 2 proven. 1568 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:40,425 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:40,426 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 31 [2018-01-29 22:38:40,426 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-01-29 22:38:40,426 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-01-29 22:38:40,426 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2018-01-29 22:38:40,426 INFO L87 Difference]: Start difference. First operand 370 states and 430 transitions. Second operand 31 states. [2018-01-29 22:38:40,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:40,560 INFO L93 Difference]: Finished difference Result 754 states and 880 transitions. [2018-01-29 22:38:40,561 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-29 22:38:40,561 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 138 [2018-01-29 22:38:40,561 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:40,562 INFO L225 Difference]: With dead ends: 754 [2018-01-29 22:38:40,562 INFO L226 Difference]: Without dead ends: 390 [2018-01-29 22:38:40,562 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 168 GetRequests, 139 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2018-01-29 22:38:40,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 390 states. [2018-01-29 22:38:40,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 390 to 382. [2018-01-29 22:38:40,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2018-01-29 22:38:40,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 444 transitions. [2018-01-29 22:38:40,565 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 444 transitions. Word has length 138 [2018-01-29 22:38:40,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:40,566 INFO L432 AbstractCegarLoop]: Abstraction has 382 states and 444 transitions. [2018-01-29 22:38:40,566 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-01-29 22:38:40,566 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 444 transitions. [2018-01-29 22:38:40,566 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-01-29 22:38:40,566 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:40,567 INFO L350 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:40,567 INFO L371 AbstractCegarLoop]: === Iteration 32 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:40,567 INFO L82 PathProgramCache]: Analyzing trace with hash -1865954790, now seen corresponding path program 29 times [2018-01-29 22:38:40,567 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:40,567 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:40,567 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:40,567 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:40,567 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:40,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:40,572 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:40,893 INFO L134 CoverageAnalysis]: Checked inductivity of 1684 backedges. 2 proven. 1682 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:40,893 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:40,893 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:40,897 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:38:40,904 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,910 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,911 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,911 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,912 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,912 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,913 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,914 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,915 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,916 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,916 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,917 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,918 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,919 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,920 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,921 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,923 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,924 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,925 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,926 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,928 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,930 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,931 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,933 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,934 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,936 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,937 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,939 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,941 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,942 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:40,943 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:40,944 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:40,959 INFO L134 CoverageAnalysis]: Checked inductivity of 1684 backedges. 2 proven. 1682 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:40,975 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:40,975 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 32 [2018-01-29 22:38:40,975 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-01-29 22:38:40,976 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-01-29 22:38:40,976 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-29 22:38:40,976 INFO L87 Difference]: Start difference. First operand 382 states and 444 transitions. Second operand 32 states. [2018-01-29 22:38:41,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:41,160 INFO L93 Difference]: Finished difference Result 778 states and 908 transitions. [2018-01-29 22:38:41,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-01-29 22:38:41,160 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 142 [2018-01-29 22:38:41,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:41,161 INFO L225 Difference]: With dead ends: 778 [2018-01-29 22:38:41,161 INFO L226 Difference]: Without dead ends: 402 [2018-01-29 22:38:41,161 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 173 GetRequests, 143 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-29 22:38:41,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 402 states. [2018-01-29 22:38:41,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 402 to 394. [2018-01-29 22:38:41,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 394 states. [2018-01-29 22:38:41,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 394 states to 394 states and 458 transitions. [2018-01-29 22:38:41,166 INFO L78 Accepts]: Start accepts. Automaton has 394 states and 458 transitions. Word has length 142 [2018-01-29 22:38:41,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:41,166 INFO L432 AbstractCegarLoop]: Abstraction has 394 states and 458 transitions. [2018-01-29 22:38:41,166 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-01-29 22:38:41,166 INFO L276 IsEmpty]: Start isEmpty. Operand 394 states and 458 transitions. [2018-01-29 22:38:41,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-01-29 22:38:41,167 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:41,167 INFO L350 BasicCegarLoop]: trace histogram [31, 30, 30, 30, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:41,167 INFO L371 AbstractCegarLoop]: === Iteration 33 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:41,167 INFO L82 PathProgramCache]: Analyzing trace with hash 1560466882, now seen corresponding path program 30 times [2018-01-29 22:38:41,167 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:41,167 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:41,168 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:41,168 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:41,168 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:41,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:41,174 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:41,513 INFO L134 CoverageAnalysis]: Checked inductivity of 1802 backedges. 2 proven. 1800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:41,513 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:41,514 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:41,518 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:38:41,522 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,523 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,523 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,524 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,525 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,525 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,526 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,527 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,528 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,529 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,529 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,530 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,531 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,532 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,537 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,538 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,539 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,540 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,541 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,542 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,543 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,544 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,545 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,546 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,547 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,548 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,550 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,551 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,552 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,553 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,555 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,556 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:41,556 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:41,558 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:41,572 INFO L134 CoverageAnalysis]: Checked inductivity of 1802 backedges. 2 proven. 1800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:41,588 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:41,588 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 33 [2018-01-29 22:38:41,589 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-29 22:38:41,589 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-29 22:38:41,589 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-01-29 22:38:41,589 INFO L87 Difference]: Start difference. First operand 394 states and 458 transitions. Second operand 33 states. [2018-01-29 22:38:41,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:41,875 INFO L93 Difference]: Finished difference Result 802 states and 936 transitions. [2018-01-29 22:38:41,878 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-01-29 22:38:41,878 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 146 [2018-01-29 22:38:41,878 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:41,879 INFO L225 Difference]: With dead ends: 802 [2018-01-29 22:38:41,879 INFO L226 Difference]: Without dead ends: 414 [2018-01-29 22:38:41,879 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 178 GetRequests, 147 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-01-29 22:38:41,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 414 states. [2018-01-29 22:38:41,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 414 to 406. [2018-01-29 22:38:41,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 406 states. [2018-01-29 22:38:41,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 406 states to 406 states and 472 transitions. [2018-01-29 22:38:41,883 INFO L78 Accepts]: Start accepts. Automaton has 406 states and 472 transitions. Word has length 146 [2018-01-29 22:38:41,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:41,883 INFO L432 AbstractCegarLoop]: Abstraction has 406 states and 472 transitions. [2018-01-29 22:38:41,883 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-29 22:38:41,883 INFO L276 IsEmpty]: Start isEmpty. Operand 406 states and 472 transitions. [2018-01-29 22:38:41,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-01-29 22:38:41,884 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:41,884 INFO L350 BasicCegarLoop]: trace histogram [32, 31, 31, 31, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:41,884 INFO L371 AbstractCegarLoop]: === Iteration 34 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:41,884 INFO L82 PathProgramCache]: Analyzing trace with hash 939511146, now seen corresponding path program 31 times [2018-01-29 22:38:41,884 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:41,884 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:41,885 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:41,885 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:41,885 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:41,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:41,889 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:42,205 INFO L134 CoverageAnalysis]: Checked inductivity of 1924 backedges. 2 proven. 1922 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:42,205 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:42,205 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:42,209 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:42,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:42,223 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:42,248 INFO L134 CoverageAnalysis]: Checked inductivity of 1924 backedges. 2 proven. 1922 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:42,271 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:42,271 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 34 [2018-01-29 22:38:42,271 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-01-29 22:38:42,271 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-01-29 22:38:42,272 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-29 22:38:42,272 INFO L87 Difference]: Start difference. First operand 406 states and 472 transitions. Second operand 34 states. [2018-01-29 22:38:42,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:42,459 INFO L93 Difference]: Finished difference Result 826 states and 964 transitions. [2018-01-29 22:38:42,460 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-01-29 22:38:42,460 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 150 [2018-01-29 22:38:42,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:42,461 INFO L225 Difference]: With dead ends: 826 [2018-01-29 22:38:42,461 INFO L226 Difference]: Without dead ends: 426 [2018-01-29 22:38:42,461 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 151 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-29 22:38:42,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 426 states. [2018-01-29 22:38:42,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 426 to 418. [2018-01-29 22:38:42,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 418 states. [2018-01-29 22:38:42,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 418 states to 418 states and 486 transitions. [2018-01-29 22:38:42,465 INFO L78 Accepts]: Start accepts. Automaton has 418 states and 486 transitions. Word has length 150 [2018-01-29 22:38:42,465 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:42,465 INFO L432 AbstractCegarLoop]: Abstraction has 418 states and 486 transitions. [2018-01-29 22:38:42,465 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-01-29 22:38:42,465 INFO L276 IsEmpty]: Start isEmpty. Operand 418 states and 486 transitions. [2018-01-29 22:38:42,466 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2018-01-29 22:38:42,466 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:42,466 INFO L350 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:42,466 INFO L371 AbstractCegarLoop]: === Iteration 35 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:42,466 INFO L82 PathProgramCache]: Analyzing trace with hash -689393390, now seen corresponding path program 32 times [2018-01-29 22:38:42,466 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:42,466 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:42,467 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:42,467 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:42,467 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:42,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:42,472 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:42,839 INFO L134 CoverageAnalysis]: Checked inductivity of 2050 backedges. 2 proven. 2048 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:42,839 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:42,839 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:42,843 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:38:42,847 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:42,856 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:42,858 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:42,859 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:42,877 INFO L134 CoverageAnalysis]: Checked inductivity of 2050 backedges. 2 proven. 2048 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:42,894 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:42,894 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 35 [2018-01-29 22:38:42,894 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-01-29 22:38:42,894 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-01-29 22:38:42,895 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2018-01-29 22:38:42,895 INFO L87 Difference]: Start difference. First operand 418 states and 486 transitions. Second operand 35 states. [2018-01-29 22:38:43,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:43,130 INFO L93 Difference]: Finished difference Result 850 states and 992 transitions. [2018-01-29 22:38:43,140 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-01-29 22:38:43,140 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 154 [2018-01-29 22:38:43,140 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:43,141 INFO L225 Difference]: With dead ends: 850 [2018-01-29 22:38:43,141 INFO L226 Difference]: Without dead ends: 438 [2018-01-29 22:38:43,141 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 188 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2018-01-29 22:38:43,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 438 states. [2018-01-29 22:38:43,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 438 to 430. [2018-01-29 22:38:43,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 430 states. [2018-01-29 22:38:43,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 500 transitions. [2018-01-29 22:38:43,145 INFO L78 Accepts]: Start accepts. Automaton has 430 states and 500 transitions. Word has length 154 [2018-01-29 22:38:43,145 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:43,145 INFO L432 AbstractCegarLoop]: Abstraction has 430 states and 500 transitions. [2018-01-29 22:38:43,145 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-01-29 22:38:43,145 INFO L276 IsEmpty]: Start isEmpty. Operand 430 states and 500 transitions. [2018-01-29 22:38:43,146 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-01-29 22:38:43,146 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:43,146 INFO L350 BasicCegarLoop]: trace histogram [34, 33, 33, 33, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:43,146 INFO L371 AbstractCegarLoop]: === Iteration 36 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:43,146 INFO L82 PathProgramCache]: Analyzing trace with hash 1239908538, now seen corresponding path program 33 times [2018-01-29 22:38:43,146 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:43,146 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:43,147 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:43,147 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:43,147 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:43,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:43,152 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:43,549 INFO L134 CoverageAnalysis]: Checked inductivity of 2180 backedges. 2 proven. 2178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:43,549 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:43,549 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:43,562 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:38:43,571 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,578 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,587 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,597 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,597 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,598 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,599 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,600 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,600 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,601 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,602 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,603 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,604 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,605 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,606 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,607 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,608 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,609 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,610 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,611 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,612 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,613 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,614 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,615 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,616 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,617 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,618 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,620 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,621 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,622 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,624 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,625 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,627 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,628 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,630 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:43,630 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:43,632 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:43,647 INFO L134 CoverageAnalysis]: Checked inductivity of 2180 backedges. 2 proven. 2178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:43,664 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:43,664 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 36 [2018-01-29 22:38:43,664 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-01-29 22:38:43,664 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-01-29 22:38:43,665 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-01-29 22:38:43,665 INFO L87 Difference]: Start difference. First operand 430 states and 500 transitions. Second operand 36 states. [2018-01-29 22:38:43,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:43,843 INFO L93 Difference]: Finished difference Result 874 states and 1020 transitions. [2018-01-29 22:38:43,846 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-01-29 22:38:43,846 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 158 [2018-01-29 22:38:43,847 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:43,847 INFO L225 Difference]: With dead ends: 874 [2018-01-29 22:38:43,847 INFO L226 Difference]: Without dead ends: 450 [2018-01-29 22:38:43,848 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 193 GetRequests, 159 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-01-29 22:38:43,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 450 states. [2018-01-29 22:38:43,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 450 to 442. [2018-01-29 22:38:43,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 442 states. [2018-01-29 22:38:43,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 442 states to 442 states and 514 transitions. [2018-01-29 22:38:43,852 INFO L78 Accepts]: Start accepts. Automaton has 442 states and 514 transitions. Word has length 158 [2018-01-29 22:38:43,852 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:43,852 INFO L432 AbstractCegarLoop]: Abstraction has 442 states and 514 transitions. [2018-01-29 22:38:43,852 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-01-29 22:38:43,852 INFO L276 IsEmpty]: Start isEmpty. Operand 442 states and 514 transitions. [2018-01-29 22:38:43,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2018-01-29 22:38:43,853 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:43,853 INFO L350 BasicCegarLoop]: trace histogram [35, 34, 34, 34, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:43,853 INFO L371 AbstractCegarLoop]: === Iteration 37 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:43,853 INFO L82 PathProgramCache]: Analyzing trace with hash 2082880610, now seen corresponding path program 34 times [2018-01-29 22:38:43,853 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:43,853 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:43,854 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:43,854 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:43,854 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:43,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:43,859 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:44,259 INFO L134 CoverageAnalysis]: Checked inductivity of 2314 backedges. 2 proven. 2312 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:44,260 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:44,260 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:44,264 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:38:44,291 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:44,292 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:44,308 INFO L134 CoverageAnalysis]: Checked inductivity of 2314 backedges. 2 proven. 2312 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:44,326 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:44,327 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 37 [2018-01-29 22:38:44,327 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-01-29 22:38:44,327 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-01-29 22:38:44,327 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2018-01-29 22:38:44,327 INFO L87 Difference]: Start difference. First operand 442 states and 514 transitions. Second operand 37 states. [2018-01-29 22:38:44,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:44,635 INFO L93 Difference]: Finished difference Result 898 states and 1048 transitions. [2018-01-29 22:38:44,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-01-29 22:38:44,636 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 162 [2018-01-29 22:38:44,636 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:44,637 INFO L225 Difference]: With dead ends: 898 [2018-01-29 22:38:44,637 INFO L226 Difference]: Without dead ends: 462 [2018-01-29 22:38:44,638 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 163 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2018-01-29 22:38:44,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-01-29 22:38:44,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 454. [2018-01-29 22:38:44,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. [2018-01-29 22:38:44,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 528 transitions. [2018-01-29 22:38:44,641 INFO L78 Accepts]: Start accepts. Automaton has 454 states and 528 transitions. Word has length 162 [2018-01-29 22:38:44,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:44,641 INFO L432 AbstractCegarLoop]: Abstraction has 454 states and 528 transitions. [2018-01-29 22:38:44,641 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-01-29 22:38:44,641 INFO L276 IsEmpty]: Start isEmpty. Operand 454 states and 528 transitions. [2018-01-29 22:38:44,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2018-01-29 22:38:44,642 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:44,642 INFO L350 BasicCegarLoop]: trace histogram [36, 35, 35, 35, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:44,642 INFO L371 AbstractCegarLoop]: === Iteration 38 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:44,642 INFO L82 PathProgramCache]: Analyzing trace with hash -1278286838, now seen corresponding path program 35 times [2018-01-29 22:38:44,642 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:44,642 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:44,643 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:44,643 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:44,643 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:44,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:44,648 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:45,090 INFO L134 CoverageAnalysis]: Checked inductivity of 2452 backedges. 2 proven. 2450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:45,090 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:45,090 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:45,095 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:38:45,098 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,099 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,099 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,100 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,101 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,101 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,102 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,103 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,104 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,105 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,105 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,106 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,107 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,108 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,109 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,110 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,111 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,112 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,113 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,114 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,116 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,117 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,118 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,119 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,120 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,122 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,123 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,124 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,125 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,127 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,129 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,130 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,132 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,134 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,136 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,138 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:45,138 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:45,140 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:45,160 INFO L134 CoverageAnalysis]: Checked inductivity of 2452 backedges. 2 proven. 2450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:45,176 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:45,176 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 38 [2018-01-29 22:38:45,177 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-01-29 22:38:45,177 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-01-29 22:38:45,177 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-29 22:38:45,177 INFO L87 Difference]: Start difference. First operand 454 states and 528 transitions. Second operand 38 states. [2018-01-29 22:38:45,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:45,611 INFO L93 Difference]: Finished difference Result 922 states and 1076 transitions. [2018-01-29 22:38:45,611 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-01-29 22:38:45,611 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 166 [2018-01-29 22:38:45,611 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:45,612 INFO L225 Difference]: With dead ends: 922 [2018-01-29 22:38:45,612 INFO L226 Difference]: Without dead ends: 474 [2018-01-29 22:38:45,613 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 167 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-29 22:38:45,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 474 states. [2018-01-29 22:38:45,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 474 to 466. [2018-01-29 22:38:45,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 466 states. [2018-01-29 22:38:45,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 466 states to 466 states and 542 transitions. [2018-01-29 22:38:45,616 INFO L78 Accepts]: Start accepts. Automaton has 466 states and 542 transitions. Word has length 166 [2018-01-29 22:38:45,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:45,616 INFO L432 AbstractCegarLoop]: Abstraction has 466 states and 542 transitions. [2018-01-29 22:38:45,616 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-01-29 22:38:45,616 INFO L276 IsEmpty]: Start isEmpty. Operand 466 states and 542 transitions. [2018-01-29 22:38:45,617 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2018-01-29 22:38:45,617 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:45,617 INFO L350 BasicCegarLoop]: trace histogram [37, 36, 36, 36, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:45,617 INFO L371 AbstractCegarLoop]: === Iteration 39 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:45,617 INFO L82 PathProgramCache]: Analyzing trace with hash 302741426, now seen corresponding path program 36 times [2018-01-29 22:38:45,617 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:45,617 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:45,618 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:45,618 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:45,618 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:45,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:45,623 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:46,748 INFO L134 CoverageAnalysis]: Checked inductivity of 2594 backedges. 2 proven. 2592 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:46,748 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:46,748 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:46,754 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:38:46,759 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,760 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,760 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,761 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,762 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,762 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,763 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,764 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,765 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,765 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,766 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,767 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,768 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,769 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,770 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,771 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,773 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,774 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,775 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,776 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,777 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,778 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,779 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,780 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,781 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,783 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,784 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,785 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,786 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,788 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,789 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,790 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,792 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,793 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,794 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,796 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,798 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,799 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:46,800 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:46,801 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:46,818 INFO L134 CoverageAnalysis]: Checked inductivity of 2594 backedges. 2 proven. 2592 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:46,835 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:46,835 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 39 [2018-01-29 22:38:46,835 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-01-29 22:38:46,835 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-01-29 22:38:46,835 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2018-01-29 22:38:46,835 INFO L87 Difference]: Start difference. First operand 466 states and 542 transitions. Second operand 39 states. [2018-01-29 22:38:47,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:47,030 INFO L93 Difference]: Finished difference Result 946 states and 1104 transitions. [2018-01-29 22:38:47,030 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-01-29 22:38:47,030 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 170 [2018-01-29 22:38:47,031 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:47,031 INFO L225 Difference]: With dead ends: 946 [2018-01-29 22:38:47,031 INFO L226 Difference]: Without dead ends: 486 [2018-01-29 22:38:47,032 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 208 GetRequests, 171 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2018-01-29 22:38:47,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 486 states. [2018-01-29 22:38:47,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 486 to 478. [2018-01-29 22:38:47,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 478 states. [2018-01-29 22:38:47,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 478 states to 478 states and 556 transitions. [2018-01-29 22:38:47,035 INFO L78 Accepts]: Start accepts. Automaton has 478 states and 556 transitions. Word has length 170 [2018-01-29 22:38:47,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:47,036 INFO L432 AbstractCegarLoop]: Abstraction has 478 states and 556 transitions. [2018-01-29 22:38:47,036 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-01-29 22:38:47,036 INFO L276 IsEmpty]: Start isEmpty. Operand 478 states and 556 transitions. [2018-01-29 22:38:47,036 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-01-29 22:38:47,036 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:47,036 INFO L350 BasicCegarLoop]: trace histogram [38, 37, 37, 37, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:47,036 INFO L371 AbstractCegarLoop]: === Iteration 40 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:47,037 INFO L82 PathProgramCache]: Analyzing trace with hash 319158106, now seen corresponding path program 37 times [2018-01-29 22:38:47,037 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:47,037 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:47,037 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:47,037 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:47,037 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:47,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:47,042 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:47,515 INFO L134 CoverageAnalysis]: Checked inductivity of 2740 backedges. 2 proven. 2738 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:47,516 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:47,516 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:47,520 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:47,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:47,534 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:47,559 INFO L134 CoverageAnalysis]: Checked inductivity of 2740 backedges. 2 proven. 2738 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:47,576 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:47,576 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 40 [2018-01-29 22:38:47,576 INFO L409 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-01-29 22:38:47,576 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-01-29 22:38:47,576 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-29 22:38:47,577 INFO L87 Difference]: Start difference. First operand 478 states and 556 transitions. Second operand 40 states. [2018-01-29 22:38:49,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:49,019 INFO L93 Difference]: Finished difference Result 970 states and 1132 transitions. [2018-01-29 22:38:49,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-01-29 22:38:49,019 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 174 [2018-01-29 22:38:49,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:49,020 INFO L225 Difference]: With dead ends: 970 [2018-01-29 22:38:49,020 INFO L226 Difference]: Without dead ends: 498 [2018-01-29 22:38:49,021 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 213 GetRequests, 175 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-29 22:38:49,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states. [2018-01-29 22:38:49,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 490. [2018-01-29 22:38:49,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 490 states. [2018-01-29 22:38:49,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 490 states to 490 states and 570 transitions. [2018-01-29 22:38:49,024 INFO L78 Accepts]: Start accepts. Automaton has 490 states and 570 transitions. Word has length 174 [2018-01-29 22:38:49,024 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:49,024 INFO L432 AbstractCegarLoop]: Abstraction has 490 states and 570 transitions. [2018-01-29 22:38:49,024 INFO L433 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-01-29 22:38:49,024 INFO L276 IsEmpty]: Start isEmpty. Operand 490 states and 570 transitions. [2018-01-29 22:38:49,025 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2018-01-29 22:38:49,025 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:49,025 INFO L350 BasicCegarLoop]: trace histogram [39, 38, 38, 38, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:49,025 INFO L371 AbstractCegarLoop]: === Iteration 41 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:49,025 INFO L82 PathProgramCache]: Analyzing trace with hash 233333506, now seen corresponding path program 38 times [2018-01-29 22:38:49,025 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:49,026 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:49,026 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:49,026 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:49,026 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:49,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:49,032 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:49,505 INFO L134 CoverageAnalysis]: Checked inductivity of 2890 backedges. 2 proven. 2888 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:49,506 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:49,506 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:49,512 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:38:49,516 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:49,524 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:49,526 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:49,528 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:49,550 INFO L134 CoverageAnalysis]: Checked inductivity of 2890 backedges. 2 proven. 2888 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:49,566 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:49,566 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41] total 41 [2018-01-29 22:38:49,567 INFO L409 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-01-29 22:38:49,567 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-01-29 22:38:49,567 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2018-01-29 22:38:49,567 INFO L87 Difference]: Start difference. First operand 490 states and 570 transitions. Second operand 41 states. [2018-01-29 22:38:49,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:49,772 INFO L93 Difference]: Finished difference Result 994 states and 1160 transitions. [2018-01-29 22:38:49,774 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-01-29 22:38:49,774 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 178 [2018-01-29 22:38:49,774 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:49,775 INFO L225 Difference]: With dead ends: 994 [2018-01-29 22:38:49,775 INFO L226 Difference]: Without dead ends: 510 [2018-01-29 22:38:49,776 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 218 GetRequests, 179 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2018-01-29 22:38:49,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 510 states. [2018-01-29 22:38:49,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 510 to 502. [2018-01-29 22:38:49,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 502 states. [2018-01-29 22:38:49,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 502 states to 502 states and 584 transitions. [2018-01-29 22:38:49,780 INFO L78 Accepts]: Start accepts. Automaton has 502 states and 584 transitions. Word has length 178 [2018-01-29 22:38:49,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:49,780 INFO L432 AbstractCegarLoop]: Abstraction has 502 states and 584 transitions. [2018-01-29 22:38:49,780 INFO L433 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-01-29 22:38:49,780 INFO L276 IsEmpty]: Start isEmpty. Operand 502 states and 584 transitions. [2018-01-29 22:38:49,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-01-29 22:38:49,781 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:49,781 INFO L350 BasicCegarLoop]: trace histogram [40, 39, 39, 39, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:49,781 INFO L371 AbstractCegarLoop]: === Iteration 42 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:49,781 INFO L82 PathProgramCache]: Analyzing trace with hash -1260602710, now seen corresponding path program 39 times [2018-01-29 22:38:49,781 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:49,781 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:49,781 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:49,782 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:49,782 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:49,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:49,787 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:50,946 INFO L134 CoverageAnalysis]: Checked inductivity of 3044 backedges. 2 proven. 3042 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:50,947 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:50,947 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:50,951 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:38:50,955 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,956 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,957 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,957 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,958 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,959 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,959 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,960 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,961 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,962 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,963 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,963 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,964 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,965 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,966 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,967 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,968 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,969 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,970 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,971 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,972 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,973 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,975 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,976 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,978 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,979 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,980 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,982 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,983 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,985 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,986 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,988 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,989 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,991 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,992 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,994 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,996 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,998 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:50,999 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:51,001 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:51,003 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:51,004 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:51,005 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:51,024 INFO L134 CoverageAnalysis]: Checked inductivity of 3044 backedges. 2 proven. 3042 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:51,043 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:51,043 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 42 [2018-01-29 22:38:51,043 INFO L409 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-01-29 22:38:51,044 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-01-29 22:38:51,044 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-01-29 22:38:51,044 INFO L87 Difference]: Start difference. First operand 502 states and 584 transitions. Second operand 42 states. [2018-01-29 22:38:51,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:51,885 INFO L93 Difference]: Finished difference Result 1018 states and 1188 transitions. [2018-01-29 22:38:51,885 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-01-29 22:38:51,885 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 182 [2018-01-29 22:38:51,885 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:51,886 INFO L225 Difference]: With dead ends: 1018 [2018-01-29 22:38:51,886 INFO L226 Difference]: Without dead ends: 522 [2018-01-29 22:38:51,886 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 223 GetRequests, 183 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-01-29 22:38:51,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states. [2018-01-29 22:38:51,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 514. [2018-01-29 22:38:51,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 514 states. [2018-01-29 22:38:51,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 514 states to 514 states and 598 transitions. [2018-01-29 22:38:51,891 INFO L78 Accepts]: Start accepts. Automaton has 514 states and 598 transitions. Word has length 182 [2018-01-29 22:38:51,891 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:51,891 INFO L432 AbstractCegarLoop]: Abstraction has 514 states and 598 transitions. [2018-01-29 22:38:51,891 INFO L433 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-01-29 22:38:51,891 INFO L276 IsEmpty]: Start isEmpty. Operand 514 states and 598 transitions. [2018-01-29 22:38:51,892 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2018-01-29 22:38:51,892 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:51,892 INFO L350 BasicCegarLoop]: trace histogram [41, 40, 40, 40, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:51,892 INFO L371 AbstractCegarLoop]: === Iteration 43 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:51,892 INFO L82 PathProgramCache]: Analyzing trace with hash -1794310574, now seen corresponding path program 40 times [2018-01-29 22:38:51,892 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:51,892 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:51,893 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:51,893 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:51,893 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:51,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:51,899 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:52,410 INFO L134 CoverageAnalysis]: Checked inductivity of 3202 backedges. 2 proven. 3200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:52,411 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:52,411 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:52,416 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:38:52,432 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:52,434 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:52,454 INFO L134 CoverageAnalysis]: Checked inductivity of 3202 backedges. 2 proven. 3200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:52,473 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:52,473 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 43 [2018-01-29 22:38:52,474 INFO L409 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-01-29 22:38:52,474 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-01-29 22:38:52,474 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2018-01-29 22:38:52,474 INFO L87 Difference]: Start difference. First operand 514 states and 598 transitions. Second operand 43 states. [2018-01-29 22:38:52,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:52,748 INFO L93 Difference]: Finished difference Result 1042 states and 1216 transitions. [2018-01-29 22:38:52,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-01-29 22:38:52,749 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 186 [2018-01-29 22:38:52,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:52,750 INFO L225 Difference]: With dead ends: 1042 [2018-01-29 22:38:52,750 INFO L226 Difference]: Without dead ends: 534 [2018-01-29 22:38:52,751 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 228 GetRequests, 187 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2018-01-29 22:38:52,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 534 states. [2018-01-29 22:38:52,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 534 to 526. [2018-01-29 22:38:52,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 526 states. [2018-01-29 22:38:52,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 526 states to 526 states and 612 transitions. [2018-01-29 22:38:52,754 INFO L78 Accepts]: Start accepts. Automaton has 526 states and 612 transitions. Word has length 186 [2018-01-29 22:38:52,754 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:52,754 INFO L432 AbstractCegarLoop]: Abstraction has 526 states and 612 transitions. [2018-01-29 22:38:52,755 INFO L433 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-01-29 22:38:52,755 INFO L276 IsEmpty]: Start isEmpty. Operand 526 states and 612 transitions. [2018-01-29 22:38:52,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2018-01-29 22:38:52,755 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:52,755 INFO L350 BasicCegarLoop]: trace histogram [42, 41, 41, 41, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:52,756 INFO L371 AbstractCegarLoop]: === Iteration 44 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:52,756 INFO L82 PathProgramCache]: Analyzing trace with hash -1767690758, now seen corresponding path program 41 times [2018-01-29 22:38:52,756 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:52,756 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:52,756 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:52,756 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:52,756 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:52,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:52,762 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:54,678 INFO L134 CoverageAnalysis]: Checked inductivity of 3364 backedges. 2 proven. 3362 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:54,678 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:54,678 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:54,696 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:38:54,699 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,710 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,720 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,726 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,727 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,728 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,729 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,730 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,730 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,731 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,732 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,733 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,734 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,735 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,736 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,737 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,738 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,739 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,741 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,742 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,744 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,745 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,746 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,747 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,748 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,750 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,751 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,752 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,754 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,755 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,756 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,758 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,759 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,760 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,762 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,763 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,765 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,766 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,768 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,769 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,771 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,773 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:54,773 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:54,775 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:54,796 INFO L134 CoverageAnalysis]: Checked inductivity of 3364 backedges. 2 proven. 3362 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:54,813 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:54,813 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 44 [2018-01-29 22:38:54,813 INFO L409 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-01-29 22:38:54,814 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-01-29 22:38:54,814 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-29 22:38:54,814 INFO L87 Difference]: Start difference. First operand 526 states and 612 transitions. Second operand 44 states. [2018-01-29 22:38:55,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:55,056 INFO L93 Difference]: Finished difference Result 1066 states and 1244 transitions. [2018-01-29 22:38:55,056 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-01-29 22:38:55,057 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 190 [2018-01-29 22:38:55,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:55,058 INFO L225 Difference]: With dead ends: 1066 [2018-01-29 22:38:55,058 INFO L226 Difference]: Without dead ends: 546 [2018-01-29 22:38:55,058 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 233 GetRequests, 191 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-29 22:38:55,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states. [2018-01-29 22:38:55,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 538. [2018-01-29 22:38:55,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-01-29 22:38:55,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 626 transitions. [2018-01-29 22:38:55,062 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 626 transitions. Word has length 190 [2018-01-29 22:38:55,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:55,062 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 626 transitions. [2018-01-29 22:38:55,062 INFO L433 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-01-29 22:38:55,062 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 626 transitions. [2018-01-29 22:38:55,063 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2018-01-29 22:38:55,063 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:55,063 INFO L350 BasicCegarLoop]: trace histogram [43, 42, 42, 42, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:55,063 INFO L371 AbstractCegarLoop]: === Iteration 45 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:55,063 INFO L82 PathProgramCache]: Analyzing trace with hash 2093566370, now seen corresponding path program 42 times [2018-01-29 22:38:55,063 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:55,063 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:55,063 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:55,063 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:55,063 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:55,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:55,075 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:56,237 INFO L134 CoverageAnalysis]: Checked inductivity of 3530 backedges. 2 proven. 3528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:56,238 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:56,238 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:56,242 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:38:56,247 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,248 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,249 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,249 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,250 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,251 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,252 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,252 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,253 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,254 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,255 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,255 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,256 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,257 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,258 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,259 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,260 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,261 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,262 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,263 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,264 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,265 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,266 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,268 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,269 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,270 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,271 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,272 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,274 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,275 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,277 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,278 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,279 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,281 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,283 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,284 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,286 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,287 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,289 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,291 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,293 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,295 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,297 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,299 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:38:56,299 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:56,301 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:56,322 INFO L134 CoverageAnalysis]: Checked inductivity of 3530 backedges. 2 proven. 3528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:56,340 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:56,341 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45] total 45 [2018-01-29 22:38:56,341 INFO L409 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-01-29 22:38:56,341 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-01-29 22:38:56,341 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2018-01-29 22:38:56,342 INFO L87 Difference]: Start difference. First operand 538 states and 626 transitions. Second operand 45 states. [2018-01-29 22:38:56,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:56,677 INFO L93 Difference]: Finished difference Result 1090 states and 1272 transitions. [2018-01-29 22:38:56,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-01-29 22:38:56,677 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 194 [2018-01-29 22:38:56,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:56,678 INFO L225 Difference]: With dead ends: 1090 [2018-01-29 22:38:56,678 INFO L226 Difference]: Without dead ends: 558 [2018-01-29 22:38:56,679 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 195 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2018-01-29 22:38:56,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 558 states. [2018-01-29 22:38:56,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 558 to 550. [2018-01-29 22:38:56,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 550 states. [2018-01-29 22:38:56,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 550 states to 550 states and 640 transitions. [2018-01-29 22:38:56,683 INFO L78 Accepts]: Start accepts. Automaton has 550 states and 640 transitions. Word has length 194 [2018-01-29 22:38:56,683 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:56,683 INFO L432 AbstractCegarLoop]: Abstraction has 550 states and 640 transitions. [2018-01-29 22:38:56,683 INFO L433 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-01-29 22:38:56,683 INFO L276 IsEmpty]: Start isEmpty. Operand 550 states and 640 transitions. [2018-01-29 22:38:56,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-01-29 22:38:56,684 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:56,684 INFO L350 BasicCegarLoop]: trace histogram [44, 43, 43, 43, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:56,684 INFO L371 AbstractCegarLoop]: === Iteration 46 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:56,684 INFO L82 PathProgramCache]: Analyzing trace with hash 1705595210, now seen corresponding path program 43 times [2018-01-29 22:38:56,684 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:56,684 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:56,685 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:56,685 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:56,685 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:56,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:56,690 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:57,250 INFO L134 CoverageAnalysis]: Checked inductivity of 3700 backedges. 2 proven. 3698 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:57,250 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:57,250 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:57,254 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:57,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:57,270 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:57,297 INFO L134 CoverageAnalysis]: Checked inductivity of 3700 backedges. 2 proven. 3698 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:57,313 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:57,313 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 46 [2018-01-29 22:38:57,314 INFO L409 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-01-29 22:38:57,314 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-01-29 22:38:57,314 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-29 22:38:57,314 INFO L87 Difference]: Start difference. First operand 550 states and 640 transitions. Second operand 46 states. [2018-01-29 22:38:57,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:57,585 INFO L93 Difference]: Finished difference Result 1114 states and 1300 transitions. [2018-01-29 22:38:57,585 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-01-29 22:38:57,585 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 198 [2018-01-29 22:38:57,586 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:57,587 INFO L225 Difference]: With dead ends: 1114 [2018-01-29 22:38:57,587 INFO L226 Difference]: Without dead ends: 570 [2018-01-29 22:38:57,588 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 243 GetRequests, 199 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-29 22:38:57,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 570 states. [2018-01-29 22:38:57,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 570 to 562. [2018-01-29 22:38:57,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 562 states. [2018-01-29 22:38:57,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 562 states to 562 states and 654 transitions. [2018-01-29 22:38:57,592 INFO L78 Accepts]: Start accepts. Automaton has 562 states and 654 transitions. Word has length 198 [2018-01-29 22:38:57,592 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:57,592 INFO L432 AbstractCegarLoop]: Abstraction has 562 states and 654 transitions. [2018-01-29 22:38:57,592 INFO L433 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-01-29 22:38:57,592 INFO L276 IsEmpty]: Start isEmpty. Operand 562 states and 654 transitions. [2018-01-29 22:38:57,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 203 [2018-01-29 22:38:57,593 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:57,593 INFO L350 BasicCegarLoop]: trace histogram [45, 44, 44, 44, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:57,593 INFO L371 AbstractCegarLoop]: === Iteration 47 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:57,593 INFO L82 PathProgramCache]: Analyzing trace with hash 1248675058, now seen corresponding path program 44 times [2018-01-29 22:38:57,593 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:57,593 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:57,593 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:57,593 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:38:57,594 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:57,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:57,599 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:58,260 INFO L134 CoverageAnalysis]: Checked inductivity of 3874 backedges. 2 proven. 3872 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:58,260 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:58,260 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:58,275 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:38:58,279 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:58,288 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:38:58,291 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:58,293 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:58,317 INFO L134 CoverageAnalysis]: Checked inductivity of 3874 backedges. 2 proven. 3872 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:58,334 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:58,334 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47] total 47 [2018-01-29 22:38:58,334 INFO L409 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-01-29 22:38:58,335 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-01-29 22:38:58,335 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2018-01-29 22:38:58,335 INFO L87 Difference]: Start difference. First operand 562 states and 654 transitions. Second operand 47 states. [2018-01-29 22:38:58,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:58,569 INFO L93 Difference]: Finished difference Result 1138 states and 1328 transitions. [2018-01-29 22:38:58,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-01-29 22:38:58,569 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 202 [2018-01-29 22:38:58,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:58,570 INFO L225 Difference]: With dead ends: 1138 [2018-01-29 22:38:58,570 INFO L226 Difference]: Without dead ends: 582 [2018-01-29 22:38:58,571 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 248 GetRequests, 203 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2018-01-29 22:38:58,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 582 states. [2018-01-29 22:38:58,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 582 to 574. [2018-01-29 22:38:58,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 574 states. [2018-01-29 22:38:58,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 574 states to 574 states and 668 transitions. [2018-01-29 22:38:58,574 INFO L78 Accepts]: Start accepts. Automaton has 574 states and 668 transitions. Word has length 202 [2018-01-29 22:38:58,574 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:58,574 INFO L432 AbstractCegarLoop]: Abstraction has 574 states and 668 transitions. [2018-01-29 22:38:58,574 INFO L433 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-01-29 22:38:58,574 INFO L276 IsEmpty]: Start isEmpty. Operand 574 states and 668 transitions. [2018-01-29 22:38:58,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 207 [2018-01-29 22:38:58,575 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:58,575 INFO L350 BasicCegarLoop]: trace histogram [46, 45, 45, 45, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:58,575 INFO L371 AbstractCegarLoop]: === Iteration 48 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:58,575 INFO L82 PathProgramCache]: Analyzing trace with hash 2134844570, now seen corresponding path program 45 times [2018-01-29 22:38:58,575 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:58,576 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:58,576 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:58,576 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:58,576 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:58,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:58,582 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:38:59,237 INFO L134 CoverageAnalysis]: Checked inductivity of 4052 backedges. 2 proven. 4050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:59,237 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:38:59,237 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:38:59,242 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:38:59,246 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,247 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,247 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,248 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,249 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,249 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,250 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,251 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,252 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,252 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,253 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,254 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,255 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,256 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,257 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,258 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,259 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,260 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,261 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,262 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,263 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,264 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,265 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,267 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,268 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,269 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,270 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,273 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,275 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,276 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,280 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,287 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,297 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,303 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,313 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,320 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,330 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,340 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,353 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,360 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,370 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,379 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,388 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,397 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,407 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,416 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,426 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:38:59,434 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:38:59,437 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:38:59,460 INFO L134 CoverageAnalysis]: Checked inductivity of 4052 backedges. 2 proven. 4050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:38:59,477 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:38:59,477 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48] total 48 [2018-01-29 22:38:59,477 INFO L409 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-01-29 22:38:59,478 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-01-29 22:38:59,478 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-01-29 22:38:59,478 INFO L87 Difference]: Start difference. First operand 574 states and 668 transitions. Second operand 48 states. [2018-01-29 22:38:59,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:38:59,804 INFO L93 Difference]: Finished difference Result 1162 states and 1356 transitions. [2018-01-29 22:38:59,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-01-29 22:38:59,814 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 206 [2018-01-29 22:38:59,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:38:59,815 INFO L225 Difference]: With dead ends: 1162 [2018-01-29 22:38:59,815 INFO L226 Difference]: Without dead ends: 594 [2018-01-29 22:38:59,815 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 253 GetRequests, 207 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-01-29 22:38:59,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 594 states. [2018-01-29 22:38:59,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 594 to 586. [2018-01-29 22:38:59,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 586 states. [2018-01-29 22:38:59,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 586 states to 586 states and 682 transitions. [2018-01-29 22:38:59,821 INFO L78 Accepts]: Start accepts. Automaton has 586 states and 682 transitions. Word has length 206 [2018-01-29 22:38:59,821 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:38:59,821 INFO L432 AbstractCegarLoop]: Abstraction has 586 states and 682 transitions. [2018-01-29 22:38:59,821 INFO L433 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-01-29 22:38:59,821 INFO L276 IsEmpty]: Start isEmpty. Operand 586 states and 682 transitions. [2018-01-29 22:38:59,822 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 211 [2018-01-29 22:38:59,822 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:38:59,822 INFO L350 BasicCegarLoop]: trace histogram [47, 46, 46, 46, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:38:59,822 INFO L371 AbstractCegarLoop]: === Iteration 49 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:38:59,822 INFO L82 PathProgramCache]: Analyzing trace with hash 860418114, now seen corresponding path program 46 times [2018-01-29 22:38:59,822 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:38:59,822 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:38:59,822 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:59,822 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:38:59,823 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:38:59,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:38:59,829 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:00,536 INFO L134 CoverageAnalysis]: Checked inductivity of 4234 backedges. 2 proven. 4232 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:00,536 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:00,536 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:00,540 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:39:00,558 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:00,560 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:00,591 INFO L134 CoverageAnalysis]: Checked inductivity of 4234 backedges. 2 proven. 4232 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:00,608 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:00,608 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 49 [2018-01-29 22:39:00,609 INFO L409 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-01-29 22:39:00,609 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-01-29 22:39:00,609 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2018-01-29 22:39:00,609 INFO L87 Difference]: Start difference. First operand 586 states and 682 transitions. Second operand 49 states. [2018-01-29 22:39:00,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:00,879 INFO L93 Difference]: Finished difference Result 1186 states and 1384 transitions. [2018-01-29 22:39:00,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-01-29 22:39:00,886 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 210 [2018-01-29 22:39:00,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:00,888 INFO L225 Difference]: With dead ends: 1186 [2018-01-29 22:39:00,888 INFO L226 Difference]: Without dead ends: 606 [2018-01-29 22:39:00,888 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 258 GetRequests, 211 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2018-01-29 22:39:00,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states. [2018-01-29 22:39:00,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 598. [2018-01-29 22:39:00,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 598 states. [2018-01-29 22:39:00,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 598 states to 598 states and 696 transitions. [2018-01-29 22:39:00,893 INFO L78 Accepts]: Start accepts. Automaton has 598 states and 696 transitions. Word has length 210 [2018-01-29 22:39:00,893 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:00,893 INFO L432 AbstractCegarLoop]: Abstraction has 598 states and 696 transitions. [2018-01-29 22:39:00,893 INFO L433 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-01-29 22:39:00,893 INFO L276 IsEmpty]: Start isEmpty. Operand 598 states and 696 transitions. [2018-01-29 22:39:00,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 215 [2018-01-29 22:39:00,894 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:00,894 INFO L350 BasicCegarLoop]: trace histogram [48, 47, 47, 47, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:00,894 INFO L371 AbstractCegarLoop]: === Iteration 50 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:00,894 INFO L82 PathProgramCache]: Analyzing trace with hash -256595990, now seen corresponding path program 47 times [2018-01-29 22:39:00,894 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:00,894 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:00,895 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:00,895 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:00,895 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:00,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:00,901 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:01,547 INFO L134 CoverageAnalysis]: Checked inductivity of 4420 backedges. 2 proven. 4418 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:01,547 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:01,548 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:01,552 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:39:01,555 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,555 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,556 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,556 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,557 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,558 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,559 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,559 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,560 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,561 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,562 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,563 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,564 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,565 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,566 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,567 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,568 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,569 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,570 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,571 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,572 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,574 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,575 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,577 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,578 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,580 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,581 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,583 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,584 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,591 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,592 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,594 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,595 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,597 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,598 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,599 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,601 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,603 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,604 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,606 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,608 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,611 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,612 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,614 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,616 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,618 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,620 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,622 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:01,623 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:01,624 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:01,649 INFO L134 CoverageAnalysis]: Checked inductivity of 4420 backedges. 2 proven. 4418 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:01,666 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:01,666 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 50 [2018-01-29 22:39:01,666 INFO L409 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-01-29 22:39:01,667 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-01-29 22:39:01,667 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-29 22:39:01,667 INFO L87 Difference]: Start difference. First operand 598 states and 696 transitions. Second operand 50 states. [2018-01-29 22:39:01,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:01,964 INFO L93 Difference]: Finished difference Result 1210 states and 1412 transitions. [2018-01-29 22:39:01,964 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-01-29 22:39:01,964 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 214 [2018-01-29 22:39:01,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:01,965 INFO L225 Difference]: With dead ends: 1210 [2018-01-29 22:39:01,965 INFO L226 Difference]: Without dead ends: 618 [2018-01-29 22:39:01,966 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 263 GetRequests, 215 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-29 22:39:01,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 618 states. [2018-01-29 22:39:01,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 618 to 610. [2018-01-29 22:39:01,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 610 states. [2018-01-29 22:39:01,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 610 states to 610 states and 710 transitions. [2018-01-29 22:39:01,969 INFO L78 Accepts]: Start accepts. Automaton has 610 states and 710 transitions. Word has length 214 [2018-01-29 22:39:01,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:01,969 INFO L432 AbstractCegarLoop]: Abstraction has 610 states and 710 transitions. [2018-01-29 22:39:01,969 INFO L433 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-01-29 22:39:01,969 INFO L276 IsEmpty]: Start isEmpty. Operand 610 states and 710 transitions. [2018-01-29 22:39:01,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 219 [2018-01-29 22:39:01,970 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:01,970 INFO L350 BasicCegarLoop]: trace histogram [49, 48, 48, 48, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:01,970 INFO L371 AbstractCegarLoop]: === Iteration 51 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:01,970 INFO L82 PathProgramCache]: Analyzing trace with hash 481053586, now seen corresponding path program 48 times [2018-01-29 22:39:01,970 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:01,971 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:01,971 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:01,971 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:01,971 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:01,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:01,976 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:02,724 INFO L134 CoverageAnalysis]: Checked inductivity of 4610 backedges. 2 proven. 4608 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:02,725 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:02,725 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:02,729 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:39:02,733 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,734 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,735 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,735 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,736 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,737 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,737 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,738 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,739 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,740 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,740 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,741 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,742 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,743 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,744 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,745 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,746 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,747 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,748 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,749 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,751 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,752 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,753 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,754 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,756 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,757 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,759 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,760 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,761 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,762 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,764 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,765 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,766 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,767 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,769 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,770 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,772 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,773 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,775 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,776 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,778 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,779 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,781 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,783 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,785 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,786 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,789 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,791 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,792 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,794 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:02,795 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:02,797 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:02,824 INFO L134 CoverageAnalysis]: Checked inductivity of 4610 backedges. 2 proven. 4608 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:02,840 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:02,841 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51] total 51 [2018-01-29 22:39:02,841 INFO L409 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-01-29 22:39:02,841 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-01-29 22:39:02,841 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2018-01-29 22:39:02,841 INFO L87 Difference]: Start difference. First operand 610 states and 710 transitions. Second operand 51 states. [2018-01-29 22:39:03,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:03,628 INFO L93 Difference]: Finished difference Result 1234 states and 1440 transitions. [2018-01-29 22:39:03,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-01-29 22:39:03,629 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 218 [2018-01-29 22:39:03,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:03,630 INFO L225 Difference]: With dead ends: 1234 [2018-01-29 22:39:03,630 INFO L226 Difference]: Without dead ends: 630 [2018-01-29 22:39:03,630 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 268 GetRequests, 219 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2018-01-29 22:39:03,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 630 states. [2018-01-29 22:39:03,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 630 to 622. [2018-01-29 22:39:03,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2018-01-29 22:39:03,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 724 transitions. [2018-01-29 22:39:03,634 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 724 transitions. Word has length 218 [2018-01-29 22:39:03,634 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:03,634 INFO L432 AbstractCegarLoop]: Abstraction has 622 states and 724 transitions. [2018-01-29 22:39:03,634 INFO L433 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-01-29 22:39:03,635 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 724 transitions. [2018-01-29 22:39:03,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 223 [2018-01-29 22:39:03,635 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:03,635 INFO L350 BasicCegarLoop]: trace histogram [50, 49, 49, 49, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:03,635 INFO L371 AbstractCegarLoop]: === Iteration 52 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:03,636 INFO L82 PathProgramCache]: Analyzing trace with hash 2002377530, now seen corresponding path program 49 times [2018-01-29 22:39:03,636 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:03,636 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:03,636 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:03,636 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:03,636 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:03,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:03,642 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:04,359 INFO L134 CoverageAnalysis]: Checked inductivity of 4804 backedges. 2 proven. 4802 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:04,359 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:04,359 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:04,363 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:39:04,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:04,381 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:04,412 INFO L134 CoverageAnalysis]: Checked inductivity of 4804 backedges. 2 proven. 4802 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:04,430 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:04,431 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52] total 52 [2018-01-29 22:39:04,431 INFO L409 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-01-29 22:39:04,431 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-01-29 22:39:04,431 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-29 22:39:04,431 INFO L87 Difference]: Start difference. First operand 622 states and 724 transitions. Second operand 52 states. [2018-01-29 22:39:04,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:04,761 INFO L93 Difference]: Finished difference Result 1258 states and 1468 transitions. [2018-01-29 22:39:04,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-01-29 22:39:04,761 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 222 [2018-01-29 22:39:04,762 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:04,763 INFO L225 Difference]: With dead ends: 1258 [2018-01-29 22:39:04,763 INFO L226 Difference]: Without dead ends: 642 [2018-01-29 22:39:04,763 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 273 GetRequests, 223 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-29 22:39:04,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 642 states. [2018-01-29 22:39:04,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 642 to 634. [2018-01-29 22:39:04,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 634 states. [2018-01-29 22:39:04,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 634 states to 634 states and 738 transitions. [2018-01-29 22:39:04,771 INFO L78 Accepts]: Start accepts. Automaton has 634 states and 738 transitions. Word has length 222 [2018-01-29 22:39:04,771 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:04,771 INFO L432 AbstractCegarLoop]: Abstraction has 634 states and 738 transitions. [2018-01-29 22:39:04,771 INFO L433 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-01-29 22:39:04,771 INFO L276 IsEmpty]: Start isEmpty. Operand 634 states and 738 transitions. [2018-01-29 22:39:04,772 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2018-01-29 22:39:04,772 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:04,772 INFO L350 BasicCegarLoop]: trace histogram [51, 50, 50, 50, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:04,772 INFO L371 AbstractCegarLoop]: === Iteration 53 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:04,772 INFO L82 PathProgramCache]: Analyzing trace with hash -1679337758, now seen corresponding path program 50 times [2018-01-29 22:39:04,772 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:04,772 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:04,773 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:04,773 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:39:04,773 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:04,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:04,779 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:05,557 INFO L134 CoverageAnalysis]: Checked inductivity of 5002 backedges. 2 proven. 5000 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:05,557 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:05,557 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:05,561 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:39:05,565 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:05,576 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:05,578 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:05,580 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:05,611 INFO L134 CoverageAnalysis]: Checked inductivity of 5002 backedges. 2 proven. 5000 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:05,627 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:05,627 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53] total 53 [2018-01-29 22:39:05,627 INFO L409 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-01-29 22:39:05,628 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-01-29 22:39:05,628 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1378, Invalid=1378, Unknown=0, NotChecked=0, Total=2756 [2018-01-29 22:39:05,628 INFO L87 Difference]: Start difference. First operand 634 states and 738 transitions. Second operand 53 states. [2018-01-29 22:39:05,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:05,933 INFO L93 Difference]: Finished difference Result 1282 states and 1496 transitions. [2018-01-29 22:39:05,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-01-29 22:39:05,933 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 226 [2018-01-29 22:39:05,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:05,934 INFO L225 Difference]: With dead ends: 1282 [2018-01-29 22:39:05,934 INFO L226 Difference]: Without dead ends: 654 [2018-01-29 22:39:05,935 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 278 GetRequests, 227 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1378, Invalid=1378, Unknown=0, NotChecked=0, Total=2756 [2018-01-29 22:39:05,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 654 states. [2018-01-29 22:39:05,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 654 to 646. [2018-01-29 22:39:05,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 646 states. [2018-01-29 22:39:05,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 646 states to 646 states and 752 transitions. [2018-01-29 22:39:05,939 INFO L78 Accepts]: Start accepts. Automaton has 646 states and 752 transitions. Word has length 226 [2018-01-29 22:39:05,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:05,939 INFO L432 AbstractCegarLoop]: Abstraction has 646 states and 752 transitions. [2018-01-29 22:39:05,939 INFO L433 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-01-29 22:39:05,939 INFO L276 IsEmpty]: Start isEmpty. Operand 646 states and 752 transitions. [2018-01-29 22:39:05,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 231 [2018-01-29 22:39:05,940 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:05,940 INFO L350 BasicCegarLoop]: trace histogram [52, 51, 51, 51, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:05,940 INFO L371 AbstractCegarLoop]: === Iteration 54 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:05,940 INFO L82 PathProgramCache]: Analyzing trace with hash -2139177334, now seen corresponding path program 51 times [2018-01-29 22:39:05,940 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:05,940 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:05,941 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:05,941 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:05,941 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:05,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:05,947 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:06,707 INFO L134 CoverageAnalysis]: Checked inductivity of 5204 backedges. 2 proven. 5202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:06,707 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:06,707 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-29 22:39:06,713 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:06,717 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,718 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,719 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,719 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,720 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,721 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,721 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,722 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,723 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,724 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,724 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,725 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,726 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,727 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,728 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,729 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,730 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,731 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,732 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,733 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,734 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,735 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,737 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,738 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,739 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,741 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,742 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,743 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,745 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,746 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,748 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,749 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,751 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,752 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,754 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,756 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,757 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,759 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,761 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,763 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,764 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,766 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,768 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,770 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,772 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,774 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,776 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,778 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,780 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,782 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,785 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,787 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,790 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:06,791 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:06,792 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:06,825 INFO L134 CoverageAnalysis]: Checked inductivity of 5204 backedges. 2 proven. 5202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:06,842 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:06,842 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54] total 54 [2018-01-29 22:39:06,842 INFO L409 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-01-29 22:39:06,842 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-01-29 22:39:06,842 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-01-29 22:39:06,842 INFO L87 Difference]: Start difference. First operand 646 states and 752 transitions. Second operand 54 states. [2018-01-29 22:39:07,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:07,264 INFO L93 Difference]: Finished difference Result 1306 states and 1524 transitions. [2018-01-29 22:39:07,265 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-01-29 22:39:07,265 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 230 [2018-01-29 22:39:07,265 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:07,266 INFO L225 Difference]: With dead ends: 1306 [2018-01-29 22:39:07,266 INFO L226 Difference]: Without dead ends: 666 [2018-01-29 22:39:07,266 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 283 GetRequests, 231 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-01-29 22:39:07,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 666 states. [2018-01-29 22:39:07,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 666 to 658. [2018-01-29 22:39:07,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 658 states. [2018-01-29 22:39:07,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 658 states to 658 states and 766 transitions. [2018-01-29 22:39:07,270 INFO L78 Accepts]: Start accepts. Automaton has 658 states and 766 transitions. Word has length 230 [2018-01-29 22:39:07,271 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:07,271 INFO L432 AbstractCegarLoop]: Abstraction has 658 states and 766 transitions. [2018-01-29 22:39:07,271 INFO L433 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-01-29 22:39:07,271 INFO L276 IsEmpty]: Start isEmpty. Operand 658 states and 766 transitions. [2018-01-29 22:39:07,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 235 [2018-01-29 22:39:07,271 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:07,272 INFO L350 BasicCegarLoop]: trace histogram [53, 52, 52, 52, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:07,272 INFO L371 AbstractCegarLoop]: === Iteration 55 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:07,272 INFO L82 PathProgramCache]: Analyzing trace with hash -162917838, now seen corresponding path program 52 times [2018-01-29 22:39:07,272 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:07,272 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:07,272 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:07,272 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:07,272 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:07,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:07,278 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:08,040 INFO L134 CoverageAnalysis]: Checked inductivity of 5410 backedges. 2 proven. 5408 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:08,040 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:08,040 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:08,045 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:39:08,064 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:08,066 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:08,094 INFO L134 CoverageAnalysis]: Checked inductivity of 5410 backedges. 2 proven. 5408 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:08,111 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:08,111 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55] total 55 [2018-01-29 22:39:08,111 INFO L409 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-01-29 22:39:08,111 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-01-29 22:39:08,112 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1485, Invalid=1485, Unknown=0, NotChecked=0, Total=2970 [2018-01-29 22:39:08,112 INFO L87 Difference]: Start difference. First operand 658 states and 766 transitions. Second operand 55 states. [2018-01-29 22:39:08,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:08,474 INFO L93 Difference]: Finished difference Result 1330 states and 1552 transitions. [2018-01-29 22:39:08,474 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-01-29 22:39:08,474 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 234 [2018-01-29 22:39:08,475 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:08,476 INFO L225 Difference]: With dead ends: 1330 [2018-01-29 22:39:08,476 INFO L226 Difference]: Without dead ends: 678 [2018-01-29 22:39:08,477 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 288 GetRequests, 235 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1485, Invalid=1485, Unknown=0, NotChecked=0, Total=2970 [2018-01-29 22:39:08,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 678 states. [2018-01-29 22:39:08,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 678 to 670. [2018-01-29 22:39:08,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 670 states. [2018-01-29 22:39:08,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 670 states to 670 states and 780 transitions. [2018-01-29 22:39:08,481 INFO L78 Accepts]: Start accepts. Automaton has 670 states and 780 transitions. Word has length 234 [2018-01-29 22:39:08,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:08,481 INFO L432 AbstractCegarLoop]: Abstraction has 670 states and 780 transitions. [2018-01-29 22:39:08,481 INFO L433 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-01-29 22:39:08,481 INFO L276 IsEmpty]: Start isEmpty. Operand 670 states and 780 transitions. [2018-01-29 22:39:08,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 239 [2018-01-29 22:39:08,482 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:08,482 INFO L350 BasicCegarLoop]: trace histogram [54, 53, 53, 53, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:08,482 INFO L371 AbstractCegarLoop]: === Iteration 56 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:08,482 INFO L82 PathProgramCache]: Analyzing trace with hash 695423450, now seen corresponding path program 53 times [2018-01-29 22:39:08,482 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:08,482 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:08,483 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:08,483 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:08,483 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:08,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:08,489 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:09,414 INFO L134 CoverageAnalysis]: Checked inductivity of 5620 backedges. 2 proven. 5618 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:09,414 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:09,414 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:09,419 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:39:09,422 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,423 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,423 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,424 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,425 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,426 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,426 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,427 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,428 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,429 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,430 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,431 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,432 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,432 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,433 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,434 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,435 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,436 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,438 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,439 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,440 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,441 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,442 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,443 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,445 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,446 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,447 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,449 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,450 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,452 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,453 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,455 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,456 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,459 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,461 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,463 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,465 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,467 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,469 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,472 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,474 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,476 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,478 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,480 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,482 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,485 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,487 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,490 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,492 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,494 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,497 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,500 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,503 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,505 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:09,506 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:09,508 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:09,537 INFO L134 CoverageAnalysis]: Checked inductivity of 5620 backedges. 2 proven. 5618 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:09,553 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:09,553 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 56] total 56 [2018-01-29 22:39:09,554 INFO L409 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-01-29 22:39:09,554 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-01-29 22:39:09,554 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-29 22:39:09,554 INFO L87 Difference]: Start difference. First operand 670 states and 780 transitions. Second operand 56 states. [2018-01-29 22:39:09,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:09,871 INFO L93 Difference]: Finished difference Result 1354 states and 1580 transitions. [2018-01-29 22:39:09,871 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-01-29 22:39:09,871 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 238 [2018-01-29 22:39:09,871 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:09,872 INFO L225 Difference]: With dead ends: 1354 [2018-01-29 22:39:09,872 INFO L226 Difference]: Without dead ends: 690 [2018-01-29 22:39:09,873 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 293 GetRequests, 239 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-29 22:39:09,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 690 states. [2018-01-29 22:39:09,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 690 to 682. [2018-01-29 22:39:09,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 682 states. [2018-01-29 22:39:09,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 682 states to 682 states and 794 transitions. [2018-01-29 22:39:09,877 INFO L78 Accepts]: Start accepts. Automaton has 682 states and 794 transitions. Word has length 238 [2018-01-29 22:39:09,877 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:09,877 INFO L432 AbstractCegarLoop]: Abstraction has 682 states and 794 transitions. [2018-01-29 22:39:09,877 INFO L433 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-01-29 22:39:09,877 INFO L276 IsEmpty]: Start isEmpty. Operand 682 states and 794 transitions. [2018-01-29 22:39:09,878 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 243 [2018-01-29 22:39:09,878 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:09,878 INFO L350 BasicCegarLoop]: trace histogram [55, 54, 54, 54, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:09,878 INFO L371 AbstractCegarLoop]: === Iteration 57 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:09,878 INFO L82 PathProgramCache]: Analyzing trace with hash 556039554, now seen corresponding path program 54 times [2018-01-29 22:39:09,878 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:09,878 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:09,879 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:09,879 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:09,879 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:09,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:09,885 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:10,713 INFO L134 CoverageAnalysis]: Checked inductivity of 5834 backedges. 2 proven. 5832 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:10,713 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:10,713 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-29 22:39:10,726 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:10,730 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,740 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,750 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,760 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,773 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,780 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,781 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,781 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,782 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,783 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,784 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,785 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,786 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,787 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,788 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,788 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,789 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,790 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,791 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,792 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,793 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,795 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,796 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,797 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,798 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,799 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,800 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,802 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,803 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,804 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,806 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,807 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,808 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,810 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,811 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,813 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,814 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,816 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,818 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,819 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,821 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,823 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,824 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,826 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,828 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,830 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,832 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,833 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,835 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,837 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,840 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,842 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,844 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,846 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,849 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,851 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:10,852 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:10,854 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:10,890 INFO L134 CoverageAnalysis]: Checked inductivity of 5834 backedges. 2 proven. 5832 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:10,907 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:10,908 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57] total 57 [2018-01-29 22:39:10,908 INFO L409 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-01-29 22:39:10,908 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-01-29 22:39:10,908 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1596, Invalid=1596, Unknown=0, NotChecked=0, Total=3192 [2018-01-29 22:39:10,908 INFO L87 Difference]: Start difference. First operand 682 states and 794 transitions. Second operand 57 states. [2018-01-29 22:39:11,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:11,269 INFO L93 Difference]: Finished difference Result 1378 states and 1608 transitions. [2018-01-29 22:39:11,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-01-29 22:39:11,269 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 242 [2018-01-29 22:39:11,269 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:11,271 INFO L225 Difference]: With dead ends: 1378 [2018-01-29 22:39:11,271 INFO L226 Difference]: Without dead ends: 702 [2018-01-29 22:39:11,271 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 298 GetRequests, 243 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1596, Invalid=1596, Unknown=0, NotChecked=0, Total=3192 [2018-01-29 22:39:11,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 702 states. [2018-01-29 22:39:11,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 702 to 694. [2018-01-29 22:39:11,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 694 states. [2018-01-29 22:39:11,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 694 states to 694 states and 808 transitions. [2018-01-29 22:39:11,275 INFO L78 Accepts]: Start accepts. Automaton has 694 states and 808 transitions. Word has length 242 [2018-01-29 22:39:11,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:11,275 INFO L432 AbstractCegarLoop]: Abstraction has 694 states and 808 transitions. [2018-01-29 22:39:11,276 INFO L433 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-01-29 22:39:11,276 INFO L276 IsEmpty]: Start isEmpty. Operand 694 states and 808 transitions. [2018-01-29 22:39:11,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 247 [2018-01-29 22:39:11,276 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:11,276 INFO L350 BasicCegarLoop]: trace histogram [56, 55, 55, 55, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:11,277 INFO L371 AbstractCegarLoop]: === Iteration 58 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:11,277 INFO L82 PathProgramCache]: Analyzing trace with hash 1065850154, now seen corresponding path program 55 times [2018-01-29 22:39:11,277 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:11,277 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:11,277 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:11,277 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:11,277 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:11,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:11,284 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:12,183 INFO L134 CoverageAnalysis]: Checked inductivity of 6052 backedges. 2 proven. 6050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:12,183 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:12,183 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:12,189 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:39:12,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:12,207 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:12,240 INFO L134 CoverageAnalysis]: Checked inductivity of 6052 backedges. 2 proven. 6050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:12,259 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:12,259 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 58] total 58 [2018-01-29 22:39:12,259 INFO L409 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-01-29 22:39:12,259 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-01-29 22:39:12,260 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-29 22:39:12,260 INFO L87 Difference]: Start difference. First operand 694 states and 808 transitions. Second operand 58 states. [2018-01-29 22:39:12,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:12,712 INFO L93 Difference]: Finished difference Result 1402 states and 1636 transitions. [2018-01-29 22:39:12,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-01-29 22:39:12,713 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 246 [2018-01-29 22:39:12,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:12,714 INFO L225 Difference]: With dead ends: 1402 [2018-01-29 22:39:12,714 INFO L226 Difference]: Without dead ends: 714 [2018-01-29 22:39:12,715 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 303 GetRequests, 247 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-29 22:39:12,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 714 states. [2018-01-29 22:39:12,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 714 to 706. [2018-01-29 22:39:12,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 706 states. [2018-01-29 22:39:12,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 706 states to 706 states and 822 transitions. [2018-01-29 22:39:12,719 INFO L78 Accepts]: Start accepts. Automaton has 706 states and 822 transitions. Word has length 246 [2018-01-29 22:39:12,719 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:12,719 INFO L432 AbstractCegarLoop]: Abstraction has 706 states and 822 transitions. [2018-01-29 22:39:12,719 INFO L433 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-01-29 22:39:12,720 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 822 transitions. [2018-01-29 22:39:12,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 251 [2018-01-29 22:39:12,720 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:12,720 INFO L350 BasicCegarLoop]: trace histogram [57, 56, 56, 56, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:12,721 INFO L371 AbstractCegarLoop]: === Iteration 59 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:12,721 INFO L82 PathProgramCache]: Analyzing trace with hash -1043949358, now seen corresponding path program 56 times [2018-01-29 22:39:12,721 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:12,721 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:12,721 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:12,721 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:39:12,721 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:12,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:12,728 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:13,628 INFO L134 CoverageAnalysis]: Checked inductivity of 6274 backedges. 2 proven. 6272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:13,629 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:13,629 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:13,634 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:39:13,638 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:13,650 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:13,653 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:13,655 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:13,686 INFO L134 CoverageAnalysis]: Checked inductivity of 6274 backedges. 2 proven. 6272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:13,702 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:13,702 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59] total 59 [2018-01-29 22:39:13,703 INFO L409 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-01-29 22:39:13,703 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-01-29 22:39:13,703 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1711, Invalid=1711, Unknown=0, NotChecked=0, Total=3422 [2018-01-29 22:39:13,703 INFO L87 Difference]: Start difference. First operand 706 states and 822 transitions. Second operand 59 states. [2018-01-29 22:39:14,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:14,113 INFO L93 Difference]: Finished difference Result 1426 states and 1664 transitions. [2018-01-29 22:39:14,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-01-29 22:39:14,113 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 250 [2018-01-29 22:39:14,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:14,115 INFO L225 Difference]: With dead ends: 1426 [2018-01-29 22:39:14,115 INFO L226 Difference]: Without dead ends: 726 [2018-01-29 22:39:14,115 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 308 GetRequests, 251 SyntacticMatches, 0 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1711, Invalid=1711, Unknown=0, NotChecked=0, Total=3422 [2018-01-29 22:39:14,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 726 states. [2018-01-29 22:39:14,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 726 to 718. [2018-01-29 22:39:14,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 718 states. [2018-01-29 22:39:14,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 718 states to 718 states and 836 transitions. [2018-01-29 22:39:14,120 INFO L78 Accepts]: Start accepts. Automaton has 718 states and 836 transitions. Word has length 250 [2018-01-29 22:39:14,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:14,120 INFO L432 AbstractCegarLoop]: Abstraction has 718 states and 836 transitions. [2018-01-29 22:39:14,120 INFO L433 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-01-29 22:39:14,120 INFO L276 IsEmpty]: Start isEmpty. Operand 718 states and 836 transitions. [2018-01-29 22:39:14,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2018-01-29 22:39:14,121 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:14,121 INFO L350 BasicCegarLoop]: trace histogram [58, 57, 57, 57, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:14,121 INFO L371 AbstractCegarLoop]: === Iteration 60 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:14,121 INFO L82 PathProgramCache]: Analyzing trace with hash 1074497658, now seen corresponding path program 57 times [2018-01-29 22:39:14,122 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:14,122 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:14,122 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:14,122 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:14,122 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:14,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:14,129 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:15,031 INFO L134 CoverageAnalysis]: Checked inductivity of 6500 backedges. 2 proven. 6498 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:15,031 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:15,031 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:15,036 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:39:15,049 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,050 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,050 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,051 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,052 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,052 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,053 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,054 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,055 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,055 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,056 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,057 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,058 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,059 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,060 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,061 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,062 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,063 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,064 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,065 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,066 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,067 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,069 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,070 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,071 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,073 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,074 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,075 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,076 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,078 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,079 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,081 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,082 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,084 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,086 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,087 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,089 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,091 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,093 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,095 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,097 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,099 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,101 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,102 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,104 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,107 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,109 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,111 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,113 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,115 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,118 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,120 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,123 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,125 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,128 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,131 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,133 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,135 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,138 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:15,139 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:15,141 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:15,173 INFO L134 CoverageAnalysis]: Checked inductivity of 6500 backedges. 2 proven. 6498 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:15,190 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:15,190 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 60] total 60 [2018-01-29 22:39:15,190 INFO L409 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-01-29 22:39:15,191 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-01-29 22:39:15,191 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-01-29 22:39:15,191 INFO L87 Difference]: Start difference. First operand 718 states and 836 transitions. Second operand 60 states. [2018-01-29 22:39:15,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:15,731 INFO L93 Difference]: Finished difference Result 1450 states and 1692 transitions. [2018-01-29 22:39:15,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-01-29 22:39:15,731 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 254 [2018-01-29 22:39:15,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:15,733 INFO L225 Difference]: With dead ends: 1450 [2018-01-29 22:39:15,733 INFO L226 Difference]: Without dead ends: 738 [2018-01-29 22:39:15,734 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 313 GetRequests, 255 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-01-29 22:39:15,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 738 states. [2018-01-29 22:39:15,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 738 to 730. [2018-01-29 22:39:15,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 730 states. [2018-01-29 22:39:15,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 730 states to 730 states and 850 transitions. [2018-01-29 22:39:15,740 INFO L78 Accepts]: Start accepts. Automaton has 730 states and 850 transitions. Word has length 254 [2018-01-29 22:39:15,740 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:15,740 INFO L432 AbstractCegarLoop]: Abstraction has 730 states and 850 transitions. [2018-01-29 22:39:15,740 INFO L433 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-01-29 22:39:15,740 INFO L276 IsEmpty]: Start isEmpty. Operand 730 states and 850 transitions. [2018-01-29 22:39:15,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 259 [2018-01-29 22:39:15,741 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:15,741 INFO L350 BasicCegarLoop]: trace histogram [59, 58, 58, 58, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:15,741 INFO L371 AbstractCegarLoop]: === Iteration 61 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:15,741 INFO L82 PathProgramCache]: Analyzing trace with hash 763388962, now seen corresponding path program 58 times [2018-01-29 22:39:15,741 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:15,742 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:15,742 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:15,742 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:15,742 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:15,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:15,749 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:16,734 INFO L134 CoverageAnalysis]: Checked inductivity of 6730 backedges. 2 proven. 6728 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:16,734 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:16,734 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:16,740 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:39:16,767 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:16,769 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:16,806 INFO L134 CoverageAnalysis]: Checked inductivity of 6730 backedges. 2 proven. 6728 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:16,823 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:16,823 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61] total 61 [2018-01-29 22:39:16,823 INFO L409 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-01-29 22:39:16,823 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-01-29 22:39:16,823 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1830, Invalid=1830, Unknown=0, NotChecked=0, Total=3660 [2018-01-29 22:39:16,824 INFO L87 Difference]: Start difference. First operand 730 states and 850 transitions. Second operand 61 states. [2018-01-29 22:39:17,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:17,179 INFO L93 Difference]: Finished difference Result 1474 states and 1720 transitions. [2018-01-29 22:39:17,179 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-01-29 22:39:17,179 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 258 [2018-01-29 22:39:17,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:17,180 INFO L225 Difference]: With dead ends: 1474 [2018-01-29 22:39:17,180 INFO L226 Difference]: Without dead ends: 750 [2018-01-29 22:39:17,181 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 318 GetRequests, 259 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1830, Invalid=1830, Unknown=0, NotChecked=0, Total=3660 [2018-01-29 22:39:17,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 750 states. [2018-01-29 22:39:17,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 750 to 742. [2018-01-29 22:39:17,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 742 states. [2018-01-29 22:39:17,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 742 states to 742 states and 864 transitions. [2018-01-29 22:39:17,185 INFO L78 Accepts]: Start accepts. Automaton has 742 states and 864 transitions. Word has length 258 [2018-01-29 22:39:17,185 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:17,186 INFO L432 AbstractCegarLoop]: Abstraction has 742 states and 864 transitions. [2018-01-29 22:39:17,186 INFO L433 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-01-29 22:39:17,186 INFO L276 IsEmpty]: Start isEmpty. Operand 742 states and 864 transitions. [2018-01-29 22:39:17,187 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 263 [2018-01-29 22:39:17,187 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:17,187 INFO L350 BasicCegarLoop]: trace histogram [60, 59, 59, 59, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:17,187 INFO L371 AbstractCegarLoop]: === Iteration 62 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:17,187 INFO L82 PathProgramCache]: Analyzing trace with hash 1481583562, now seen corresponding path program 59 times [2018-01-29 22:39:17,187 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:17,187 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:17,187 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:17,188 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:17,188 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:17,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:17,195 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:18,185 INFO L134 CoverageAnalysis]: Checked inductivity of 6964 backedges. 2 proven. 6962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:18,186 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:18,186 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:18,190 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:39:18,193 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,194 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,195 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,195 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,196 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,197 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,197 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,198 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,199 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,200 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,200 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,201 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,202 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,203 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,204 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,205 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,206 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,207 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,208 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,209 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,210 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,211 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,212 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,213 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,214 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,215 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,217 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,218 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,219 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,221 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,222 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,223 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,225 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,226 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,228 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,229 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,231 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,232 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,234 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,236 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,238 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,239 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,241 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,243 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,245 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,247 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,248 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,250 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,252 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,254 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,256 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,258 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,260 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,262 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,265 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,267 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,269 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,271 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,274 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,276 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:18,277 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:18,279 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:18,312 INFO L134 CoverageAnalysis]: Checked inductivity of 6964 backedges. 2 proven. 6962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:18,329 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:18,329 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 62] total 62 [2018-01-29 22:39:18,329 INFO L409 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-01-29 22:39:18,329 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-01-29 22:39:18,329 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-29 22:39:18,329 INFO L87 Difference]: Start difference. First operand 742 states and 864 transitions. Second operand 62 states. [2018-01-29 22:39:18,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:18,772 INFO L93 Difference]: Finished difference Result 1498 states and 1748 transitions. [2018-01-29 22:39:18,772 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-01-29 22:39:18,773 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 262 [2018-01-29 22:39:18,773 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:18,774 INFO L225 Difference]: With dead ends: 1498 [2018-01-29 22:39:18,774 INFO L226 Difference]: Without dead ends: 762 [2018-01-29 22:39:18,775 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 323 GetRequests, 263 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-29 22:39:18,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 762 states. [2018-01-29 22:39:18,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 762 to 754. [2018-01-29 22:39:18,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 754 states. [2018-01-29 22:39:18,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 754 states to 754 states and 878 transitions. [2018-01-29 22:39:18,779 INFO L78 Accepts]: Start accepts. Automaton has 754 states and 878 transitions. Word has length 262 [2018-01-29 22:39:18,779 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:18,779 INFO L432 AbstractCegarLoop]: Abstraction has 754 states and 878 transitions. [2018-01-29 22:39:18,779 INFO L433 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-01-29 22:39:18,780 INFO L276 IsEmpty]: Start isEmpty. Operand 754 states and 878 transitions. [2018-01-29 22:39:18,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 267 [2018-01-29 22:39:18,780 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:18,780 INFO L350 BasicCegarLoop]: trace histogram [61, 60, 60, 60, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:18,781 INFO L371 AbstractCegarLoop]: === Iteration 63 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:18,781 INFO L82 PathProgramCache]: Analyzing trace with hash 1772216178, now seen corresponding path program 60 times [2018-01-29 22:39:18,781 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:18,781 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:18,781 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:18,781 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:18,781 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:18,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:18,788 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:19,786 INFO L134 CoverageAnalysis]: Checked inductivity of 7202 backedges. 2 proven. 7200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:19,787 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:19,787 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:19,792 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:39:19,796 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,796 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,797 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,798 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,799 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,799 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,800 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,801 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,801 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,802 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,803 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,804 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,805 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,806 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,807 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,808 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,809 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,810 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,811 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,812 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,813 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,814 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,815 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,816 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,817 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,818 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,820 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,821 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,822 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,823 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,825 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,826 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,828 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,829 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,831 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,832 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,834 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,835 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,837 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,839 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,841 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,843 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,844 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,846 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,848 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,850 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,852 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,854 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,856 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,858 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,860 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,862 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,865 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,867 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,870 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,872 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,874 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,876 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,878 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,881 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,884 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,887 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:19,888 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:19,890 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:19,931 INFO L134 CoverageAnalysis]: Checked inductivity of 7202 backedges. 2 proven. 7200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:19,948 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:19,948 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 63] total 63 [2018-01-29 22:39:19,948 INFO L409 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-01-29 22:39:19,948 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-01-29 22:39:19,948 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1953, Invalid=1953, Unknown=0, NotChecked=0, Total=3906 [2018-01-29 22:39:19,948 INFO L87 Difference]: Start difference. First operand 754 states and 878 transitions. Second operand 63 states. [2018-01-29 22:39:20,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:20,357 INFO L93 Difference]: Finished difference Result 1522 states and 1776 transitions. [2018-01-29 22:39:20,357 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-01-29 22:39:20,358 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 266 [2018-01-29 22:39:20,358 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:20,359 INFO L225 Difference]: With dead ends: 1522 [2018-01-29 22:39:20,359 INFO L226 Difference]: Without dead ends: 774 [2018-01-29 22:39:20,360 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 328 GetRequests, 267 SyntacticMatches, 0 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1953, Invalid=1953, Unknown=0, NotChecked=0, Total=3906 [2018-01-29 22:39:20,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 774 states. [2018-01-29 22:39:20,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 774 to 766. [2018-01-29 22:39:20,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 766 states. [2018-01-29 22:39:20,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 766 states to 766 states and 892 transitions. [2018-01-29 22:39:20,364 INFO L78 Accepts]: Start accepts. Automaton has 766 states and 892 transitions. Word has length 266 [2018-01-29 22:39:20,364 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:20,364 INFO L432 AbstractCegarLoop]: Abstraction has 766 states and 892 transitions. [2018-01-29 22:39:20,364 INFO L433 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-01-29 22:39:20,364 INFO L276 IsEmpty]: Start isEmpty. Operand 766 states and 892 transitions. [2018-01-29 22:39:20,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 271 [2018-01-29 22:39:20,365 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:20,365 INFO L350 BasicCegarLoop]: trace histogram [62, 61, 61, 61, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:20,365 INFO L371 AbstractCegarLoop]: === Iteration 64 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:20,365 INFO L82 PathProgramCache]: Analyzing trace with hash 1705148186, now seen corresponding path program 61 times [2018-01-29 22:39:20,366 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:20,366 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:20,366 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:20,366 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:20,366 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:20,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:20,374 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:21,434 INFO L134 CoverageAnalysis]: Checked inductivity of 7444 backedges. 2 proven. 7442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:21,434 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:21,434 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:21,439 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:39:21,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:21,460 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:21,496 INFO L134 CoverageAnalysis]: Checked inductivity of 7444 backedges. 2 proven. 7442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:21,513 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:21,513 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 64] total 64 [2018-01-29 22:39:21,514 INFO L409 AbstractCegarLoop]: Interpolant automaton has 64 states [2018-01-29 22:39:21,514 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2018-01-29 22:39:21,514 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-29 22:39:21,514 INFO L87 Difference]: Start difference. First operand 766 states and 892 transitions. Second operand 64 states. [2018-01-29 22:39:22,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:22,106 INFO L93 Difference]: Finished difference Result 1546 states and 1804 transitions. [2018-01-29 22:39:22,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2018-01-29 22:39:22,106 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 270 [2018-01-29 22:39:22,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:22,107 INFO L225 Difference]: With dead ends: 1546 [2018-01-29 22:39:22,107 INFO L226 Difference]: Without dead ends: 786 [2018-01-29 22:39:22,108 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 333 GetRequests, 271 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-29 22:39:22,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 786 states. [2018-01-29 22:39:22,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 786 to 778. [2018-01-29 22:39:22,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 778 states. [2018-01-29 22:39:22,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 778 states to 778 states and 906 transitions. [2018-01-29 22:39:22,113 INFO L78 Accepts]: Start accepts. Automaton has 778 states and 906 transitions. Word has length 270 [2018-01-29 22:39:22,113 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:22,113 INFO L432 AbstractCegarLoop]: Abstraction has 778 states and 906 transitions. [2018-01-29 22:39:22,113 INFO L433 AbstractCegarLoop]: Interpolant automaton has 64 states. [2018-01-29 22:39:22,113 INFO L276 IsEmpty]: Start isEmpty. Operand 778 states and 906 transitions. [2018-01-29 22:39:22,114 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 275 [2018-01-29 22:39:22,114 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:22,114 INFO L350 BasicCegarLoop]: trace histogram [63, 62, 62, 62, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:22,114 INFO L371 AbstractCegarLoop]: === Iteration 65 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:22,114 INFO L82 PathProgramCache]: Analyzing trace with hash 729483970, now seen corresponding path program 62 times [2018-01-29 22:39:22,114 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:22,114 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:22,115 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:22,115 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:39:22,115 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:22,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:22,123 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:23,215 INFO L134 CoverageAnalysis]: Checked inductivity of 7690 backedges. 2 proven. 7688 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:23,216 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:23,216 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:23,221 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 22:39:23,224 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:23,236 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:23,240 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:23,243 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:23,281 INFO L134 CoverageAnalysis]: Checked inductivity of 7690 backedges. 2 proven. 7688 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:23,299 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:23,299 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 65] total 65 [2018-01-29 22:39:23,299 INFO L409 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-01-29 22:39:23,299 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-01-29 22:39:23,300 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2080, Invalid=2080, Unknown=0, NotChecked=0, Total=4160 [2018-01-29 22:39:23,300 INFO L87 Difference]: Start difference. First operand 778 states and 906 transitions. Second operand 65 states. [2018-01-29 22:39:23,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:23,831 INFO L93 Difference]: Finished difference Result 1570 states and 1832 transitions. [2018-01-29 22:39:23,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-01-29 22:39:23,831 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 274 [2018-01-29 22:39:23,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:23,832 INFO L225 Difference]: With dead ends: 1570 [2018-01-29 22:39:23,833 INFO L226 Difference]: Without dead ends: 798 [2018-01-29 22:39:23,833 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 275 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=2080, Invalid=2080, Unknown=0, NotChecked=0, Total=4160 [2018-01-29 22:39:23,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 798 states. [2018-01-29 22:39:23,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 798 to 790. [2018-01-29 22:39:23,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 790 states. [2018-01-29 22:39:23,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 790 states and 920 transitions. [2018-01-29 22:39:23,838 INFO L78 Accepts]: Start accepts. Automaton has 790 states and 920 transitions. Word has length 274 [2018-01-29 22:39:23,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:23,838 INFO L432 AbstractCegarLoop]: Abstraction has 790 states and 920 transitions. [2018-01-29 22:39:23,838 INFO L433 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-01-29 22:39:23,839 INFO L276 IsEmpty]: Start isEmpty. Operand 790 states and 920 transitions. [2018-01-29 22:39:23,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 279 [2018-01-29 22:39:23,839 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:23,840 INFO L350 BasicCegarLoop]: trace histogram [64, 63, 63, 63, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:23,840 INFO L371 AbstractCegarLoop]: === Iteration 66 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:23,840 INFO L82 PathProgramCache]: Analyzing trace with hash -178945430, now seen corresponding path program 63 times [2018-01-29 22:39:23,840 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:23,840 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:23,841 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:23,841 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:23,841 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:23,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:23,851 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:24,950 INFO L134 CoverageAnalysis]: Checked inductivity of 7940 backedges. 2 proven. 7938 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:24,950 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:24,950 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:24,957 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 22:39:24,962 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,963 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,963 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,964 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,965 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,966 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,966 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,967 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,968 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,969 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,970 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,971 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,972 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,973 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,974 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,975 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,976 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,977 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,978 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,979 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,980 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,981 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,983 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,984 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,985 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,987 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,988 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,989 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,991 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,992 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,994 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,995 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,997 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:24,998 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,000 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,002 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,003 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,005 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,007 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,008 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,011 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,012 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,014 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,016 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,018 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,020 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,022 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,024 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,026 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,028 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,031 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,033 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,035 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,037 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,040 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,042 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,044 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,047 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,049 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,052 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,054 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,057 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,059 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,062 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,065 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 22:39:25,066 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:25,068 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:25,112 INFO L134 CoverageAnalysis]: Checked inductivity of 7940 backedges. 2 proven. 7938 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:25,129 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:25,129 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 66] total 66 [2018-01-29 22:39:25,130 INFO L409 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-01-29 22:39:25,130 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-01-29 22:39:25,130 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-01-29 22:39:25,130 INFO L87 Difference]: Start difference. First operand 790 states and 920 transitions. Second operand 66 states. [2018-01-29 22:39:25,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:25,702 INFO L93 Difference]: Finished difference Result 1594 states and 1860 transitions. [2018-01-29 22:39:25,702 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-01-29 22:39:25,702 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 278 [2018-01-29 22:39:25,702 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:25,704 INFO L225 Difference]: With dead ends: 1594 [2018-01-29 22:39:25,704 INFO L226 Difference]: Without dead ends: 810 [2018-01-29 22:39:25,704 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 279 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-01-29 22:39:25,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 810 states. [2018-01-29 22:39:25,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 810 to 802. [2018-01-29 22:39:25,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 802 states. [2018-01-29 22:39:25,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 802 states to 802 states and 934 transitions. [2018-01-29 22:39:25,709 INFO L78 Accepts]: Start accepts. Automaton has 802 states and 934 transitions. Word has length 278 [2018-01-29 22:39:25,710 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:25,710 INFO L432 AbstractCegarLoop]: Abstraction has 802 states and 934 transitions. [2018-01-29 22:39:25,710 INFO L433 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-01-29 22:39:25,710 INFO L276 IsEmpty]: Start isEmpty. Operand 802 states and 934 transitions. [2018-01-29 22:39:25,711 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 283 [2018-01-29 22:39:25,711 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:25,711 INFO L350 BasicCegarLoop]: trace histogram [65, 64, 64, 64, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:25,711 INFO L371 AbstractCegarLoop]: === Iteration 67 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:25,711 INFO L82 PathProgramCache]: Analyzing trace with hash -665065966, now seen corresponding path program 64 times [2018-01-29 22:39:25,711 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:25,711 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:25,711 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:25,712 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:25,712 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:25,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:25,720 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:26,899 INFO L134 CoverageAnalysis]: Checked inductivity of 8194 backedges. 2 proven. 8192 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:26,900 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:26,900 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:26,906 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 22:39:26,929 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:26,931 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:26,971 INFO L134 CoverageAnalysis]: Checked inductivity of 8194 backedges. 2 proven. 8192 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:26,988 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:26,988 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [67, 67] total 67 [2018-01-29 22:39:26,988 INFO L409 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-01-29 22:39:26,989 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-01-29 22:39:26,989 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2211, Invalid=2211, Unknown=0, NotChecked=0, Total=4422 [2018-01-29 22:39:26,989 INFO L87 Difference]: Start difference. First operand 802 states and 934 transitions. Second operand 67 states. [2018-01-29 22:39:27,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:27,544 INFO L93 Difference]: Finished difference Result 1618 states and 1888 transitions. [2018-01-29 22:39:27,544 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-01-29 22:39:27,544 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 282 [2018-01-29 22:39:27,544 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:27,546 INFO L225 Difference]: With dead ends: 1618 [2018-01-29 22:39:27,546 INFO L226 Difference]: Without dead ends: 822 [2018-01-29 22:39:27,547 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 348 GetRequests, 283 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2211, Invalid=2211, Unknown=0, NotChecked=0, Total=4422 [2018-01-29 22:39:27,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 822 states. [2018-01-29 22:39:27,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 822 to 814. [2018-01-29 22:39:27,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 814 states. [2018-01-29 22:39:27,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 814 states to 814 states and 948 transitions. [2018-01-29 22:39:27,561 INFO L78 Accepts]: Start accepts. Automaton has 814 states and 948 transitions. Word has length 282 [2018-01-29 22:39:27,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:27,561 INFO L432 AbstractCegarLoop]: Abstraction has 814 states and 948 transitions. [2018-01-29 22:39:27,561 INFO L433 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-01-29 22:39:27,561 INFO L276 IsEmpty]: Start isEmpty. Operand 814 states and 948 transitions. [2018-01-29 22:39:27,562 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 287 [2018-01-29 22:39:27,562 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:27,562 INFO L350 BasicCegarLoop]: trace histogram [66, 65, 65, 65, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:27,562 INFO L371 AbstractCegarLoop]: === Iteration 68 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:27,563 INFO L82 PathProgramCache]: Analyzing trace with hash 1152923066, now seen corresponding path program 65 times [2018-01-29 22:39:27,563 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:27,563 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:27,563 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:27,563 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:27,563 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:27,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:27,572 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:28,743 INFO L134 CoverageAnalysis]: Checked inductivity of 8452 backedges. 2 proven. 8450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:28,743 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:28,743 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:28,747 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 22:39:28,751 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,757 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,760 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,761 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,762 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,763 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,763 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,764 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,765 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,766 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,766 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,767 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,768 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,769 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,770 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,771 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,772 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,773 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,774 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,776 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,777 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,778 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,779 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,780 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,781 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,783 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,784 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,785 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,787 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,788 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,790 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,791 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,793 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,795 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,796 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,798 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,799 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,801 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,802 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,804 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,806 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,808 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,810 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,811 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,813 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,815 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,817 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,819 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,821 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,823 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,825 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,827 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,830 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,832 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,834 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,837 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,839 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,842 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,844 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,846 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,849 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,852 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,854 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,857 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,860 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,863 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 22:39:28,864 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:28,866 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:28,906 INFO L134 CoverageAnalysis]: Checked inductivity of 8452 backedges. 2 proven. 8450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:28,923 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:28,923 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 68] total 68 [2018-01-29 22:39:28,924 INFO L409 AbstractCegarLoop]: Interpolant automaton has 68 states [2018-01-29 22:39:28,924 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2018-01-29 22:39:28,924 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-01-29 22:39:28,924 INFO L87 Difference]: Start difference. First operand 814 states and 948 transitions. Second operand 68 states. [2018-01-29 22:39:29,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:29,455 INFO L93 Difference]: Finished difference Result 1642 states and 1916 transitions. [2018-01-29 22:39:29,455 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-01-29 22:39:29,455 INFO L78 Accepts]: Start accepts. Automaton has 68 states. Word has length 286 [2018-01-29 22:39:29,456 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:29,457 INFO L225 Difference]: With dead ends: 1642 [2018-01-29 22:39:29,457 INFO L226 Difference]: Without dead ends: 834 [2018-01-29 22:39:29,458 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 353 GetRequests, 287 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-01-29 22:39:29,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 834 states. [2018-01-29 22:39:29,462 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 834 to 826. [2018-01-29 22:39:29,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 826 states. [2018-01-29 22:39:29,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 826 states to 826 states and 962 transitions. [2018-01-29 22:39:29,463 INFO L78 Accepts]: Start accepts. Automaton has 826 states and 962 transitions. Word has length 286 [2018-01-29 22:39:29,463 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:29,463 INFO L432 AbstractCegarLoop]: Abstraction has 826 states and 962 transitions. [2018-01-29 22:39:29,463 INFO L433 AbstractCegarLoop]: Interpolant automaton has 68 states. [2018-01-29 22:39:29,463 INFO L276 IsEmpty]: Start isEmpty. Operand 826 states and 962 transitions. [2018-01-29 22:39:29,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 291 [2018-01-29 22:39:29,464 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:29,464 INFO L350 BasicCegarLoop]: trace histogram [67, 66, 66, 66, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:29,464 INFO L371 AbstractCegarLoop]: === Iteration 69 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:29,464 INFO L82 PathProgramCache]: Analyzing trace with hash -2053869214, now seen corresponding path program 66 times [2018-01-29 22:39:29,464 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:29,464 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:29,465 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:29,465 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:29,465 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:29,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:29,473 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:30,891 INFO L134 CoverageAnalysis]: Checked inductivity of 8714 backedges. 2 proven. 8712 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:30,892 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:30,892 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:30,896 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 22:39:30,901 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,902 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,902 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,903 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,904 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,904 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,905 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,906 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,907 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,907 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,908 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,909 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,910 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,911 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,912 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,913 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,914 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,915 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,916 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,917 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,918 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,919 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,920 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,921 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,922 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,924 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,925 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,926 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,927 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,928 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,930 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,931 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,932 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,934 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,935 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,937 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,938 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,940 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,941 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,943 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,944 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,946 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,948 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,949 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,951 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,953 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,955 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,956 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,958 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,960 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,962 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,964 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,966 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,968 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,970 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,972 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,974 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,976 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,978 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,980 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,983 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,985 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,987 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,989 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,992 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,994 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,996 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:30,999 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 22:39:31,000 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 22:39:31,002 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:31,043 INFO L134 CoverageAnalysis]: Checked inductivity of 8714 backedges. 2 proven. 8712 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:31,060 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:31,060 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [69, 69] total 69 [2018-01-29 22:39:31,061 INFO L409 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-01-29 22:39:31,061 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-01-29 22:39:31,061 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2346, Invalid=2346, Unknown=0, NotChecked=0, Total=4692 [2018-01-29 22:39:31,061 INFO L87 Difference]: Start difference. First operand 826 states and 962 transitions. Second operand 69 states. [2018-01-29 22:39:31,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:31,653 INFO L93 Difference]: Finished difference Result 1666 states and 1944 transitions. [2018-01-29 22:39:31,654 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-01-29 22:39:31,654 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 290 [2018-01-29 22:39:31,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:31,655 INFO L225 Difference]: With dead ends: 1666 [2018-01-29 22:39:31,655 INFO L226 Difference]: Without dead ends: 846 [2018-01-29 22:39:31,656 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 358 GetRequests, 291 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=2346, Invalid=2346, Unknown=0, NotChecked=0, Total=4692 [2018-01-29 22:39:31,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 846 states. [2018-01-29 22:39:31,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 846 to 838. [2018-01-29 22:39:31,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 838 states. [2018-01-29 22:39:31,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 976 transitions. [2018-01-29 22:39:31,662 INFO L78 Accepts]: Start accepts. Automaton has 838 states and 976 transitions. Word has length 290 [2018-01-29 22:39:31,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:31,662 INFO L432 AbstractCegarLoop]: Abstraction has 838 states and 976 transitions. [2018-01-29 22:39:31,662 INFO L433 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-01-29 22:39:31,662 INFO L276 IsEmpty]: Start isEmpty. Operand 838 states and 976 transitions. [2018-01-29 22:39:31,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 295 [2018-01-29 22:39:31,663 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:31,663 INFO L350 BasicCegarLoop]: trace histogram [68, 67, 67, 67, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:31,663 INFO L371 AbstractCegarLoop]: === Iteration 70 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:31,663 INFO L82 PathProgramCache]: Analyzing trace with hash 1092262154, now seen corresponding path program 67 times [2018-01-29 22:39:31,663 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:31,663 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:31,664 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:31,664 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 22:39:31,664 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:31,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:31,673 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 22:39:32,944 INFO L134 CoverageAnalysis]: Checked inductivity of 8980 backedges. 2 proven. 8978 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:32,944 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 22:39:32,944 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 22:39:32,949 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:39:32,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:32,971 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 22:39:33,022 INFO L134 CoverageAnalysis]: Checked inductivity of 8980 backedges. 2 proven. 8978 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 22:39:33,039 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 22:39:33,039 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 70] total 70 [2018-01-29 22:39:33,039 INFO L409 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-01-29 22:39:33,039 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-01-29 22:39:33,040 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2018-01-29 22:39:33,040 INFO L87 Difference]: Start difference. First operand 838 states and 976 transitions. Second operand 70 states. [2018-01-29 22:39:33,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 22:39:33,634 INFO L93 Difference]: Finished difference Result 1690 states and 1972 transitions. [2018-01-29 22:39:33,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2018-01-29 22:39:33,634 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 294 [2018-01-29 22:39:33,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 22:39:33,635 INFO L225 Difference]: With dead ends: 1690 [2018-01-29 22:39:33,635 INFO L226 Difference]: Without dead ends: 858 [2018-01-29 22:39:33,636 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 363 GetRequests, 295 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2018-01-29 22:39:33,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 858 states. [2018-01-29 22:39:33,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 858 to 850. [2018-01-29 22:39:33,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 850 states. [2018-01-29 22:39:33,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 850 states to 850 states and 990 transitions. [2018-01-29 22:39:33,642 INFO L78 Accepts]: Start accepts. Automaton has 850 states and 990 transitions. Word has length 294 [2018-01-29 22:39:33,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 22:39:33,642 INFO L432 AbstractCegarLoop]: Abstraction has 850 states and 990 transitions. [2018-01-29 22:39:33,642 INFO L433 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-01-29 22:39:33,642 INFO L276 IsEmpty]: Start isEmpty. Operand 850 states and 990 transitions. [2018-01-29 22:39:33,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 299 [2018-01-29 22:39:33,643 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 22:39:33,643 INFO L350 BasicCegarLoop]: trace histogram [69, 68, 68, 68, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 22:39:33,643 INFO L371 AbstractCegarLoop]: === Iteration 71 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 22:39:33,643 INFO L82 PathProgramCache]: Analyzing trace with hash -126571342, now seen corresponding path program 68 times [2018-01-29 22:39:33,643 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 22:39:33,643 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 22:39:33,644 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:33,644 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 22:39:33,644 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 22:39:33,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 22:39:33,653 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. Received shutdown request... [2018-01-29 22:39:33,899 FATAL L265 ToolchainWalker]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: Timeout exceeded at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.walkLeafNode(Interpolator.java:265) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.access$1(Interpolator.java:263) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator$ProofTreeWalker.walk(Interpolator.java:132) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:122) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:113) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.interpolate(Interpolator.java:220) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.getInterpolants(Interpolator.java:201) at de.uni_freiburg.informatik.ultimate.smtinterpol.smtlib2.SMTInterpol.getInterpolants(SMTInterpol.java:915) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.managedscript.ManagedScript.getInterpolants(ManagedScript.java:192) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.NestedInterpolantsBuilder.computeCraigInterpolants(NestedInterpolantsBuilder.java:281) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.NestedInterpolantsBuilder.(NestedInterpolantsBuilder.java:164) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.computeInterpolantsTree(InterpolatingTraceCheckCraig.java:263) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.computeInterpolants(InterpolatingTraceCheckCraig.java:199) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.(InterpolatingTraceCheckCraig.java:106) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructCraig(TraceCheckConstructor.java:222) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.get(TraceCheckConstructor.java:179) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.MultiTrackTraceAbstractionRefinementStrategy.getTraceCheck(MultiTrackTraceAbstractionRefinementStrategy.java:218) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.checkFeasibility(BaseRefinementStrategy.java:231) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.executeStrategy(BaseRefinementStrategy.java:205) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:68) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:396) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:381) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:316) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:292) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:147) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:115) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:119) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:324) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.runToolchainDefault(DefaultToolchainJob.java:221) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.BasicToolchainJob.run(BasicToolchainJob.java:134) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) [2018-01-29 22:39:33,902 INFO L168 Benchmark]: Toolchain (without parser) took 67517.38 ms. Allocated memory was 146.8 MB in the beginning and 1.1 GB in the end (delta: 929.0 MB). Free memory was 111.9 MB in the beginning and 1.0 GB in the end (delta: -904.1 MB). Peak memory consumption was 955.6 MB. Max. memory is 5.3 GB. [2018-01-29 22:39:33,903 INFO L168 Benchmark]: CDTParser took 0.09 ms. Allocated memory is still 146.8 MB. Free memory is still 116.6 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-29 22:39:33,903 INFO L168 Benchmark]: CACSL2BoogieTranslator took 103.83 ms. Allocated memory is still 146.8 MB. Free memory was 111.7 MB in the beginning and 103.5 MB in the end (delta: 8.2 MB). Peak memory consumption was 8.2 MB. Max. memory is 5.3 GB. [2018-01-29 22:39:33,904 INFO L168 Benchmark]: Boogie Preprocessor took 17.99 ms. Allocated memory is still 146.8 MB. Free memory was 103.5 MB in the beginning and 102.1 MB in the end (delta: 1.4 MB). Peak memory consumption was 1.4 MB. Max. memory is 5.3 GB. [2018-01-29 22:39:33,904 INFO L168 Benchmark]: RCFGBuilder took 417.03 ms. Allocated memory is still 146.8 MB. Free memory was 101.8 MB in the beginning and 88.9 MB in the end (delta: 12.9 MB). Peak memory consumption was 12.9 MB. Max. memory is 5.3 GB. [2018-01-29 22:39:33,904 INFO L168 Benchmark]: TraceAbstraction took 66976.22 ms. Allocated memory was 146.8 MB in the beginning and 1.1 GB in the end (delta: 929.0 MB). Free memory was 88.7 MB in the beginning and 1.0 GB in the end (delta: -927.3 MB). Peak memory consumption was 932.4 MB. Max. memory is 5.3 GB. [2018-01-29 22:39:33,905 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.09 ms. Allocated memory is still 146.8 MB. Free memory is still 116.6 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 103.83 ms. Allocated memory is still 146.8 MB. Free memory was 111.7 MB in the beginning and 103.5 MB in the end (delta: 8.2 MB). Peak memory consumption was 8.2 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 17.99 ms. Allocated memory is still 146.8 MB. Free memory was 103.5 MB in the beginning and 102.1 MB in the end (delta: 1.4 MB). Peak memory consumption was 1.4 MB. Max. memory is 5.3 GB. * RCFGBuilder took 417.03 ms. Allocated memory is still 146.8 MB. Free memory was 101.8 MB in the beginning and 88.9 MB in the end (delta: 12.9 MB). Peak memory consumption was 12.9 MB. Max. memory is 5.3 GB. * TraceAbstraction took 66976.22 ms. Allocated memory was 146.8 MB in the beginning and 1.1 GB in the end (delta: 929.0 MB). Free memory was 88.7 MB in the beginning and 1.0 GB in the end (delta: -927.3 MB). Peak memory consumption was 932.4 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: Timeout exceeded de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: Timeout exceeded: de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.walkLeafNode(Interpolator.java:265) RESULT: Ultimate could not prove your program: Toolchain returned no result. Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sorting_bubblesort_false-unreach-call_ground.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-29_22-39-33-913.csv Completed graceful shutdown