java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/array-examples/standard_init1_true-unreach-call_ground.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-1cceb4a-m [2018-01-29 23:37:37,567 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-29 23:37:37,569 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-29 23:37:37,581 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-29 23:37:37,581 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-29 23:37:37,582 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-29 23:37:37,582 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-29 23:37:37,584 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-29 23:37:37,585 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-29 23:37:37,586 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-29 23:37:37,586 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-29 23:37:37,586 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-29 23:37:37,587 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-29 23:37:37,587 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-29 23:37:37,588 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-29 23:37:37,589 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-29 23:37:37,591 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-29 23:37:37,592 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-29 23:37:37,592 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-29 23:37:37,596 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-29 23:37:37,597 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-29 23:37:37,597 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-29 23:37:37,597 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-29 23:37:37,598 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-29 23:37:37,598 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-29 23:37:37,599 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-29 23:37:37,599 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-29 23:37:37,599 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-29 23:37:37,602 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-29 23:37:37,602 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-29 23:37:37,603 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-29 23:37:37,603 INFO L98 SettingsManager]: Beginning loading settings from /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf [2018-01-29 23:37:37,611 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-29 23:37:37,611 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-29 23:37:37,611 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-29 23:37:37,611 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-29 23:37:37,611 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-29 23:37:37,611 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-29 23:37:37,612 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-29 23:37:37,612 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-29 23:37:37,612 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-29 23:37:37,612 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-29 23:37:37,612 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-29 23:37:37,612 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-29 23:37:37,612 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-01-29 23:37:37,612 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-29 23:37:37,612 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-01-29 23:37:37,612 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-29 23:37:37,613 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-01-29 23:37:37,613 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-01-29 23:37:37,614 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-29 23:37:37,614 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-01-29 23:37:37,614 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-29 23:37:37,614 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-29 23:37:37,614 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-29 23:37:37,614 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-29 23:37:37,614 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-29 23:37:37,614 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-29 23:37:37,614 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-29 23:37:37,614 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-29 23:37:37,615 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-29 23:37:37,615 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-29 23:37:37,615 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-29 23:37:37,615 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-29 23:37:37,615 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-29 23:37:37,615 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-29 23:37:37,639 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-29 23:37:37,647 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-29 23:37:37,649 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-29 23:37:37,652 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-29 23:37:37,652 INFO L276 PluginConnector]: CDTParser initialized [2018-01-29 23:37:37,653 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/standard_init1_true-unreach-call_ground.i [2018-01-29 23:37:37,715 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-29 23:37:37,715 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-29 23:37:37,716 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-29 23:37:37,716 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-29 23:37:37,720 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-29 23:37:37,720 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.01 11:37:37" (1/1) ... [2018-01-29 23:37:37,722 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@575e8500 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 11:37:37, skipping insertion in model container [2018-01-29 23:37:37,722 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.01 11:37:37" (1/1) ... [2018-01-29 23:37:37,731 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-29 23:37:37,739 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-29 23:37:37,817 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-29 23:37:37,825 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-29 23:37:37,828 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 11:37:37 WrapperNode [2018-01-29 23:37:37,828 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-29 23:37:37,829 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-29 23:37:37,829 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-29 23:37:37,829 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-29 23:37:37,837 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 11:37:37" (1/1) ... [2018-01-29 23:37:37,837 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 11:37:37" (1/1) ... [2018-01-29 23:37:37,842 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 11:37:37" (1/1) ... [2018-01-29 23:37:37,842 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 11:37:37" (1/1) ... [2018-01-29 23:37:37,842 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 11:37:37" (1/1) ... [2018-01-29 23:37:37,845 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 11:37:37" (1/1) ... [2018-01-29 23:37:37,845 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 11:37:37" (1/1) ... [2018-01-29 23:37:37,846 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-29 23:37:37,846 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-29 23:37:37,846 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-29 23:37:37,846 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-29 23:37:37,847 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 11:37:37" (1/1) ... No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-29 23:37:37,889 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-29 23:37:37,889 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-29 23:37:37,889 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-29 23:37:37,889 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-29 23:37:37,889 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-29 23:37:37,889 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-29 23:37:37,889 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-29 23:37:37,890 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-29 23:37:37,890 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-29 23:37:38,176 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-29 23:37:38,177 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.01 11:37:38 BoogieIcfgContainer [2018-01-29 23:37:38,177 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-29 23:37:38,177 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-29 23:37:38,177 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-29 23:37:38,179 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-29 23:37:38,179 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 29.01 11:37:37" (1/3) ... [2018-01-29 23:37:38,180 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1c4bdab1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 29.01 11:37:38, skipping insertion in model container [2018-01-29 23:37:38,180 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.01 11:37:37" (2/3) ... [2018-01-29 23:37:38,180 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1c4bdab1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 29.01 11:37:38, skipping insertion in model container [2018-01-29 23:37:38,180 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.01 11:37:38" (3/3) ... [2018-01-29 23:37:38,181 INFO L107 eAbstractionObserver]: Analyzing ICFG standard_init1_true-unreach-call_ground.i [2018-01-29 23:37:38,186 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-29 23:37:38,190 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-01-29 23:37:38,213 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-29 23:37:38,213 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-29 23:37:38,213 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-29 23:37:38,213 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-29 23:37:38,214 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-29 23:37:38,214 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-29 23:37:38,214 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-29 23:37:38,214 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-29 23:37:38,214 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-29 23:37:38,223 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states. [2018-01-29 23:37:38,227 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-01-29 23:37:38,227 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:38,227 INFO L350 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:38,227 INFO L371 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:38,230 INFO L82 PathProgramCache]: Analyzing trace with hash -867029826, now seen corresponding path program 1 times [2018-01-29 23:37:38,231 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:38,231 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:38,258 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:38,259 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:38,259 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:38,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:38,278 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:38,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:38,294 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-29 23:37:38,294 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-29 23:37:38,295 INFO L409 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-01-29 23:37:38,302 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-01-29 23:37:38,303 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-29 23:37:38,304 INFO L87 Difference]: Start difference. First operand 29 states. Second operand 2 states. [2018-01-29 23:37:38,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:38,316 INFO L93 Difference]: Finished difference Result 48 states and 54 transitions. [2018-01-29 23:37:38,316 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-01-29 23:37:38,317 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 15 [2018-01-29 23:37:38,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:38,322 INFO L225 Difference]: With dead ends: 48 [2018-01-29 23:37:38,322 INFO L226 Difference]: Without dead ends: 24 [2018-01-29 23:37:38,324 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-29 23:37:38,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2018-01-29 23:37:38,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2018-01-29 23:37:38,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-01-29 23:37:38,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 26 transitions. [2018-01-29 23:37:38,344 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 26 transitions. Word has length 15 [2018-01-29 23:37:38,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:38,344 INFO L432 AbstractCegarLoop]: Abstraction has 24 states and 26 transitions. [2018-01-29 23:37:38,344 INFO L433 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-01-29 23:37:38,344 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 26 transitions. [2018-01-29 23:37:38,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-01-29 23:37:38,345 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:38,345 INFO L350 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:38,345 INFO L371 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:38,345 INFO L82 PathProgramCache]: Analyzing trace with hash 1267176939, now seen corresponding path program 1 times [2018-01-29 23:37:38,345 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:38,345 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:38,346 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:38,346 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:38,346 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:38,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:38,351 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:38,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:38,402 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-29 23:37:38,402 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-29 23:37:38,403 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-29 23:37:38,403 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-29 23:37:38,403 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-29 23:37:38,403 INFO L87 Difference]: Start difference. First operand 24 states and 26 transitions. Second operand 3 states. [2018-01-29 23:37:38,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:38,444 INFO L93 Difference]: Finished difference Result 42 states and 46 transitions. [2018-01-29 23:37:38,444 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-29 23:37:38,444 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 16 [2018-01-29 23:37:38,444 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:38,445 INFO L225 Difference]: With dead ends: 42 [2018-01-29 23:37:38,445 INFO L226 Difference]: Without dead ends: 28 [2018-01-29 23:37:38,446 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-29 23:37:38,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-01-29 23:37:38,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 26. [2018-01-29 23:37:38,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-01-29 23:37:38,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 28 transitions. [2018-01-29 23:37:38,448 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 28 transitions. Word has length 16 [2018-01-29 23:37:38,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:38,448 INFO L432 AbstractCegarLoop]: Abstraction has 26 states and 28 transitions. [2018-01-29 23:37:38,449 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-29 23:37:38,449 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 28 transitions. [2018-01-29 23:37:38,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-01-29 23:37:38,449 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:38,449 INFO L350 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:38,449 INFO L371 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:38,449 INFO L82 PathProgramCache]: Analyzing trace with hash -1171211310, now seen corresponding path program 1 times [2018-01-29 23:37:38,449 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:38,450 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:38,457 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:38,457 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:38,457 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:38,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:38,467 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:38,507 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:38,507 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:38,508 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:38,520 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:38,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:38,585 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:38,596 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:38,612 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:38,612 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2018-01-29 23:37:38,613 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-29 23:37:38,613 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-29 23:37:38,613 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-29 23:37:38,613 INFO L87 Difference]: Start difference. First operand 26 states and 28 transitions. Second operand 4 states. [2018-01-29 23:37:38,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:38,658 INFO L93 Difference]: Finished difference Result 46 states and 50 transitions. [2018-01-29 23:37:38,658 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-29 23:37:38,659 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 20 [2018-01-29 23:37:38,659 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:38,659 INFO L225 Difference]: With dead ends: 46 [2018-01-29 23:37:38,659 INFO L226 Difference]: Without dead ends: 32 [2018-01-29 23:37:38,659 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 21 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-29 23:37:38,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2018-01-29 23:37:38,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 30. [2018-01-29 23:37:38,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-01-29 23:37:38,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 32 transitions. [2018-01-29 23:37:38,662 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 32 transitions. Word has length 20 [2018-01-29 23:37:38,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:38,662 INFO L432 AbstractCegarLoop]: Abstraction has 30 states and 32 transitions. [2018-01-29 23:37:38,662 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-29 23:37:38,662 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 32 transitions. [2018-01-29 23:37:38,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-01-29 23:37:38,664 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:38,664 INFO L350 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:38,664 INFO L371 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:38,664 INFO L82 PathProgramCache]: Analyzing trace with hash -1032415687, now seen corresponding path program 2 times [2018-01-29 23:37:38,664 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:38,664 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:38,665 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:38,665 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:38,665 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:38,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:38,672 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:38,747 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:38,747 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:38,747 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:38,764 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 23:37:38,773 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:38,775 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:38,779 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:38,781 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:38,784 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:38,801 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:38,801 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-01-29 23:37:38,801 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-29 23:37:38,802 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-29 23:37:38,802 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-01-29 23:37:38,802 INFO L87 Difference]: Start difference. First operand 30 states and 32 transitions. Second operand 5 states. [2018-01-29 23:37:38,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:38,837 INFO L93 Difference]: Finished difference Result 50 states and 54 transitions. [2018-01-29 23:37:38,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-29 23:37:38,837 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 24 [2018-01-29 23:37:38,838 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:38,838 INFO L225 Difference]: With dead ends: 50 [2018-01-29 23:37:38,838 INFO L226 Difference]: Without dead ends: 36 [2018-01-29 23:37:38,838 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 25 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-01-29 23:37:38,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2018-01-29 23:37:38,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 34. [2018-01-29 23:37:38,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2018-01-29 23:37:38,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 36 transitions. [2018-01-29 23:37:38,841 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 36 transitions. Word has length 24 [2018-01-29 23:37:38,841 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:38,841 INFO L432 AbstractCegarLoop]: Abstraction has 34 states and 36 transitions. [2018-01-29 23:37:38,841 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-29 23:37:38,841 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 36 transitions. [2018-01-29 23:37:38,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-01-29 23:37:38,842 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:38,842 INFO L350 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:38,842 INFO L371 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:38,842 INFO L82 PathProgramCache]: Analyzing trace with hash 636151072, now seen corresponding path program 3 times [2018-01-29 23:37:38,842 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:38,842 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:38,843 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:38,843 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:38,843 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:38,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:38,848 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:39,037 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:39,037 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:39,037 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:39,049 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 23:37:39,054 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:39,067 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:39,080 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:39,089 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:39,090 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:39,091 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:39,095 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:39,111 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:39,111 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-01-29 23:37:39,111 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-29 23:37:39,112 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-29 23:37:39,112 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-29 23:37:39,112 INFO L87 Difference]: Start difference. First operand 34 states and 36 transitions. Second operand 6 states. [2018-01-29 23:37:39,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:39,180 INFO L93 Difference]: Finished difference Result 54 states and 58 transitions. [2018-01-29 23:37:39,181 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-29 23:37:39,181 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2018-01-29 23:37:39,181 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:39,181 INFO L225 Difference]: With dead ends: 54 [2018-01-29 23:37:39,181 INFO L226 Difference]: Without dead ends: 40 [2018-01-29 23:37:39,182 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-29 23:37:39,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-01-29 23:37:39,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 38. [2018-01-29 23:37:39,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-01-29 23:37:39,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 40 transitions. [2018-01-29 23:37:39,185 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 40 transitions. Word has length 28 [2018-01-29 23:37:39,185 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:39,185 INFO L432 AbstractCegarLoop]: Abstraction has 38 states and 40 transitions. [2018-01-29 23:37:39,185 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-29 23:37:39,185 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 40 transitions. [2018-01-29 23:37:39,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-29 23:37:39,185 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:39,185 INFO L350 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:39,185 INFO L371 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:39,186 INFO L82 PathProgramCache]: Analyzing trace with hash 121596039, now seen corresponding path program 4 times [2018-01-29 23:37:39,186 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:39,186 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:39,186 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:39,186 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:39,186 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:39,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:39,194 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:39,261 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:39,261 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:39,261 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:39,275 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 23:37:39,303 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:39,304 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:39,307 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:39,324 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:39,324 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2018-01-29 23:37:39,324 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-29 23:37:39,324 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-29 23:37:39,325 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-01-29 23:37:39,325 INFO L87 Difference]: Start difference. First operand 38 states and 40 transitions. Second operand 7 states. [2018-01-29 23:37:39,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:39,428 INFO L93 Difference]: Finished difference Result 58 states and 62 transitions. [2018-01-29 23:37:39,429 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-29 23:37:39,429 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 32 [2018-01-29 23:37:39,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:39,429 INFO L225 Difference]: With dead ends: 58 [2018-01-29 23:37:39,430 INFO L226 Difference]: Without dead ends: 44 [2018-01-29 23:37:39,430 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-01-29 23:37:39,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-01-29 23:37:39,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 42. [2018-01-29 23:37:39,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-01-29 23:37:39,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 44 transitions. [2018-01-29 23:37:39,434 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 44 transitions. Word has length 32 [2018-01-29 23:37:39,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:39,434 INFO L432 AbstractCegarLoop]: Abstraction has 42 states and 44 transitions. [2018-01-29 23:37:39,434 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-29 23:37:39,434 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 44 transitions. [2018-01-29 23:37:39,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-29 23:37:39,435 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:39,435 INFO L350 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:39,435 INFO L371 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:39,435 INFO L82 PathProgramCache]: Analyzing trace with hash 1514528878, now seen corresponding path program 5 times [2018-01-29 23:37:39,435 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:39,435 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:39,436 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:39,436 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:39,436 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:39,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:39,442 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:39,547 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:39,547 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:39,547 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-29 23:37:39,560 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:39,562 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:39,564 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:39,565 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:39,566 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:39,567 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:39,570 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:39,571 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:39,571 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:39,576 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:39,593 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:39,593 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2018-01-29 23:37:39,593 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-29 23:37:39,593 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-29 23:37:39,593 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-29 23:37:39,593 INFO L87 Difference]: Start difference. First operand 42 states and 44 transitions. Second operand 8 states. [2018-01-29 23:37:39,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:39,628 INFO L93 Difference]: Finished difference Result 62 states and 66 transitions. [2018-01-29 23:37:39,629 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-29 23:37:39,629 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 36 [2018-01-29 23:37:39,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:39,629 INFO L225 Difference]: With dead ends: 62 [2018-01-29 23:37:39,629 INFO L226 Difference]: Without dead ends: 48 [2018-01-29 23:37:39,629 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-29 23:37:39,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-01-29 23:37:39,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 46. [2018-01-29 23:37:39,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-01-29 23:37:39,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 48 transitions. [2018-01-29 23:37:39,633 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 48 transitions. Word has length 36 [2018-01-29 23:37:39,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:39,633 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 48 transitions. [2018-01-29 23:37:39,633 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-29 23:37:39,633 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 48 transitions. [2018-01-29 23:37:39,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-01-29 23:37:39,633 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:39,634 INFO L350 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:39,634 INFO L371 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:39,634 INFO L82 PathProgramCache]: Analyzing trace with hash 1408240853, now seen corresponding path program 6 times [2018-01-29 23:37:39,634 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:39,634 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:39,635 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:39,635 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:39,635 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:39,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:39,642 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:39,879 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:39,879 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:39,879 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:39,885 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 23:37:39,893 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:39,902 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:39,903 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:39,904 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:39,905 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:39,906 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:39,907 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:39,908 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:39,909 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:39,914 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:39,931 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:39,931 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2018-01-29 23:37:39,931 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-29 23:37:39,931 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-29 23:37:39,931 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-01-29 23:37:39,931 INFO L87 Difference]: Start difference. First operand 46 states and 48 transitions. Second operand 9 states. [2018-01-29 23:37:39,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:39,987 INFO L93 Difference]: Finished difference Result 66 states and 70 transitions. [2018-01-29 23:37:39,987 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-29 23:37:39,987 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 40 [2018-01-29 23:37:39,987 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:39,988 INFO L225 Difference]: With dead ends: 66 [2018-01-29 23:37:39,988 INFO L226 Difference]: Without dead ends: 52 [2018-01-29 23:37:39,988 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 41 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-01-29 23:37:39,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-01-29 23:37:39,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 50. [2018-01-29 23:37:39,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-29 23:37:39,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 52 transitions. [2018-01-29 23:37:39,990 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 52 transitions. Word has length 40 [2018-01-29 23:37:39,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:39,990 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 52 transitions. [2018-01-29 23:37:39,990 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-29 23:37:39,990 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 52 transitions. [2018-01-29 23:37:39,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-29 23:37:39,991 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:39,991 INFO L350 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:39,991 INFO L371 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:39,991 INFO L82 PathProgramCache]: Analyzing trace with hash -632312388, now seen corresponding path program 7 times [2018-01-29 23:37:39,991 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:39,991 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:39,992 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:39,992 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:39,992 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:39,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:39,998 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:40,139 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:40,140 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:40,140 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:40,147 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:40,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:40,154 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:40,160 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:40,176 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:40,176 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2018-01-29 23:37:40,177 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-29 23:37:40,177 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-29 23:37:40,177 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-29 23:37:40,177 INFO L87 Difference]: Start difference. First operand 50 states and 52 transitions. Second operand 10 states. [2018-01-29 23:37:40,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:40,226 INFO L93 Difference]: Finished difference Result 70 states and 74 transitions. [2018-01-29 23:37:40,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-29 23:37:40,226 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 44 [2018-01-29 23:37:40,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:40,227 INFO L225 Difference]: With dead ends: 70 [2018-01-29 23:37:40,227 INFO L226 Difference]: Without dead ends: 56 [2018-01-29 23:37:40,227 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-29 23:37:40,227 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2018-01-29 23:37:40,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 54. [2018-01-29 23:37:40,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-01-29 23:37:40,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 56 transitions. [2018-01-29 23:37:40,229 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 56 transitions. Word has length 44 [2018-01-29 23:37:40,229 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:40,230 INFO L432 AbstractCegarLoop]: Abstraction has 54 states and 56 transitions. [2018-01-29 23:37:40,230 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-29 23:37:40,230 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 56 transitions. [2018-01-29 23:37:40,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-01-29 23:37:40,230 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:40,230 INFO L350 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:40,230 INFO L371 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:40,230 INFO L82 PathProgramCache]: Analyzing trace with hash -191462621, now seen corresponding path program 8 times [2018-01-29 23:37:40,230 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:40,230 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:40,231 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:40,231 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:40,231 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:40,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:40,237 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:40,388 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:40,389 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:40,389 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:40,394 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 23:37:40,399 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:40,405 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:40,405 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:40,407 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:40,412 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:40,428 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:40,428 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2018-01-29 23:37:40,429 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-29 23:37:40,429 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-29 23:37:40,429 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-01-29 23:37:40,429 INFO L87 Difference]: Start difference. First operand 54 states and 56 transitions. Second operand 11 states. [2018-01-29 23:37:40,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:40,559 INFO L93 Difference]: Finished difference Result 74 states and 78 transitions. [2018-01-29 23:37:40,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-29 23:37:40,559 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 48 [2018-01-29 23:37:40,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:40,560 INFO L225 Difference]: With dead ends: 74 [2018-01-29 23:37:40,560 INFO L226 Difference]: Without dead ends: 60 [2018-01-29 23:37:40,560 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-01-29 23:37:40,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-01-29 23:37:40,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 58. [2018-01-29 23:37:40,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-01-29 23:37:40,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 60 transitions. [2018-01-29 23:37:40,563 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 60 transitions. Word has length 48 [2018-01-29 23:37:40,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:40,563 INFO L432 AbstractCegarLoop]: Abstraction has 58 states and 60 transitions. [2018-01-29 23:37:40,563 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-29 23:37:40,563 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 60 transitions. [2018-01-29 23:37:40,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-29 23:37:40,563 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:40,563 INFO L350 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:40,563 INFO L371 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:40,564 INFO L82 PathProgramCache]: Analyzing trace with hash 991317258, now seen corresponding path program 9 times [2018-01-29 23:37:40,564 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:40,564 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:40,564 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:40,564 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:40,564 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:40,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:40,570 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:40,908 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:40,908 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:40,908 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:40,914 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 23:37:40,925 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:40,930 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:40,931 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:40,932 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:40,932 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:40,933 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:40,934 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:40,935 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:40,937 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:40,938 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:40,938 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:40,940 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:40,945 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:40,962 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:40,962 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2018-01-29 23:37:40,962 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-29 23:37:40,962 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-29 23:37:40,962 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-01-29 23:37:40,962 INFO L87 Difference]: Start difference. First operand 58 states and 60 transitions. Second operand 12 states. [2018-01-29 23:37:41,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:41,016 INFO L93 Difference]: Finished difference Result 78 states and 82 transitions. [2018-01-29 23:37:41,016 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-29 23:37:41,016 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 52 [2018-01-29 23:37:41,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:41,016 INFO L225 Difference]: With dead ends: 78 [2018-01-29 23:37:41,016 INFO L226 Difference]: Without dead ends: 64 [2018-01-29 23:37:41,017 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-01-29 23:37:41,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-01-29 23:37:41,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 62. [2018-01-29 23:37:41,020 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-01-29 23:37:41,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 64 transitions. [2018-01-29 23:37:41,021 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 64 transitions. Word has length 52 [2018-01-29 23:37:41,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:41,021 INFO L432 AbstractCegarLoop]: Abstraction has 62 states and 64 transitions. [2018-01-29 23:37:41,021 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-29 23:37:41,021 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 64 transitions. [2018-01-29 23:37:41,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-01-29 23:37:41,022 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:41,022 INFO L350 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:41,022 INFO L371 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:41,022 INFO L82 PathProgramCache]: Analyzing trace with hash 1195428721, now seen corresponding path program 10 times [2018-01-29 23:37:41,022 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:41,022 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:41,022 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:41,022 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:41,023 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:41,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:41,028 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:41,124 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:41,124 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:41,124 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:41,129 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 23:37:41,136 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:41,137 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:41,149 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:41,166 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:41,166 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2018-01-29 23:37:41,167 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-29 23:37:41,167 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-29 23:37:41,167 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-01-29 23:37:41,167 INFO L87 Difference]: Start difference. First operand 62 states and 64 transitions. Second operand 13 states. [2018-01-29 23:37:41,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:41,213 INFO L93 Difference]: Finished difference Result 82 states and 86 transitions. [2018-01-29 23:37:41,213 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-29 23:37:41,213 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 56 [2018-01-29 23:37:41,214 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:41,214 INFO L225 Difference]: With dead ends: 82 [2018-01-29 23:37:41,214 INFO L226 Difference]: Without dead ends: 68 [2018-01-29 23:37:41,214 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-01-29 23:37:41,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2018-01-29 23:37:41,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 66. [2018-01-29 23:37:41,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-01-29 23:37:41,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 68 transitions. [2018-01-29 23:37:41,218 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 68 transitions. Word has length 56 [2018-01-29 23:37:41,218 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:41,218 INFO L432 AbstractCegarLoop]: Abstraction has 66 states and 68 transitions. [2018-01-29 23:37:41,218 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-29 23:37:41,218 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 68 transitions. [2018-01-29 23:37:41,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-01-29 23:37:41,219 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:41,219 INFO L350 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:41,219 INFO L371 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:41,219 INFO L82 PathProgramCache]: Analyzing trace with hash 598195800, now seen corresponding path program 11 times [2018-01-29 23:37:41,219 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:41,219 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:41,219 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:41,219 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:41,219 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:41,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:41,224 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:41,319 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:41,320 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:41,320 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:41,327 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 23:37:41,329 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:41,330 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:41,331 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:41,331 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:41,332 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:41,333 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:41,334 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:41,335 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:41,336 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:41,338 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:41,339 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:41,342 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:41,342 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:41,343 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:41,350 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:41,376 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:41,376 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 14 [2018-01-29 23:37:41,376 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-29 23:37:41,376 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-29 23:37:41,377 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-29 23:37:41,377 INFO L87 Difference]: Start difference. First operand 66 states and 68 transitions. Second operand 14 states. [2018-01-29 23:37:41,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:41,456 INFO L93 Difference]: Finished difference Result 86 states and 90 transitions. [2018-01-29 23:37:41,456 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-29 23:37:41,456 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 60 [2018-01-29 23:37:41,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:41,457 INFO L225 Difference]: With dead ends: 86 [2018-01-29 23:37:41,457 INFO L226 Difference]: Without dead ends: 72 [2018-01-29 23:37:41,457 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 61 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-29 23:37:41,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-01-29 23:37:41,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 70. [2018-01-29 23:37:41,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-01-29 23:37:41,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 72 transitions. [2018-01-29 23:37:41,460 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 72 transitions. Word has length 60 [2018-01-29 23:37:41,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:41,460 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 72 transitions. [2018-01-29 23:37:41,460 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-29 23:37:41,460 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 72 transitions. [2018-01-29 23:37:41,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-01-29 23:37:41,460 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:41,460 INFO L350 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:41,461 INFO L371 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:41,461 INFO L82 PathProgramCache]: Analyzing trace with hash -1141054017, now seen corresponding path program 12 times [2018-01-29 23:37:41,461 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:41,461 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:41,461 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:41,461 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:41,461 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:41,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:41,467 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:41,558 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:41,558 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:41,558 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:41,563 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 23:37:41,567 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:41,583 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:41,593 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:41,603 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:41,613 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:41,623 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:41,633 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:41,643 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:41,653 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:41,666 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:41,676 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:41,686 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:41,697 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:41,704 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:41,706 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:41,713 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:41,730 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:41,730 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 15 [2018-01-29 23:37:41,730 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-29 23:37:41,730 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-29 23:37:41,730 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2018-01-29 23:37:41,730 INFO L87 Difference]: Start difference. First operand 70 states and 72 transitions. Second operand 15 states. [2018-01-29 23:37:41,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:41,802 INFO L93 Difference]: Finished difference Result 90 states and 94 transitions. [2018-01-29 23:37:41,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-29 23:37:41,802 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 64 [2018-01-29 23:37:41,802 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:41,803 INFO L225 Difference]: With dead ends: 90 [2018-01-29 23:37:41,803 INFO L226 Difference]: Without dead ends: 76 [2018-01-29 23:37:41,803 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2018-01-29 23:37:41,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-01-29 23:37:41,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 74. [2018-01-29 23:37:41,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-29 23:37:41,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 76 transitions. [2018-01-29 23:37:41,805 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 76 transitions. Word has length 64 [2018-01-29 23:37:41,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:41,806 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 76 transitions. [2018-01-29 23:37:41,806 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-29 23:37:41,806 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 76 transitions. [2018-01-29 23:37:41,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-01-29 23:37:41,806 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:41,806 INFO L350 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:41,806 INFO L371 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:41,806 INFO L82 PathProgramCache]: Analyzing trace with hash 1293025702, now seen corresponding path program 13 times [2018-01-29 23:37:41,806 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:41,807 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:41,807 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:41,807 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:41,807 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:41,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:41,812 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:41,922 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:41,922 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:41,922 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:41,928 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:41,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:41,952 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:41,960 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:41,977 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:41,977 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 16 [2018-01-29 23:37:41,977 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-29 23:37:41,977 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-29 23:37:41,977 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-29 23:37:41,977 INFO L87 Difference]: Start difference. First operand 74 states and 76 transitions. Second operand 16 states. [2018-01-29 23:37:42,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:42,071 INFO L93 Difference]: Finished difference Result 94 states and 98 transitions. [2018-01-29 23:37:42,071 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-29 23:37:42,072 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 68 [2018-01-29 23:37:42,072 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:42,072 INFO L225 Difference]: With dead ends: 94 [2018-01-29 23:37:42,072 INFO L226 Difference]: Without dead ends: 80 [2018-01-29 23:37:42,073 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 69 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-29 23:37:42,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-29 23:37:42,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 78. [2018-01-29 23:37:42,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-01-29 23:37:42,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 80 transitions. [2018-01-29 23:37:42,075 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 80 transitions. Word has length 68 [2018-01-29 23:37:42,075 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:42,075 INFO L432 AbstractCegarLoop]: Abstraction has 78 states and 80 transitions. [2018-01-29 23:37:42,075 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-29 23:37:42,076 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 80 transitions. [2018-01-29 23:37:42,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-01-29 23:37:42,081 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:42,081 INFO L350 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:42,081 INFO L371 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:42,081 INFO L82 PathProgramCache]: Analyzing trace with hash -723987955, now seen corresponding path program 14 times [2018-01-29 23:37:42,081 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:42,082 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:42,082 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:42,082 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:42,082 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:42,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:42,089 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:42,244 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:42,244 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:42,244 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:42,256 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 23:37:42,260 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:42,263 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:42,264 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:42,265 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:42,274 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:42,296 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:42,296 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 17 [2018-01-29 23:37:42,297 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-29 23:37:42,297 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-29 23:37:42,297 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2018-01-29 23:37:42,297 INFO L87 Difference]: Start difference. First operand 78 states and 80 transitions. Second operand 17 states. [2018-01-29 23:37:42,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:42,378 INFO L93 Difference]: Finished difference Result 98 states and 102 transitions. [2018-01-29 23:37:42,378 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-29 23:37:42,378 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2018-01-29 23:37:42,378 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:42,379 INFO L225 Difference]: With dead ends: 98 [2018-01-29 23:37:42,379 INFO L226 Difference]: Without dead ends: 84 [2018-01-29 23:37:42,379 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 73 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2018-01-29 23:37:42,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-01-29 23:37:42,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 82. [2018-01-29 23:37:42,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-01-29 23:37:42,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 84 transitions. [2018-01-29 23:37:42,381 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 84 transitions. Word has length 72 [2018-01-29 23:37:42,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:42,381 INFO L432 AbstractCegarLoop]: Abstraction has 82 states and 84 transitions. [2018-01-29 23:37:42,382 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-29 23:37:42,382 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 84 transitions. [2018-01-29 23:37:42,382 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-01-29 23:37:42,382 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:42,382 INFO L350 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:42,382 INFO L371 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:42,382 INFO L82 PathProgramCache]: Analyzing trace with hash -2107435276, now seen corresponding path program 15 times [2018-01-29 23:37:42,382 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:42,382 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:42,385 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:42,385 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:42,385 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:42,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:42,389 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:42,808 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:42,808 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:42,808 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:42,815 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 23:37:42,819 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,820 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,820 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,821 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,822 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,823 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,824 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,825 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,826 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,827 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,829 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,830 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,832 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,833 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,835 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,837 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:42,837 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:42,838 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:42,853 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:42,871 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:42,871 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2018-01-29 23:37:42,871 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-29 23:37:42,871 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-29 23:37:42,871 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-01-29 23:37:42,871 INFO L87 Difference]: Start difference. First operand 82 states and 84 transitions. Second operand 18 states. [2018-01-29 23:37:42,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:42,937 INFO L93 Difference]: Finished difference Result 102 states and 106 transitions. [2018-01-29 23:37:42,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-29 23:37:42,938 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 76 [2018-01-29 23:37:42,938 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:42,938 INFO L225 Difference]: With dead ends: 102 [2018-01-29 23:37:42,938 INFO L226 Difference]: Without dead ends: 88 [2018-01-29 23:37:42,938 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-01-29 23:37:42,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-01-29 23:37:42,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 86. [2018-01-29 23:37:42,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-01-29 23:37:42,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 88 transitions. [2018-01-29 23:37:42,941 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 88 transitions. Word has length 76 [2018-01-29 23:37:42,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:42,941 INFO L432 AbstractCegarLoop]: Abstraction has 86 states and 88 transitions. [2018-01-29 23:37:42,941 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-29 23:37:42,941 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 88 transitions. [2018-01-29 23:37:42,941 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-01-29 23:37:42,941 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:42,941 INFO L350 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:42,942 INFO L371 AbstractCegarLoop]: === Iteration 18 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:42,942 INFO L82 PathProgramCache]: Analyzing trace with hash 635605083, now seen corresponding path program 16 times [2018-01-29 23:37:42,942 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:42,942 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:42,942 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:42,942 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:42,942 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:42,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:42,948 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:43,125 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:43,125 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:43,125 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:43,131 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 23:37:43,140 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:43,141 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:43,149 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:43,165 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:43,166 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 19 [2018-01-29 23:37:43,166 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-29 23:37:43,166 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-29 23:37:43,166 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-01-29 23:37:43,166 INFO L87 Difference]: Start difference. First operand 86 states and 88 transitions. Second operand 19 states. [2018-01-29 23:37:43,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:43,236 INFO L93 Difference]: Finished difference Result 106 states and 110 transitions. [2018-01-29 23:37:43,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-29 23:37:43,236 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 80 [2018-01-29 23:37:43,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:43,236 INFO L225 Difference]: With dead ends: 106 [2018-01-29 23:37:43,237 INFO L226 Difference]: Without dead ends: 92 [2018-01-29 23:37:43,237 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 81 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-01-29 23:37:43,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states. [2018-01-29 23:37:43,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 90. [2018-01-29 23:37:43,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2018-01-29 23:37:43,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 92 transitions. [2018-01-29 23:37:43,239 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 92 transitions. Word has length 80 [2018-01-29 23:37:43,239 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:43,239 INFO L432 AbstractCegarLoop]: Abstraction has 90 states and 92 transitions. [2018-01-29 23:37:43,239 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-29 23:37:43,239 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 92 transitions. [2018-01-29 23:37:43,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-01-29 23:37:43,239 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:43,239 INFO L350 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:43,239 INFO L371 AbstractCegarLoop]: === Iteration 19 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:43,240 INFO L82 PathProgramCache]: Analyzing trace with hash -1599537598, now seen corresponding path program 17 times [2018-01-29 23:37:43,240 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:43,240 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:43,240 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:43,240 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:43,240 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:43,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:43,245 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:43,436 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:43,436 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:43,436 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:43,441 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 23:37:43,445 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,445 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,446 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,447 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,448 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,449 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,450 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,451 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,453 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,454 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,456 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,457 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,459 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,462 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,464 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,467 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,470 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,474 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:43,474 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:43,475 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:43,484 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:43,506 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:43,506 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 20 [2018-01-29 23:37:43,506 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-29 23:37:43,507 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-29 23:37:43,507 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-29 23:37:43,507 INFO L87 Difference]: Start difference. First operand 90 states and 92 transitions. Second operand 20 states. [2018-01-29 23:37:43,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:43,675 INFO L93 Difference]: Finished difference Result 110 states and 114 transitions. [2018-01-29 23:37:43,675 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-29 23:37:43,675 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 84 [2018-01-29 23:37:43,676 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:43,676 INFO L225 Difference]: With dead ends: 110 [2018-01-29 23:37:43,676 INFO L226 Difference]: Without dead ends: 96 [2018-01-29 23:37:43,676 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 85 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-29 23:37:43,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-01-29 23:37:43,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 94. [2018-01-29 23:37:43,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-01-29 23:37:43,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 96 transitions. [2018-01-29 23:37:43,678 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 96 transitions. Word has length 84 [2018-01-29 23:37:43,678 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:43,678 INFO L432 AbstractCegarLoop]: Abstraction has 94 states and 96 transitions. [2018-01-29 23:37:43,678 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-29 23:37:43,678 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 96 transitions. [2018-01-29 23:37:43,679 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-01-29 23:37:43,679 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:43,679 INFO L350 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:43,679 INFO L371 AbstractCegarLoop]: === Iteration 20 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:43,679 INFO L82 PathProgramCache]: Analyzing trace with hash 1428693161, now seen corresponding path program 18 times [2018-01-29 23:37:43,679 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:43,679 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:43,680 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:43,680 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:43,680 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:43,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:43,685 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:43,907 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:43,907 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:43,907 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:43,912 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 23:37:43,916 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,917 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,918 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,918 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,919 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,920 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,921 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,921 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,922 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,923 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,925 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,926 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,927 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,928 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,930 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,931 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,935 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,938 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,940 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:43,940 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:43,941 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:43,951 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:43,968 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:43,968 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 21 [2018-01-29 23:37:43,968 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-29 23:37:43,968 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-29 23:37:43,968 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2018-01-29 23:37:43,968 INFO L87 Difference]: Start difference. First operand 94 states and 96 transitions. Second operand 21 states. [2018-01-29 23:37:44,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:44,006 INFO L93 Difference]: Finished difference Result 114 states and 118 transitions. [2018-01-29 23:37:44,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-29 23:37:44,006 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 88 [2018-01-29 23:37:44,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:44,007 INFO L225 Difference]: With dead ends: 114 [2018-01-29 23:37:44,007 INFO L226 Difference]: Without dead ends: 100 [2018-01-29 23:37:44,007 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2018-01-29 23:37:44,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-01-29 23:37:44,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 98. [2018-01-29 23:37:44,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98 states. [2018-01-29 23:37:44,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 100 transitions. [2018-01-29 23:37:44,009 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 100 transitions. Word has length 88 [2018-01-29 23:37:44,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:44,009 INFO L432 AbstractCegarLoop]: Abstraction has 98 states and 100 transitions. [2018-01-29 23:37:44,009 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-29 23:37:44,009 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 100 transitions. [2018-01-29 23:37:44,009 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-29 23:37:44,009 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:44,009 INFO L350 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:44,009 INFO L371 AbstractCegarLoop]: === Iteration 21 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:44,010 INFO L82 PathProgramCache]: Analyzing trace with hash -1762543728, now seen corresponding path program 19 times [2018-01-29 23:37:44,010 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:44,010 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:44,010 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:44,010 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:44,010 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:44,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:44,015 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:44,208 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 0 proven. 722 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:44,208 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:44,208 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:44,216 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:44,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:44,241 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:44,249 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 0 proven. 722 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:44,266 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:44,267 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 22 [2018-01-29 23:37:44,267 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-29 23:37:44,267 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-29 23:37:44,267 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-29 23:37:44,267 INFO L87 Difference]: Start difference. First operand 98 states and 100 transitions. Second operand 22 states. [2018-01-29 23:37:44,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:44,484 INFO L93 Difference]: Finished difference Result 118 states and 122 transitions. [2018-01-29 23:37:44,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-29 23:37:44,484 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 92 [2018-01-29 23:37:44,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:44,484 INFO L225 Difference]: With dead ends: 118 [2018-01-29 23:37:44,484 INFO L226 Difference]: Without dead ends: 104 [2018-01-29 23:37:44,485 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 93 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-29 23:37:44,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-01-29 23:37:44,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 102. [2018-01-29 23:37:44,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-01-29 23:37:44,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 104 transitions. [2018-01-29 23:37:44,486 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 104 transitions. Word has length 92 [2018-01-29 23:37:44,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:44,487 INFO L432 AbstractCegarLoop]: Abstraction has 102 states and 104 transitions. [2018-01-29 23:37:44,487 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-29 23:37:44,487 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 104 transitions. [2018-01-29 23:37:44,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-01-29 23:37:44,487 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:44,487 INFO L350 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:44,487 INFO L371 AbstractCegarLoop]: === Iteration 22 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:44,487 INFO L82 PathProgramCache]: Analyzing trace with hash 448234231, now seen corresponding path program 20 times [2018-01-29 23:37:44,487 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:44,487 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:44,488 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:44,488 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:44,488 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:44,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:44,499 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:44,730 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:44,731 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:44,731 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:44,735 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 23:37:44,739 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:44,744 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:44,745 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:44,747 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:44,755 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:44,777 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:44,777 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 23 [2018-01-29 23:37:44,777 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-29 23:37:44,777 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-29 23:37:44,777 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2018-01-29 23:37:44,778 INFO L87 Difference]: Start difference. First operand 102 states and 104 transitions. Second operand 23 states. [2018-01-29 23:37:44,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:44,979 INFO L93 Difference]: Finished difference Result 122 states and 126 transitions. [2018-01-29 23:37:44,980 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-29 23:37:44,980 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 96 [2018-01-29 23:37:44,980 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:44,980 INFO L225 Difference]: With dead ends: 122 [2018-01-29 23:37:44,980 INFO L226 Difference]: Without dead ends: 108 [2018-01-29 23:37:44,981 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 97 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2018-01-29 23:37:44,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2018-01-29 23:37:44,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 106. [2018-01-29 23:37:44,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-01-29 23:37:44,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 108 transitions. [2018-01-29 23:37:44,983 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 108 transitions. Word has length 96 [2018-01-29 23:37:44,983 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:44,983 INFO L432 AbstractCegarLoop]: Abstraction has 106 states and 108 transitions. [2018-01-29 23:37:44,983 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-29 23:37:44,983 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 108 transitions. [2018-01-29 23:37:44,984 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-01-29 23:37:44,984 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:44,984 INFO L350 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:44,984 INFO L371 AbstractCegarLoop]: === Iteration 23 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:44,984 INFO L82 PathProgramCache]: Analyzing trace with hash 1716208350, now seen corresponding path program 21 times [2018-01-29 23:37:44,984 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:44,984 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:44,984 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:44,985 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:44,985 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:44,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:44,989 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:45,191 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:45,191 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:45,191 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:45,195 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 23:37:45,199 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,200 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,201 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,202 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,203 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,203 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,204 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,205 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,206 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,207 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,209 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,210 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,217 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,218 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,220 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,223 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,225 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,227 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,230 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,233 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,236 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,239 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:45,239 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:45,241 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:45,250 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:45,268 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:45,268 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 24 [2018-01-29 23:37:45,268 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-29 23:37:45,269 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-29 23:37:45,269 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-01-29 23:37:45,269 INFO L87 Difference]: Start difference. First operand 106 states and 108 transitions. Second operand 24 states. [2018-01-29 23:37:45,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:45,355 INFO L93 Difference]: Finished difference Result 126 states and 130 transitions. [2018-01-29 23:37:45,355 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-29 23:37:45,355 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 100 [2018-01-29 23:37:45,355 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:45,356 INFO L225 Difference]: With dead ends: 126 [2018-01-29 23:37:45,356 INFO L226 Difference]: Without dead ends: 112 [2018-01-29 23:37:45,356 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 101 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-01-29 23:37:45,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-01-29 23:37:45,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 110. [2018-01-29 23:37:45,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-01-29 23:37:45,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 112 transitions. [2018-01-29 23:37:45,358 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 112 transitions. Word has length 100 [2018-01-29 23:37:45,358 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:45,358 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 112 transitions. [2018-01-29 23:37:45,358 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-29 23:37:45,358 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 112 transitions. [2018-01-29 23:37:45,358 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-01-29 23:37:45,358 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:45,359 INFO L350 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:45,359 INFO L371 AbstractCegarLoop]: === Iteration 24 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:45,359 INFO L82 PathProgramCache]: Analyzing trace with hash 1084143429, now seen corresponding path program 22 times [2018-01-29 23:37:45,359 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:45,359 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:45,359 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:45,359 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:45,359 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:45,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:45,370 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:45,559 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 0 proven. 968 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:45,559 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:45,559 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:45,565 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 23:37:45,575 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:45,576 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:45,585 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 0 proven. 968 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:45,602 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:45,602 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 25 [2018-01-29 23:37:45,602 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-29 23:37:45,602 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-29 23:37:45,602 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-01-29 23:37:45,602 INFO L87 Difference]: Start difference. First operand 110 states and 112 transitions. Second operand 25 states. [2018-01-29 23:37:45,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:45,649 INFO L93 Difference]: Finished difference Result 130 states and 134 transitions. [2018-01-29 23:37:45,650 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-29 23:37:45,650 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 104 [2018-01-29 23:37:45,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:45,650 INFO L225 Difference]: With dead ends: 130 [2018-01-29 23:37:45,650 INFO L226 Difference]: Without dead ends: 116 [2018-01-29 23:37:45,650 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 128 GetRequests, 105 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-01-29 23:37:45,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-01-29 23:37:45,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 114. [2018-01-29 23:37:45,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-01-29 23:37:45,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 116 transitions. [2018-01-29 23:37:45,652 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 116 transitions. Word has length 104 [2018-01-29 23:37:45,652 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:45,652 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 116 transitions. [2018-01-29 23:37:45,652 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-29 23:37:45,652 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 116 transitions. [2018-01-29 23:37:45,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-01-29 23:37:45,653 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:45,653 INFO L350 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:45,653 INFO L371 AbstractCegarLoop]: === Iteration 25 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:45,653 INFO L82 PathProgramCache]: Analyzing trace with hash 566468652, now seen corresponding path program 23 times [2018-01-29 23:37:45,653 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:45,653 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:45,653 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:45,654 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:45,654 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:45,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:45,658 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:46,092 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:46,092 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:46,092 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:46,096 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 23:37:46,099 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,113 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,118 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,119 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,120 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,121 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,122 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,123 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,124 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,125 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,126 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,128 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,130 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,132 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,134 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,137 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,139 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,142 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,146 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,149 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,153 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,158 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,163 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,170 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:46,170 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:46,171 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:46,181 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:46,203 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:46,203 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 26 [2018-01-29 23:37:46,203 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-29 23:37:46,203 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-29 23:37:46,204 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-29 23:37:46,204 INFO L87 Difference]: Start difference. First operand 114 states and 116 transitions. Second operand 26 states. [2018-01-29 23:37:46,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:46,301 INFO L93 Difference]: Finished difference Result 134 states and 138 transitions. [2018-01-29 23:37:46,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-29 23:37:46,301 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 108 [2018-01-29 23:37:46,302 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:46,302 INFO L225 Difference]: With dead ends: 134 [2018-01-29 23:37:46,302 INFO L226 Difference]: Without dead ends: 120 [2018-01-29 23:37:46,302 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-29 23:37:46,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-01-29 23:37:46,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 118. [2018-01-29 23:37:46,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-29 23:37:46,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 120 transitions. [2018-01-29 23:37:46,304 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 120 transitions. Word has length 108 [2018-01-29 23:37:46,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:46,305 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 120 transitions. [2018-01-29 23:37:46,305 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-29 23:37:46,305 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 120 transitions. [2018-01-29 23:37:46,305 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-01-29 23:37:46,305 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:46,305 INFO L350 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:46,305 INFO L371 AbstractCegarLoop]: === Iteration 26 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:46,306 INFO L82 PathProgramCache]: Analyzing trace with hash -1561608813, now seen corresponding path program 24 times [2018-01-29 23:37:46,306 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:46,306 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:46,314 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:46,314 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:46,314 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:46,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:46,322 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:46,683 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:46,683 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:46,683 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:46,689 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 23:37:46,693 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,694 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,695 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,695 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,696 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,697 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,698 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,698 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,713 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,714 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,715 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,716 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,717 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,718 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,720 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,721 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,723 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,724 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,726 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,728 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,730 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,732 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,734 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,739 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,744 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:46,744 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:46,745 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:46,755 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:46,772 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:46,772 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 27 [2018-01-29 23:37:46,773 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-29 23:37:46,773 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-29 23:37:46,773 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2018-01-29 23:37:46,773 INFO L87 Difference]: Start difference. First operand 118 states and 120 transitions. Second operand 27 states. [2018-01-29 23:37:46,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:46,841 INFO L93 Difference]: Finished difference Result 138 states and 142 transitions. [2018-01-29 23:37:46,841 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-29 23:37:46,841 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 112 [2018-01-29 23:37:46,841 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:46,842 INFO L225 Difference]: With dead ends: 138 [2018-01-29 23:37:46,842 INFO L226 Difference]: Without dead ends: 124 [2018-01-29 23:37:46,842 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 138 GetRequests, 113 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2018-01-29 23:37:46,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-01-29 23:37:46,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 122. [2018-01-29 23:37:46,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-01-29 23:37:46,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 124 transitions. [2018-01-29 23:37:46,844 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 124 transitions. Word has length 112 [2018-01-29 23:37:46,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:46,844 INFO L432 AbstractCegarLoop]: Abstraction has 122 states and 124 transitions. [2018-01-29 23:37:46,844 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-29 23:37:46,844 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 124 transitions. [2018-01-29 23:37:46,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-01-29 23:37:46,844 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:46,844 INFO L350 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:46,844 INFO L371 AbstractCegarLoop]: === Iteration 27 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:46,844 INFO L82 PathProgramCache]: Analyzing trace with hash -295121030, now seen corresponding path program 25 times [2018-01-29 23:37:46,844 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:46,845 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:46,845 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:46,845 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:46,845 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:46,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:46,850 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:47,478 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 0 proven. 1250 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:47,478 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:47,478 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:47,482 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:47,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:47,493 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:47,504 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 0 proven. 1250 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:47,520 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:47,520 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 28 [2018-01-29 23:37:47,521 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-29 23:37:47,521 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-29 23:37:47,521 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-29 23:37:47,521 INFO L87 Difference]: Start difference. First operand 122 states and 124 transitions. Second operand 28 states. [2018-01-29 23:37:47,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:47,603 INFO L93 Difference]: Finished difference Result 142 states and 146 transitions. [2018-01-29 23:37:47,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-29 23:37:47,603 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 116 [2018-01-29 23:37:47,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:47,603 INFO L225 Difference]: With dead ends: 142 [2018-01-29 23:37:47,604 INFO L226 Difference]: Without dead ends: 128 [2018-01-29 23:37:47,604 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 143 GetRequests, 117 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-29 23:37:47,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-01-29 23:37:47,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 126. [2018-01-29 23:37:47,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-01-29 23:37:47,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 128 transitions. [2018-01-29 23:37:47,606 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 128 transitions. Word has length 116 [2018-01-29 23:37:47,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:47,606 INFO L432 AbstractCegarLoop]: Abstraction has 126 states and 128 transitions. [2018-01-29 23:37:47,606 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-29 23:37:47,606 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 128 transitions. [2018-01-29 23:37:47,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-01-29 23:37:47,606 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:47,606 INFO L350 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:47,606 INFO L371 AbstractCegarLoop]: === Iteration 28 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:47,606 INFO L82 PathProgramCache]: Analyzing trace with hash 799839713, now seen corresponding path program 26 times [2018-01-29 23:37:47,606 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:47,607 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:47,607 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:47,607 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:47,607 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:47,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:47,612 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:48,050 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:48,050 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:48,051 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:48,055 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 23:37:48,059 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:48,065 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:48,066 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:48,067 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:48,078 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:48,094 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:48,095 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 29 [2018-01-29 23:37:48,095 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-29 23:37:48,095 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-29 23:37:48,095 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2018-01-29 23:37:48,095 INFO L87 Difference]: Start difference. First operand 126 states and 128 transitions. Second operand 29 states. [2018-01-29 23:37:48,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:48,156 INFO L93 Difference]: Finished difference Result 146 states and 150 transitions. [2018-01-29 23:37:48,157 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-29 23:37:48,157 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 120 [2018-01-29 23:37:48,157 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:48,157 INFO L225 Difference]: With dead ends: 146 [2018-01-29 23:37:48,157 INFO L226 Difference]: Without dead ends: 132 [2018-01-29 23:37:48,158 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 121 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2018-01-29 23:37:48,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-01-29 23:37:48,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 130. [2018-01-29 23:37:48,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-01-29 23:37:48,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 132 transitions. [2018-01-29 23:37:48,159 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 132 transitions. Word has length 120 [2018-01-29 23:37:48,159 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:48,160 INFO L432 AbstractCegarLoop]: Abstraction has 130 states and 132 transitions. [2018-01-29 23:37:48,160 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-29 23:37:48,160 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 132 transitions. [2018-01-29 23:37:48,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2018-01-29 23:37:48,160 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:48,160 INFO L350 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:48,160 INFO L371 AbstractCegarLoop]: === Iteration 29 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:48,160 INFO L82 PathProgramCache]: Analyzing trace with hash 55103688, now seen corresponding path program 27 times [2018-01-29 23:37:48,160 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:48,160 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:48,161 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:48,161 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:48,161 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:48,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:48,165 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:48,453 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:48,453 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:48,453 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:48,458 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 23:37:48,462 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,463 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,464 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,464 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,465 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,466 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,466 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,467 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,469 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,470 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,471 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,472 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,474 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,475 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,477 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,479 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,481 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,483 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,486 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,488 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,491 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,494 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,497 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,501 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,505 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,509 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,514 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,519 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:48,520 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:48,521 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:48,540 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:48,556 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:48,557 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 30 [2018-01-29 23:37:48,557 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-29 23:37:48,557 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-29 23:37:48,557 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-01-29 23:37:48,557 INFO L87 Difference]: Start difference. First operand 130 states and 132 transitions. Second operand 30 states. [2018-01-29 23:37:48,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:48,716 INFO L93 Difference]: Finished difference Result 150 states and 154 transitions. [2018-01-29 23:37:48,717 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-29 23:37:48,717 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 124 [2018-01-29 23:37:48,717 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:48,717 INFO L225 Difference]: With dead ends: 150 [2018-01-29 23:37:48,717 INFO L226 Difference]: Without dead ends: 136 [2018-01-29 23:37:48,718 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 153 GetRequests, 125 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-01-29 23:37:48,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-01-29 23:37:48,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 134. [2018-01-29 23:37:48,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-01-29 23:37:48,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 136 transitions. [2018-01-29 23:37:48,719 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 136 transitions. Word has length 124 [2018-01-29 23:37:48,719 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:48,719 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 136 transitions. [2018-01-29 23:37:48,720 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-29 23:37:48,720 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 136 transitions. [2018-01-29 23:37:48,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-01-29 23:37:48,720 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:48,720 INFO L350 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:48,720 INFO L371 AbstractCegarLoop]: === Iteration 30 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:48,720 INFO L82 PathProgramCache]: Analyzing trace with hash -420528081, now seen corresponding path program 28 times [2018-01-29 23:37:48,720 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:48,720 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:48,721 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:48,721 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:48,721 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:48,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:48,725 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:49,018 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 0 proven. 1568 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:49,018 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:49,018 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:49,023 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 23:37:49,034 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:49,035 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:49,049 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 0 proven. 1568 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:49,071 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:49,071 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 31 [2018-01-29 23:37:49,071 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-01-29 23:37:49,071 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-01-29 23:37:49,071 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2018-01-29 23:37:49,072 INFO L87 Difference]: Start difference. First operand 134 states and 136 transitions. Second operand 31 states. [2018-01-29 23:37:49,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:49,130 INFO L93 Difference]: Finished difference Result 154 states and 158 transitions. [2018-01-29 23:37:49,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-29 23:37:49,130 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 128 [2018-01-29 23:37:49,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:49,131 INFO L225 Difference]: With dead ends: 154 [2018-01-29 23:37:49,131 INFO L226 Difference]: Without dead ends: 140 [2018-01-29 23:37:49,131 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 129 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2018-01-29 23:37:49,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-01-29 23:37:49,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 138. [2018-01-29 23:37:49,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-01-29 23:37:49,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 140 transitions. [2018-01-29 23:37:49,134 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 140 transitions. Word has length 128 [2018-01-29 23:37:49,134 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:49,134 INFO L432 AbstractCegarLoop]: Abstraction has 138 states and 140 transitions. [2018-01-29 23:37:49,134 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-01-29 23:37:49,134 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 140 transitions. [2018-01-29 23:37:49,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-01-29 23:37:49,134 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:49,134 INFO L350 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:49,135 INFO L371 AbstractCegarLoop]: === Iteration 31 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:49,135 INFO L82 PathProgramCache]: Analyzing trace with hash -1452170218, now seen corresponding path program 29 times [2018-01-29 23:37:49,135 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:49,135 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:49,135 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:49,135 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:49,135 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:49,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:49,142 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:49,599 INFO L134 CoverageAnalysis]: Checked inductivity of 1682 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:49,599 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:49,599 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:49,604 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 23:37:49,607 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,608 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,608 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,609 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,610 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,611 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,612 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,613 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,614 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,616 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,620 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,623 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,624 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,627 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,629 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,632 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,634 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,637 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,641 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,645 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,649 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,653 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,658 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,664 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,670 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,678 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,685 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,694 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,704 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,715 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:49,716 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:49,717 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:49,730 INFO L134 CoverageAnalysis]: Checked inductivity of 1682 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:49,747 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:49,747 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 32 [2018-01-29 23:37:49,747 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-01-29 23:37:49,748 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-01-29 23:37:49,748 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-29 23:37:49,748 INFO L87 Difference]: Start difference. First operand 138 states and 140 transitions. Second operand 32 states. [2018-01-29 23:37:49,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:49,847 INFO L93 Difference]: Finished difference Result 158 states and 162 transitions. [2018-01-29 23:37:49,849 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-01-29 23:37:49,849 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 132 [2018-01-29 23:37:49,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:49,850 INFO L225 Difference]: With dead ends: 158 [2018-01-29 23:37:49,850 INFO L226 Difference]: Without dead ends: 144 [2018-01-29 23:37:49,850 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 133 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-29 23:37:49,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-01-29 23:37:49,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 142. [2018-01-29 23:37:49,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-01-29 23:37:49,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 144 transitions. [2018-01-29 23:37:49,852 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 144 transitions. Word has length 132 [2018-01-29 23:37:49,852 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:49,852 INFO L432 AbstractCegarLoop]: Abstraction has 142 states and 144 transitions. [2018-01-29 23:37:49,852 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-01-29 23:37:49,853 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 144 transitions. [2018-01-29 23:37:49,859 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2018-01-29 23:37:49,859 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:49,860 INFO L350 BasicCegarLoop]: trace histogram [31, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:49,860 INFO L371 AbstractCegarLoop]: === Iteration 32 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:49,860 INFO L82 PathProgramCache]: Analyzing trace with hash -624837507, now seen corresponding path program 30 times [2018-01-29 23:37:49,860 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:49,860 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:49,860 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:49,860 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:49,860 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:49,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:49,868 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:50,173 INFO L134 CoverageAnalysis]: Checked inductivity of 1800 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:50,173 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:50,173 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:50,178 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 23:37:50,182 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,183 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,184 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,184 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,185 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,186 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,186 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,187 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,188 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,189 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,191 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,192 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,193 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,194 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,196 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,197 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,199 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,200 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,202 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,204 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,206 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,208 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,210 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,212 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,215 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,217 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,220 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,223 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,227 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,230 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,242 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:50,242 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:50,244 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:50,257 INFO L134 CoverageAnalysis]: Checked inductivity of 1800 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:50,276 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:50,276 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 33 [2018-01-29 23:37:50,276 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-29 23:37:50,277 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-29 23:37:50,277 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-01-29 23:37:50,277 INFO L87 Difference]: Start difference. First operand 142 states and 144 transitions. Second operand 33 states. [2018-01-29 23:37:50,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:50,575 INFO L93 Difference]: Finished difference Result 162 states and 166 transitions. [2018-01-29 23:37:50,575 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-01-29 23:37:50,575 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 136 [2018-01-29 23:37:50,575 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:50,575 INFO L225 Difference]: With dead ends: 162 [2018-01-29 23:37:50,575 INFO L226 Difference]: Without dead ends: 148 [2018-01-29 23:37:50,576 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 168 GetRequests, 137 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-01-29 23:37:50,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-01-29 23:37:50,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 146. [2018-01-29 23:37:50,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2018-01-29 23:37:50,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 148 transitions. [2018-01-29 23:37:50,578 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 148 transitions. Word has length 136 [2018-01-29 23:37:50,578 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:50,578 INFO L432 AbstractCegarLoop]: Abstraction has 146 states and 148 transitions. [2018-01-29 23:37:50,578 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-29 23:37:50,578 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 148 transitions. [2018-01-29 23:37:50,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-01-29 23:37:50,578 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:50,578 INFO L350 BasicCegarLoop]: trace histogram [32, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:50,579 INFO L371 AbstractCegarLoop]: === Iteration 33 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:50,579 INFO L82 PathProgramCache]: Analyzing trace with hash 1005668708, now seen corresponding path program 31 times [2018-01-29 23:37:50,579 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:50,579 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:50,579 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:50,579 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:50,579 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:50,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:50,584 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:51,250 INFO L134 CoverageAnalysis]: Checked inductivity of 1922 backedges. 0 proven. 1922 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:51,250 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:51,250 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:51,254 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:51,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:51,271 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:51,286 INFO L134 CoverageAnalysis]: Checked inductivity of 1922 backedges. 0 proven. 1922 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:51,302 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:51,303 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 34 [2018-01-29 23:37:51,303 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-01-29 23:37:51,303 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-01-29 23:37:51,303 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-29 23:37:51,303 INFO L87 Difference]: Start difference. First operand 146 states and 148 transitions. Second operand 34 states. [2018-01-29 23:37:51,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:51,375 INFO L93 Difference]: Finished difference Result 166 states and 170 transitions. [2018-01-29 23:37:51,375 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-01-29 23:37:51,375 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 140 [2018-01-29 23:37:51,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:51,376 INFO L225 Difference]: With dead ends: 166 [2018-01-29 23:37:51,376 INFO L226 Difference]: Without dead ends: 152 [2018-01-29 23:37:51,376 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 173 GetRequests, 141 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-29 23:37:51,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-01-29 23:37:51,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 150. [2018-01-29 23:37:51,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-01-29 23:37:51,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 152 transitions. [2018-01-29 23:37:51,378 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 152 transitions. Word has length 140 [2018-01-29 23:37:51,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:51,379 INFO L432 AbstractCegarLoop]: Abstraction has 150 states and 152 transitions. [2018-01-29 23:37:51,379 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-01-29 23:37:51,379 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 152 transitions. [2018-01-29 23:37:51,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2018-01-29 23:37:51,379 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:51,379 INFO L350 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:51,379 INFO L371 AbstractCegarLoop]: === Iteration 34 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:51,380 INFO L82 PathProgramCache]: Analyzing trace with hash 791808715, now seen corresponding path program 32 times [2018-01-29 23:37:51,380 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:51,380 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:51,380 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:51,380 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:51,380 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:51,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:51,386 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:51,722 INFO L134 CoverageAnalysis]: Checked inductivity of 2048 backedges. 0 proven. 2048 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:51,722 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:51,722 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:51,726 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 23:37:51,730 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:51,749 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:51,753 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:51,754 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:51,768 INFO L134 CoverageAnalysis]: Checked inductivity of 2048 backedges. 0 proven. 2048 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:51,786 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:51,786 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 35 [2018-01-29 23:37:51,787 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-01-29 23:37:51,787 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-01-29 23:37:51,787 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2018-01-29 23:37:51,787 INFO L87 Difference]: Start difference. First operand 150 states and 152 transitions. Second operand 35 states. [2018-01-29 23:37:52,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:52,452 INFO L93 Difference]: Finished difference Result 170 states and 174 transitions. [2018-01-29 23:37:52,452 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-01-29 23:37:52,452 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 144 [2018-01-29 23:37:52,453 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:52,453 INFO L225 Difference]: With dead ends: 170 [2018-01-29 23:37:52,453 INFO L226 Difference]: Without dead ends: 156 [2018-01-29 23:37:52,453 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 178 GetRequests, 145 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2018-01-29 23:37:52,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-01-29 23:37:52,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 154. [2018-01-29 23:37:52,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-01-29 23:37:52,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 156 transitions. [2018-01-29 23:37:52,455 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 156 transitions. Word has length 144 [2018-01-29 23:37:52,455 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:52,455 INFO L432 AbstractCegarLoop]: Abstraction has 154 states and 156 transitions. [2018-01-29 23:37:52,455 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-01-29 23:37:52,455 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 156 transitions. [2018-01-29 23:37:52,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-01-29 23:37:52,456 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:52,456 INFO L350 BasicCegarLoop]: trace histogram [34, 33, 33, 33, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:52,456 INFO L371 AbstractCegarLoop]: === Iteration 35 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:52,456 INFO L82 PathProgramCache]: Analyzing trace with hash 668319922, now seen corresponding path program 33 times [2018-01-29 23:37:52,456 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:52,456 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:52,457 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:52,457 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:52,457 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:52,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:52,463 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:53,114 INFO L134 CoverageAnalysis]: Checked inductivity of 2178 backedges. 0 proven. 2178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:53,114 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:53,114 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:53,119 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 23:37:53,126 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,127 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,127 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,128 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,129 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,129 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,130 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,131 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,133 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,134 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,135 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,136 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,137 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,139 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,141 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,143 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,145 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,147 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,149 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,152 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,155 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,158 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,161 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,165 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,169 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,173 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,178 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,183 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,188 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,194 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,201 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,208 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,216 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,224 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:37:53,225 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:53,226 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:53,242 INFO L134 CoverageAnalysis]: Checked inductivity of 2178 backedges. 0 proven. 2178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:53,259 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:53,259 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 36 [2018-01-29 23:37:53,259 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-01-29 23:37:53,259 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-01-29 23:37:53,259 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-01-29 23:37:53,259 INFO L87 Difference]: Start difference. First operand 154 states and 156 transitions. Second operand 36 states. [2018-01-29 23:37:53,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:53,460 INFO L93 Difference]: Finished difference Result 174 states and 178 transitions. [2018-01-29 23:37:53,460 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-01-29 23:37:53,460 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 148 [2018-01-29 23:37:53,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:53,461 INFO L225 Difference]: With dead ends: 174 [2018-01-29 23:37:53,461 INFO L226 Difference]: Without dead ends: 160 [2018-01-29 23:37:53,461 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 149 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-01-29 23:37:53,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-01-29 23:37:53,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 158. [2018-01-29 23:37:53,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-01-29 23:37:53,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 160 transitions. [2018-01-29 23:37:53,467 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 160 transitions. Word has length 148 [2018-01-29 23:37:53,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:53,467 INFO L432 AbstractCegarLoop]: Abstraction has 158 states and 160 transitions. [2018-01-29 23:37:53,467 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-01-29 23:37:53,467 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 160 transitions. [2018-01-29 23:37:53,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-01-29 23:37:53,468 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:53,468 INFO L350 BasicCegarLoop]: trace histogram [35, 34, 34, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:53,468 INFO L371 AbstractCegarLoop]: === Iteration 36 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:53,468 INFO L82 PathProgramCache]: Analyzing trace with hash 441330457, now seen corresponding path program 34 times [2018-01-29 23:37:53,468 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:53,468 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:53,468 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:53,468 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:53,468 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:53,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:53,474 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:53,868 INFO L134 CoverageAnalysis]: Checked inductivity of 2312 backedges. 0 proven. 2312 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:53,868 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:53,868 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:53,873 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 23:37:53,906 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:53,908 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:53,923 INFO L134 CoverageAnalysis]: Checked inductivity of 2312 backedges. 0 proven. 2312 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:53,939 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:53,940 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 37 [2018-01-29 23:37:53,940 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-01-29 23:37:53,940 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-01-29 23:37:53,940 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2018-01-29 23:37:53,940 INFO L87 Difference]: Start difference. First operand 158 states and 160 transitions. Second operand 37 states. [2018-01-29 23:37:54,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:54,103 INFO L93 Difference]: Finished difference Result 178 states and 182 transitions. [2018-01-29 23:37:54,104 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-01-29 23:37:54,104 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 152 [2018-01-29 23:37:54,104 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:54,104 INFO L225 Difference]: With dead ends: 178 [2018-01-29 23:37:54,104 INFO L226 Difference]: Without dead ends: 164 [2018-01-29 23:37:54,105 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 188 GetRequests, 153 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2018-01-29 23:37:54,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164 states. [2018-01-29 23:37:54,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164 to 162. [2018-01-29 23:37:54,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-01-29 23:37:54,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 164 transitions. [2018-01-29 23:37:54,106 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 164 transitions. Word has length 152 [2018-01-29 23:37:54,107 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:54,107 INFO L432 AbstractCegarLoop]: Abstraction has 162 states and 164 transitions. [2018-01-29 23:37:54,107 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-01-29 23:37:54,107 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 164 transitions. [2018-01-29 23:37:54,107 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2018-01-29 23:37:54,107 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:54,107 INFO L350 BasicCegarLoop]: trace histogram [36, 35, 35, 35, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:54,107 INFO L371 AbstractCegarLoop]: === Iteration 37 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:54,107 INFO L82 PathProgramCache]: Analyzing trace with hash -332592640, now seen corresponding path program 35 times [2018-01-29 23:37:54,107 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:54,107 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:54,108 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:54,108 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:54,108 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:54,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:54,113 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:54,759 INFO L134 CoverageAnalysis]: Checked inductivity of 2450 backedges. 0 proven. 2450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:54,759 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:54,760 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:54,764 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 23:37:54,768 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,769 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,770 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,771 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,771 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,772 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,773 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,774 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,775 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,777 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,778 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,780 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,781 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,783 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,786 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,788 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,791 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,794 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,798 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,802 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,806 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,810 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,815 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,821 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,827 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,835 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,843 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,851 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,861 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,871 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,883 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,895 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,909 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,924 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,940 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,959 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:54,960 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:54,962 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:54,977 INFO L134 CoverageAnalysis]: Checked inductivity of 2450 backedges. 0 proven. 2450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:54,996 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:54,996 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 38 [2018-01-29 23:37:54,997 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-01-29 23:37:54,997 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-01-29 23:37:54,997 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-29 23:37:54,997 INFO L87 Difference]: Start difference. First operand 162 states and 164 transitions. Second operand 38 states. [2018-01-29 23:37:55,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:55,087 INFO L93 Difference]: Finished difference Result 182 states and 186 transitions. [2018-01-29 23:37:55,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-01-29 23:37:55,093 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 156 [2018-01-29 23:37:55,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:55,094 INFO L225 Difference]: With dead ends: 182 [2018-01-29 23:37:55,094 INFO L226 Difference]: Without dead ends: 168 [2018-01-29 23:37:55,094 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 193 GetRequests, 157 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-29 23:37:55,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168 states. [2018-01-29 23:37:55,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168 to 166. [2018-01-29 23:37:55,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-01-29 23:37:55,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 168 transitions. [2018-01-29 23:37:55,096 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 168 transitions. Word has length 156 [2018-01-29 23:37:55,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:55,096 INFO L432 AbstractCegarLoop]: Abstraction has 166 states and 168 transitions. [2018-01-29 23:37:55,096 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-01-29 23:37:55,096 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 168 transitions. [2018-01-29 23:37:55,097 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 161 [2018-01-29 23:37:55,097 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:55,097 INFO L350 BasicCegarLoop]: trace histogram [37, 36, 36, 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:55,097 INFO L371 AbstractCegarLoop]: === Iteration 38 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:55,097 INFO L82 PathProgramCache]: Analyzing trace with hash -467395225, now seen corresponding path program 36 times [2018-01-29 23:37:55,097 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:55,097 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:55,098 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:55,098 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:55,098 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:55,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:55,104 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:56,667 INFO L134 CoverageAnalysis]: Checked inductivity of 2592 backedges. 0 proven. 2592 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:56,668 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:56,668 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:56,673 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 23:37:56,677 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,678 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,678 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,679 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,680 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,680 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,681 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,682 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,683 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,684 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,685 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,686 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,688 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,689 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,690 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,692 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,693 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,695 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,697 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,699 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,701 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,703 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,705 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,707 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,710 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,713 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,716 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,719 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,722 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,725 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,729 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,732 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,736 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,741 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,746 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,751 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,760 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:37:56,760 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:56,762 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:56,778 INFO L134 CoverageAnalysis]: Checked inductivity of 2592 backedges. 0 proven. 2592 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:56,795 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:56,795 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 39 [2018-01-29 23:37:56,795 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-01-29 23:37:56,796 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-01-29 23:37:56,796 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2018-01-29 23:37:56,796 INFO L87 Difference]: Start difference. First operand 166 states and 168 transitions. Second operand 39 states. [2018-01-29 23:37:56,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:56,901 INFO L93 Difference]: Finished difference Result 186 states and 190 transitions. [2018-01-29 23:37:56,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-01-29 23:37:56,901 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 160 [2018-01-29 23:37:56,901 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:56,901 INFO L225 Difference]: With dead ends: 186 [2018-01-29 23:37:56,901 INFO L226 Difference]: Without dead ends: 172 [2018-01-29 23:37:56,902 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 161 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2018-01-29 23:37:56,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-01-29 23:37:56,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 170. [2018-01-29 23:37:56,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-01-29 23:37:56,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 172 transitions. [2018-01-29 23:37:56,904 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 172 transitions. Word has length 160 [2018-01-29 23:37:56,904 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:56,904 INFO L432 AbstractCegarLoop]: Abstraction has 170 states and 172 transitions. [2018-01-29 23:37:56,904 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-01-29 23:37:56,904 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 172 transitions. [2018-01-29 23:37:56,904 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-01-29 23:37:56,904 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:56,904 INFO L350 BasicCegarLoop]: trace histogram [38, 37, 37, 37, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:56,904 INFO L371 AbstractCegarLoop]: === Iteration 39 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:56,904 INFO L82 PathProgramCache]: Analyzing trace with hash 436544846, now seen corresponding path program 37 times [2018-01-29 23:37:56,905 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:56,905 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:56,905 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:56,905 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:56,905 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:56,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:56,910 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:57,682 INFO L134 CoverageAnalysis]: Checked inductivity of 2738 backedges. 0 proven. 2738 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:57,682 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:57,682 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:57,687 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:57,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:57,703 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:57,719 INFO L134 CoverageAnalysis]: Checked inductivity of 2738 backedges. 0 proven. 2738 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:57,736 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:57,736 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 40 [2018-01-29 23:37:57,737 INFO L409 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-01-29 23:37:57,737 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-01-29 23:37:57,737 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-29 23:37:57,737 INFO L87 Difference]: Start difference. First operand 170 states and 172 transitions. Second operand 40 states. [2018-01-29 23:37:59,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:59,089 INFO L93 Difference]: Finished difference Result 190 states and 194 transitions. [2018-01-29 23:37:59,089 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-01-29 23:37:59,089 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 164 [2018-01-29 23:37:59,089 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:59,090 INFO L225 Difference]: With dead ends: 190 [2018-01-29 23:37:59,090 INFO L226 Difference]: Without dead ends: 176 [2018-01-29 23:37:59,090 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-29 23:37:59,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-01-29 23:37:59,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 174. [2018-01-29 23:37:59,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-01-29 23:37:59,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 176 transitions. [2018-01-29 23:37:59,092 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 176 transitions. Word has length 164 [2018-01-29 23:37:59,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:59,092 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 176 transitions. [2018-01-29 23:37:59,092 INFO L433 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-01-29 23:37:59,092 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 176 transitions. [2018-01-29 23:37:59,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2018-01-29 23:37:59,093 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:59,093 INFO L350 BasicCegarLoop]: trace histogram [39, 38, 38, 38, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:59,093 INFO L371 AbstractCegarLoop]: === Iteration 40 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:59,093 INFO L82 PathProgramCache]: Analyzing trace with hash -423501387, now seen corresponding path program 38 times [2018-01-29 23:37:59,093 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:59,093 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:59,094 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:59,094 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:37:59,094 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:59,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:59,099 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:37:59,641 INFO L134 CoverageAnalysis]: Checked inductivity of 2888 backedges. 0 proven. 2888 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:59,641 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:37:59,641 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:37:59,646 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 23:37:59,650 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:59,658 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:37:59,660 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:37:59,661 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:37:59,678 INFO L134 CoverageAnalysis]: Checked inductivity of 2888 backedges. 0 proven. 2888 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:37:59,696 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:37:59,696 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41] total 41 [2018-01-29 23:37:59,696 INFO L409 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-01-29 23:37:59,697 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-01-29 23:37:59,697 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2018-01-29 23:37:59,697 INFO L87 Difference]: Start difference. First operand 174 states and 176 transitions. Second operand 41 states. [2018-01-29 23:37:59,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:37:59,796 INFO L93 Difference]: Finished difference Result 194 states and 198 transitions. [2018-01-29 23:37:59,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-01-29 23:37:59,796 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 168 [2018-01-29 23:37:59,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:37:59,797 INFO L225 Difference]: With dead ends: 194 [2018-01-29 23:37:59,797 INFO L226 Difference]: Without dead ends: 180 [2018-01-29 23:37:59,797 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 208 GetRequests, 169 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2018-01-29 23:37:59,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-01-29 23:37:59,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 178. [2018-01-29 23:37:59,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178 states. [2018-01-29 23:37:59,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 180 transitions. [2018-01-29 23:37:59,799 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 180 transitions. Word has length 168 [2018-01-29 23:37:59,799 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:37:59,799 INFO L432 AbstractCegarLoop]: Abstraction has 178 states and 180 transitions. [2018-01-29 23:37:59,799 INFO L433 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-01-29 23:37:59,799 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 180 transitions. [2018-01-29 23:37:59,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2018-01-29 23:37:59,800 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:37:59,800 INFO L350 BasicCegarLoop]: trace histogram [40, 39, 39, 39, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:37:59,800 INFO L371 AbstractCegarLoop]: === Iteration 41 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:37:59,800 INFO L82 PathProgramCache]: Analyzing trace with hash 1416368796, now seen corresponding path program 39 times [2018-01-29 23:37:59,800 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:37:59,800 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:37:59,800 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:59,800 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:37:59,800 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:37:59,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:37:59,806 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:00,465 INFO L134 CoverageAnalysis]: Checked inductivity of 3042 backedges. 0 proven. 3042 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:00,465 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:00,465 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:00,470 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 23:38:00,474 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,475 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,476 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,476 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,477 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,478 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,479 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,480 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,481 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,482 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,483 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,485 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,486 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,487 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,489 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,491 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,493 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,495 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,498 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,500 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,503 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,506 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,509 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,513 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,517 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,521 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,526 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,531 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,536 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,542 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,548 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,556 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,563 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,572 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,580 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,590 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,600 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,610 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,622 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,635 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:00,636 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:00,637 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:00,655 INFO L134 CoverageAnalysis]: Checked inductivity of 3042 backedges. 0 proven. 3042 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:00,672 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:00,672 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 42 [2018-01-29 23:38:00,672 INFO L409 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-01-29 23:38:00,672 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-01-29 23:38:00,673 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-01-29 23:38:00,673 INFO L87 Difference]: Start difference. First operand 178 states and 180 transitions. Second operand 42 states. [2018-01-29 23:38:00,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:00,767 INFO L93 Difference]: Finished difference Result 198 states and 202 transitions. [2018-01-29 23:38:00,767 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-01-29 23:38:00,767 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 172 [2018-01-29 23:38:00,767 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:00,767 INFO L225 Difference]: With dead ends: 198 [2018-01-29 23:38:00,768 INFO L226 Difference]: Without dead ends: 184 [2018-01-29 23:38:00,768 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 213 GetRequests, 173 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-01-29 23:38:00,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-01-29 23:38:00,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 182. [2018-01-29 23:38:00,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-01-29 23:38:00,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 184 transitions. [2018-01-29 23:38:00,770 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 184 transitions. Word has length 172 [2018-01-29 23:38:00,770 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:00,770 INFO L432 AbstractCegarLoop]: Abstraction has 182 states and 184 transitions. [2018-01-29 23:38:00,770 INFO L433 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-01-29 23:38:00,770 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 184 transitions. [2018-01-29 23:38:00,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2018-01-29 23:38:00,771 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:00,771 INFO L350 BasicCegarLoop]: trace histogram [41, 40, 40, 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:00,771 INFO L371 AbstractCegarLoop]: === Iteration 42 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:00,771 INFO L82 PathProgramCache]: Analyzing trace with hash -1909098493, now seen corresponding path program 40 times [2018-01-29 23:38:00,771 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:00,771 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:00,771 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:00,771 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:00,771 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:00,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:00,776 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:01,283 INFO L134 CoverageAnalysis]: Checked inductivity of 3200 backedges. 0 proven. 3200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:01,283 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:01,283 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:01,288 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 23:38:01,302 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:01,303 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:01,326 INFO L134 CoverageAnalysis]: Checked inductivity of 3200 backedges. 0 proven. 3200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:01,342 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:01,342 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 43 [2018-01-29 23:38:01,343 INFO L409 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-01-29 23:38:01,343 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-01-29 23:38:01,343 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2018-01-29 23:38:01,343 INFO L87 Difference]: Start difference. First operand 182 states and 184 transitions. Second operand 43 states. [2018-01-29 23:38:01,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:01,432 INFO L93 Difference]: Finished difference Result 202 states and 206 transitions. [2018-01-29 23:38:01,432 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-01-29 23:38:01,432 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 176 [2018-01-29 23:38:01,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:01,433 INFO L225 Difference]: With dead ends: 202 [2018-01-29 23:38:01,433 INFO L226 Difference]: Without dead ends: 188 [2018-01-29 23:38:01,433 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 218 GetRequests, 177 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2018-01-29 23:38:01,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-01-29 23:38:01,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 186. [2018-01-29 23:38:01,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-01-29 23:38:01,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 188 transitions. [2018-01-29 23:38:01,435 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 188 transitions. Word has length 176 [2018-01-29 23:38:01,435 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:01,435 INFO L432 AbstractCegarLoop]: Abstraction has 186 states and 188 transitions. [2018-01-29 23:38:01,435 INFO L433 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-01-29 23:38:01,435 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 188 transitions. [2018-01-29 23:38:01,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2018-01-29 23:38:01,436 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:01,437 INFO L350 BasicCegarLoop]: trace histogram [42, 41, 41, 41, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:01,437 INFO L371 AbstractCegarLoop]: === Iteration 43 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:01,437 INFO L82 PathProgramCache]: Analyzing trace with hash 1349505514, now seen corresponding path program 41 times [2018-01-29 23:38:01,437 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:01,437 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:01,438 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:01,438 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:01,438 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:01,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:01,443 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:02,412 INFO L134 CoverageAnalysis]: Checked inductivity of 3362 backedges. 0 proven. 3362 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:02,412 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:02,412 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:02,433 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 23:38:02,437 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,444 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,453 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,463 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,464 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,464 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,465 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,467 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,468 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,469 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,471 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,472 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,474 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,476 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,478 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,481 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,483 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,486 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,490 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,494 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,498 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,502 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,507 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,513 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,519 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,526 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,534 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,543 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,553 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,563 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,574 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,587 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,601 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,616 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,632 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,649 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,669 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,690 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,714 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,739 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,766 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,795 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:02,796 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:02,798 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:02,817 INFO L134 CoverageAnalysis]: Checked inductivity of 3362 backedges. 0 proven. 3362 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:02,834 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:02,834 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 44 [2018-01-29 23:38:02,835 INFO L409 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-01-29 23:38:02,835 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-01-29 23:38:02,835 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-29 23:38:02,835 INFO L87 Difference]: Start difference. First operand 186 states and 188 transitions. Second operand 44 states. [2018-01-29 23:38:02,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:02,913 INFO L93 Difference]: Finished difference Result 206 states and 210 transitions. [2018-01-29 23:38:02,913 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-01-29 23:38:02,913 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 180 [2018-01-29 23:38:02,914 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:02,914 INFO L225 Difference]: With dead ends: 206 [2018-01-29 23:38:02,914 INFO L226 Difference]: Without dead ends: 192 [2018-01-29 23:38:02,915 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 223 GetRequests, 181 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-29 23:38:02,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 192 states. [2018-01-29 23:38:02,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 192 to 190. [2018-01-29 23:38:02,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-01-29 23:38:02,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 192 transitions. [2018-01-29 23:38:02,917 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 192 transitions. Word has length 180 [2018-01-29 23:38:02,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:02,917 INFO L432 AbstractCegarLoop]: Abstraction has 190 states and 192 transitions. [2018-01-29 23:38:02,917 INFO L433 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-01-29 23:38:02,917 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 192 transitions. [2018-01-29 23:38:02,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2018-01-29 23:38:02,917 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:02,917 INFO L350 BasicCegarLoop]: trace histogram [43, 42, 42, 42, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:02,917 INFO L371 AbstractCegarLoop]: === Iteration 44 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:02,918 INFO L82 PathProgramCache]: Analyzing trace with hash 1485627473, now seen corresponding path program 42 times [2018-01-29 23:38:02,918 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:02,918 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:02,918 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:02,918 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:02,918 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:02,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:02,923 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:03,641 INFO L134 CoverageAnalysis]: Checked inductivity of 3528 backedges. 0 proven. 3528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:03,641 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:03,641 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:03,646 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 23:38:03,650 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,651 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,651 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,652 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,653 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,653 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,654 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,655 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,656 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,657 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,658 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,659 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,660 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,661 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,663 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,664 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,666 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,667 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,669 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,671 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,673 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,675 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,677 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,679 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,682 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,684 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,688 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,690 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,694 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,697 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,701 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,705 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,709 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,713 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,717 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,723 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,728 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,733 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,739 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,745 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,773 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,793 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,804 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:03,805 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:03,807 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:03,826 INFO L134 CoverageAnalysis]: Checked inductivity of 3528 backedges. 0 proven. 3528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:03,846 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:03,846 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45] total 45 [2018-01-29 23:38:03,846 INFO L409 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-01-29 23:38:03,847 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-01-29 23:38:03,847 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2018-01-29 23:38:03,847 INFO L87 Difference]: Start difference. First operand 190 states and 192 transitions. Second operand 45 states. [2018-01-29 23:38:03,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:03,956 INFO L93 Difference]: Finished difference Result 210 states and 214 transitions. [2018-01-29 23:38:03,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-01-29 23:38:03,957 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 184 [2018-01-29 23:38:03,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:03,957 INFO L225 Difference]: With dead ends: 210 [2018-01-29 23:38:03,957 INFO L226 Difference]: Without dead ends: 196 [2018-01-29 23:38:03,958 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 228 GetRequests, 185 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2018-01-29 23:38:03,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states. [2018-01-29 23:38:03,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 194. [2018-01-29 23:38:03,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194 states. [2018-01-29 23:38:03,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 196 transitions. [2018-01-29 23:38:03,960 INFO L78 Accepts]: Start accepts. Automaton has 194 states and 196 transitions. Word has length 184 [2018-01-29 23:38:03,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:03,960 INFO L432 AbstractCegarLoop]: Abstraction has 194 states and 196 transitions. [2018-01-29 23:38:03,960 INFO L433 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-01-29 23:38:03,960 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 196 transitions. [2018-01-29 23:38:03,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 189 [2018-01-29 23:38:03,961 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:03,961 INFO L350 BasicCegarLoop]: trace histogram [44, 43, 43, 43, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:03,961 INFO L371 AbstractCegarLoop]: === Iteration 45 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:03,961 INFO L82 PathProgramCache]: Analyzing trace with hash -719428808, now seen corresponding path program 43 times [2018-01-29 23:38:03,961 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:03,961 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:03,962 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:03,962 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:03,962 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:03,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:03,967 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:04,596 INFO L134 CoverageAnalysis]: Checked inductivity of 3698 backedges. 0 proven. 3698 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:04,597 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:04,597 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:04,601 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:38:04,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:04,617 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:04,645 INFO L134 CoverageAnalysis]: Checked inductivity of 3698 backedges. 0 proven. 3698 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:04,661 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:04,661 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 46 [2018-01-29 23:38:04,662 INFO L409 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-01-29 23:38:04,662 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-01-29 23:38:04,662 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-29 23:38:04,662 INFO L87 Difference]: Start difference. First operand 194 states and 196 transitions. Second operand 46 states. [2018-01-29 23:38:04,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:04,764 INFO L93 Difference]: Finished difference Result 214 states and 218 transitions. [2018-01-29 23:38:04,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-01-29 23:38:04,765 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 188 [2018-01-29 23:38:04,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:04,765 INFO L225 Difference]: With dead ends: 214 [2018-01-29 23:38:04,765 INFO L226 Difference]: Without dead ends: 200 [2018-01-29 23:38:04,765 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 233 GetRequests, 189 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-29 23:38:04,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states. [2018-01-29 23:38:04,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 198. [2018-01-29 23:38:04,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 198 states. [2018-01-29 23:38:04,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 200 transitions. [2018-01-29 23:38:04,767 INFO L78 Accepts]: Start accepts. Automaton has 198 states and 200 transitions. Word has length 188 [2018-01-29 23:38:04,767 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:04,767 INFO L432 AbstractCegarLoop]: Abstraction has 198 states and 200 transitions. [2018-01-29 23:38:04,768 INFO L433 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-01-29 23:38:04,768 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 200 transitions. [2018-01-29 23:38:04,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 193 [2018-01-29 23:38:04,768 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:04,768 INFO L350 BasicCegarLoop]: trace histogram [45, 44, 44, 44, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:04,768 INFO L371 AbstractCegarLoop]: === Iteration 46 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:04,768 INFO L82 PathProgramCache]: Analyzing trace with hash -707388769, now seen corresponding path program 44 times [2018-01-29 23:38:04,768 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:04,768 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:04,769 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:04,769 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:38:04,769 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:04,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:04,774 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:05,420 INFO L134 CoverageAnalysis]: Checked inductivity of 3872 backedges. 0 proven. 3872 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:05,420 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:05,420 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:05,442 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 23:38:05,447 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:05,457 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:05,458 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:05,460 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:05,481 INFO L134 CoverageAnalysis]: Checked inductivity of 3872 backedges. 0 proven. 3872 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:05,497 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:05,497 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47] total 47 [2018-01-29 23:38:05,497 INFO L409 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-01-29 23:38:05,497 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-01-29 23:38:05,497 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2018-01-29 23:38:05,498 INFO L87 Difference]: Start difference. First operand 198 states and 200 transitions. Second operand 47 states. [2018-01-29 23:38:05,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:05,580 INFO L93 Difference]: Finished difference Result 218 states and 222 transitions. [2018-01-29 23:38:05,580 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-01-29 23:38:05,580 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 192 [2018-01-29 23:38:05,580 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:05,581 INFO L225 Difference]: With dead ends: 218 [2018-01-29 23:38:05,581 INFO L226 Difference]: Without dead ends: 204 [2018-01-29 23:38:05,581 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 193 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2018-01-29 23:38:05,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states. [2018-01-29 23:38:05,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 202. [2018-01-29 23:38:05,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202 states. [2018-01-29 23:38:05,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202 states to 202 states and 204 transitions. [2018-01-29 23:38:05,583 INFO L78 Accepts]: Start accepts. Automaton has 202 states and 204 transitions. Word has length 192 [2018-01-29 23:38:05,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:05,583 INFO L432 AbstractCegarLoop]: Abstraction has 202 states and 204 transitions. [2018-01-29 23:38:05,583 INFO L433 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-01-29 23:38:05,583 INFO L276 IsEmpty]: Start isEmpty. Operand 202 states and 204 transitions. [2018-01-29 23:38:05,583 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 197 [2018-01-29 23:38:05,583 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:05,584 INFO L350 BasicCegarLoop]: trace histogram [46, 45, 45, 45, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:05,584 INFO L371 AbstractCegarLoop]: === Iteration 47 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:05,584 INFO L82 PathProgramCache]: Analyzing trace with hash -1148860794, now seen corresponding path program 45 times [2018-01-29 23:38:05,584 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:05,584 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:05,584 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:05,584 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:05,584 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:05,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:05,590 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:06,286 INFO L134 CoverageAnalysis]: Checked inductivity of 4050 backedges. 0 proven. 4050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:06,287 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:06,287 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:06,292 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 23:38:06,297 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,298 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,299 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,299 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,300 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,301 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,302 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,303 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,304 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,305 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,306 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,308 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,309 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,311 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,313 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,315 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,317 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,319 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,322 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,324 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,327 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,330 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,334 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,337 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,341 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,346 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,350 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,356 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,361 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,367 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,373 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,381 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,388 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,396 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,405 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,415 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,424 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,436 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,447 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,460 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,473 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,488 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,504 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,521 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,538 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,556 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:06,557 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:06,559 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:06,588 INFO L134 CoverageAnalysis]: Checked inductivity of 4050 backedges. 0 proven. 4050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:06,605 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:06,605 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48] total 48 [2018-01-29 23:38:06,605 INFO L409 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-01-29 23:38:06,605 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-01-29 23:38:06,606 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-01-29 23:38:06,606 INFO L87 Difference]: Start difference. First operand 202 states and 204 transitions. Second operand 48 states. [2018-01-29 23:38:06,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:06,704 INFO L93 Difference]: Finished difference Result 222 states and 226 transitions. [2018-01-29 23:38:06,704 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-01-29 23:38:06,704 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 196 [2018-01-29 23:38:06,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:06,705 INFO L225 Difference]: With dead ends: 222 [2018-01-29 23:38:06,705 INFO L226 Difference]: Without dead ends: 208 [2018-01-29 23:38:06,705 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 243 GetRequests, 197 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-01-29 23:38:06,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states. [2018-01-29 23:38:06,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 206. [2018-01-29 23:38:06,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-01-29 23:38:06,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 208 transitions. [2018-01-29 23:38:06,707 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 208 transitions. Word has length 196 [2018-01-29 23:38:06,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:06,707 INFO L432 AbstractCegarLoop]: Abstraction has 206 states and 208 transitions. [2018-01-29 23:38:06,707 INFO L433 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-01-29 23:38:06,707 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 208 transitions. [2018-01-29 23:38:06,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2018-01-29 23:38:06,708 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:06,708 INFO L350 BasicCegarLoop]: trace histogram [47, 46, 46, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:06,708 INFO L371 AbstractCegarLoop]: === Iteration 48 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:06,708 INFO L82 PathProgramCache]: Analyzing trace with hash -1474353427, now seen corresponding path program 46 times [2018-01-29 23:38:06,708 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:06,708 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:06,708 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:06,708 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:06,708 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:06,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:06,714 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:07,344 INFO L134 CoverageAnalysis]: Checked inductivity of 4232 backedges. 0 proven. 4232 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:07,344 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:07,344 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:07,349 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 23:38:07,370 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:07,372 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:07,394 INFO L134 CoverageAnalysis]: Checked inductivity of 4232 backedges. 0 proven. 4232 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:07,413 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:07,413 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 49 [2018-01-29 23:38:07,413 INFO L409 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-01-29 23:38:07,413 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-01-29 23:38:07,413 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2018-01-29 23:38:07,414 INFO L87 Difference]: Start difference. First operand 206 states and 208 transitions. Second operand 49 states. [2018-01-29 23:38:07,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:07,670 INFO L93 Difference]: Finished difference Result 226 states and 230 transitions. [2018-01-29 23:38:07,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-01-29 23:38:07,670 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 200 [2018-01-29 23:38:07,671 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:07,671 INFO L225 Difference]: With dead ends: 226 [2018-01-29 23:38:07,671 INFO L226 Difference]: Without dead ends: 212 [2018-01-29 23:38:07,671 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 248 GetRequests, 201 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2018-01-29 23:38:07,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states. [2018-01-29 23:38:07,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 210. [2018-01-29 23:38:07,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 210 states. [2018-01-29 23:38:07,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 212 transitions. [2018-01-29 23:38:07,673 INFO L78 Accepts]: Start accepts. Automaton has 210 states and 212 transitions. Word has length 200 [2018-01-29 23:38:07,673 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:07,674 INFO L432 AbstractCegarLoop]: Abstraction has 210 states and 212 transitions. [2018-01-29 23:38:07,674 INFO L433 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-01-29 23:38:07,674 INFO L276 IsEmpty]: Start isEmpty. Operand 210 states and 212 transitions. [2018-01-29 23:38:07,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 205 [2018-01-29 23:38:07,674 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:07,674 INFO L350 BasicCegarLoop]: trace histogram [48, 47, 47, 47, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:07,674 INFO L371 AbstractCegarLoop]: === Iteration 49 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:07,674 INFO L82 PathProgramCache]: Analyzing trace with hash -290194476, now seen corresponding path program 47 times [2018-01-29 23:38:07,674 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:07,674 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:07,675 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:07,675 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:07,675 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:07,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:07,681 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:08,348 INFO L134 CoverageAnalysis]: Checked inductivity of 4418 backedges. 0 proven. 4418 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:08,348 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:08,348 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:08,353 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 23:38:08,357 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,357 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,358 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,359 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,359 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,360 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,361 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,362 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,363 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,365 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,366 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,367 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,369 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,371 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,373 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,376 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,379 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,382 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,385 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,389 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,393 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,398 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,403 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,408 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,415 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,422 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,430 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,439 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,448 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,458 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,470 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,482 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,496 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,511 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,527 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,545 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,565 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,586 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,609 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,634 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,660 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,689 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,718 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,751 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,786 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,823 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,862 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,906 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:08,907 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:08,910 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:08,940 INFO L134 CoverageAnalysis]: Checked inductivity of 4418 backedges. 0 proven. 4418 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:08,957 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:08,957 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 50 [2018-01-29 23:38:08,958 INFO L409 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-01-29 23:38:08,958 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-01-29 23:38:08,958 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-29 23:38:08,958 INFO L87 Difference]: Start difference. First operand 210 states and 212 transitions. Second operand 50 states. [2018-01-29 23:38:09,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:09,087 INFO L93 Difference]: Finished difference Result 230 states and 234 transitions. [2018-01-29 23:38:09,087 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-01-29 23:38:09,087 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 204 [2018-01-29 23:38:09,087 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:09,088 INFO L225 Difference]: With dead ends: 230 [2018-01-29 23:38:09,088 INFO L226 Difference]: Without dead ends: 216 [2018-01-29 23:38:09,088 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 253 GetRequests, 205 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-29 23:38:09,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-01-29 23:38:09,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 214. [2018-01-29 23:38:09,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-01-29 23:38:09,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 216 transitions. [2018-01-29 23:38:09,091 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 216 transitions. Word has length 204 [2018-01-29 23:38:09,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:09,091 INFO L432 AbstractCegarLoop]: Abstraction has 214 states and 216 transitions. [2018-01-29 23:38:09,091 INFO L433 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-01-29 23:38:09,091 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 216 transitions. [2018-01-29 23:38:09,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 209 [2018-01-29 23:38:09,091 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:09,092 INFO L350 BasicCegarLoop]: trace histogram [49, 48, 48, 48, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:09,092 INFO L371 AbstractCegarLoop]: === Iteration 50 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:09,092 INFO L82 PathProgramCache]: Analyzing trace with hash -2089417413, now seen corresponding path program 48 times [2018-01-29 23:38:09,092 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:09,092 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:09,092 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:09,092 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:09,092 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:09,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:09,098 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:09,995 INFO L134 CoverageAnalysis]: Checked inductivity of 4608 backedges. 0 proven. 4608 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:09,996 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:09,996 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:10,000 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 23:38:10,005 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,006 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,007 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,007 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,008 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,009 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,009 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,010 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,011 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,012 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,013 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,014 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,015 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,016 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,018 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,019 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,020 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,022 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,024 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,026 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,028 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,030 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,032 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,034 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,037 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,040 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,042 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,046 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,049 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,052 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,056 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,060 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,064 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,068 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,072 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,077 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,082 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,089 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,095 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,101 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,108 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,116 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,123 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,131 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,140 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,149 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,158 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,181 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,201 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:10,202 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:10,205 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:10,229 INFO L134 CoverageAnalysis]: Checked inductivity of 4608 backedges. 0 proven. 4608 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:10,246 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:10,246 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51] total 51 [2018-01-29 23:38:10,246 INFO L409 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-01-29 23:38:10,247 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-01-29 23:38:10,247 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2018-01-29 23:38:10,247 INFO L87 Difference]: Start difference. First operand 214 states and 216 transitions. Second operand 51 states. [2018-01-29 23:38:10,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:10,346 INFO L93 Difference]: Finished difference Result 234 states and 238 transitions. [2018-01-29 23:38:10,347 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-01-29 23:38:10,347 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 208 [2018-01-29 23:38:10,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:10,347 INFO L225 Difference]: With dead ends: 234 [2018-01-29 23:38:10,347 INFO L226 Difference]: Without dead ends: 220 [2018-01-29 23:38:10,348 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 258 GetRequests, 209 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2018-01-29 23:38:10,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-01-29 23:38:10,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 218. [2018-01-29 23:38:10,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 218 states. [2018-01-29 23:38:10,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 220 transitions. [2018-01-29 23:38:10,350 INFO L78 Accepts]: Start accepts. Automaton has 218 states and 220 transitions. Word has length 208 [2018-01-29 23:38:10,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:10,350 INFO L432 AbstractCegarLoop]: Abstraction has 218 states and 220 transitions. [2018-01-29 23:38:10,350 INFO L433 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-01-29 23:38:10,350 INFO L276 IsEmpty]: Start isEmpty. Operand 218 states and 220 transitions. [2018-01-29 23:38:10,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 213 [2018-01-29 23:38:10,350 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:10,351 INFO L350 BasicCegarLoop]: trace histogram [50, 49, 49, 49, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:10,351 INFO L371 AbstractCegarLoop]: === Iteration 51 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:10,351 INFO L82 PathProgramCache]: Analyzing trace with hash 1807156002, now seen corresponding path program 49 times [2018-01-29 23:38:10,351 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:10,351 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:10,351 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:10,351 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:10,351 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:10,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:10,357 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:11,088 INFO L134 CoverageAnalysis]: Checked inductivity of 4802 backedges. 0 proven. 4802 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:11,088 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:11,088 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:11,092 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:38:11,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:11,110 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:11,134 INFO L134 CoverageAnalysis]: Checked inductivity of 4802 backedges. 0 proven. 4802 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:11,153 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:11,153 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52] total 52 [2018-01-29 23:38:11,153 INFO L409 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-01-29 23:38:11,153 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-01-29 23:38:11,154 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-29 23:38:11,154 INFO L87 Difference]: Start difference. First operand 218 states and 220 transitions. Second operand 52 states. [2018-01-29 23:38:11,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:11,358 INFO L93 Difference]: Finished difference Result 238 states and 242 transitions. [2018-01-29 23:38:11,358 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-01-29 23:38:11,358 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 212 [2018-01-29 23:38:11,359 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:11,359 INFO L225 Difference]: With dead ends: 238 [2018-01-29 23:38:11,359 INFO L226 Difference]: Without dead ends: 224 [2018-01-29 23:38:11,360 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 263 GetRequests, 213 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-29 23:38:11,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-01-29 23:38:11,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 222. [2018-01-29 23:38:11,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222 states. [2018-01-29 23:38:11,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 224 transitions. [2018-01-29 23:38:11,362 INFO L78 Accepts]: Start accepts. Automaton has 222 states and 224 transitions. Word has length 212 [2018-01-29 23:38:11,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:11,362 INFO L432 AbstractCegarLoop]: Abstraction has 222 states and 224 transitions. [2018-01-29 23:38:11,362 INFO L433 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-01-29 23:38:11,362 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 224 transitions. [2018-01-29 23:38:11,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 217 [2018-01-29 23:38:11,363 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:11,363 INFO L350 BasicCegarLoop]: trace histogram [51, 50, 50, 50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:11,364 INFO L371 AbstractCegarLoop]: === Iteration 52 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:11,364 INFO L82 PathProgramCache]: Analyzing trace with hash 770225545, now seen corresponding path program 50 times [2018-01-29 23:38:11,364 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:11,364 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:11,364 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:11,364 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:38:11,364 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:11,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:11,371 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:12,111 INFO L134 CoverageAnalysis]: Checked inductivity of 5000 backedges. 0 proven. 5000 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:12,112 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:12,112 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:12,118 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 23:38:12,122 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:12,131 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:12,133 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:12,136 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:12,163 INFO L134 CoverageAnalysis]: Checked inductivity of 5000 backedges. 0 proven. 5000 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:12,179 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:12,180 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53] total 53 [2018-01-29 23:38:12,180 INFO L409 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-01-29 23:38:12,180 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-01-29 23:38:12,180 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1378, Invalid=1378, Unknown=0, NotChecked=0, Total=2756 [2018-01-29 23:38:12,180 INFO L87 Difference]: Start difference. First operand 222 states and 224 transitions. Second operand 53 states. [2018-01-29 23:38:12,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:12,772 INFO L93 Difference]: Finished difference Result 242 states and 246 transitions. [2018-01-29 23:38:12,772 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-01-29 23:38:12,772 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 216 [2018-01-29 23:38:12,772 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:12,773 INFO L225 Difference]: With dead ends: 242 [2018-01-29 23:38:12,773 INFO L226 Difference]: Without dead ends: 228 [2018-01-29 23:38:12,773 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 268 GetRequests, 217 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1378, Invalid=1378, Unknown=0, NotChecked=0, Total=2756 [2018-01-29 23:38:12,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states. [2018-01-29 23:38:12,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 226. [2018-01-29 23:38:12,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-01-29 23:38:12,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 228 transitions. [2018-01-29 23:38:12,776 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 228 transitions. Word has length 216 [2018-01-29 23:38:12,776 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:12,776 INFO L432 AbstractCegarLoop]: Abstraction has 226 states and 228 transitions. [2018-01-29 23:38:12,776 INFO L433 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-01-29 23:38:12,776 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 228 transitions. [2018-01-29 23:38:12,777 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 221 [2018-01-29 23:38:12,777 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:12,778 INFO L350 BasicCegarLoop]: trace histogram [52, 51, 51, 51, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:12,778 INFO L371 AbstractCegarLoop]: === Iteration 53 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:12,778 INFO L82 PathProgramCache]: Analyzing trace with hash 1100799088, now seen corresponding path program 51 times [2018-01-29 23:38:12,778 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:12,778 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:12,778 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:12,778 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:12,778 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:12,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:12,785 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:13,672 INFO L134 CoverageAnalysis]: Checked inductivity of 5202 backedges. 0 proven. 5202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:13,672 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:13,674 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:13,678 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 23:38:13,683 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,684 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,684 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,685 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,685 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,686 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,687 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,688 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,689 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,690 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,691 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,693 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,694 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,696 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,697 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,699 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,701 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,704 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,706 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,708 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,711 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,714 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,718 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,721 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,725 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,730 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,734 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,740 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,744 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,750 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,757 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,764 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,772 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,780 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,789 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,799 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,809 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,819 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,831 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,844 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,857 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,872 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,887 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,904 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,921 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,940 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,961 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:13,983 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:14,005 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:14,030 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:14,057 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:14,085 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:14,085 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:14,088 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:14,113 INFO L134 CoverageAnalysis]: Checked inductivity of 5202 backedges. 0 proven. 5202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:14,131 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:14,131 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54] total 54 [2018-01-29 23:38:14,131 INFO L409 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-01-29 23:38:14,131 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-01-29 23:38:14,131 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-01-29 23:38:14,132 INFO L87 Difference]: Start difference. First operand 226 states and 228 transitions. Second operand 54 states. [2018-01-29 23:38:14,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:14,249 INFO L93 Difference]: Finished difference Result 246 states and 250 transitions. [2018-01-29 23:38:14,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-01-29 23:38:14,249 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 220 [2018-01-29 23:38:14,250 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:14,250 INFO L225 Difference]: With dead ends: 246 [2018-01-29 23:38:14,250 INFO L226 Difference]: Without dead ends: 232 [2018-01-29 23:38:14,250 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 273 GetRequests, 221 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-01-29 23:38:14,250 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232 states. [2018-01-29 23:38:14,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232 to 230. [2018-01-29 23:38:14,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-01-29 23:38:14,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 232 transitions. [2018-01-29 23:38:14,252 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 232 transitions. Word has length 220 [2018-01-29 23:38:14,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:14,252 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 232 transitions. [2018-01-29 23:38:14,252 INFO L433 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-01-29 23:38:14,253 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 232 transitions. [2018-01-29 23:38:14,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 225 [2018-01-29 23:38:14,253 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:14,253 INFO L350 BasicCegarLoop]: trace histogram [53, 52, 52, 52, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:14,253 INFO L371 AbstractCegarLoop]: === Iteration 54 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:14,253 INFO L82 PathProgramCache]: Analyzing trace with hash 2139437015, now seen corresponding path program 52 times [2018-01-29 23:38:14,253 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:14,253 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:14,254 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:14,254 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:14,254 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:14,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:14,260 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:15,191 INFO L134 CoverageAnalysis]: Checked inductivity of 5408 backedges. 0 proven. 5408 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:15,192 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:15,192 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:15,196 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 23:38:15,213 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:15,215 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:15,242 INFO L134 CoverageAnalysis]: Checked inductivity of 5408 backedges. 0 proven. 5408 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:15,259 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:15,260 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55] total 55 [2018-01-29 23:38:15,260 INFO L409 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-01-29 23:38:15,260 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-01-29 23:38:15,260 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1485, Invalid=1485, Unknown=0, NotChecked=0, Total=2970 [2018-01-29 23:38:15,260 INFO L87 Difference]: Start difference. First operand 230 states and 232 transitions. Second operand 55 states. [2018-01-29 23:38:16,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:16,439 INFO L93 Difference]: Finished difference Result 250 states and 254 transitions. [2018-01-29 23:38:16,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-01-29 23:38:16,439 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 224 [2018-01-29 23:38:16,440 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:16,440 INFO L225 Difference]: With dead ends: 250 [2018-01-29 23:38:16,440 INFO L226 Difference]: Without dead ends: 236 [2018-01-29 23:38:16,441 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 278 GetRequests, 225 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1485, Invalid=1485, Unknown=0, NotChecked=0, Total=2970 [2018-01-29 23:38:16,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-01-29 23:38:16,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 234. [2018-01-29 23:38:16,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234 states. [2018-01-29 23:38:16,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234 states to 234 states and 236 transitions. [2018-01-29 23:38:16,442 INFO L78 Accepts]: Start accepts. Automaton has 234 states and 236 transitions. Word has length 224 [2018-01-29 23:38:16,443 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:16,443 INFO L432 AbstractCegarLoop]: Abstraction has 234 states and 236 transitions. [2018-01-29 23:38:16,443 INFO L433 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-01-29 23:38:16,443 INFO L276 IsEmpty]: Start isEmpty. Operand 234 states and 236 transitions. [2018-01-29 23:38:16,444 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 229 [2018-01-29 23:38:16,444 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:16,444 INFO L350 BasicCegarLoop]: trace histogram [54, 53, 53, 53, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:16,444 INFO L371 AbstractCegarLoop]: === Iteration 55 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:16,444 INFO L82 PathProgramCache]: Analyzing trace with hash -1854699586, now seen corresponding path program 53 times [2018-01-29 23:38:16,444 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:16,444 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:16,444 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:16,445 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:16,445 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:16,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:16,451 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:17,262 INFO L134 CoverageAnalysis]: Checked inductivity of 5618 backedges. 0 proven. 5618 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:17,262 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:17,262 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:17,266 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 23:38:17,270 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,276 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,277 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,278 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,278 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,279 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,280 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,281 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,282 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,283 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,285 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,286 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,288 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,290 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,292 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,295 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,298 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,301 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,304 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,308 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,312 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,317 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,322 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,327 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,334 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,341 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,349 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,358 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,368 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,378 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,389 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,402 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,416 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,431 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,447 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,466 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,485 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,506 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,530 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,555 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,582 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,611 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,641 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,674 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,709 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,746 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,786 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,829 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,874 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,922 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:17,974 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:18,029 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:18,089 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:18,153 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:18,154 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:18,157 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:18,184 INFO L134 CoverageAnalysis]: Checked inductivity of 5618 backedges. 0 proven. 5618 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:18,202 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:18,202 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 56] total 56 [2018-01-29 23:38:18,203 INFO L409 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-01-29 23:38:18,203 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-01-29 23:38:18,203 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-29 23:38:18,203 INFO L87 Difference]: Start difference. First operand 234 states and 236 transitions. Second operand 56 states. [2018-01-29 23:38:18,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:18,332 INFO L93 Difference]: Finished difference Result 254 states and 258 transitions. [2018-01-29 23:38:18,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-01-29 23:38:18,332 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 228 [2018-01-29 23:38:18,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:18,333 INFO L225 Difference]: With dead ends: 254 [2018-01-29 23:38:18,333 INFO L226 Difference]: Without dead ends: 240 [2018-01-29 23:38:18,333 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 283 GetRequests, 229 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-29 23:38:18,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240 states. [2018-01-29 23:38:18,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240 to 238. [2018-01-29 23:38:18,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-01-29 23:38:18,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 240 transitions. [2018-01-29 23:38:18,335 INFO L78 Accepts]: Start accepts. Automaton has 238 states and 240 transitions. Word has length 228 [2018-01-29 23:38:18,335 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:18,335 INFO L432 AbstractCegarLoop]: Abstraction has 238 states and 240 transitions. [2018-01-29 23:38:18,335 INFO L433 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-01-29 23:38:18,335 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 240 transitions. [2018-01-29 23:38:18,336 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 233 [2018-01-29 23:38:18,336 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:18,336 INFO L350 BasicCegarLoop]: trace histogram [55, 54, 54, 54, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:18,336 INFO L371 AbstractCegarLoop]: === Iteration 56 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:18,336 INFO L82 PathProgramCache]: Analyzing trace with hash 1650035749, now seen corresponding path program 54 times [2018-01-29 23:38:18,339 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:18,339 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:18,340 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:18,340 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:18,340 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:18,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:18,346 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:19,250 INFO L134 CoverageAnalysis]: Checked inductivity of 5832 backedges. 0 proven. 5832 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:19,250 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:19,250 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:19,255 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 23:38:19,260 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,269 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,270 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,270 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,271 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,272 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,273 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,273 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,274 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,275 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,276 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,277 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,278 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,280 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,281 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,282 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,284 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,285 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,287 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,289 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,291 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,293 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,295 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,297 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,300 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,303 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,306 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,309 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,312 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,316 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,319 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,323 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,327 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,331 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,336 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,340 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,345 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,351 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,357 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,362 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,369 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,376 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,384 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,391 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,399 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,407 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,416 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,425 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,435 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,445 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,456 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,468 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,481 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,494 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,542 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:19,543 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:19,545 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:19,573 INFO L134 CoverageAnalysis]: Checked inductivity of 5832 backedges. 0 proven. 5832 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:19,591 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:19,591 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57] total 57 [2018-01-29 23:38:19,592 INFO L409 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-01-29 23:38:19,592 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-01-29 23:38:19,592 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1596, Invalid=1596, Unknown=0, NotChecked=0, Total=3192 [2018-01-29 23:38:19,592 INFO L87 Difference]: Start difference. First operand 238 states and 240 transitions. Second operand 57 states. [2018-01-29 23:38:19,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:19,718 INFO L93 Difference]: Finished difference Result 258 states and 262 transitions. [2018-01-29 23:38:19,718 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-01-29 23:38:19,718 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 232 [2018-01-29 23:38:19,718 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:19,719 INFO L225 Difference]: With dead ends: 258 [2018-01-29 23:38:19,719 INFO L226 Difference]: Without dead ends: 244 [2018-01-29 23:38:19,719 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 288 GetRequests, 233 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1596, Invalid=1596, Unknown=0, NotChecked=0, Total=3192 [2018-01-29 23:38:19,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 244 states. [2018-01-29 23:38:19,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 244 to 242. [2018-01-29 23:38:19,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 242 states. [2018-01-29 23:38:19,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242 states to 242 states and 244 transitions. [2018-01-29 23:38:19,721 INFO L78 Accepts]: Start accepts. Automaton has 242 states and 244 transitions. Word has length 232 [2018-01-29 23:38:19,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:19,721 INFO L432 AbstractCegarLoop]: Abstraction has 242 states and 244 transitions. [2018-01-29 23:38:19,721 INFO L433 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-01-29 23:38:19,721 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 244 transitions. [2018-01-29 23:38:19,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 237 [2018-01-29 23:38:19,722 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:19,722 INFO L350 BasicCegarLoop]: trace histogram [56, 55, 55, 55, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:19,722 INFO L371 AbstractCegarLoop]: === Iteration 57 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:19,722 INFO L82 PathProgramCache]: Analyzing trace with hash -1907817204, now seen corresponding path program 55 times [2018-01-29 23:38:19,722 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:19,722 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:19,722 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:19,722 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:19,722 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:19,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:19,729 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:20,703 INFO L134 CoverageAnalysis]: Checked inductivity of 6050 backedges. 0 proven. 6050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:20,703 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:20,703 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:20,716 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:38:20,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:20,735 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:20,787 INFO L134 CoverageAnalysis]: Checked inductivity of 6050 backedges. 0 proven. 6050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:20,804 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:20,805 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 58] total 58 [2018-01-29 23:38:20,805 INFO L409 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-01-29 23:38:20,805 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-01-29 23:38:20,805 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-29 23:38:20,805 INFO L87 Difference]: Start difference. First operand 242 states and 244 transitions. Second operand 58 states. [2018-01-29 23:38:20,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:20,945 INFO L93 Difference]: Finished difference Result 262 states and 266 transitions. [2018-01-29 23:38:20,946 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-01-29 23:38:20,946 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 236 [2018-01-29 23:38:20,946 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:20,946 INFO L225 Difference]: With dead ends: 262 [2018-01-29 23:38:20,946 INFO L226 Difference]: Without dead ends: 248 [2018-01-29 23:38:20,947 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 293 GetRequests, 237 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-29 23:38:20,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248 states. [2018-01-29 23:38:20,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248 to 246. [2018-01-29 23:38:20,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 246 states. [2018-01-29 23:38:20,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 246 states to 246 states and 248 transitions. [2018-01-29 23:38:20,949 INFO L78 Accepts]: Start accepts. Automaton has 246 states and 248 transitions. Word has length 236 [2018-01-29 23:38:20,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:20,949 INFO L432 AbstractCegarLoop]: Abstraction has 246 states and 248 transitions. [2018-01-29 23:38:20,949 INFO L433 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-01-29 23:38:20,950 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 248 transitions. [2018-01-29 23:38:20,950 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 241 [2018-01-29 23:38:20,950 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:20,950 INFO L350 BasicCegarLoop]: trace histogram [57, 56, 56, 56, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:20,950 INFO L371 AbstractCegarLoop]: === Iteration 58 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:20,951 INFO L82 PathProgramCache]: Analyzing trace with hash -764169613, now seen corresponding path program 56 times [2018-01-29 23:38:20,951 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:20,951 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:20,951 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:20,951 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:38:20,951 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:20,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:20,958 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:21,958 INFO L134 CoverageAnalysis]: Checked inductivity of 6272 backedges. 0 proven. 6272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:21,958 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:21,958 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:21,971 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 23:38:21,977 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:21,990 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:21,992 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:21,994 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:22,023 INFO L134 CoverageAnalysis]: Checked inductivity of 6272 backedges. 0 proven. 6272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:22,040 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:22,040 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59] total 59 [2018-01-29 23:38:22,040 INFO L409 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-01-29 23:38:22,040 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-01-29 23:38:22,040 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1711, Invalid=1711, Unknown=0, NotChecked=0, Total=3422 [2018-01-29 23:38:22,040 INFO L87 Difference]: Start difference. First operand 246 states and 248 transitions. Second operand 59 states. [2018-01-29 23:38:22,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:22,200 INFO L93 Difference]: Finished difference Result 266 states and 270 transitions. [2018-01-29 23:38:22,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-01-29 23:38:22,201 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 240 [2018-01-29 23:38:22,201 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:22,201 INFO L225 Difference]: With dead ends: 266 [2018-01-29 23:38:22,201 INFO L226 Difference]: Without dead ends: 252 [2018-01-29 23:38:22,202 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 298 GetRequests, 241 SyntacticMatches, 0 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1711, Invalid=1711, Unknown=0, NotChecked=0, Total=3422 [2018-01-29 23:38:22,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252 states. [2018-01-29 23:38:22,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 252 to 250. [2018-01-29 23:38:22,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-01-29 23:38:22,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 252 transitions. [2018-01-29 23:38:22,204 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 252 transitions. Word has length 240 [2018-01-29 23:38:22,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:22,204 INFO L432 AbstractCegarLoop]: Abstraction has 250 states and 252 transitions. [2018-01-29 23:38:22,204 INFO L433 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-01-29 23:38:22,204 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 252 transitions. [2018-01-29 23:38:22,204 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 245 [2018-01-29 23:38:22,204 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:22,205 INFO L350 BasicCegarLoop]: trace histogram [58, 57, 57, 57, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:22,205 INFO L371 AbstractCegarLoop]: === Iteration 59 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:22,205 INFO L82 PathProgramCache]: Analyzing trace with hash 2099991642, now seen corresponding path program 57 times [2018-01-29 23:38:22,205 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:22,205 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:22,205 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:22,205 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:22,205 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:22,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:22,212 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:23,140 INFO L134 CoverageAnalysis]: Checked inductivity of 6498 backedges. 0 proven. 6498 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:23,140 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:23,140 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:23,144 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 23:38:23,149 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,163 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,173 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,183 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,193 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,203 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,213 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,223 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,229 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,230 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,231 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,233 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,234 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,235 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,237 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,239 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,241 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,243 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,246 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,248 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,251 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,254 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,257 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,261 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,265 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,269 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,274 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,279 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,284 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,290 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,297 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,304 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,311 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,320 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,329 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,338 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,348 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,359 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,371 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,384 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,396 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,411 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,427 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,444 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,461 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,479 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,500 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,523 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,545 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,570 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,596 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,624 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,652 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,682 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,714 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,747 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,783 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,820 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:23,821 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:23,824 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:23,855 INFO L134 CoverageAnalysis]: Checked inductivity of 6498 backedges. 0 proven. 6498 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:23,873 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:23,873 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 60] total 60 [2018-01-29 23:38:23,873 INFO L409 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-01-29 23:38:23,873 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-01-29 23:38:23,874 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-01-29 23:38:23,874 INFO L87 Difference]: Start difference. First operand 250 states and 252 transitions. Second operand 60 states. [2018-01-29 23:38:24,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:24,069 INFO L93 Difference]: Finished difference Result 270 states and 274 transitions. [2018-01-29 23:38:24,069 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-01-29 23:38:24,069 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 244 [2018-01-29 23:38:24,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:24,069 INFO L225 Difference]: With dead ends: 270 [2018-01-29 23:38:24,070 INFO L226 Difference]: Without dead ends: 256 [2018-01-29 23:38:24,070 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 303 GetRequests, 245 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-01-29 23:38:24,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-01-29 23:38:24,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 254. [2018-01-29 23:38:24,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 254 states. [2018-01-29 23:38:24,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254 states to 254 states and 256 transitions. [2018-01-29 23:38:24,072 INFO L78 Accepts]: Start accepts. Automaton has 254 states and 256 transitions. Word has length 244 [2018-01-29 23:38:24,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:24,072 INFO L432 AbstractCegarLoop]: Abstraction has 254 states and 256 transitions. [2018-01-29 23:38:24,072 INFO L433 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-01-29 23:38:24,072 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 256 transitions. [2018-01-29 23:38:24,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 249 [2018-01-29 23:38:24,073 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:24,073 INFO L350 BasicCegarLoop]: trace histogram [59, 58, 58, 58, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:24,073 INFO L371 AbstractCegarLoop]: === Iteration 60 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:24,073 INFO L82 PathProgramCache]: Analyzing trace with hash -572413247, now seen corresponding path program 58 times [2018-01-29 23:38:24,073 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:24,073 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:24,073 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:24,073 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:24,073 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:24,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:24,080 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:25,101 INFO L134 CoverageAnalysis]: Checked inductivity of 6728 backedges. 0 proven. 6728 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:25,101 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:25,102 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:25,108 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 23:38:25,128 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:25,130 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:25,161 INFO L134 CoverageAnalysis]: Checked inductivity of 6728 backedges. 0 proven. 6728 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:25,178 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:25,178 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61] total 61 [2018-01-29 23:38:25,178 INFO L409 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-01-29 23:38:25,179 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-01-29 23:38:25,179 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1830, Invalid=1830, Unknown=0, NotChecked=0, Total=3660 [2018-01-29 23:38:25,179 INFO L87 Difference]: Start difference. First operand 254 states and 256 transitions. Second operand 61 states. [2018-01-29 23:38:25,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:25,338 INFO L93 Difference]: Finished difference Result 274 states and 278 transitions. [2018-01-29 23:38:25,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-01-29 23:38:25,339 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 248 [2018-01-29 23:38:25,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:25,339 INFO L225 Difference]: With dead ends: 274 [2018-01-29 23:38:25,339 INFO L226 Difference]: Without dead ends: 260 [2018-01-29 23:38:25,339 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 308 GetRequests, 249 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1830, Invalid=1830, Unknown=0, NotChecked=0, Total=3660 [2018-01-29 23:38:25,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 260 states. [2018-01-29 23:38:25,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 260 to 258. [2018-01-29 23:38:25,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 258 states. [2018-01-29 23:38:25,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 258 states to 258 states and 260 transitions. [2018-01-29 23:38:25,341 INFO L78 Accepts]: Start accepts. Automaton has 258 states and 260 transitions. Word has length 248 [2018-01-29 23:38:25,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:25,342 INFO L432 AbstractCegarLoop]: Abstraction has 258 states and 260 transitions. [2018-01-29 23:38:25,342 INFO L433 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-01-29 23:38:25,342 INFO L276 IsEmpty]: Start isEmpty. Operand 258 states and 260 transitions. [2018-01-29 23:38:25,342 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 253 [2018-01-29 23:38:25,342 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:25,342 INFO L350 BasicCegarLoop]: trace histogram [60, 59, 59, 59, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:25,342 INFO L371 AbstractCegarLoop]: === Iteration 61 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:25,343 INFO L82 PathProgramCache]: Analyzing trace with hash -1255639640, now seen corresponding path program 59 times [2018-01-29 23:38:25,344 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:25,344 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:25,344 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:25,344 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:25,344 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:25,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:25,352 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:26,350 INFO L134 CoverageAnalysis]: Checked inductivity of 6962 backedges. 0 proven. 6962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:26,350 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:26,350 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:26,354 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 23:38:26,359 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,359 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,360 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,361 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,361 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,362 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,363 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,364 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,366 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,367 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,368 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,370 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,372 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,374 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,376 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,379 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,382 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,385 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,388 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,392 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,396 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,401 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,406 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,411 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,418 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,425 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,432 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,441 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,451 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,461 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,472 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,484 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,498 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,513 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,530 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,548 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,567 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,588 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,611 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,636 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,662 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,691 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,721 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,753 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,788 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,825 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,865 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,908 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:26,953 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:27,002 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:27,054 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:27,109 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:27,169 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:27,230 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:27,298 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:27,369 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:27,443 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:27,521 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:27,603 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:27,688 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:27,690 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:27,693 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:27,725 INFO L134 CoverageAnalysis]: Checked inductivity of 6962 backedges. 0 proven. 6962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:27,744 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:27,744 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 62] total 62 [2018-01-29 23:38:27,744 INFO L409 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-01-29 23:38:27,744 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-01-29 23:38:27,744 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-29 23:38:27,744 INFO L87 Difference]: Start difference. First operand 258 states and 260 transitions. Second operand 62 states. [2018-01-29 23:38:27,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:27,880 INFO L93 Difference]: Finished difference Result 278 states and 282 transitions. [2018-01-29 23:38:27,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-01-29 23:38:27,881 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 252 [2018-01-29 23:38:27,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:27,881 INFO L225 Difference]: With dead ends: 278 [2018-01-29 23:38:27,881 INFO L226 Difference]: Without dead ends: 264 [2018-01-29 23:38:27,881 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 313 GetRequests, 253 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-29 23:38:27,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 264 states. [2018-01-29 23:38:27,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 264 to 262. [2018-01-29 23:38:27,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 262 states. [2018-01-29 23:38:27,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 264 transitions. [2018-01-29 23:38:27,883 INFO L78 Accepts]: Start accepts. Automaton has 262 states and 264 transitions. Word has length 252 [2018-01-29 23:38:27,884 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:27,884 INFO L432 AbstractCegarLoop]: Abstraction has 262 states and 264 transitions. [2018-01-29 23:38:27,884 INFO L433 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-01-29 23:38:27,884 INFO L276 IsEmpty]: Start isEmpty. Operand 262 states and 264 transitions. [2018-01-29 23:38:27,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 257 [2018-01-29 23:38:27,884 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:27,884 INFO L350 BasicCegarLoop]: trace histogram [61, 60, 60, 60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:27,885 INFO L371 AbstractCegarLoop]: === Iteration 62 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:27,885 INFO L82 PathProgramCache]: Analyzing trace with hash -1531874033, now seen corresponding path program 60 times [2018-01-29 23:38:27,885 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:27,885 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:27,885 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:27,885 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:27,885 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:27,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:27,893 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:28,896 INFO L134 CoverageAnalysis]: Checked inductivity of 7200 backedges. 0 proven. 7200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:28,896 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:28,896 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:28,901 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 23:38:28,907 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,907 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,908 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,909 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,909 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,910 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,911 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,912 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,913 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,914 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,914 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,916 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,917 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,918 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,919 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,921 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,922 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,924 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,926 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,928 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,930 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,932 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,934 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,936 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,939 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,941 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,944 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,947 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,951 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,954 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,958 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,961 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,965 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,969 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,974 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,979 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,984 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,990 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:28,996 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,002 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,008 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,015 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,022 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,029 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,038 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,046 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,055 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,064 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,074 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,084 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,096 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,108 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,121 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,134 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,148 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,162 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,178 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,195 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,213 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,232 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,265 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:29,266 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:29,269 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:29,302 INFO L134 CoverageAnalysis]: Checked inductivity of 7200 backedges. 0 proven. 7200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:29,319 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:29,319 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 63] total 63 [2018-01-29 23:38:29,320 INFO L409 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-01-29 23:38:29,320 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-01-29 23:38:29,320 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1953, Invalid=1953, Unknown=0, NotChecked=0, Total=3906 [2018-01-29 23:38:29,320 INFO L87 Difference]: Start difference. First operand 262 states and 264 transitions. Second operand 63 states. [2018-01-29 23:38:29,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:29,456 INFO L93 Difference]: Finished difference Result 282 states and 286 transitions. [2018-01-29 23:38:29,456 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-01-29 23:38:29,456 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 256 [2018-01-29 23:38:29,456 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:29,457 INFO L225 Difference]: With dead ends: 282 [2018-01-29 23:38:29,457 INFO L226 Difference]: Without dead ends: 268 [2018-01-29 23:38:29,457 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 318 GetRequests, 257 SyntacticMatches, 0 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1953, Invalid=1953, Unknown=0, NotChecked=0, Total=3906 [2018-01-29 23:38:29,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 268 states. [2018-01-29 23:38:29,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 268 to 266. [2018-01-29 23:38:29,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 266 states. [2018-01-29 23:38:29,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 266 states to 266 states and 268 transitions. [2018-01-29 23:38:29,459 INFO L78 Accepts]: Start accepts. Automaton has 266 states and 268 transitions. Word has length 256 [2018-01-29 23:38:29,464 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:29,464 INFO L432 AbstractCegarLoop]: Abstraction has 266 states and 268 transitions. [2018-01-29 23:38:29,464 INFO L433 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-01-29 23:38:29,465 INFO L276 IsEmpty]: Start isEmpty. Operand 266 states and 268 transitions. [2018-01-29 23:38:29,465 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 261 [2018-01-29 23:38:29,465 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:29,465 INFO L350 BasicCegarLoop]: trace histogram [62, 61, 61, 61, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:29,465 INFO L371 AbstractCegarLoop]: === Iteration 63 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:29,465 INFO L82 PathProgramCache]: Analyzing trace with hash -1622251274, now seen corresponding path program 61 times [2018-01-29 23:38:29,465 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:29,466 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:29,466 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:29,466 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:29,466 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:29,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:29,474 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:30,635 INFO L134 CoverageAnalysis]: Checked inductivity of 7442 backedges. 0 proven. 7442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:30,636 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:30,636 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:30,640 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:38:30,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:30,661 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:30,695 INFO L134 CoverageAnalysis]: Checked inductivity of 7442 backedges. 0 proven. 7442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:30,711 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:30,711 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 64] total 64 [2018-01-29 23:38:30,712 INFO L409 AbstractCegarLoop]: Interpolant automaton has 64 states [2018-01-29 23:38:30,712 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2018-01-29 23:38:30,712 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-29 23:38:30,712 INFO L87 Difference]: Start difference. First operand 266 states and 268 transitions. Second operand 64 states. [2018-01-29 23:38:30,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:30,854 INFO L93 Difference]: Finished difference Result 286 states and 290 transitions. [2018-01-29 23:38:30,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2018-01-29 23:38:30,855 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 260 [2018-01-29 23:38:30,855 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:30,855 INFO L225 Difference]: With dead ends: 286 [2018-01-29 23:38:30,856 INFO L226 Difference]: Without dead ends: 272 [2018-01-29 23:38:30,856 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 323 GetRequests, 261 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-29 23:38:30,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272 states. [2018-01-29 23:38:30,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272 to 270. [2018-01-29 23:38:30,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2018-01-29 23:38:30,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 272 transitions. [2018-01-29 23:38:30,858 INFO L78 Accepts]: Start accepts. Automaton has 270 states and 272 transitions. Word has length 260 [2018-01-29 23:38:30,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:30,858 INFO L432 AbstractCegarLoop]: Abstraction has 270 states and 272 transitions. [2018-01-29 23:38:30,858 INFO L433 AbstractCegarLoop]: Interpolant automaton has 64 states. [2018-01-29 23:38:30,858 INFO L276 IsEmpty]: Start isEmpty. Operand 270 states and 272 transitions. [2018-01-29 23:38:30,859 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 265 [2018-01-29 23:38:30,859 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:30,860 INFO L350 BasicCegarLoop]: trace histogram [63, 62, 62, 62, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:30,860 INFO L371 AbstractCegarLoop]: === Iteration 64 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:30,860 INFO L82 PathProgramCache]: Analyzing trace with hash 1492193629, now seen corresponding path program 62 times [2018-01-29 23:38:30,860 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:30,861 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:30,861 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:30,861 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:38:30,861 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:30,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:30,870 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:31,981 INFO L134 CoverageAnalysis]: Checked inductivity of 7688 backedges. 0 proven. 7688 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:31,981 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:31,981 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:31,986 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 23:38:31,992 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:32,004 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:32,007 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:32,009 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:32,043 INFO L134 CoverageAnalysis]: Checked inductivity of 7688 backedges. 0 proven. 7688 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:32,060 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:32,060 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 65] total 65 [2018-01-29 23:38:32,060 INFO L409 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-01-29 23:38:32,060 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-01-29 23:38:32,060 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2080, Invalid=2080, Unknown=0, NotChecked=0, Total=4160 [2018-01-29 23:38:32,061 INFO L87 Difference]: Start difference. First operand 270 states and 272 transitions. Second operand 65 states. [2018-01-29 23:38:32,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:32,211 INFO L93 Difference]: Finished difference Result 290 states and 294 transitions. [2018-01-29 23:38:32,212 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-01-29 23:38:32,212 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 264 [2018-01-29 23:38:32,212 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:32,213 INFO L225 Difference]: With dead ends: 290 [2018-01-29 23:38:32,213 INFO L226 Difference]: Without dead ends: 276 [2018-01-29 23:38:32,213 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 328 GetRequests, 265 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=2080, Invalid=2080, Unknown=0, NotChecked=0, Total=4160 [2018-01-29 23:38:32,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states. [2018-01-29 23:38:32,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 274. [2018-01-29 23:38:32,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 274 states. [2018-01-29 23:38:32,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 274 states to 274 states and 276 transitions. [2018-01-29 23:38:32,216 INFO L78 Accepts]: Start accepts. Automaton has 274 states and 276 transitions. Word has length 264 [2018-01-29 23:38:32,216 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:32,216 INFO L432 AbstractCegarLoop]: Abstraction has 274 states and 276 transitions. [2018-01-29 23:38:32,216 INFO L433 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-01-29 23:38:32,217 INFO L276 IsEmpty]: Start isEmpty. Operand 274 states and 276 transitions. [2018-01-29 23:38:32,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 269 [2018-01-29 23:38:32,218 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:32,218 INFO L350 BasicCegarLoop]: trace histogram [64, 63, 63, 63, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:32,218 INFO L371 AbstractCegarLoop]: === Iteration 65 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:32,218 INFO L82 PathProgramCache]: Analyzing trace with hash -1230295484, now seen corresponding path program 63 times [2018-01-29 23:38:32,218 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:32,218 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:32,219 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:32,219 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:32,219 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:32,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:32,227 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:33,465 INFO L134 CoverageAnalysis]: Checked inductivity of 7938 backedges. 0 proven. 7938 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:33,465 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:33,465 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:33,470 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-29 23:38:33,475 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,476 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,477 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,477 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,478 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,479 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,480 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,480 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,482 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,483 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,484 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,485 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,487 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,488 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,490 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,492 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,494 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,496 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,498 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,501 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,504 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,507 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,510 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,514 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,518 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,522 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,527 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,532 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,537 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,543 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,549 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,557 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,564 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,573 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,582 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,592 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,602 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,612 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,624 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,638 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,651 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,666 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,681 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,698 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,716 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,735 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,756 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,778 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,801 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,826 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,853 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,881 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,908 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,938 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:33,971 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:34,005 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:34,040 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:34,078 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:34,118 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:34,160 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:34,204 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:34,249 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:34,298 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:34,350 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-29 23:38:34,352 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:34,355 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:34,391 INFO L134 CoverageAnalysis]: Checked inductivity of 7938 backedges. 0 proven. 7938 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:34,409 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:34,409 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 66] total 66 [2018-01-29 23:38:34,410 INFO L409 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-01-29 23:38:34,410 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-01-29 23:38:34,410 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-01-29 23:38:34,410 INFO L87 Difference]: Start difference. First operand 274 states and 276 transitions. Second operand 66 states. [2018-01-29 23:38:34,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:34,580 INFO L93 Difference]: Finished difference Result 294 states and 298 transitions. [2018-01-29 23:38:34,580 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-01-29 23:38:34,580 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 268 [2018-01-29 23:38:34,580 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:34,581 INFO L225 Difference]: With dead ends: 294 [2018-01-29 23:38:34,581 INFO L226 Difference]: Without dead ends: 280 [2018-01-29 23:38:34,581 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 333 GetRequests, 269 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-01-29 23:38:34,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 280 states. [2018-01-29 23:38:34,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 280 to 278. [2018-01-29 23:38:34,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 278 states. [2018-01-29 23:38:34,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 278 states to 278 states and 280 transitions. [2018-01-29 23:38:34,583 INFO L78 Accepts]: Start accepts. Automaton has 278 states and 280 transitions. Word has length 268 [2018-01-29 23:38:34,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:34,583 INFO L432 AbstractCegarLoop]: Abstraction has 278 states and 280 transitions. [2018-01-29 23:38:34,583 INFO L433 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-01-29 23:38:34,583 INFO L276 IsEmpty]: Start isEmpty. Operand 278 states and 280 transitions. [2018-01-29 23:38:34,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 273 [2018-01-29 23:38:34,584 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:34,584 INFO L350 BasicCegarLoop]: trace histogram [65, 64, 64, 64, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:34,584 INFO L371 AbstractCegarLoop]: === Iteration 66 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:34,584 INFO L82 PathProgramCache]: Analyzing trace with hash 1051623339, now seen corresponding path program 64 times [2018-01-29 23:38:34,584 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:34,584 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:34,585 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:34,585 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:34,585 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:34,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:34,593 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:35,851 INFO L134 CoverageAnalysis]: Checked inductivity of 8192 backedges. 0 proven. 8192 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:35,851 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:35,851 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:35,856 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-29 23:38:35,881 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:35,883 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:35,922 INFO L134 CoverageAnalysis]: Checked inductivity of 8192 backedges. 0 proven. 8192 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:35,940 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:35,940 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [67, 67] total 67 [2018-01-29 23:38:35,940 INFO L409 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-01-29 23:38:35,941 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-01-29 23:38:35,941 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2211, Invalid=2211, Unknown=0, NotChecked=0, Total=4422 [2018-01-29 23:38:35,941 INFO L87 Difference]: Start difference. First operand 278 states and 280 transitions. Second operand 67 states. [2018-01-29 23:38:36,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:36,108 INFO L93 Difference]: Finished difference Result 298 states and 302 transitions. [2018-01-29 23:38:36,108 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-01-29 23:38:36,108 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 272 [2018-01-29 23:38:36,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:36,109 INFO L225 Difference]: With dead ends: 298 [2018-01-29 23:38:36,109 INFO L226 Difference]: Without dead ends: 284 [2018-01-29 23:38:36,109 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 273 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=2211, Invalid=2211, Unknown=0, NotChecked=0, Total=4422 [2018-01-29 23:38:36,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states. [2018-01-29 23:38:36,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 282. [2018-01-29 23:38:36,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 282 states. [2018-01-29 23:38:36,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 282 states to 282 states and 284 transitions. [2018-01-29 23:38:36,111 INFO L78 Accepts]: Start accepts. Automaton has 282 states and 284 transitions. Word has length 272 [2018-01-29 23:38:36,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:36,112 INFO L432 AbstractCegarLoop]: Abstraction has 282 states and 284 transitions. [2018-01-29 23:38:36,112 INFO L433 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-01-29 23:38:36,112 INFO L276 IsEmpty]: Start isEmpty. Operand 282 states and 284 transitions. [2018-01-29 23:38:36,112 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 277 [2018-01-29 23:38:36,112 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:36,112 INFO L350 BasicCegarLoop]: trace histogram [66, 65, 65, 65, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:36,112 INFO L371 AbstractCegarLoop]: === Iteration 67 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:36,113 INFO L82 PathProgramCache]: Analyzing trace with hash -2008234606, now seen corresponding path program 65 times [2018-01-29 23:38:36,113 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:36,113 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:36,113 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:36,113 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:36,113 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:36,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:36,122 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:37,324 INFO L134 CoverageAnalysis]: Checked inductivity of 8450 backedges. 0 proven. 8450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:37,324 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:37,325 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:37,329 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-29 23:38:37,333 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,334 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,335 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,335 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,336 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,337 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,338 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,339 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,340 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,341 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,343 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,344 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,346 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,348 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,350 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,353 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,355 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,359 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,362 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,366 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,370 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,374 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,379 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,385 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,391 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,398 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,406 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,415 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,424 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,435 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,446 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,458 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,472 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,487 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,503 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,521 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,541 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,563 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,586 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,612 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,639 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,667 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,697 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,730 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,765 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,802 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,842 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,884 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,929 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:37,978 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:38,030 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:38,084 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:38,144 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:38,206 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:38,272 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:38,344 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:38,418 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:38,497 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:38,578 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:38,662 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:38,749 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:38,840 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:38,936 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:39,038 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:39,143 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:39,254 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:39,256 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:39,259 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:39,297 INFO L134 CoverageAnalysis]: Checked inductivity of 8450 backedges. 0 proven. 8450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:39,316 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:39,316 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 68] total 68 [2018-01-29 23:38:39,316 INFO L409 AbstractCegarLoop]: Interpolant automaton has 68 states [2018-01-29 23:38:39,317 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2018-01-29 23:38:39,317 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-01-29 23:38:39,317 INFO L87 Difference]: Start difference. First operand 282 states and 284 transitions. Second operand 68 states. [2018-01-29 23:38:39,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:39,502 INFO L93 Difference]: Finished difference Result 302 states and 306 transitions. [2018-01-29 23:38:39,502 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-01-29 23:38:39,502 INFO L78 Accepts]: Start accepts. Automaton has 68 states. Word has length 276 [2018-01-29 23:38:39,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:39,503 INFO L225 Difference]: With dead ends: 302 [2018-01-29 23:38:39,503 INFO L226 Difference]: Without dead ends: 288 [2018-01-29 23:38:39,503 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 277 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-01-29 23:38:39,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states. [2018-01-29 23:38:39,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 286. [2018-01-29 23:38:39,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 286 states. [2018-01-29 23:38:39,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 286 states to 286 states and 288 transitions. [2018-01-29 23:38:39,505 INFO L78 Accepts]: Start accepts. Automaton has 286 states and 288 transitions. Word has length 276 [2018-01-29 23:38:39,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:39,506 INFO L432 AbstractCegarLoop]: Abstraction has 286 states and 288 transitions. [2018-01-29 23:38:39,506 INFO L433 AbstractCegarLoop]: Interpolant automaton has 68 states. [2018-01-29 23:38:39,506 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 288 transitions. [2018-01-29 23:38:39,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 281 [2018-01-29 23:38:39,506 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:39,507 INFO L350 BasicCegarLoop]: trace histogram [67, 66, 66, 66, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:39,507 INFO L371 AbstractCegarLoop]: === Iteration 68 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:39,507 INFO L82 PathProgramCache]: Analyzing trace with hash -1409826823, now seen corresponding path program 66 times [2018-01-29 23:38:39,507 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:39,507 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:39,507 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:39,507 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:39,507 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:39,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:39,517 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:40,964 INFO L134 CoverageAnalysis]: Checked inductivity of 8712 backedges. 0 proven. 8712 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:40,964 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:40,964 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:40,969 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-29 23:38:40,975 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,976 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,976 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,977 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,977 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,978 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,979 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,980 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,981 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,981 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,983 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,984 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,985 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,986 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,987 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,989 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,990 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,992 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,993 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,995 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:40,997 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,000 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,002 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,004 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,006 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,009 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,012 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,015 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,018 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,022 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,026 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,029 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,033 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,037 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,041 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,046 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,051 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,057 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,063 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,069 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,076 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,084 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,091 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,099 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,107 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,117 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,126 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,135 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,146 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,156 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,169 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,180 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,193 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,206 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,221 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,236 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,251 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,268 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,285 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,303 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,323 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,342 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,364 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,385 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,426 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,466 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,508 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-29 23:38:41,509 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:41,512 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:41,555 INFO L134 CoverageAnalysis]: Checked inductivity of 8712 backedges. 0 proven. 8712 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:41,574 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:41,574 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [69, 69] total 69 [2018-01-29 23:38:41,575 INFO L409 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-01-29 23:38:41,575 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-01-29 23:38:41,575 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2346, Invalid=2346, Unknown=0, NotChecked=0, Total=4692 [2018-01-29 23:38:41,575 INFO L87 Difference]: Start difference. First operand 286 states and 288 transitions. Second operand 69 states. [2018-01-29 23:38:41,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:41,714 INFO L93 Difference]: Finished difference Result 306 states and 310 transitions. [2018-01-29 23:38:41,714 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-01-29 23:38:41,714 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 280 [2018-01-29 23:38:41,714 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:41,715 INFO L225 Difference]: With dead ends: 306 [2018-01-29 23:38:41,715 INFO L226 Difference]: Without dead ends: 292 [2018-01-29 23:38:41,715 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 348 GetRequests, 281 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=2346, Invalid=2346, Unknown=0, NotChecked=0, Total=4692 [2018-01-29 23:38:41,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 292 states. [2018-01-29 23:38:41,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 292 to 290. [2018-01-29 23:38:41,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 290 states. [2018-01-29 23:38:41,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 290 states to 290 states and 292 transitions. [2018-01-29 23:38:41,717 INFO L78 Accepts]: Start accepts. Automaton has 290 states and 292 transitions. Word has length 280 [2018-01-29 23:38:41,717 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:41,717 INFO L432 AbstractCegarLoop]: Abstraction has 290 states and 292 transitions. [2018-01-29 23:38:41,717 INFO L433 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-01-29 23:38:41,717 INFO L276 IsEmpty]: Start isEmpty. Operand 290 states and 292 transitions. [2018-01-29 23:38:41,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 285 [2018-01-29 23:38:41,718 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:41,718 INFO L350 BasicCegarLoop]: trace histogram [68, 67, 67, 67, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:41,718 INFO L371 AbstractCegarLoop]: === Iteration 69 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:41,718 INFO L82 PathProgramCache]: Analyzing trace with hash -1287573792, now seen corresponding path program 67 times [2018-01-29 23:38:41,718 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:41,718 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:41,719 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:41,719 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:41,719 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:41,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:41,727 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:43,189 INFO L134 CoverageAnalysis]: Checked inductivity of 8978 backedges. 0 proven. 8978 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:43,190 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:43,190 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:43,194 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:38:43,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:43,216 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:43,257 INFO L134 CoverageAnalysis]: Checked inductivity of 8978 backedges. 0 proven. 8978 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:43,273 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:43,274 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 70] total 70 [2018-01-29 23:38:43,274 INFO L409 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-01-29 23:38:43,274 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-01-29 23:38:43,274 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2018-01-29 23:38:43,274 INFO L87 Difference]: Start difference. First operand 290 states and 292 transitions. Second operand 70 states. [2018-01-29 23:38:43,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:43,410 INFO L93 Difference]: Finished difference Result 310 states and 314 transitions. [2018-01-29 23:38:43,410 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2018-01-29 23:38:43,410 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 284 [2018-01-29 23:38:43,411 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:43,411 INFO L225 Difference]: With dead ends: 310 [2018-01-29 23:38:43,411 INFO L226 Difference]: Without dead ends: 296 [2018-01-29 23:38:43,411 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 353 GetRequests, 285 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2018-01-29 23:38:43,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 296 states. [2018-01-29 23:38:43,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 296 to 294. [2018-01-29 23:38:43,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 294 states. [2018-01-29 23:38:43,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 294 states to 294 states and 296 transitions. [2018-01-29 23:38:43,413 INFO L78 Accepts]: Start accepts. Automaton has 294 states and 296 transitions. Word has length 284 [2018-01-29 23:38:43,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:43,414 INFO L432 AbstractCegarLoop]: Abstraction has 294 states and 296 transitions. [2018-01-29 23:38:43,414 INFO L433 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-01-29 23:38:43,414 INFO L276 IsEmpty]: Start isEmpty. Operand 294 states and 296 transitions. [2018-01-29 23:38:43,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 289 [2018-01-29 23:38:43,414 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:43,414 INFO L350 BasicCegarLoop]: trace histogram [69, 68, 68, 68, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:43,415 INFO L371 AbstractCegarLoop]: === Iteration 70 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:43,415 INFO L82 PathProgramCache]: Analyzing trace with hash 148558407, now seen corresponding path program 68 times [2018-01-29 23:38:43,415 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:43,415 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:43,415 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:43,415 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-29 23:38:43,415 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:43,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:43,424 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-29 23:38:44,713 INFO L134 CoverageAnalysis]: Checked inductivity of 9248 backedges. 0 proven. 9248 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:44,713 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-29 23:38:44,713 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-29 23:38:44,718 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-29 23:38:44,723 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:44,737 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-29 23:38:44,740 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-29 23:38:44,742 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-29 23:38:44,782 INFO L134 CoverageAnalysis]: Checked inductivity of 9248 backedges. 0 proven. 9248 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-29 23:38:44,799 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-29 23:38:44,799 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [71, 71] total 71 [2018-01-29 23:38:44,799 INFO L409 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-01-29 23:38:44,800 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-01-29 23:38:44,800 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2485, Invalid=2485, Unknown=0, NotChecked=0, Total=4970 [2018-01-29 23:38:44,800 INFO L87 Difference]: Start difference. First operand 294 states and 296 transitions. Second operand 71 states. [2018-01-29 23:38:44,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-29 23:38:44,941 INFO L93 Difference]: Finished difference Result 314 states and 318 transitions. [2018-01-29 23:38:44,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-01-29 23:38:44,941 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 288 [2018-01-29 23:38:44,941 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-29 23:38:44,942 INFO L225 Difference]: With dead ends: 314 [2018-01-29 23:38:44,942 INFO L226 Difference]: Without dead ends: 300 [2018-01-29 23:38:44,942 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 358 GetRequests, 289 SyntacticMatches, 0 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2485, Invalid=2485, Unknown=0, NotChecked=0, Total=4970 [2018-01-29 23:38:44,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 300 states. [2018-01-29 23:38:44,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 300 to 298. [2018-01-29 23:38:44,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 298 states. [2018-01-29 23:38:44,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 300 transitions. [2018-01-29 23:38:44,944 INFO L78 Accepts]: Start accepts. Automaton has 298 states and 300 transitions. Word has length 288 [2018-01-29 23:38:44,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-29 23:38:44,944 INFO L432 AbstractCegarLoop]: Abstraction has 298 states and 300 transitions. [2018-01-29 23:38:44,944 INFO L433 AbstractCegarLoop]: Interpolant automaton has 71 states. [2018-01-29 23:38:44,944 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 300 transitions. [2018-01-29 23:38:44,945 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 293 [2018-01-29 23:38:44,945 INFO L342 BasicCegarLoop]: Found error trace [2018-01-29 23:38:44,945 INFO L350 BasicCegarLoop]: trace histogram [70, 69, 69, 69, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-29 23:38:44,945 INFO L371 AbstractCegarLoop]: === Iteration 71 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-29 23:38:44,945 INFO L82 PathProgramCache]: Analyzing trace with hash -392795602, now seen corresponding path program 69 times [2018-01-29 23:38:44,945 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-29 23:38:44,945 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-29 23:38:44,946 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:44,946 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-29 23:38:44,946 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-29 23:38:44,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-29 23:38:44,955 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. Received shutdown request... [2018-01-29 23:38:45,590 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-29 23:38:45,593 WARN L185 ceAbstractionStarter]: Timeout [2018-01-29 23:38:45,593 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 29.01 11:38:45 BoogieIcfgContainer [2018-01-29 23:38:45,593 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-29 23:38:45,593 INFO L168 Benchmark]: Toolchain (without parser) took 67878.34 ms. Allocated memory was 149.4 MB in the beginning and 902.3 MB in the end (delta: 752.9 MB). Free memory was 114.5 MB in the beginning and 805.0 MB in the end (delta: -690.5 MB). Peak memory consumption was 62.4 MB. Max. memory is 5.3 GB. [2018-01-29 23:38:45,594 INFO L168 Benchmark]: CDTParser took 0.10 ms. Allocated memory is still 149.4 MB. Free memory is still 119.2 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-29 23:38:45,594 INFO L168 Benchmark]: CACSL2BoogieTranslator took 112.40 ms. Allocated memory is still 149.4 MB. Free memory was 114.3 MB in the beginning and 106.3 MB in the end (delta: 8.0 MB). Peak memory consumption was 8.0 MB. Max. memory is 5.3 GB. [2018-01-29 23:38:45,594 INFO L168 Benchmark]: Boogie Preprocessor took 17.09 ms. Allocated memory is still 149.4 MB. Free memory was 106.3 MB in the beginning and 104.9 MB in the end (delta: 1.4 MB). Peak memory consumption was 1.4 MB. Max. memory is 5.3 GB. [2018-01-29 23:38:45,594 INFO L168 Benchmark]: RCFGBuilder took 330.99 ms. Allocated memory is still 149.4 MB. Free memory was 104.7 MB in the beginning and 94.0 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 5.3 GB. [2018-01-29 23:38:45,595 INFO L168 Benchmark]: TraceAbstraction took 67415.57 ms. Allocated memory was 149.4 MB in the beginning and 902.3 MB in the end (delta: 752.9 MB). Free memory was 93.8 MB in the beginning and 805.0 MB in the end (delta: -711.2 MB). Peak memory consumption was 41.6 MB. Max. memory is 5.3 GB. [2018-01-29 23:38:45,595 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10 ms. Allocated memory is still 149.4 MB. Free memory is still 119.2 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 112.40 ms. Allocated memory is still 149.4 MB. Free memory was 114.3 MB in the beginning and 106.3 MB in the end (delta: 8.0 MB). Peak memory consumption was 8.0 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 17.09 ms. Allocated memory is still 149.4 MB. Free memory was 106.3 MB in the beginning and 104.9 MB in the end (delta: 1.4 MB). Peak memory consumption was 1.4 MB. Max. memory is 5.3 GB. * RCFGBuilder took 330.99 ms. Allocated memory is still 149.4 MB. Free memory was 104.7 MB in the beginning and 94.0 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 5.3 GB. * TraceAbstraction took 67415.57 ms. Allocated memory was 149.4 MB in the beginning and 902.3 MB in the end (delta: 752.9 MB). Free memory was 93.8 MB in the beginning and 805.0 MB in the end (delta: -711.2 MB). Peak memory consumption was 41.6 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 2]: Timeout (TraceAbstraction) Unable to prove that call of __VERIFIER_error() unreachable (line 2). Cancelled while BasicCegarLoop was analyzing trace of length 293 with TraceHistMax 70, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 43 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 29 locations, 1 error locations. TIMEOUT Result, 67.3s OverallTime, 71 OverallIterations, 70 TraceHistogramMax, 11.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1618 SDtfs, 4830 SDslu, 37115 SDs, 0 SdLazy, 9187 SolverSat, 104 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 9.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 12959 GetRequests, 10544 SyntacticMatches, 0 SemanticMatches, 2415 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 33.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=298occurred in iteration=70, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 70 MinimizatonAttempts, 138 StatesRemovedByMinimization, 69 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 10.9s SatisfiabilityAnalysisTime, 41.2s InterpolantComputationTime, 20975 NumberOfCodeBlocks, 20975 NumberOfCodeBlocksAsserted, 1305 NumberOfCheckSat, 20837 ConstructedInterpolants, 0 QuantifiedInterpolants, 11525257 SizeOfPredicates, 68 NumberOfNonLiveVariables, 13702 ConjunctsInSsa, 2482 ConjunctsInUnsatCore, 138 InterpolantComputations, 2 PerfectInterpolantSequences, 0/428536 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_init1_true-unreach-call_ground.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-29_23-38-45-602.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_init1_true-unreach-call_ground.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-29_23-38-45-602.csv Completed graceful shutdown