java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/array-examples/standard_init1_true-unreach-call_ground.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-1cceb4a-m [2018-01-30 03:30:44,265 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-30 03:30:44,266 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-30 03:30:44,275 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-30 03:30:44,275 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-30 03:30:44,276 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-30 03:30:44,276 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-30 03:30:44,277 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-30 03:30:44,279 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-30 03:30:44,279 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-30 03:30:44,279 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-30 03:30:44,280 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-30 03:30:44,280 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-30 03:30:44,281 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-30 03:30:44,281 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-30 03:30:44,282 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-30 03:30:44,283 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-30 03:30:44,284 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-30 03:30:44,285 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-30 03:30:44,285 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-30 03:30:44,287 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-30 03:30:44,287 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-30 03:30:44,287 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-30 03:30:44,287 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-30 03:30:44,288 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-30 03:30:44,288 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-30 03:30:44,288 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-30 03:30:44,289 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-30 03:30:44,289 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-30 03:30:44,289 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-30 03:30:44,289 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-30 03:30:44,289 INFO L98 SettingsManager]: Beginning loading settings from /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf [2018-01-30 03:30:44,295 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-30 03:30:44,295 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-30 03:30:44,295 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-30 03:30:44,295 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-30 03:30:44,295 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-30 03:30:44,295 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-30 03:30:44,296 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-30 03:30:44,296 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-30 03:30:44,296 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-30 03:30:44,296 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-30 03:30:44,296 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-30 03:30:44,296 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-30 03:30:44,296 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-01-30 03:30:44,296 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-30 03:30:44,297 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-01-30 03:30:44,297 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-30 03:30:44,297 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-01-30 03:30:44,297 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-01-30 03:30:44,297 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-30 03:30:44,297 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-01-30 03:30:44,297 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-30 03:30:44,297 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-30 03:30:44,297 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-30 03:30:44,297 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-30 03:30:44,297 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-30 03:30:44,298 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-30 03:30:44,298 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-30 03:30:44,298 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-30 03:30:44,298 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-30 03:30:44,298 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-30 03:30:44,298 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-30 03:30:44,298 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-30 03:30:44,299 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-30 03:30:44,299 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-30 03:30:44,317 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-30 03:30:44,324 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-30 03:30:44,326 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-30 03:30:44,327 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-30 03:30:44,327 INFO L276 PluginConnector]: CDTParser initialized [2018-01-30 03:30:44,327 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/standard_init1_true-unreach-call_ground.i [2018-01-30 03:30:44,391 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-30 03:30:44,392 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-01-30 03:30:44,393 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-30 03:30:44,393 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-30 03:30:44,397 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-30 03:30:44,397 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 30.01 03:30:44" (1/1) ... [2018-01-30 03:30:44,399 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@74663061 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 03:30:44, skipping insertion in model container [2018-01-30 03:30:44,399 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 30.01 03:30:44" (1/1) ... [2018-01-30 03:30:44,408 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-30 03:30:44,416 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-30 03:30:44,486 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-30 03:30:44,493 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-30 03:30:44,496 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 03:30:44 WrapperNode [2018-01-30 03:30:44,496 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-30 03:30:44,496 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-30 03:30:44,496 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-30 03:30:44,497 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-30 03:30:44,505 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 03:30:44" (1/1) ... [2018-01-30 03:30:44,505 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 03:30:44" (1/1) ... [2018-01-30 03:30:44,509 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 03:30:44" (1/1) ... [2018-01-30 03:30:44,509 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 03:30:44" (1/1) ... [2018-01-30 03:30:44,510 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 03:30:44" (1/1) ... [2018-01-30 03:30:44,512 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 03:30:44" (1/1) ... [2018-01-30 03:30:44,513 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 03:30:44" (1/1) ... [2018-01-30 03:30:44,514 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-30 03:30:44,514 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-30 03:30:44,514 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-30 03:30:44,514 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-30 03:30:44,515 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 03:30:44" (1/1) ... No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-30 03:30:44,562 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-30 03:30:44,562 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-30 03:30:44,562 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-30 03:30:44,562 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-30 03:30:44,562 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-30 03:30:44,562 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-30 03:30:44,562 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-30 03:30:44,563 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-30 03:30:44,563 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-30 03:30:44,780 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-30 03:30:44,780 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 30.01 03:30:44 BoogieIcfgContainer [2018-01-30 03:30:44,780 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-30 03:30:44,781 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2018-01-30 03:30:44,781 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2018-01-30 03:30:44,781 INFO L276 PluginConnector]: IcfgTransformer initialized [2018-01-30 03:30:44,783 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 30.01 03:30:44" (1/1) ... [2018-01-30 03:30:44,786 WARN L213 ansformationObserver]: HeapSeparator: input icfg has no '#valid' array -- returning unchanged Icfg! [2018-01-30 03:30:44,792 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 30.01 03:30:44 BasicIcfg [2018-01-30 03:30:44,792 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2018-01-30 03:30:44,792 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-30 03:30:44,792 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-30 03:30:44,794 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-30 03:30:44,794 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 30.01 03:30:44" (1/4) ... [2018-01-30 03:30:44,795 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5ffa554e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 30.01 03:30:44, skipping insertion in model container [2018-01-30 03:30:44,795 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 03:30:44" (2/4) ... [2018-01-30 03:30:44,795 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5ffa554e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 30.01 03:30:44, skipping insertion in model container [2018-01-30 03:30:44,795 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 30.01 03:30:44" (3/4) ... [2018-01-30 03:30:44,795 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5ffa554e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 30.01 03:30:44, skipping insertion in model container [2018-01-30 03:30:44,796 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 30.01 03:30:44" (4/4) ... [2018-01-30 03:30:44,796 INFO L107 eAbstractionObserver]: Analyzing ICFG standard_init1_true-unreach-call_ground.ileft_unchanged_by_heapseparator [2018-01-30 03:30:44,801 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-30 03:30:44,806 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-01-30 03:30:44,829 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-30 03:30:44,829 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-30 03:30:44,829 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-30 03:30:44,829 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-30 03:30:44,829 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-30 03:30:44,830 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-30 03:30:44,830 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-30 03:30:44,830 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-30 03:30:44,830 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-30 03:30:44,840 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states. [2018-01-30 03:30:44,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-01-30 03:30:44,846 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:44,847 INFO L350 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:44,847 INFO L371 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:44,851 INFO L82 PathProgramCache]: Analyzing trace with hash 1772997611, now seen corresponding path program 1 times [2018-01-30 03:30:44,852 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:44,852 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:44,881 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:44,882 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:30:44,882 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:44,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:44,906 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:44,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:44,926 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-30 03:30:44,926 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-30 03:30:44,927 INFO L409 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-01-30 03:30:44,937 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-01-30 03:30:44,938 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-30 03:30:44,939 INFO L87 Difference]: Start difference. First operand 29 states. Second operand 2 states. [2018-01-30 03:30:44,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:44,954 INFO L93 Difference]: Finished difference Result 48 states and 54 transitions. [2018-01-30 03:30:44,954 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-01-30 03:30:44,954 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 15 [2018-01-30 03:30:44,956 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:44,961 INFO L225 Difference]: With dead ends: 48 [2018-01-30 03:30:44,962 INFO L226 Difference]: Without dead ends: 24 [2018-01-30 03:30:44,964 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-30 03:30:44,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2018-01-30 03:30:44,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2018-01-30 03:30:44,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-01-30 03:30:44,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 26 transitions. [2018-01-30 03:30:44,987 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 26 transitions. Word has length 15 [2018-01-30 03:30:44,988 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:44,988 INFO L432 AbstractCegarLoop]: Abstraction has 24 states and 26 transitions. [2018-01-30 03:30:44,988 INFO L433 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-01-30 03:30:44,988 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 26 transitions. [2018-01-30 03:30:44,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-01-30 03:30:44,988 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:44,988 INFO L350 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:44,988 INFO L371 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:44,989 INFO L82 PathProgramCache]: Analyzing trace with hash 1886286932, now seen corresponding path program 1 times [2018-01-30 03:30:44,989 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:44,989 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:44,990 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:44,990 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:30:44,990 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:44,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:44,996 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:45,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:45,050 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-30 03:30:45,050 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-30 03:30:45,051 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-30 03:30:45,051 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-30 03:30:45,052 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-30 03:30:45,052 INFO L87 Difference]: Start difference. First operand 24 states and 26 transitions. Second operand 3 states. [2018-01-30 03:30:45,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:45,176 INFO L93 Difference]: Finished difference Result 42 states and 46 transitions. [2018-01-30 03:30:45,176 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-30 03:30:45,176 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 16 [2018-01-30 03:30:45,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:45,177 INFO L225 Difference]: With dead ends: 42 [2018-01-30 03:30:45,177 INFO L226 Difference]: Without dead ends: 28 [2018-01-30 03:30:45,178 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-30 03:30:45,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-01-30 03:30:45,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 26. [2018-01-30 03:30:45,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-01-30 03:30:45,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 28 transitions. [2018-01-30 03:30:45,181 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 28 transitions. Word has length 16 [2018-01-30 03:30:45,181 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:45,181 INFO L432 AbstractCegarLoop]: Abstraction has 26 states and 28 transitions. [2018-01-30 03:30:45,181 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-30 03:30:45,181 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 28 transitions. [2018-01-30 03:30:45,182 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-01-30 03:30:45,182 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:45,182 INFO L350 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:45,182 INFO L371 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:45,182 INFO L82 PathProgramCache]: Analyzing trace with hash -644035591, now seen corresponding path program 1 times [2018-01-30 03:30:45,182 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:45,182 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:45,183 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:45,183 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:30:45,183 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:45,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:45,192 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:45,249 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:45,250 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:45,250 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:45,257 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:30:45,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:45,272 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:45,283 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:45,300 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:45,300 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2018-01-30 03:30:45,301 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-30 03:30:45,301 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-30 03:30:45,301 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-30 03:30:45,301 INFO L87 Difference]: Start difference. First operand 26 states and 28 transitions. Second operand 4 states. [2018-01-30 03:30:45,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:45,362 INFO L93 Difference]: Finished difference Result 46 states and 50 transitions. [2018-01-30 03:30:45,362 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-30 03:30:45,362 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 20 [2018-01-30 03:30:45,362 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:45,362 INFO L225 Difference]: With dead ends: 46 [2018-01-30 03:30:45,362 INFO L226 Difference]: Without dead ends: 32 [2018-01-30 03:30:45,363 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 21 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-30 03:30:45,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2018-01-30 03:30:45,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 30. [2018-01-30 03:30:45,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-01-30 03:30:45,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 32 transitions. [2018-01-30 03:30:45,365 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 32 transitions. Word has length 20 [2018-01-30 03:30:45,366 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:45,366 INFO L432 AbstractCegarLoop]: Abstraction has 30 states and 32 transitions. [2018-01-30 03:30:45,366 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-30 03:30:45,366 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 32 transitions. [2018-01-30 03:30:45,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-01-30 03:30:45,366 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:45,366 INFO L350 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:45,366 INFO L371 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:45,366 INFO L82 PathProgramCache]: Analyzing trace with hash -824391394, now seen corresponding path program 2 times [2018-01-30 03:30:45,366 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:45,367 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:45,367 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:45,367 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:30:45,367 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:45,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:45,373 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:45,421 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:45,421 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:45,421 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:45,442 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 03:30:45,451 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:45,459 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:45,463 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:45,464 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:45,468 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:45,484 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:45,484 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-01-30 03:30:45,485 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-30 03:30:45,485 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-30 03:30:45,485 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-01-30 03:30:45,485 INFO L87 Difference]: Start difference. First operand 30 states and 32 transitions. Second operand 5 states. [2018-01-30 03:30:45,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:45,593 INFO L93 Difference]: Finished difference Result 50 states and 54 transitions. [2018-01-30 03:30:45,593 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-30 03:30:45,593 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 24 [2018-01-30 03:30:45,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:45,594 INFO L225 Difference]: With dead ends: 50 [2018-01-30 03:30:45,594 INFO L226 Difference]: Without dead ends: 36 [2018-01-30 03:30:45,594 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 25 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-01-30 03:30:45,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2018-01-30 03:30:45,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 34. [2018-01-30 03:30:45,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2018-01-30 03:30:45,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 36 transitions. [2018-01-30 03:30:45,598 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 36 transitions. Word has length 24 [2018-01-30 03:30:45,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:45,598 INFO L432 AbstractCegarLoop]: Abstraction has 34 states and 36 transitions. [2018-01-30 03:30:45,598 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-30 03:30:45,598 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 36 transitions. [2018-01-30 03:30:45,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-01-30 03:30:45,598 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:45,598 INFO L350 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:45,598 INFO L371 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:45,599 INFO L82 PathProgramCache]: Analyzing trace with hash -69227581, now seen corresponding path program 3 times [2018-01-30 03:30:45,599 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:45,599 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:45,599 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:45,599 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:45,599 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:45,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:45,605 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:45,748 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:45,749 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:45,749 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:45,760 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 03:30:45,764 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:45,766 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:45,767 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:45,772 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:45,778 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:45,779 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:45,783 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:45,799 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:45,799 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-01-30 03:30:45,800 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-30 03:30:45,800 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-30 03:30:45,800 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-30 03:30:45,800 INFO L87 Difference]: Start difference. First operand 34 states and 36 transitions. Second operand 6 states. [2018-01-30 03:30:45,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:45,848 INFO L93 Difference]: Finished difference Result 54 states and 58 transitions. [2018-01-30 03:30:45,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-30 03:30:45,848 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2018-01-30 03:30:45,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:45,849 INFO L225 Difference]: With dead ends: 54 [2018-01-30 03:30:45,849 INFO L226 Difference]: Without dead ends: 40 [2018-01-30 03:30:45,849 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-30 03:30:45,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-01-30 03:30:45,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 38. [2018-01-30 03:30:45,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-01-30 03:30:45,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 40 transitions. [2018-01-30 03:30:45,852 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 40 transitions. Word has length 28 [2018-01-30 03:30:45,852 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:45,852 INFO L432 AbstractCegarLoop]: Abstraction has 38 states and 40 transitions. [2018-01-30 03:30:45,852 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-30 03:30:45,852 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 40 transitions. [2018-01-30 03:30:45,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-30 03:30:45,852 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:45,852 INFO L350 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:45,852 INFO L371 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:45,853 INFO L82 PathProgramCache]: Analyzing trace with hash 1370928104, now seen corresponding path program 4 times [2018-01-30 03:30:45,853 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:45,853 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:45,853 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:45,853 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:45,853 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:45,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:45,862 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:45,903 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:45,904 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:45,904 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:45,915 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 03:30:45,939 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:45,940 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:45,944 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:45,961 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:45,962 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2018-01-30 03:30:45,962 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-30 03:30:45,962 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-30 03:30:45,962 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-01-30 03:30:45,962 INFO L87 Difference]: Start difference. First operand 38 states and 40 transitions. Second operand 7 states. [2018-01-30 03:30:46,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:46,087 INFO L93 Difference]: Finished difference Result 58 states and 62 transitions. [2018-01-30 03:30:46,087 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-30 03:30:46,087 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 32 [2018-01-30 03:30:46,087 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:46,088 INFO L225 Difference]: With dead ends: 58 [2018-01-30 03:30:46,088 INFO L226 Difference]: Without dead ends: 44 [2018-01-30 03:30:46,088 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-01-30 03:30:46,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-01-30 03:30:46,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 42. [2018-01-30 03:30:46,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-01-30 03:30:46,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 44 transitions. [2018-01-30 03:30:46,090 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 44 transitions. Word has length 32 [2018-01-30 03:30:46,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:46,091 INFO L432 AbstractCegarLoop]: Abstraction has 42 states and 44 transitions. [2018-01-30 03:30:46,091 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-30 03:30:46,091 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 44 transitions. [2018-01-30 03:30:46,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-30 03:30:46,092 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:46,092 INFO L350 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:46,092 INFO L371 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:46,092 INFO L82 PathProgramCache]: Analyzing trace with hash 1456677261, now seen corresponding path program 5 times [2018-01-30 03:30:46,092 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:46,092 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:46,093 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:46,093 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:46,093 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:46,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:46,100 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:46,180 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:46,180 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:46,180 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-30 03:30:46,188 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:46,192 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:46,203 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:46,204 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:46,204 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:46,206 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:46,209 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:46,209 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:46,210 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:46,214 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:46,232 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:46,232 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2018-01-30 03:30:46,232 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-30 03:30:46,233 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-30 03:30:46,233 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-30 03:30:46,233 INFO L87 Difference]: Start difference. First operand 42 states and 44 transitions. Second operand 8 states. [2018-01-30 03:30:46,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:46,262 INFO L93 Difference]: Finished difference Result 62 states and 66 transitions. [2018-01-30 03:30:46,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-30 03:30:46,263 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 36 [2018-01-30 03:30:46,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:46,263 INFO L225 Difference]: With dead ends: 62 [2018-01-30 03:30:46,263 INFO L226 Difference]: Without dead ends: 48 [2018-01-30 03:30:46,263 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-30 03:30:46,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-01-30 03:30:46,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 46. [2018-01-30 03:30:46,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-01-30 03:30:46,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 48 transitions. [2018-01-30 03:30:46,266 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 48 transitions. Word has length 36 [2018-01-30 03:30:46,267 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:46,267 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 48 transitions. [2018-01-30 03:30:46,267 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-30 03:30:46,267 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 48 transitions. [2018-01-30 03:30:46,267 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-01-30 03:30:46,267 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:46,267 INFO L350 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:46,267 INFO L371 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:46,267 INFO L82 PathProgramCache]: Analyzing trace with hash 1996895410, now seen corresponding path program 6 times [2018-01-30 03:30:46,268 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:46,268 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:46,268 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:46,268 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:46,268 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:46,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:46,274 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:46,530 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:46,530 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:46,530 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:46,540 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 03:30:46,544 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:46,545 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:46,546 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:46,547 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:46,553 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:46,554 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:46,556 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:46,556 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:46,557 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:46,562 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:46,579 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:46,579 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2018-01-30 03:30:46,579 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-30 03:30:46,579 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-30 03:30:46,579 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-01-30 03:30:46,580 INFO L87 Difference]: Start difference. First operand 46 states and 48 transitions. Second operand 9 states. [2018-01-30 03:30:46,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:46,639 INFO L93 Difference]: Finished difference Result 66 states and 70 transitions. [2018-01-30 03:30:46,639 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-30 03:30:46,639 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 40 [2018-01-30 03:30:46,639 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:46,640 INFO L225 Difference]: With dead ends: 66 [2018-01-30 03:30:46,640 INFO L226 Difference]: Without dead ends: 52 [2018-01-30 03:30:46,640 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 41 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-01-30 03:30:46,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-01-30 03:30:46,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 50. [2018-01-30 03:30:46,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-30 03:30:46,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 52 transitions. [2018-01-30 03:30:46,642 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 52 transitions. Word has length 40 [2018-01-30 03:30:46,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:46,642 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 52 transitions. [2018-01-30 03:30:46,643 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-30 03:30:46,643 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 52 transitions. [2018-01-30 03:30:46,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-30 03:30:46,643 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:46,643 INFO L350 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:46,643 INFO L371 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:46,643 INFO L82 PathProgramCache]: Analyzing trace with hash 1400974679, now seen corresponding path program 7 times [2018-01-30 03:30:46,643 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:46,644 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:46,644 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:46,644 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:46,644 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:46,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:46,650 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:46,797 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:46,797 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:46,797 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:46,802 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:30:46,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:46,809 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:46,814 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:46,831 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:46,832 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2018-01-30 03:30:46,832 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-30 03:30:46,832 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-30 03:30:46,832 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-30 03:30:46,832 INFO L87 Difference]: Start difference. First operand 50 states and 52 transitions. Second operand 10 states. [2018-01-30 03:30:46,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:46,884 INFO L93 Difference]: Finished difference Result 70 states and 74 transitions. [2018-01-30 03:30:46,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-30 03:30:46,889 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 44 [2018-01-30 03:30:46,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:46,889 INFO L225 Difference]: With dead ends: 70 [2018-01-30 03:30:46,890 INFO L226 Difference]: Without dead ends: 56 [2018-01-30 03:30:46,890 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-30 03:30:46,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2018-01-30 03:30:46,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 54. [2018-01-30 03:30:46,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-01-30 03:30:46,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 56 transitions. [2018-01-30 03:30:46,898 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 56 transitions. Word has length 44 [2018-01-30 03:30:46,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:46,898 INFO L432 AbstractCegarLoop]: Abstraction has 54 states and 56 transitions. [2018-01-30 03:30:46,898 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-30 03:30:46,898 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 56 transitions. [2018-01-30 03:30:46,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-01-30 03:30:46,899 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:46,899 INFO L350 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:46,899 INFO L371 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:46,899 INFO L82 PathProgramCache]: Analyzing trace with hash 315968380, now seen corresponding path program 8 times [2018-01-30 03:30:46,899 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:46,899 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:46,900 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:46,900 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:30:46,900 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:46,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:46,906 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:47,061 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:47,061 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:47,061 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-30 03:30:47,066 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:47,069 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:47,072 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:47,072 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:47,074 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:47,079 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:47,095 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:47,095 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2018-01-30 03:30:47,095 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-30 03:30:47,096 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-30 03:30:47,096 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-01-30 03:30:47,096 INFO L87 Difference]: Start difference. First operand 54 states and 56 transitions. Second operand 11 states. [2018-01-30 03:30:47,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:47,231 INFO L93 Difference]: Finished difference Result 74 states and 78 transitions. [2018-01-30 03:30:47,231 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-30 03:30:47,231 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 48 [2018-01-30 03:30:47,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:47,233 INFO L225 Difference]: With dead ends: 74 [2018-01-30 03:30:47,233 INFO L226 Difference]: Without dead ends: 60 [2018-01-30 03:30:47,233 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-01-30 03:30:47,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-01-30 03:30:47,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 58. [2018-01-30 03:30:47,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-01-30 03:30:47,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 60 transitions. [2018-01-30 03:30:47,236 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 60 transitions. Word has length 48 [2018-01-30 03:30:47,236 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:47,236 INFO L432 AbstractCegarLoop]: Abstraction has 58 states and 60 transitions. [2018-01-30 03:30:47,236 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-30 03:30:47,236 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 60 transitions. [2018-01-30 03:30:47,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-30 03:30:47,236 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:47,236 INFO L350 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:47,237 INFO L371 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:47,237 INFO L82 PathProgramCache]: Analyzing trace with hash -1326199007, now seen corresponding path program 9 times [2018-01-30 03:30:47,237 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:47,237 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:47,238 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:47,238 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:47,238 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:47,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:47,244 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:47,590 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:47,590 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:47,590 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:47,596 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 03:30:47,605 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:47,606 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:47,606 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:47,607 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:47,608 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:47,609 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:47,610 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:47,611 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:47,612 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:47,613 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:47,613 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:47,615 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:47,623 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:47,640 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:47,640 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2018-01-30 03:30:47,640 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-30 03:30:47,640 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-30 03:30:47,640 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-01-30 03:30:47,641 INFO L87 Difference]: Start difference. First operand 58 states and 60 transitions. Second operand 12 states. [2018-01-30 03:30:47,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:47,667 INFO L93 Difference]: Finished difference Result 78 states and 82 transitions. [2018-01-30 03:30:47,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-30 03:30:47,667 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 52 [2018-01-30 03:30:47,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:47,668 INFO L225 Difference]: With dead ends: 78 [2018-01-30 03:30:47,668 INFO L226 Difference]: Without dead ends: 64 [2018-01-30 03:30:47,668 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-01-30 03:30:47,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-01-30 03:30:47,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 62. [2018-01-30 03:30:47,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-01-30 03:30:47,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 64 transitions. [2018-01-30 03:30:47,670 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 64 transitions. Word has length 52 [2018-01-30 03:30:47,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:47,671 INFO L432 AbstractCegarLoop]: Abstraction has 62 states and 64 transitions. [2018-01-30 03:30:47,671 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-30 03:30:47,671 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 64 transitions. [2018-01-30 03:30:47,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-01-30 03:30:47,671 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:47,671 INFO L350 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:47,671 INFO L371 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:47,671 INFO L82 PathProgramCache]: Analyzing trace with hash 1328412742, now seen corresponding path program 10 times [2018-01-30 03:30:47,671 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:47,672 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:47,672 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:47,672 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:47,672 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:47,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:47,679 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:47,800 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:47,800 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:47,800 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:47,805 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 03:30:47,813 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:47,817 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:47,823 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:47,840 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:47,840 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2018-01-30 03:30:47,840 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-30 03:30:47,840 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-30 03:30:47,840 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-01-30 03:30:47,841 INFO L87 Difference]: Start difference. First operand 62 states and 64 transitions. Second operand 13 states. [2018-01-30 03:30:47,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:47,889 INFO L93 Difference]: Finished difference Result 82 states and 86 transitions. [2018-01-30 03:30:47,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-30 03:30:47,889 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 56 [2018-01-30 03:30:47,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:47,889 INFO L225 Difference]: With dead ends: 82 [2018-01-30 03:30:47,889 INFO L226 Difference]: Without dead ends: 68 [2018-01-30 03:30:47,890 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-01-30 03:30:47,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2018-01-30 03:30:47,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 66. [2018-01-30 03:30:47,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-01-30 03:30:47,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 68 transitions. [2018-01-30 03:30:47,892 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 68 transitions. Word has length 56 [2018-01-30 03:30:47,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:47,892 INFO L432 AbstractCegarLoop]: Abstraction has 66 states and 68 transitions. [2018-01-30 03:30:47,892 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-30 03:30:47,892 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 68 transitions. [2018-01-30 03:30:47,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-01-30 03:30:47,893 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:47,893 INFO L350 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:47,893 INFO L371 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:47,893 INFO L82 PathProgramCache]: Analyzing trace with hash -2076899605, now seen corresponding path program 11 times [2018-01-30 03:30:47,893 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:47,893 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:47,894 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:47,894 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:47,894 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:47,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:47,899 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:48,009 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:48,010 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:48,010 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:48,014 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 03:30:48,021 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:48,021 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:48,022 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:48,023 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:48,024 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:48,024 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:48,025 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:48,026 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:48,028 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:48,029 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:48,030 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:48,033 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:48,033 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:48,035 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:48,045 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:48,061 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:48,061 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 14 [2018-01-30 03:30:48,062 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-30 03:30:48,062 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-30 03:30:48,062 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-30 03:30:48,062 INFO L87 Difference]: Start difference. First operand 66 states and 68 transitions. Second operand 14 states. [2018-01-30 03:30:48,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:48,110 INFO L93 Difference]: Finished difference Result 86 states and 90 transitions. [2018-01-30 03:30:48,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-30 03:30:48,110 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 60 [2018-01-30 03:30:48,110 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:48,111 INFO L225 Difference]: With dead ends: 86 [2018-01-30 03:30:48,111 INFO L226 Difference]: Without dead ends: 72 [2018-01-30 03:30:48,111 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 61 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-30 03:30:48,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-01-30 03:30:48,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 70. [2018-01-30 03:30:48,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-01-30 03:30:48,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 72 transitions. [2018-01-30 03:30:48,113 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 72 transitions. Word has length 60 [2018-01-30 03:30:48,113 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:48,113 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 72 transitions. [2018-01-30 03:30:48,113 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-30 03:30:48,113 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 72 transitions. [2018-01-30 03:30:48,114 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-01-30 03:30:48,114 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:48,114 INFO L350 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:48,114 INFO L371 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:48,114 INFO L82 PathProgramCache]: Analyzing trace with hash -1407567088, now seen corresponding path program 12 times [2018-01-30 03:30:48,114 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:48,114 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:48,115 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:48,115 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:48,115 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:48,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:48,121 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:48,222 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:48,222 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:48,222 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:48,227 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 03:30:48,230 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:48,245 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:48,255 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:48,265 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:48,275 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:48,288 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:48,302 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:48,308 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:48,318 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:48,328 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:48,338 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:48,348 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:48,358 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:48,368 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:48,369 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:48,390 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:48,407 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:48,407 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 15 [2018-01-30 03:30:48,407 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-30 03:30:48,408 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-30 03:30:48,408 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2018-01-30 03:30:48,408 INFO L87 Difference]: Start difference. First operand 70 states and 72 transitions. Second operand 15 states. [2018-01-30 03:30:48,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:48,505 INFO L93 Difference]: Finished difference Result 90 states and 94 transitions. [2018-01-30 03:30:48,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-30 03:30:48,506 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 64 [2018-01-30 03:30:48,506 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:48,506 INFO L225 Difference]: With dead ends: 90 [2018-01-30 03:30:48,506 INFO L226 Difference]: Without dead ends: 76 [2018-01-30 03:30:48,506 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2018-01-30 03:30:48,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-01-30 03:30:48,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 74. [2018-01-30 03:30:48,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-30 03:30:48,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 76 transitions. [2018-01-30 03:30:48,509 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 76 transitions. Word has length 64 [2018-01-30 03:30:48,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:48,510 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 76 transitions. [2018-01-30 03:30:48,510 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-30 03:30:48,510 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 76 transitions. [2018-01-30 03:30:48,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-01-30 03:30:48,510 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:48,510 INFO L350 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:48,510 INFO L371 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:48,510 INFO L82 PathProgramCache]: Analyzing trace with hash 944690357, now seen corresponding path program 13 times [2018-01-30 03:30:48,511 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:48,511 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:48,511 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:48,511 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:48,511 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:48,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:48,518 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:48,623 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:48,623 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:48,623 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:48,628 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:30:48,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:48,653 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:48,664 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:48,686 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:48,686 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 16 [2018-01-30 03:30:48,686 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-30 03:30:48,687 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-30 03:30:48,687 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-30 03:30:48,687 INFO L87 Difference]: Start difference. First operand 74 states and 76 transitions. Second operand 16 states. [2018-01-30 03:30:48,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:48,793 INFO L93 Difference]: Finished difference Result 94 states and 98 transitions. [2018-01-30 03:30:48,793 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-30 03:30:48,793 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 68 [2018-01-30 03:30:48,793 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:48,794 INFO L225 Difference]: With dead ends: 94 [2018-01-30 03:30:48,794 INFO L226 Difference]: Without dead ends: 80 [2018-01-30 03:30:48,794 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 69 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-30 03:30:48,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-30 03:30:48,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 78. [2018-01-30 03:30:48,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-01-30 03:30:48,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 80 transitions. [2018-01-30 03:30:48,796 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 80 transitions. Word has length 68 [2018-01-30 03:30:48,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:48,797 INFO L432 AbstractCegarLoop]: Abstraction has 78 states and 80 transitions. [2018-01-30 03:30:48,797 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-30 03:30:48,797 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 80 transitions. [2018-01-30 03:30:48,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-01-30 03:30:48,797 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:48,797 INFO L350 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:48,797 INFO L371 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:48,797 INFO L82 PathProgramCache]: Analyzing trace with hash -6024230, now seen corresponding path program 14 times [2018-01-30 03:30:48,797 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:48,797 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:48,798 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:48,798 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:30:48,798 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:48,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:48,806 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:48,917 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:48,917 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:48,917 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-30 03:30:48,931 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:48,935 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:48,948 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:48,958 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:48,959 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:48,967 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:48,983 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:48,984 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 17 [2018-01-30 03:30:48,984 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-30 03:30:48,984 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-30 03:30:48,984 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2018-01-30 03:30:48,984 INFO L87 Difference]: Start difference. First operand 78 states and 80 transitions. Second operand 17 states. [2018-01-30 03:30:49,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:49,029 INFO L93 Difference]: Finished difference Result 98 states and 102 transitions. [2018-01-30 03:30:49,029 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-30 03:30:49,030 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2018-01-30 03:30:49,030 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:49,030 INFO L225 Difference]: With dead ends: 98 [2018-01-30 03:30:49,030 INFO L226 Difference]: Without dead ends: 84 [2018-01-30 03:30:49,030 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 73 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2018-01-30 03:30:49,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-01-30 03:30:49,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 82. [2018-01-30 03:30:49,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-01-30 03:30:49,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 84 transitions. [2018-01-30 03:30:49,033 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 84 transitions. Word has length 72 [2018-01-30 03:30:49,033 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:49,033 INFO L432 AbstractCegarLoop]: Abstraction has 82 states and 84 transitions. [2018-01-30 03:30:49,033 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-30 03:30:49,033 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 84 transitions. [2018-01-30 03:30:49,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-01-30 03:30:49,034 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:49,034 INFO L350 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:49,034 INFO L371 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:49,034 INFO L82 PathProgramCache]: Analyzing trace with hash -1907672961, now seen corresponding path program 15 times [2018-01-30 03:30:49,034 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:49,034 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:49,035 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:49,035 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:49,035 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:49,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:49,041 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:49,476 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:49,476 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:49,476 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:49,481 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 03:30:49,484 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,486 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,487 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,493 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,494 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,495 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,508 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,518 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,527 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,528 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,529 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,530 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,532 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,533 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,535 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,537 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:49,537 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:49,539 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:49,546 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:49,563 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:49,563 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2018-01-30 03:30:49,564 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-30 03:30:49,564 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-30 03:30:49,564 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-01-30 03:30:49,564 INFO L87 Difference]: Start difference. First operand 82 states and 84 transitions. Second operand 18 states. [2018-01-30 03:30:49,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:49,637 INFO L93 Difference]: Finished difference Result 102 states and 106 transitions. [2018-01-30 03:30:49,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-30 03:30:49,638 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 76 [2018-01-30 03:30:49,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:49,639 INFO L225 Difference]: With dead ends: 102 [2018-01-30 03:30:49,639 INFO L226 Difference]: Without dead ends: 88 [2018-01-30 03:30:49,639 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-01-30 03:30:49,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-01-30 03:30:49,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 86. [2018-01-30 03:30:49,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-01-30 03:30:49,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 88 transitions. [2018-01-30 03:30:49,641 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 88 transitions. Word has length 76 [2018-01-30 03:30:49,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:49,641 INFO L432 AbstractCegarLoop]: Abstraction has 86 states and 88 transitions. [2018-01-30 03:30:49,641 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-30 03:30:49,641 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 88 transitions. [2018-01-30 03:30:49,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-01-30 03:30:49,642 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:49,642 INFO L350 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:49,642 INFO L371 AbstractCegarLoop]: === Iteration 18 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:49,642 INFO L82 PathProgramCache]: Analyzing trace with hash 1976926884, now seen corresponding path program 16 times [2018-01-30 03:30:49,642 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:49,642 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:49,643 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:49,643 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:49,643 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:49,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:49,648 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:49,846 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:49,846 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:49,846 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:49,851 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 03:30:49,860 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:49,862 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:49,875 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:49,891 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:49,891 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 19 [2018-01-30 03:30:49,892 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-30 03:30:49,892 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-30 03:30:49,892 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-01-30 03:30:49,892 INFO L87 Difference]: Start difference. First operand 86 states and 88 transitions. Second operand 19 states. [2018-01-30 03:30:50,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:50,016 INFO L93 Difference]: Finished difference Result 106 states and 110 transitions. [2018-01-30 03:30:50,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-30 03:30:50,018 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 80 [2018-01-30 03:30:50,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:50,019 INFO L225 Difference]: With dead ends: 106 [2018-01-30 03:30:50,019 INFO L226 Difference]: Without dead ends: 92 [2018-01-30 03:30:50,019 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 81 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-01-30 03:30:50,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states. [2018-01-30 03:30:50,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 90. [2018-01-30 03:30:50,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2018-01-30 03:30:50,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 92 transitions. [2018-01-30 03:30:50,021 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 92 transitions. Word has length 80 [2018-01-30 03:30:50,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:50,021 INFO L432 AbstractCegarLoop]: Abstraction has 90 states and 92 transitions. [2018-01-30 03:30:50,021 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-30 03:30:50,021 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 92 transitions. [2018-01-30 03:30:50,022 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-01-30 03:30:50,022 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:50,022 INFO L350 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:50,022 INFO L371 AbstractCegarLoop]: === Iteration 19 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:50,022 INFO L82 PathProgramCache]: Analyzing trace with hash -1657523639, now seen corresponding path program 17 times [2018-01-30 03:30:50,022 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:50,022 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:50,023 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:50,023 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:50,023 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:50,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:50,028 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:50,183 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:50,184 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:50,184 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:50,189 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 03:30:50,192 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,193 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,193 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,194 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,195 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,196 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,196 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,197 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,204 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,205 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,207 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,214 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,223 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,232 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,242 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,252 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,258 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,263 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:50,263 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:50,264 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:50,272 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:50,291 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:50,291 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 20 [2018-01-30 03:30:50,291 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-30 03:30:50,295 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-30 03:30:50,295 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-30 03:30:50,295 INFO L87 Difference]: Start difference. First operand 90 states and 92 transitions. Second operand 20 states. [2018-01-30 03:30:50,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:50,358 INFO L93 Difference]: Finished difference Result 110 states and 114 transitions. [2018-01-30 03:30:50,358 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-30 03:30:50,358 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 84 [2018-01-30 03:30:50,359 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:50,359 INFO L225 Difference]: With dead ends: 110 [2018-01-30 03:30:50,359 INFO L226 Difference]: Without dead ends: 96 [2018-01-30 03:30:50,359 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 85 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-30 03:30:50,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-01-30 03:30:50,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 94. [2018-01-30 03:30:50,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-01-30 03:30:50,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 96 transitions. [2018-01-30 03:30:50,363 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 96 transitions. Word has length 84 [2018-01-30 03:30:50,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:50,363 INFO L432 AbstractCegarLoop]: Abstraction has 94 states and 96 transitions. [2018-01-30 03:30:50,363 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-30 03:30:50,363 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 96 transitions. [2018-01-30 03:30:50,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-01-30 03:30:50,363 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:50,364 INFO L350 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:50,364 INFO L371 AbstractCegarLoop]: === Iteration 20 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:50,364 INFO L82 PathProgramCache]: Analyzing trace with hash -1866954898, now seen corresponding path program 18 times [2018-01-30 03:30:50,364 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:50,364 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:50,364 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:50,364 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:50,365 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:50,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:50,375 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:50,511 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:50,511 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:50,511 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:50,516 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 03:30:50,520 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,520 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,521 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,522 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,522 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,523 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,524 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,525 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,526 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,526 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,528 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,529 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,530 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,531 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,532 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,534 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,538 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,540 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,542 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:50,543 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:50,544 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:50,552 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:50,569 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:50,569 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 21 [2018-01-30 03:30:50,570 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-30 03:30:50,570 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-30 03:30:50,570 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2018-01-30 03:30:50,570 INFO L87 Difference]: Start difference. First operand 94 states and 96 transitions. Second operand 21 states. [2018-01-30 03:30:50,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:50,619 INFO L93 Difference]: Finished difference Result 114 states and 118 transitions. [2018-01-30 03:30:50,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-30 03:30:50,620 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 88 [2018-01-30 03:30:50,620 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:50,620 INFO L225 Difference]: With dead ends: 114 [2018-01-30 03:30:50,620 INFO L226 Difference]: Without dead ends: 100 [2018-01-30 03:30:50,620 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2018-01-30 03:30:50,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-01-30 03:30:50,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 98. [2018-01-30 03:30:50,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98 states. [2018-01-30 03:30:50,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 100 transitions. [2018-01-30 03:30:50,622 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 100 transitions. Word has length 88 [2018-01-30 03:30:50,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:50,622 INFO L432 AbstractCegarLoop]: Abstraction has 98 states and 100 transitions. [2018-01-30 03:30:50,622 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-30 03:30:50,622 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 100 transitions. [2018-01-30 03:30:50,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-30 03:30:50,623 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:50,623 INFO L350 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:50,623 INFO L371 AbstractCegarLoop]: === Iteration 21 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:50,623 INFO L82 PathProgramCache]: Analyzing trace with hash -770457069, now seen corresponding path program 19 times [2018-01-30 03:30:50,623 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:50,623 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:50,624 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:50,624 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:50,624 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:50,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:50,628 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:50,841 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 0 proven. 722 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:50,841 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:50,841 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:50,854 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:30:50,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:50,868 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:50,877 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 0 proven. 722 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:50,894 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:50,894 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 22 [2018-01-30 03:30:50,894 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-30 03:30:50,894 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-30 03:30:50,894 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-30 03:30:50,894 INFO L87 Difference]: Start difference. First operand 98 states and 100 transitions. Second operand 22 states. [2018-01-30 03:30:51,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:51,019 INFO L93 Difference]: Finished difference Result 118 states and 122 transitions. [2018-01-30 03:30:51,020 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-30 03:30:51,020 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 92 [2018-01-30 03:30:51,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:51,020 INFO L225 Difference]: With dead ends: 118 [2018-01-30 03:30:51,020 INFO L226 Difference]: Without dead ends: 104 [2018-01-30 03:30:51,021 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 93 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-30 03:30:51,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-01-30 03:30:51,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 102. [2018-01-30 03:30:51,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-01-30 03:30:51,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 104 transitions. [2018-01-30 03:30:51,022 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 104 transitions. Word has length 92 [2018-01-30 03:30:51,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:51,023 INFO L432 AbstractCegarLoop]: Abstraction has 102 states and 104 transitions. [2018-01-30 03:30:51,023 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-30 03:30:51,023 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 104 transitions. [2018-01-30 03:30:51,023 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-01-30 03:30:51,023 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:51,023 INFO L350 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:51,023 INFO L371 AbstractCegarLoop]: === Iteration 22 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:51,023 INFO L82 PathProgramCache]: Analyzing trace with hash 676799032, now seen corresponding path program 20 times [2018-01-30 03:30:51,024 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:51,024 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:51,024 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:51,024 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:30:51,024 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:51,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:51,030 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:51,381 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:51,382 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:51,382 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:51,387 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 03:30:51,390 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:51,394 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:51,396 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:51,397 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:51,407 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:51,428 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:51,428 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 23 [2018-01-30 03:30:51,428 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-30 03:30:51,429 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-30 03:30:51,429 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2018-01-30 03:30:51,429 INFO L87 Difference]: Start difference. First operand 102 states and 104 transitions. Second operand 23 states. [2018-01-30 03:30:51,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:51,635 INFO L93 Difference]: Finished difference Result 122 states and 126 transitions. [2018-01-30 03:30:51,637 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-30 03:30:51,637 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 96 [2018-01-30 03:30:51,637 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:51,637 INFO L225 Difference]: With dead ends: 122 [2018-01-30 03:30:51,637 INFO L226 Difference]: Without dead ends: 108 [2018-01-30 03:30:51,638 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 97 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2018-01-30 03:30:51,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2018-01-30 03:30:51,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 106. [2018-01-30 03:30:51,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-01-30 03:30:51,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 108 transitions. [2018-01-30 03:30:51,639 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 108 transitions. Word has length 96 [2018-01-30 03:30:51,639 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:51,639 INFO L432 AbstractCegarLoop]: Abstraction has 106 states and 108 transitions. [2018-01-30 03:30:51,640 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-30 03:30:51,640 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 108 transitions. [2018-01-30 03:30:51,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-01-30 03:30:51,640 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:51,640 INFO L350 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:51,640 INFO L371 AbstractCegarLoop]: === Iteration 23 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:51,640 INFO L82 PathProgramCache]: Analyzing trace with hash -269228067, now seen corresponding path program 21 times [2018-01-30 03:30:51,640 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:51,640 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:51,641 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:51,641 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:51,641 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:51,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:51,645 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:51,813 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:51,813 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:51,813 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:51,821 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 03:30:51,828 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,829 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,830 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,830 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,831 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,833 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,834 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,835 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,836 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,837 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,839 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,840 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,841 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,843 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,845 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,847 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,849 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,851 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,853 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,856 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,859 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,862 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:51,862 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:51,863 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:51,881 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:51,898 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:51,898 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 24 [2018-01-30 03:30:51,898 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-30 03:30:51,898 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-30 03:30:51,898 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-01-30 03:30:51,899 INFO L87 Difference]: Start difference. First operand 106 states and 108 transitions. Second operand 24 states. [2018-01-30 03:30:51,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:51,986 INFO L93 Difference]: Finished difference Result 126 states and 130 transitions. [2018-01-30 03:30:51,986 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-30 03:30:51,986 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 100 [2018-01-30 03:30:51,986 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:51,986 INFO L225 Difference]: With dead ends: 126 [2018-01-30 03:30:51,986 INFO L226 Difference]: Without dead ends: 112 [2018-01-30 03:30:51,987 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 101 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-01-30 03:30:51,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-01-30 03:30:51,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 110. [2018-01-30 03:30:51,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-01-30 03:30:51,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 112 transitions. [2018-01-30 03:30:51,989 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 112 transitions. Word has length 100 [2018-01-30 03:30:51,989 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:51,989 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 112 transitions. [2018-01-30 03:30:51,989 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-30 03:30:51,989 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 112 transitions. [2018-01-30 03:30:51,989 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-01-30 03:30:51,989 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:51,989 INFO L350 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:51,989 INFO L371 AbstractCegarLoop]: === Iteration 24 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:51,989 INFO L82 PathProgramCache]: Analyzing trace with hash 1790661378, now seen corresponding path program 22 times [2018-01-30 03:30:51,990 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:51,990 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:51,990 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:51,990 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:51,990 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:51,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:51,996 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:52,251 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 0 proven. 968 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:52,251 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:52,251 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:52,257 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 03:30:52,267 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:52,268 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:52,288 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 0 proven. 968 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:52,307 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:52,307 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 25 [2018-01-30 03:30:52,307 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-30 03:30:52,307 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-30 03:30:52,308 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-01-30 03:30:52,308 INFO L87 Difference]: Start difference. First operand 110 states and 112 transitions. Second operand 25 states. [2018-01-30 03:30:52,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:52,373 INFO L93 Difference]: Finished difference Result 130 states and 134 transitions. [2018-01-30 03:30:52,373 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-30 03:30:52,373 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 104 [2018-01-30 03:30:52,374 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:52,374 INFO L225 Difference]: With dead ends: 130 [2018-01-30 03:30:52,374 INFO L226 Difference]: Without dead ends: 116 [2018-01-30 03:30:52,374 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 128 GetRequests, 105 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-01-30 03:30:52,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-01-30 03:30:52,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 114. [2018-01-30 03:30:52,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-01-30 03:30:52,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 116 transitions. [2018-01-30 03:30:52,376 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 116 transitions. Word has length 104 [2018-01-30 03:30:52,377 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:52,377 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 116 transitions. [2018-01-30 03:30:52,377 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-30 03:30:52,377 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 116 transitions. [2018-01-30 03:30:52,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-01-30 03:30:52,377 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:52,377 INFO L350 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:52,377 INFO L371 AbstractCegarLoop]: === Iteration 25 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:52,377 INFO L82 PathProgramCache]: Analyzing trace with hash 266249127, now seen corresponding path program 23 times [2018-01-30 03:30:52,377 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:52,378 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:52,378 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:52,378 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:52,378 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:52,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:52,383 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:52,986 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:52,986 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:52,986 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:52,991 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 03:30:52,993 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:52,994 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:52,995 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:52,996 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:52,996 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:52,997 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:52,998 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:52,999 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,000 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,002 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,003 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,005 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,006 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,008 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,011 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,013 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,016 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,019 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,022 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,026 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,030 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,035 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,040 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,046 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:53,047 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:53,048 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:53,058 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:53,081 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:53,081 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 26 [2018-01-30 03:30:53,082 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-30 03:30:53,082 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-30 03:30:53,082 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-30 03:30:53,082 INFO L87 Difference]: Start difference. First operand 114 states and 116 transitions. Second operand 26 states. [2018-01-30 03:30:53,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:53,169 INFO L93 Difference]: Finished difference Result 134 states and 138 transitions. [2018-01-30 03:30:53,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-30 03:30:53,170 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 108 [2018-01-30 03:30:53,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:53,170 INFO L225 Difference]: With dead ends: 134 [2018-01-30 03:30:53,170 INFO L226 Difference]: Without dead ends: 120 [2018-01-30 03:30:53,170 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-30 03:30:53,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-01-30 03:30:53,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 118. [2018-01-30 03:30:53,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-30 03:30:53,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 120 transitions. [2018-01-30 03:30:53,172 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 120 transitions. Word has length 108 [2018-01-30 03:30:53,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:53,172 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 120 transitions. [2018-01-30 03:30:53,172 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-30 03:30:53,172 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 120 transitions. [2018-01-30 03:30:53,173 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-01-30 03:30:53,173 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:53,173 INFO L350 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:53,173 INFO L371 AbstractCegarLoop]: === Iteration 26 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:53,173 INFO L82 PathProgramCache]: Analyzing trace with hash -605087284, now seen corresponding path program 24 times [2018-01-30 03:30:53,173 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:53,173 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:53,174 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:53,174 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:53,174 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:53,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:53,178 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:53,582 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:53,582 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:53,582 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:53,587 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 03:30:53,590 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,591 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,592 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,592 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,593 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,594 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,595 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,595 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,608 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,610 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,611 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,612 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,614 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,615 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,616 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,618 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,619 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,621 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,623 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,624 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,626 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,629 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,631 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,635 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,640 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:53,640 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:53,642 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:53,652 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:53,669 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:53,669 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 27 [2018-01-30 03:30:53,669 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-30 03:30:53,669 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-30 03:30:53,669 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2018-01-30 03:30:53,670 INFO L87 Difference]: Start difference. First operand 118 states and 120 transitions. Second operand 27 states. [2018-01-30 03:30:53,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:53,750 INFO L93 Difference]: Finished difference Result 138 states and 142 transitions. [2018-01-30 03:30:53,750 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-30 03:30:53,750 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 112 [2018-01-30 03:30:53,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:53,750 INFO L225 Difference]: With dead ends: 138 [2018-01-30 03:30:53,751 INFO L226 Difference]: Without dead ends: 124 [2018-01-30 03:30:53,751 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 138 GetRequests, 113 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2018-01-30 03:30:53,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-01-30 03:30:53,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 122. [2018-01-30 03:30:53,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-01-30 03:30:53,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 124 transitions. [2018-01-30 03:30:53,753 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 124 transitions. Word has length 112 [2018-01-30 03:30:53,753 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:53,753 INFO L432 AbstractCegarLoop]: Abstraction has 122 states and 124 transitions. [2018-01-30 03:30:53,753 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-30 03:30:53,753 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 124 transitions. [2018-01-30 03:30:53,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-01-30 03:30:53,754 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:53,754 INFO L350 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:53,754 INFO L371 AbstractCegarLoop]: === Iteration 27 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:53,754 INFO L82 PathProgramCache]: Analyzing trace with hash -1596066447, now seen corresponding path program 25 times [2018-01-30 03:30:53,754 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:53,754 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:53,754 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:53,759 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:53,759 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:53,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:53,764 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:54,111 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 0 proven. 1250 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:54,112 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:54,112 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-30 03:30:54,126 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:54,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:54,137 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:54,147 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 0 proven. 1250 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:54,164 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:54,164 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 28 [2018-01-30 03:30:54,164 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-30 03:30:54,164 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-30 03:30:54,165 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-30 03:30:54,165 INFO L87 Difference]: Start difference. First operand 122 states and 124 transitions. Second operand 28 states. [2018-01-30 03:30:54,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:54,265 INFO L93 Difference]: Finished difference Result 142 states and 146 transitions. [2018-01-30 03:30:54,265 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-30 03:30:54,265 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 116 [2018-01-30 03:30:54,266 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:54,266 INFO L225 Difference]: With dead ends: 142 [2018-01-30 03:30:54,266 INFO L226 Difference]: Without dead ends: 128 [2018-01-30 03:30:54,266 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 143 GetRequests, 117 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-30 03:30:54,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-01-30 03:30:54,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 126. [2018-01-30 03:30:54,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-01-30 03:30:54,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 128 transitions. [2018-01-30 03:30:54,268 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 128 transitions. Word has length 116 [2018-01-30 03:30:54,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:54,268 INFO L432 AbstractCegarLoop]: Abstraction has 126 states and 128 transitions. [2018-01-30 03:30:54,268 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-30 03:30:54,268 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 128 transitions. [2018-01-30 03:30:54,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-01-30 03:30:54,269 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:54,269 INFO L350 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:54,269 INFO L371 AbstractCegarLoop]: === Iteration 28 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:54,269 INFO L82 PathProgramCache]: Analyzing trace with hash 1442608790, now seen corresponding path program 26 times [2018-01-30 03:30:54,269 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:54,269 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:54,269 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:54,269 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:30:54,269 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:54,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:54,275 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:54,997 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:54,998 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:54,998 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:55,003 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 03:30:55,006 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:55,012 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:55,014 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:55,016 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:55,029 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:55,046 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:55,046 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 29 [2018-01-30 03:30:55,046 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-30 03:30:55,046 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-30 03:30:55,046 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2018-01-30 03:30:55,047 INFO L87 Difference]: Start difference. First operand 126 states and 128 transitions. Second operand 29 states. [2018-01-30 03:30:55,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:55,102 INFO L93 Difference]: Finished difference Result 146 states and 150 transitions. [2018-01-30 03:30:55,102 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-30 03:30:55,102 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 120 [2018-01-30 03:30:55,102 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:55,102 INFO L225 Difference]: With dead ends: 146 [2018-01-30 03:30:55,103 INFO L226 Difference]: Without dead ends: 132 [2018-01-30 03:30:55,103 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 121 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2018-01-30 03:30:55,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-01-30 03:30:55,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 130. [2018-01-30 03:30:55,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-01-30 03:30:55,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 132 transitions. [2018-01-30 03:30:55,105 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 132 transitions. Word has length 120 [2018-01-30 03:30:55,105 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:55,105 INFO L432 AbstractCegarLoop]: Abstraction has 130 states and 132 transitions. [2018-01-30 03:30:55,105 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-30 03:30:55,105 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 132 transitions. [2018-01-30 03:30:55,106 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2018-01-30 03:30:55,106 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:55,106 INFO L350 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:55,106 INFO L371 AbstractCegarLoop]: === Iteration 29 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:55,106 INFO L82 PathProgramCache]: Analyzing trace with hash 1744559419, now seen corresponding path program 27 times [2018-01-30 03:30:55,106 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:55,106 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:55,107 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:55,107 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:55,107 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:55,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:55,112 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:55,485 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:55,485 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:55,486 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:55,491 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 03:30:55,497 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,498 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,499 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,499 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,500 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,501 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,502 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,503 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,504 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,506 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,507 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,509 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,510 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,512 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,514 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,516 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,518 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,520 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,522 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,525 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,528 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,531 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,534 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,538 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,542 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,546 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,551 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,556 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:55,557 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:55,558 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:55,570 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:55,587 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:55,587 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 30 [2018-01-30 03:30:55,587 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-30 03:30:55,587 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-30 03:30:55,587 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-01-30 03:30:55,587 INFO L87 Difference]: Start difference. First operand 130 states and 132 transitions. Second operand 30 states. [2018-01-30 03:30:55,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:55,733 INFO L93 Difference]: Finished difference Result 150 states and 154 transitions. [2018-01-30 03:30:55,733 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-30 03:30:55,733 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 124 [2018-01-30 03:30:55,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:55,734 INFO L225 Difference]: With dead ends: 150 [2018-01-30 03:30:55,734 INFO L226 Difference]: Without dead ends: 136 [2018-01-30 03:30:55,734 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 153 GetRequests, 125 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-01-30 03:30:55,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-01-30 03:30:55,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 134. [2018-01-30 03:30:55,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-01-30 03:30:55,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 136 transitions. [2018-01-30 03:30:55,736 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 136 transitions. Word has length 124 [2018-01-30 03:30:55,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:55,736 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 136 transitions. [2018-01-30 03:30:55,736 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-30 03:30:55,736 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 136 transitions. [2018-01-30 03:30:55,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-01-30 03:30:55,737 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:55,737 INFO L350 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:55,737 INFO L371 AbstractCegarLoop]: === Iteration 30 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:55,737 INFO L82 PathProgramCache]: Analyzing trace with hash 149776736, now seen corresponding path program 28 times [2018-01-30 03:30:55,737 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:55,737 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:55,737 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:55,737 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:55,738 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:55,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:55,746 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:56,003 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 0 proven. 1568 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:56,003 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:56,003 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:56,009 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 03:30:56,020 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:56,022 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:56,035 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 0 proven. 1568 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:56,051 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:56,051 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 31 [2018-01-30 03:30:56,052 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-01-30 03:30:56,052 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-01-30 03:30:56,052 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2018-01-30 03:30:56,052 INFO L87 Difference]: Start difference. First operand 134 states and 136 transitions. Second operand 31 states. [2018-01-30 03:30:56,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:56,110 INFO L93 Difference]: Finished difference Result 154 states and 158 transitions. [2018-01-30 03:30:56,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-30 03:30:56,110 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 128 [2018-01-30 03:30:56,110 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:56,111 INFO L225 Difference]: With dead ends: 154 [2018-01-30 03:30:56,111 INFO L226 Difference]: Without dead ends: 140 [2018-01-30 03:30:56,111 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 129 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2018-01-30 03:30:56,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-01-30 03:30:56,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 138. [2018-01-30 03:30:56,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-01-30 03:30:56,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 140 transitions. [2018-01-30 03:30:56,113 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 140 transitions. Word has length 128 [2018-01-30 03:30:56,113 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:56,113 INFO L432 AbstractCegarLoop]: Abstraction has 138 states and 140 transitions. [2018-01-30 03:30:56,113 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-01-30 03:30:56,113 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 140 transitions. [2018-01-30 03:30:56,113 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-01-30 03:30:56,113 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:56,114 INFO L350 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:56,114 INFO L371 AbstractCegarLoop]: === Iteration 31 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:56,114 INFO L82 PathProgramCache]: Analyzing trace with hash -2143134971, now seen corresponding path program 29 times [2018-01-30 03:30:56,114 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:56,114 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:56,114 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:56,114 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:56,114 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:56,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:56,119 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:56,788 INFO L134 CoverageAnalysis]: Checked inductivity of 1682 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:56,788 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:56,788 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:56,792 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 03:30:56,795 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,798 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,798 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,799 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,800 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,801 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,802 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,803 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,804 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,805 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,809 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,810 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,812 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,814 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,825 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,828 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,830 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,833 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,837 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,841 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,845 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,850 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,855 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,860 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,867 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,874 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,882 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,891 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,900 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,911 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:56,912 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:56,913 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:56,926 INFO L134 CoverageAnalysis]: Checked inductivity of 1682 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:56,943 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:56,943 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 32 [2018-01-30 03:30:56,943 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-01-30 03:30:56,943 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-01-30 03:30:56,944 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-30 03:30:56,944 INFO L87 Difference]: Start difference. First operand 138 states and 140 transitions. Second operand 32 states. [2018-01-30 03:30:57,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:57,392 INFO L93 Difference]: Finished difference Result 158 states and 162 transitions. [2018-01-30 03:30:57,392 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-01-30 03:30:57,392 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 132 [2018-01-30 03:30:57,392 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:57,393 INFO L225 Difference]: With dead ends: 158 [2018-01-30 03:30:57,393 INFO L226 Difference]: Without dead ends: 144 [2018-01-30 03:30:57,393 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 133 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-30 03:30:57,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-01-30 03:30:57,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 142. [2018-01-30 03:30:57,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-01-30 03:30:57,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 144 transitions. [2018-01-30 03:30:57,395 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 144 transitions. Word has length 132 [2018-01-30 03:30:57,395 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:57,395 INFO L432 AbstractCegarLoop]: Abstraction has 142 states and 144 transitions. [2018-01-30 03:30:57,395 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-01-30 03:30:57,395 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 144 transitions. [2018-01-30 03:30:57,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2018-01-30 03:30:57,396 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:57,396 INFO L350 BasicCegarLoop]: trace histogram [31, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:57,396 INFO L371 AbstractCegarLoop]: === Iteration 32 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:57,396 INFO L82 PathProgramCache]: Analyzing trace with hash 2060186154, now seen corresponding path program 30 times [2018-01-30 03:30:57,396 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:57,396 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:57,397 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:57,397 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:57,397 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:57,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:57,402 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:57,729 INFO L134 CoverageAnalysis]: Checked inductivity of 1800 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:57,729 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:57,729 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:57,734 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 03:30:57,738 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,738 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,740 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,741 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,741 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,742 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,743 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,743 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,744 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,745 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,746 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,747 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,748 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,750 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,751 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,752 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,754 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,756 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,757 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,759 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,761 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,763 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,766 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,768 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,770 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,773 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,776 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,779 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,782 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,786 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,797 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:30:57,798 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:57,799 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:57,812 INFO L134 CoverageAnalysis]: Checked inductivity of 1800 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:57,829 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:57,829 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 33 [2018-01-30 03:30:57,829 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-30 03:30:57,829 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-30 03:30:57,829 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-01-30 03:30:57,829 INFO L87 Difference]: Start difference. First operand 142 states and 144 transitions. Second operand 33 states. [2018-01-30 03:30:57,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:57,967 INFO L93 Difference]: Finished difference Result 162 states and 166 transitions. [2018-01-30 03:30:57,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-01-30 03:30:57,968 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 136 [2018-01-30 03:30:57,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:57,968 INFO L225 Difference]: With dead ends: 162 [2018-01-30 03:30:57,968 INFO L226 Difference]: Without dead ends: 148 [2018-01-30 03:30:57,969 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 168 GetRequests, 137 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-01-30 03:30:57,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-01-30 03:30:57,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 146. [2018-01-30 03:30:57,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2018-01-30 03:30:57,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 148 transitions. [2018-01-30 03:30:57,971 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 148 transitions. Word has length 136 [2018-01-30 03:30:57,971 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:57,971 INFO L432 AbstractCegarLoop]: Abstraction has 146 states and 148 transitions. [2018-01-30 03:30:57,971 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-30 03:30:57,971 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 148 transitions. [2018-01-30 03:30:57,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-01-30 03:30:57,971 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:57,971 INFO L350 BasicCegarLoop]: trace histogram [32, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:57,971 INFO L371 AbstractCegarLoop]: === Iteration 33 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:57,972 INFO L82 PathProgramCache]: Analyzing trace with hash 1522233039, now seen corresponding path program 31 times [2018-01-30 03:30:57,972 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:57,972 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:57,972 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:57,972 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:57,972 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:57,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:57,977 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:58,299 INFO L134 CoverageAnalysis]: Checked inductivity of 1922 backedges. 0 proven. 1922 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:58,299 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:58,299 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:58,304 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:30:58,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:58,319 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:58,340 INFO L134 CoverageAnalysis]: Checked inductivity of 1922 backedges. 0 proven. 1922 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:58,356 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:58,357 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 34 [2018-01-30 03:30:58,357 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-01-30 03:30:58,357 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-01-30 03:30:58,357 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-30 03:30:58,357 INFO L87 Difference]: Start difference. First operand 146 states and 148 transitions. Second operand 34 states. [2018-01-30 03:30:58,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:58,425 INFO L93 Difference]: Finished difference Result 166 states and 170 transitions. [2018-01-30 03:30:58,426 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-01-30 03:30:58,426 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 140 [2018-01-30 03:30:58,426 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:58,427 INFO L225 Difference]: With dead ends: 166 [2018-01-30 03:30:58,427 INFO L226 Difference]: Without dead ends: 152 [2018-01-30 03:30:58,427 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 173 GetRequests, 141 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-30 03:30:58,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-01-30 03:30:58,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 150. [2018-01-30 03:30:58,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-01-30 03:30:58,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 152 transitions. [2018-01-30 03:30:58,429 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 152 transitions. Word has length 140 [2018-01-30 03:30:58,429 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:58,429 INFO L432 AbstractCegarLoop]: Abstraction has 150 states and 152 transitions. [2018-01-30 03:30:58,429 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-01-30 03:30:58,429 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 152 transitions. [2018-01-30 03:30:58,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2018-01-30 03:30:58,429 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:58,430 INFO L350 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:58,430 INFO L371 AbstractCegarLoop]: === Iteration 34 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:58,430 INFO L82 PathProgramCache]: Analyzing trace with hash -2019421964, now seen corresponding path program 32 times [2018-01-30 03:30:58,430 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:58,430 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:58,430 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:58,430 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:30:58,430 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:58,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:58,435 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:58,921 INFO L134 CoverageAnalysis]: Checked inductivity of 2048 backedges. 0 proven. 2048 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:58,921 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:58,921 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:58,926 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 03:30:58,930 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:58,941 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:30:58,942 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:30:58,943 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:30:58,957 INFO L134 CoverageAnalysis]: Checked inductivity of 2048 backedges. 0 proven. 2048 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:58,974 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:30:58,974 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 35 [2018-01-30 03:30:58,974 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-01-30 03:30:58,974 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-01-30 03:30:58,974 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2018-01-30 03:30:58,975 INFO L87 Difference]: Start difference. First operand 150 states and 152 transitions. Second operand 35 states. [2018-01-30 03:30:59,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:30:59,398 INFO L93 Difference]: Finished difference Result 170 states and 174 transitions. [2018-01-30 03:30:59,398 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-01-30 03:30:59,398 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 144 [2018-01-30 03:30:59,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:30:59,399 INFO L225 Difference]: With dead ends: 170 [2018-01-30 03:30:59,399 INFO L226 Difference]: Without dead ends: 156 [2018-01-30 03:30:59,399 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 178 GetRequests, 145 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2018-01-30 03:30:59,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-01-30 03:30:59,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 154. [2018-01-30 03:30:59,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-01-30 03:30:59,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 156 transitions. [2018-01-30 03:30:59,401 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 156 transitions. Word has length 144 [2018-01-30 03:30:59,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:30:59,401 INFO L432 AbstractCegarLoop]: Abstraction has 154 states and 156 transitions. [2018-01-30 03:30:59,401 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-01-30 03:30:59,402 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 156 transitions. [2018-01-30 03:30:59,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-01-30 03:30:59,402 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:30:59,402 INFO L350 BasicCegarLoop]: trace histogram [34, 33, 33, 33, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:30:59,402 INFO L371 AbstractCegarLoop]: === Iteration 35 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:30:59,402 INFO L82 PathProgramCache]: Analyzing trace with hash -1099884391, now seen corresponding path program 33 times [2018-01-30 03:30:59,402 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:30:59,402 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:30:59,403 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:59,403 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:30:59,403 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:30:59,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:30:59,408 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:30:59,968 INFO L134 CoverageAnalysis]: Checked inductivity of 2178 backedges. 0 proven. 2178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:30:59,968 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:30:59,968 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:30:59,974 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 03:30:59,978 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,978 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,979 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,980 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,980 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,981 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,982 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,983 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,984 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,985 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,987 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,989 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,990 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,992 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,993 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,996 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:30:59,998 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,000 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,002 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,005 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,008 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,011 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,014 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,018 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,021 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,026 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,031 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,036 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,041 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,047 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,053 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,061 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,068 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,076 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:00,077 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:00,078 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:00,099 INFO L134 CoverageAnalysis]: Checked inductivity of 2178 backedges. 0 proven. 2178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:00,116 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:00,116 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 36 [2018-01-30 03:31:00,117 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-01-30 03:31:00,117 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-01-30 03:31:00,117 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-01-30 03:31:00,117 INFO L87 Difference]: Start difference. First operand 154 states and 156 transitions. Second operand 36 states. [2018-01-30 03:31:00,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:00,246 INFO L93 Difference]: Finished difference Result 174 states and 178 transitions. [2018-01-30 03:31:00,246 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-01-30 03:31:00,246 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 148 [2018-01-30 03:31:00,247 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:00,247 INFO L225 Difference]: With dead ends: 174 [2018-01-30 03:31:00,247 INFO L226 Difference]: Without dead ends: 160 [2018-01-30 03:31:00,247 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 149 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-01-30 03:31:00,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-01-30 03:31:00,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 158. [2018-01-30 03:31:00,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-01-30 03:31:00,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 160 transitions. [2018-01-30 03:31:00,249 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 160 transitions. Word has length 148 [2018-01-30 03:31:00,249 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:00,250 INFO L432 AbstractCegarLoop]: Abstraction has 158 states and 160 transitions. [2018-01-30 03:31:00,250 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-01-30 03:31:00,250 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 160 transitions. [2018-01-30 03:31:00,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-01-30 03:31:00,250 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:00,250 INFO L350 BasicCegarLoop]: trace histogram [35, 34, 34, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:00,250 INFO L371 AbstractCegarLoop]: === Iteration 36 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:00,250 INFO L82 PathProgramCache]: Analyzing trace with hash 1635370430, now seen corresponding path program 34 times [2018-01-30 03:31:00,250 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:00,250 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:00,251 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:00,251 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:00,251 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:00,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:00,256 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:01,011 INFO L134 CoverageAnalysis]: Checked inductivity of 2312 backedges. 0 proven. 2312 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:01,011 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:01,011 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:01,016 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 03:31:01,035 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:01,037 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:01,052 INFO L134 CoverageAnalysis]: Checked inductivity of 2312 backedges. 0 proven. 2312 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:01,069 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:01,069 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 37 [2018-01-30 03:31:01,070 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-01-30 03:31:01,070 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-01-30 03:31:01,070 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2018-01-30 03:31:01,070 INFO L87 Difference]: Start difference. First operand 158 states and 160 transitions. Second operand 37 states. [2018-01-30 03:31:01,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:01,133 INFO L93 Difference]: Finished difference Result 178 states and 182 transitions. [2018-01-30 03:31:01,133 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-01-30 03:31:01,133 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 152 [2018-01-30 03:31:01,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:01,134 INFO L225 Difference]: With dead ends: 178 [2018-01-30 03:31:01,134 INFO L226 Difference]: Without dead ends: 164 [2018-01-30 03:31:01,134 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 188 GetRequests, 153 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2018-01-30 03:31:01,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164 states. [2018-01-30 03:31:01,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164 to 162. [2018-01-30 03:31:01,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-01-30 03:31:01,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 164 transitions. [2018-01-30 03:31:01,136 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 164 transitions. Word has length 152 [2018-01-30 03:31:01,137 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:01,137 INFO L432 AbstractCegarLoop]: Abstraction has 162 states and 164 transitions. [2018-01-30 03:31:01,137 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-01-30 03:31:01,137 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 164 transitions. [2018-01-30 03:31:01,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2018-01-30 03:31:01,137 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:01,137 INFO L350 BasicCegarLoop]: trace histogram [36, 35, 35, 35, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:01,137 INFO L371 AbstractCegarLoop]: === Iteration 37 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:01,137 INFO L82 PathProgramCache]: Analyzing trace with hash -932358045, now seen corresponding path program 35 times [2018-01-30 03:31:01,137 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:01,137 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:01,138 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:01,138 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:01,138 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:01,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:01,143 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:02,085 INFO L134 CoverageAnalysis]: Checked inductivity of 2450 backedges. 0 proven. 2450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:02,085 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:02,085 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:02,091 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 03:31:02,094 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,105 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,115 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,125 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,131 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,132 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,133 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,134 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,135 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,136 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,138 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,139 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,141 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,143 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,145 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,148 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,150 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,153 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,157 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,161 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,165 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,170 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,175 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,181 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,187 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,194 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,202 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,211 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,220 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,231 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,242 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,254 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,268 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,282 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,299 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,317 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:02,318 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:02,320 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:02,341 INFO L134 CoverageAnalysis]: Checked inductivity of 2450 backedges. 0 proven. 2450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:02,362 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:02,362 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 38 [2018-01-30 03:31:02,362 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-01-30 03:31:02,362 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-01-30 03:31:02,362 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-30 03:31:02,363 INFO L87 Difference]: Start difference. First operand 162 states and 164 transitions. Second operand 38 states. [2018-01-30 03:31:02,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:02,466 INFO L93 Difference]: Finished difference Result 182 states and 186 transitions. [2018-01-30 03:31:02,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-01-30 03:31:02,466 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 156 [2018-01-30 03:31:02,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:02,467 INFO L225 Difference]: With dead ends: 182 [2018-01-30 03:31:02,467 INFO L226 Difference]: Without dead ends: 168 [2018-01-30 03:31:02,467 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 193 GetRequests, 157 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-30 03:31:02,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168 states. [2018-01-30 03:31:02,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168 to 166. [2018-01-30 03:31:02,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-01-30 03:31:02,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 168 transitions. [2018-01-30 03:31:02,469 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 168 transitions. Word has length 156 [2018-01-30 03:31:02,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:02,470 INFO L432 AbstractCegarLoop]: Abstraction has 166 states and 168 transitions. [2018-01-30 03:31:02,470 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-01-30 03:31:02,470 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 168 transitions. [2018-01-30 03:31:02,470 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 161 [2018-01-30 03:31:02,470 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:02,470 INFO L350 BasicCegarLoop]: trace histogram [37, 36, 36, 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:02,470 INFO L371 AbstractCegarLoop]: === Iteration 38 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:02,470 INFO L82 PathProgramCache]: Analyzing trace with hash -1872949112, now seen corresponding path program 36 times [2018-01-30 03:31:02,471 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:02,471 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:02,471 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:02,471 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:02,471 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:02,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:02,476 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:04,559 INFO L134 CoverageAnalysis]: Checked inductivity of 2592 backedges. 0 proven. 2592 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:04,559 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:04,559 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:04,565 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 03:31:04,571 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,572 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,573 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,574 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,574 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,575 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,576 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,577 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,577 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,578 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,579 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,581 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,582 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,583 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,584 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,586 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,587 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,589 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,591 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,593 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,594 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,601 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,603 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,605 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,608 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,610 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,613 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,616 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,620 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,623 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,627 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,630 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,634 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,639 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,644 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,649 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,658 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:04,659 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:04,661 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:04,676 INFO L134 CoverageAnalysis]: Checked inductivity of 2592 backedges. 0 proven. 2592 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:04,695 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:04,695 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 39 [2018-01-30 03:31:04,695 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-01-30 03:31:04,696 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-01-30 03:31:04,696 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2018-01-30 03:31:04,696 INFO L87 Difference]: Start difference. First operand 166 states and 168 transitions. Second operand 39 states. [2018-01-30 03:31:04,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:04,805 INFO L93 Difference]: Finished difference Result 186 states and 190 transitions. [2018-01-30 03:31:04,805 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-01-30 03:31:04,805 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 160 [2018-01-30 03:31:04,805 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:04,806 INFO L225 Difference]: With dead ends: 186 [2018-01-30 03:31:04,806 INFO L226 Difference]: Without dead ends: 172 [2018-01-30 03:31:04,806 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 161 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2018-01-30 03:31:04,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-01-30 03:31:04,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 170. [2018-01-30 03:31:04,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-01-30 03:31:04,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 172 transitions. [2018-01-30 03:31:04,808 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 172 transitions. Word has length 160 [2018-01-30 03:31:04,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:04,808 INFO L432 AbstractCegarLoop]: Abstraction has 170 states and 172 transitions. [2018-01-30 03:31:04,808 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-01-30 03:31:04,808 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 172 transitions. [2018-01-30 03:31:04,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-01-30 03:31:04,809 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:04,809 INFO L350 BasicCegarLoop]: trace histogram [38, 37, 37, 37, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:04,809 INFO L371 AbstractCegarLoop]: === Iteration 39 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:04,809 INFO L82 PathProgramCache]: Analyzing trace with hash -340120019, now seen corresponding path program 37 times [2018-01-30 03:31:04,809 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:04,809 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:04,810 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:04,810 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:04,810 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:04,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:04,815 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:05,751 INFO L134 CoverageAnalysis]: Checked inductivity of 2738 backedges. 0 proven. 2738 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:05,751 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:05,751 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:05,756 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:31:05,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:05,770 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:05,786 INFO L134 CoverageAnalysis]: Checked inductivity of 2738 backedges. 0 proven. 2738 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:05,805 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:05,805 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 40 [2018-01-30 03:31:05,805 INFO L409 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-01-30 03:31:05,805 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-01-30 03:31:05,806 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-30 03:31:05,806 INFO L87 Difference]: Start difference. First operand 170 states and 172 transitions. Second operand 40 states. [2018-01-30 03:31:06,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:06,654 INFO L93 Difference]: Finished difference Result 190 states and 194 transitions. [2018-01-30 03:31:06,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-01-30 03:31:06,655 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 164 [2018-01-30 03:31:06,655 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:06,655 INFO L225 Difference]: With dead ends: 190 [2018-01-30 03:31:06,655 INFO L226 Difference]: Without dead ends: 176 [2018-01-30 03:31:06,656 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-30 03:31:06,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-01-30 03:31:06,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 174. [2018-01-30 03:31:06,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-01-30 03:31:06,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 176 transitions. [2018-01-30 03:31:06,658 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 176 transitions. Word has length 164 [2018-01-30 03:31:06,658 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:06,658 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 176 transitions. [2018-01-30 03:31:06,658 INFO L433 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-01-30 03:31:06,658 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 176 transitions. [2018-01-30 03:31:06,658 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2018-01-30 03:31:06,658 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:06,659 INFO L350 BasicCegarLoop]: trace histogram [39, 38, 38, 38, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:06,659 INFO L371 AbstractCegarLoop]: === Iteration 40 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:06,659 INFO L82 PathProgramCache]: Analyzing trace with hash -229248686, now seen corresponding path program 38 times [2018-01-30 03:31:06,659 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:06,659 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:06,659 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:06,659 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:31:06,659 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:06,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:06,665 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:07,148 INFO L134 CoverageAnalysis]: Checked inductivity of 2888 backedges. 0 proven. 2888 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:07,149 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:07,149 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:07,153 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 03:31:07,158 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:07,166 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:07,167 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:07,169 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:07,187 INFO L134 CoverageAnalysis]: Checked inductivity of 2888 backedges. 0 proven. 2888 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:07,205 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:07,205 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41] total 41 [2018-01-30 03:31:07,205 INFO L409 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-01-30 03:31:07,205 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-01-30 03:31:07,206 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2018-01-30 03:31:07,206 INFO L87 Difference]: Start difference. First operand 174 states and 176 transitions. Second operand 41 states. [2018-01-30 03:31:07,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:07,353 INFO L93 Difference]: Finished difference Result 194 states and 198 transitions. [2018-01-30 03:31:07,354 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-01-30 03:31:07,354 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 168 [2018-01-30 03:31:07,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:07,354 INFO L225 Difference]: With dead ends: 194 [2018-01-30 03:31:07,354 INFO L226 Difference]: Without dead ends: 180 [2018-01-30 03:31:07,355 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 208 GetRequests, 169 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2018-01-30 03:31:07,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-01-30 03:31:07,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 178. [2018-01-30 03:31:07,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178 states. [2018-01-30 03:31:07,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 180 transitions. [2018-01-30 03:31:07,356 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 180 transitions. Word has length 168 [2018-01-30 03:31:07,357 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:07,357 INFO L432 AbstractCegarLoop]: Abstraction has 178 states and 180 transitions. [2018-01-30 03:31:07,357 INFO L433 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-01-30 03:31:07,357 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 180 transitions. [2018-01-30 03:31:07,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2018-01-30 03:31:07,357 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:07,357 INFO L350 BasicCegarLoop]: trace histogram [40, 39, 39, 39, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:07,357 INFO L371 AbstractCegarLoop]: === Iteration 41 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:07,357 INFO L82 PathProgramCache]: Analyzing trace with hash -245261833, now seen corresponding path program 39 times [2018-01-30 03:31:07,357 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:07,357 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:07,358 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:07,358 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:07,358 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:07,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:07,363 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:07,836 INFO L134 CoverageAnalysis]: Checked inductivity of 3042 backedges. 0 proven. 3042 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:07,837 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:07,837 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:07,845 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 03:31:07,852 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,853 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,854 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,855 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,855 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,856 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,857 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,858 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,859 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,860 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,861 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,863 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,864 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,865 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,867 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,869 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,871 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,873 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,876 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,879 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,881 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,884 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,888 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,891 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,895 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,899 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,904 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,910 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,914 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,920 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,927 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,934 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,942 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,950 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,959 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,969 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,979 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:07,989 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:08,001 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:08,014 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:08,015 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:08,016 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:08,034 INFO L134 CoverageAnalysis]: Checked inductivity of 3042 backedges. 0 proven. 3042 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:08,051 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:08,051 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 42 [2018-01-30 03:31:08,051 INFO L409 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-01-30 03:31:08,051 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-01-30 03:31:08,052 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-01-30 03:31:08,052 INFO L87 Difference]: Start difference. First operand 178 states and 180 transitions. Second operand 42 states. [2018-01-30 03:31:08,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:08,155 INFO L93 Difference]: Finished difference Result 198 states and 202 transitions. [2018-01-30 03:31:08,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-01-30 03:31:08,156 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 172 [2018-01-30 03:31:08,156 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:08,156 INFO L225 Difference]: With dead ends: 198 [2018-01-30 03:31:08,156 INFO L226 Difference]: Without dead ends: 184 [2018-01-30 03:31:08,157 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 213 GetRequests, 173 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-01-30 03:31:08,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-01-30 03:31:08,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 182. [2018-01-30 03:31:08,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-01-30 03:31:08,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 184 transitions. [2018-01-30 03:31:08,159 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 184 transitions. Word has length 172 [2018-01-30 03:31:08,159 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:08,159 INFO L432 AbstractCegarLoop]: Abstraction has 182 states and 184 transitions. [2018-01-30 03:31:08,159 INFO L433 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-01-30 03:31:08,159 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 184 transitions. [2018-01-30 03:31:08,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2018-01-30 03:31:08,159 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:08,159 INFO L350 BasicCegarLoop]: trace histogram [41, 40, 40, 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:08,160 INFO L371 AbstractCegarLoop]: === Iteration 42 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:08,160 INFO L82 PathProgramCache]: Analyzing trace with hash -1150392292, now seen corresponding path program 40 times [2018-01-30 03:31:08,160 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:08,160 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:08,160 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:08,160 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:08,160 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:08,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:08,166 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:08,915 INFO L134 CoverageAnalysis]: Checked inductivity of 3200 backedges. 0 proven. 3200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:08,916 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:08,916 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:08,920 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 03:31:08,937 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:08,938 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:08,956 INFO L134 CoverageAnalysis]: Checked inductivity of 3200 backedges. 0 proven. 3200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:08,972 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:08,972 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 43 [2018-01-30 03:31:08,972 INFO L409 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-01-30 03:31:08,973 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-01-30 03:31:08,973 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2018-01-30 03:31:08,973 INFO L87 Difference]: Start difference. First operand 182 states and 184 transitions. Second operand 43 states. [2018-01-30 03:31:09,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:09,059 INFO L93 Difference]: Finished difference Result 202 states and 206 transitions. [2018-01-30 03:31:09,059 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-01-30 03:31:09,059 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 176 [2018-01-30 03:31:09,059 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:09,059 INFO L225 Difference]: With dead ends: 202 [2018-01-30 03:31:09,060 INFO L226 Difference]: Without dead ends: 188 [2018-01-30 03:31:09,060 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 218 GetRequests, 177 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2018-01-30 03:31:09,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-01-30 03:31:09,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 186. [2018-01-30 03:31:09,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-01-30 03:31:09,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 188 transitions. [2018-01-30 03:31:09,062 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 188 transitions. Word has length 176 [2018-01-30 03:31:09,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:09,062 INFO L432 AbstractCegarLoop]: Abstraction has 186 states and 188 transitions. [2018-01-30 03:31:09,062 INFO L433 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-01-30 03:31:09,062 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 188 transitions. [2018-01-30 03:31:09,063 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2018-01-30 03:31:09,063 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:09,063 INFO L350 BasicCegarLoop]: trace histogram [42, 41, 41, 41, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:09,063 INFO L371 AbstractCegarLoop]: === Iteration 43 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:09,063 INFO L82 PathProgramCache]: Analyzing trace with hash -127034431, now seen corresponding path program 41 times [2018-01-30 03:31:09,063 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:09,063 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:09,063 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:09,063 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:09,063 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:09,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:09,069 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:09,790 INFO L134 CoverageAnalysis]: Checked inductivity of 3362 backedges. 0 proven. 3362 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:09,790 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:09,790 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:09,809 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 03:31:09,813 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,820 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,829 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,838 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,848 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,852 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,853 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,854 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,855 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,857 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,858 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,860 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,862 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,864 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,866 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,869 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,872 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,875 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,878 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,882 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,886 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,891 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,896 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,901 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,908 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,915 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,923 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,932 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,941 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,952 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,963 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,976 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:09,990 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:10,005 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:10,022 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:10,040 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:10,059 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:10,081 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:10,104 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:10,129 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:10,156 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:10,185 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:10,186 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:10,188 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:10,215 INFO L134 CoverageAnalysis]: Checked inductivity of 3362 backedges. 0 proven. 3362 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:10,233 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:10,233 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 44 [2018-01-30 03:31:10,233 INFO L409 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-01-30 03:31:10,233 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-01-30 03:31:10,234 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-30 03:31:10,234 INFO L87 Difference]: Start difference. First operand 186 states and 188 transitions. Second operand 44 states. [2018-01-30 03:31:11,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:11,046 INFO L93 Difference]: Finished difference Result 206 states and 210 transitions. [2018-01-30 03:31:11,047 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-01-30 03:31:11,047 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 180 [2018-01-30 03:31:11,047 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:11,048 INFO L225 Difference]: With dead ends: 206 [2018-01-30 03:31:11,048 INFO L226 Difference]: Without dead ends: 192 [2018-01-30 03:31:11,048 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 223 GetRequests, 181 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-30 03:31:11,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 192 states. [2018-01-30 03:31:11,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 192 to 190. [2018-01-30 03:31:11,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-01-30 03:31:11,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 192 transitions. [2018-01-30 03:31:11,051 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 192 transitions. Word has length 180 [2018-01-30 03:31:11,051 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:11,051 INFO L432 AbstractCegarLoop]: Abstraction has 190 states and 192 transitions. [2018-01-30 03:31:11,051 INFO L433 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-01-30 03:31:11,051 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 192 transitions. [2018-01-30 03:31:11,052 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2018-01-30 03:31:11,052 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:11,052 INFO L350 BasicCegarLoop]: trace histogram [43, 42, 42, 42, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:11,052 INFO L371 AbstractCegarLoop]: === Iteration 44 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:11,052 INFO L82 PathProgramCache]: Analyzing trace with hash 1974498534, now seen corresponding path program 42 times [2018-01-30 03:31:11,053 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:11,053 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:11,053 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:11,053 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:11,053 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:11,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:11,059 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:11,606 INFO L134 CoverageAnalysis]: Checked inductivity of 3528 backedges. 0 proven. 3528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:11,607 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:11,607 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:11,613 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 03:31:11,617 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,618 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,619 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,620 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,620 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,621 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,622 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,623 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,624 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,625 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,626 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,627 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,628 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,629 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,631 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,632 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,634 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,635 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,637 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,639 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,641 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,643 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,645 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,647 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,650 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,653 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,656 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,659 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,662 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,665 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,669 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,673 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,677 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,681 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,686 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,690 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,696 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,701 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,707 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,713 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,741 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,762 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,772 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:11,773 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:11,775 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:11,794 INFO L134 CoverageAnalysis]: Checked inductivity of 3528 backedges. 0 proven. 3528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:11,815 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:11,815 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45] total 45 [2018-01-30 03:31:11,815 INFO L409 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-01-30 03:31:11,815 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-01-30 03:31:11,816 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2018-01-30 03:31:11,816 INFO L87 Difference]: Start difference. First operand 190 states and 192 transitions. Second operand 45 states. [2018-01-30 03:31:11,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:11,926 INFO L93 Difference]: Finished difference Result 210 states and 214 transitions. [2018-01-30 03:31:11,927 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-01-30 03:31:11,927 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 184 [2018-01-30 03:31:11,927 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:11,927 INFO L225 Difference]: With dead ends: 210 [2018-01-30 03:31:11,927 INFO L226 Difference]: Without dead ends: 196 [2018-01-30 03:31:11,928 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 228 GetRequests, 185 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2018-01-30 03:31:11,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states. [2018-01-30 03:31:11,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 194. [2018-01-30 03:31:11,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194 states. [2018-01-30 03:31:11,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 196 transitions. [2018-01-30 03:31:11,930 INFO L78 Accepts]: Start accepts. Automaton has 194 states and 196 transitions. Word has length 184 [2018-01-30 03:31:11,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:11,931 INFO L432 AbstractCegarLoop]: Abstraction has 194 states and 196 transitions. [2018-01-30 03:31:11,931 INFO L433 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-01-30 03:31:11,931 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 196 transitions. [2018-01-30 03:31:11,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 189 [2018-01-30 03:31:11,932 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:11,932 INFO L350 BasicCegarLoop]: trace histogram [44, 43, 43, 43, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:11,932 INFO L371 AbstractCegarLoop]: === Iteration 45 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:11,932 INFO L82 PathProgramCache]: Analyzing trace with hash 1978151819, now seen corresponding path program 43 times [2018-01-30 03:31:11,933 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:11,933 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:11,933 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:11,933 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:11,933 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:11,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:11,939 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:12,523 INFO L134 CoverageAnalysis]: Checked inductivity of 3698 backedges. 0 proven. 3698 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:12,523 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:12,523 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:12,528 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:31:12,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:12,544 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:12,564 INFO L134 CoverageAnalysis]: Checked inductivity of 3698 backedges. 0 proven. 3698 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:12,581 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:12,581 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 46 [2018-01-30 03:31:12,581 INFO L409 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-01-30 03:31:12,581 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-01-30 03:31:12,582 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-30 03:31:12,582 INFO L87 Difference]: Start difference. First operand 194 states and 196 transitions. Second operand 46 states. [2018-01-30 03:31:12,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:12,670 INFO L93 Difference]: Finished difference Result 214 states and 218 transitions. [2018-01-30 03:31:12,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-01-30 03:31:12,670 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 188 [2018-01-30 03:31:12,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:12,671 INFO L225 Difference]: With dead ends: 214 [2018-01-30 03:31:12,671 INFO L226 Difference]: Without dead ends: 200 [2018-01-30 03:31:12,671 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 233 GetRequests, 189 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-30 03:31:12,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states. [2018-01-30 03:31:12,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 198. [2018-01-30 03:31:12,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 198 states. [2018-01-30 03:31:12,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 200 transitions. [2018-01-30 03:31:12,673 INFO L78 Accepts]: Start accepts. Automaton has 198 states and 200 transitions. Word has length 188 [2018-01-30 03:31:12,673 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:12,673 INFO L432 AbstractCegarLoop]: Abstraction has 198 states and 200 transitions. [2018-01-30 03:31:12,673 INFO L433 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-01-30 03:31:12,673 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 200 transitions. [2018-01-30 03:31:12,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 193 [2018-01-30 03:31:12,674 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:12,674 INFO L350 BasicCegarLoop]: trace histogram [45, 44, 44, 44, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:12,674 INFO L371 AbstractCegarLoop]: === Iteration 46 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:12,674 INFO L82 PathProgramCache]: Analyzing trace with hash 19273648, now seen corresponding path program 44 times [2018-01-30 03:31:12,674 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:12,674 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:12,674 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:12,674 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:31:12,674 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:12,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:12,680 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:13,405 INFO L134 CoverageAnalysis]: Checked inductivity of 3872 backedges. 0 proven. 3872 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:13,405 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:13,405 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:13,409 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 03:31:13,414 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:13,423 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:13,425 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:13,427 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:13,468 INFO L134 CoverageAnalysis]: Checked inductivity of 3872 backedges. 0 proven. 3872 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:13,484 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:13,485 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47] total 47 [2018-01-30 03:31:13,485 INFO L409 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-01-30 03:31:13,485 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-01-30 03:31:13,485 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2018-01-30 03:31:13,485 INFO L87 Difference]: Start difference. First operand 198 states and 200 transitions. Second operand 47 states. [2018-01-30 03:31:13,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:13,595 INFO L93 Difference]: Finished difference Result 218 states and 222 transitions. [2018-01-30 03:31:13,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-01-30 03:31:13,595 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 192 [2018-01-30 03:31:13,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:13,595 INFO L225 Difference]: With dead ends: 218 [2018-01-30 03:31:13,596 INFO L226 Difference]: Without dead ends: 204 [2018-01-30 03:31:13,596 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 193 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2018-01-30 03:31:13,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states. [2018-01-30 03:31:13,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 202. [2018-01-30 03:31:13,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202 states. [2018-01-30 03:31:13,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202 states to 202 states and 204 transitions. [2018-01-30 03:31:13,598 INFO L78 Accepts]: Start accepts. Automaton has 202 states and 204 transitions. Word has length 192 [2018-01-30 03:31:13,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:13,598 INFO L432 AbstractCegarLoop]: Abstraction has 202 states and 204 transitions. [2018-01-30 03:31:13,598 INFO L433 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-01-30 03:31:13,598 INFO L276 IsEmpty]: Start isEmpty. Operand 202 states and 204 transitions. [2018-01-30 03:31:13,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 197 [2018-01-30 03:31:13,598 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:13,599 INFO L350 BasicCegarLoop]: trace histogram [46, 45, 45, 45, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:13,599 INFO L371 AbstractCegarLoop]: === Iteration 47 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:13,599 INFO L82 PathProgramCache]: Analyzing trace with hash 886792533, now seen corresponding path program 45 times [2018-01-30 03:31:13,599 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:13,599 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:13,599 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:13,599 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:13,599 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:13,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:13,609 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:14,326 INFO L134 CoverageAnalysis]: Checked inductivity of 4050 backedges. 0 proven. 4050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:14,327 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:14,327 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:14,332 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 03:31:14,336 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,337 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,338 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,339 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,339 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,340 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,341 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,342 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,343 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,344 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,345 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,347 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,348 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,350 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,352 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,354 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,355 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,358 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,360 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,363 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,365 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,368 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,372 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,376 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,379 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,384 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,388 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,393 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,399 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,405 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,411 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,419 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,426 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,434 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,443 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,453 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,463 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,474 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,486 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,499 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,511 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,526 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,542 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,559 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,576 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,595 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:14,596 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:14,598 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:14,619 INFO L134 CoverageAnalysis]: Checked inductivity of 4050 backedges. 0 proven. 4050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:14,636 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:14,636 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48] total 48 [2018-01-30 03:31:14,637 INFO L409 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-01-30 03:31:14,637 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-01-30 03:31:14,637 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-01-30 03:31:14,637 INFO L87 Difference]: Start difference. First operand 202 states and 204 transitions. Second operand 48 states. [2018-01-30 03:31:14,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:14,809 INFO L93 Difference]: Finished difference Result 222 states and 226 transitions. [2018-01-30 03:31:14,809 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-01-30 03:31:14,809 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 196 [2018-01-30 03:31:14,810 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:14,810 INFO L225 Difference]: With dead ends: 222 [2018-01-30 03:31:14,810 INFO L226 Difference]: Without dead ends: 208 [2018-01-30 03:31:14,810 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 243 GetRequests, 197 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-01-30 03:31:14,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states. [2018-01-30 03:31:14,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 206. [2018-01-30 03:31:14,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-01-30 03:31:14,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 208 transitions. [2018-01-30 03:31:14,812 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 208 transitions. Word has length 196 [2018-01-30 03:31:14,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:14,812 INFO L432 AbstractCegarLoop]: Abstraction has 206 states and 208 transitions. [2018-01-30 03:31:14,813 INFO L433 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-01-30 03:31:14,813 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 208 transitions. [2018-01-30 03:31:14,813 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2018-01-30 03:31:14,813 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:14,813 INFO L350 BasicCegarLoop]: trace histogram [47, 46, 46, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:14,813 INFO L371 AbstractCegarLoop]: === Iteration 48 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:14,813 INFO L82 PathProgramCache]: Analyzing trace with hash -1814474630, now seen corresponding path program 46 times [2018-01-30 03:31:14,813 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:14,813 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:14,814 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:14,814 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:14,814 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:14,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:14,819 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:15,452 INFO L134 CoverageAnalysis]: Checked inductivity of 4232 backedges. 0 proven. 4232 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:15,452 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:15,452 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:15,457 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 03:31:15,485 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:15,487 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:15,522 INFO L134 CoverageAnalysis]: Checked inductivity of 4232 backedges. 0 proven. 4232 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:15,539 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:15,539 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 49 [2018-01-30 03:31:15,540 INFO L409 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-01-30 03:31:15,540 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-01-30 03:31:15,540 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2018-01-30 03:31:15,540 INFO L87 Difference]: Start difference. First operand 206 states and 208 transitions. Second operand 49 states. [2018-01-30 03:31:15,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:15,881 INFO L93 Difference]: Finished difference Result 226 states and 230 transitions. [2018-01-30 03:31:15,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-01-30 03:31:15,881 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 200 [2018-01-30 03:31:15,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:15,882 INFO L225 Difference]: With dead ends: 226 [2018-01-30 03:31:15,882 INFO L226 Difference]: Without dead ends: 212 [2018-01-30 03:31:15,882 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 248 GetRequests, 201 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2018-01-30 03:31:15,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states. [2018-01-30 03:31:15,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 210. [2018-01-30 03:31:15,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 210 states. [2018-01-30 03:31:15,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 212 transitions. [2018-01-30 03:31:15,885 INFO L78 Accepts]: Start accepts. Automaton has 210 states and 212 transitions. Word has length 200 [2018-01-30 03:31:15,885 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:15,886 INFO L432 AbstractCegarLoop]: Abstraction has 210 states and 212 transitions. [2018-01-30 03:31:15,886 INFO L433 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-01-30 03:31:15,886 INFO L276 IsEmpty]: Start isEmpty. Operand 210 states and 212 transitions. [2018-01-30 03:31:15,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 205 [2018-01-30 03:31:15,886 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:15,886 INFO L350 BasicCegarLoop]: trace histogram [48, 47, 47, 47, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:15,886 INFO L371 AbstractCegarLoop]: === Iteration 49 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:15,887 INFO L82 PathProgramCache]: Analyzing trace with hash 1448158495, now seen corresponding path program 47 times [2018-01-30 03:31:15,887 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:15,887 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:15,887 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:15,887 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:15,887 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:15,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:15,893 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:16,559 INFO L134 CoverageAnalysis]: Checked inductivity of 4418 backedges. 0 proven. 4418 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:16,559 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:16,559 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:16,563 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 03:31:16,568 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,568 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,569 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,570 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,570 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,571 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,572 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,573 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,574 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,575 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,577 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,578 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,580 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,582 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,585 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,587 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,590 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,593 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,596 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,600 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,604 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,609 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,614 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,619 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,626 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,633 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,641 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,652 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,661 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,672 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,683 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,695 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,709 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,724 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,740 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,757 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,777 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,798 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,821 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,846 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,873 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,901 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,931 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,963 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:16,998 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:17,035 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:17,074 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:17,117 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:17,118 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:17,121 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:17,149 INFO L134 CoverageAnalysis]: Checked inductivity of 4418 backedges. 0 proven. 4418 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:17,167 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:17,167 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 50 [2018-01-30 03:31:17,167 INFO L409 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-01-30 03:31:17,167 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-01-30 03:31:17,168 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-30 03:31:17,168 INFO L87 Difference]: Start difference. First operand 210 states and 212 transitions. Second operand 50 states. [2018-01-30 03:31:17,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:17,295 INFO L93 Difference]: Finished difference Result 230 states and 234 transitions. [2018-01-30 03:31:17,295 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-01-30 03:31:17,295 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 204 [2018-01-30 03:31:17,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:17,296 INFO L225 Difference]: With dead ends: 230 [2018-01-30 03:31:17,296 INFO L226 Difference]: Without dead ends: 216 [2018-01-30 03:31:17,296 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 253 GetRequests, 205 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-30 03:31:17,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-01-30 03:31:17,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 214. [2018-01-30 03:31:17,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-01-30 03:31:17,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 216 transitions. [2018-01-30 03:31:17,298 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 216 transitions. Word has length 204 [2018-01-30 03:31:17,298 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:17,298 INFO L432 AbstractCegarLoop]: Abstraction has 214 states and 216 transitions. [2018-01-30 03:31:17,298 INFO L433 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-01-30 03:31:17,298 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 216 transitions. [2018-01-30 03:31:17,299 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 209 [2018-01-30 03:31:17,299 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:17,299 INFO L350 BasicCegarLoop]: trace histogram [49, 48, 48, 48, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:17,299 INFO L371 AbstractCegarLoop]: === Iteration 50 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:17,299 INFO L82 PathProgramCache]: Analyzing trace with hash -1177280700, now seen corresponding path program 48 times [2018-01-30 03:31:17,299 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:17,299 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:17,299 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:17,299 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:17,300 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:17,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:17,305 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:18,030 INFO L134 CoverageAnalysis]: Checked inductivity of 4608 backedges. 0 proven. 4608 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:18,030 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:18,030 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:18,035 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 03:31:18,040 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,040 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,041 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,045 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,046 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,046 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,047 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,048 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,049 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,050 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,051 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,052 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,053 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,055 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,056 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,058 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,059 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,062 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,063 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,065 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,067 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,069 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,072 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,074 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,076 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,079 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,082 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,085 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,089 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,092 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,096 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,100 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,104 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,108 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,112 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,118 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,124 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,132 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,139 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,145 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,152 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,160 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,167 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,175 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,183 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,191 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,201 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,223 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,241 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:18,242 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:18,244 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:18,274 INFO L134 CoverageAnalysis]: Checked inductivity of 4608 backedges. 0 proven. 4608 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:18,291 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:18,292 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51] total 51 [2018-01-30 03:31:18,292 INFO L409 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-01-30 03:31:18,292 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-01-30 03:31:18,292 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2018-01-30 03:31:18,292 INFO L87 Difference]: Start difference. First operand 214 states and 216 transitions. Second operand 51 states. [2018-01-30 03:31:18,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:18,602 INFO L93 Difference]: Finished difference Result 234 states and 238 transitions. [2018-01-30 03:31:18,602 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-01-30 03:31:18,602 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 208 [2018-01-30 03:31:18,602 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:18,602 INFO L225 Difference]: With dead ends: 234 [2018-01-30 03:31:18,603 INFO L226 Difference]: Without dead ends: 220 [2018-01-30 03:31:18,603 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 258 GetRequests, 209 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2018-01-30 03:31:18,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-01-30 03:31:18,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 218. [2018-01-30 03:31:18,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 218 states. [2018-01-30 03:31:18,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 220 transitions. [2018-01-30 03:31:18,605 INFO L78 Accepts]: Start accepts. Automaton has 218 states and 220 transitions. Word has length 208 [2018-01-30 03:31:18,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:18,606 INFO L432 AbstractCegarLoop]: Abstraction has 218 states and 220 transitions. [2018-01-30 03:31:18,606 INFO L433 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-01-30 03:31:18,606 INFO L276 IsEmpty]: Start isEmpty. Operand 218 states and 220 transitions. [2018-01-30 03:31:18,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 213 [2018-01-30 03:31:18,606 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:18,606 INFO L350 BasicCegarLoop]: trace histogram [50, 49, 49, 49, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:18,607 INFO L371 AbstractCegarLoop]: === Iteration 51 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:18,607 INFO L82 PathProgramCache]: Analyzing trace with hash 1364426473, now seen corresponding path program 49 times [2018-01-30 03:31:18,607 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:18,607 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:18,607 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:18,607 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:18,607 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:18,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:18,619 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:19,401 INFO L134 CoverageAnalysis]: Checked inductivity of 4802 backedges. 0 proven. 4802 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:19,401 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:19,401 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:19,405 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:31:19,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:19,423 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:19,447 INFO L134 CoverageAnalysis]: Checked inductivity of 4802 backedges. 0 proven. 4802 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:19,463 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:19,463 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52] total 52 [2018-01-30 03:31:19,464 INFO L409 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-01-30 03:31:19,464 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-01-30 03:31:19,464 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-30 03:31:19,464 INFO L87 Difference]: Start difference. First operand 218 states and 220 transitions. Second operand 52 states. [2018-01-30 03:31:19,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:19,603 INFO L93 Difference]: Finished difference Result 238 states and 242 transitions. [2018-01-30 03:31:19,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-01-30 03:31:19,603 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 212 [2018-01-30 03:31:19,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:19,604 INFO L225 Difference]: With dead ends: 238 [2018-01-30 03:31:19,604 INFO L226 Difference]: Without dead ends: 224 [2018-01-30 03:31:19,604 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 263 GetRequests, 213 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-30 03:31:19,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-01-30 03:31:19,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 222. [2018-01-30 03:31:19,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222 states. [2018-01-30 03:31:19,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 224 transitions. [2018-01-30 03:31:19,606 INFO L78 Accepts]: Start accepts. Automaton has 222 states and 224 transitions. Word has length 212 [2018-01-30 03:31:19,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:19,606 INFO L432 AbstractCegarLoop]: Abstraction has 222 states and 224 transitions. [2018-01-30 03:31:19,606 INFO L433 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-01-30 03:31:19,606 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 224 transitions. [2018-01-30 03:31:19,607 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 217 [2018-01-30 03:31:19,607 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:19,607 INFO L350 BasicCegarLoop]: trace histogram [51, 50, 50, 50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:19,607 INFO L371 AbstractCegarLoop]: === Iteration 52 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:19,607 INFO L82 PathProgramCache]: Analyzing trace with hash 1428194318, now seen corresponding path program 50 times [2018-01-30 03:31:19,607 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:19,607 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:19,607 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:19,607 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:31:19,608 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:19,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:19,614 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:20,502 INFO L134 CoverageAnalysis]: Checked inductivity of 5000 backedges. 0 proven. 5000 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:20,502 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:20,502 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:20,507 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 03:31:20,513 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:20,524 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:20,526 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:20,528 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:20,552 INFO L134 CoverageAnalysis]: Checked inductivity of 5000 backedges. 0 proven. 5000 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:20,569 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:20,569 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53] total 53 [2018-01-30 03:31:20,569 INFO L409 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-01-30 03:31:20,569 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-01-30 03:31:20,570 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1378, Invalid=1378, Unknown=0, NotChecked=0, Total=2756 [2018-01-30 03:31:20,570 INFO L87 Difference]: Start difference. First operand 222 states and 224 transitions. Second operand 53 states. [2018-01-30 03:31:20,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:20,694 INFO L93 Difference]: Finished difference Result 242 states and 246 transitions. [2018-01-30 03:31:20,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-01-30 03:31:20,695 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 216 [2018-01-30 03:31:20,695 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:20,695 INFO L225 Difference]: With dead ends: 242 [2018-01-30 03:31:20,695 INFO L226 Difference]: Without dead ends: 228 [2018-01-30 03:31:20,696 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 268 GetRequests, 217 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1378, Invalid=1378, Unknown=0, NotChecked=0, Total=2756 [2018-01-30 03:31:20,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states. [2018-01-30 03:31:20,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 226. [2018-01-30 03:31:20,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-01-30 03:31:20,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 228 transitions. [2018-01-30 03:31:20,698 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 228 transitions. Word has length 216 [2018-01-30 03:31:20,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:20,698 INFO L432 AbstractCegarLoop]: Abstraction has 226 states and 228 transitions. [2018-01-30 03:31:20,698 INFO L433 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-01-30 03:31:20,698 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 228 transitions. [2018-01-30 03:31:20,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 221 [2018-01-30 03:31:20,698 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:20,698 INFO L350 BasicCegarLoop]: trace histogram [52, 51, 51, 51, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:20,699 INFO L371 AbstractCegarLoop]: === Iteration 53 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:20,699 INFO L82 PathProgramCache]: Analyzing trace with hash -219386189, now seen corresponding path program 51 times [2018-01-30 03:31:20,699 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:20,699 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:20,699 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:20,699 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:20,699 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:20,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:20,705 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:21,473 INFO L134 CoverageAnalysis]: Checked inductivity of 5202 backedges. 0 proven. 5202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:21,474 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:21,474 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:21,478 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 03:31:21,483 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,484 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,485 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,486 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,486 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,487 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,488 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,489 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,490 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,491 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,492 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,494 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,495 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,496 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,498 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,500 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,502 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,504 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,507 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,509 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,512 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,515 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,518 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,522 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,526 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,530 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,535 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,540 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,545 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,551 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,557 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,565 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,572 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,581 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,589 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,599 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,609 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,620 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,632 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,645 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,658 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,673 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,688 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,705 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,723 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,741 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,762 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,784 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,807 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,832 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,858 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,886 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:21,887 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:21,889 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:21,915 INFO L134 CoverageAnalysis]: Checked inductivity of 5202 backedges. 0 proven. 5202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:21,935 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:21,935 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54] total 54 [2018-01-30 03:31:21,935 INFO L409 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-01-30 03:31:21,935 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-01-30 03:31:21,936 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-01-30 03:31:21,936 INFO L87 Difference]: Start difference. First operand 226 states and 228 transitions. Second operand 54 states. [2018-01-30 03:31:22,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:22,081 INFO L93 Difference]: Finished difference Result 246 states and 250 transitions. [2018-01-30 03:31:22,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-01-30 03:31:22,081 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 220 [2018-01-30 03:31:22,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:22,082 INFO L225 Difference]: With dead ends: 246 [2018-01-30 03:31:22,082 INFO L226 Difference]: Without dead ends: 232 [2018-01-30 03:31:22,082 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 273 GetRequests, 221 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-01-30 03:31:22,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232 states. [2018-01-30 03:31:22,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232 to 230. [2018-01-30 03:31:22,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-01-30 03:31:22,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 232 transitions. [2018-01-30 03:31:22,084 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 232 transitions. Word has length 220 [2018-01-30 03:31:22,084 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:22,084 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 232 transitions. [2018-01-30 03:31:22,084 INFO L433 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-01-30 03:31:22,084 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 232 transitions. [2018-01-30 03:31:22,085 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 225 [2018-01-30 03:31:22,085 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:22,085 INFO L350 BasicCegarLoop]: trace histogram [53, 52, 52, 52, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:22,085 INFO L371 AbstractCegarLoop]: === Iteration 54 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:22,085 INFO L82 PathProgramCache]: Analyzing trace with hash -1647804712, now seen corresponding path program 52 times [2018-01-30 03:31:22,085 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:22,085 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:22,086 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:22,086 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:22,086 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:22,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:22,092 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:23,013 INFO L134 CoverageAnalysis]: Checked inductivity of 5408 backedges. 0 proven. 5408 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:23,013 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:23,014 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:23,018 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 03:31:23,036 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:23,038 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:23,072 INFO L134 CoverageAnalysis]: Checked inductivity of 5408 backedges. 0 proven. 5408 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:23,089 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:23,089 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55] total 55 [2018-01-30 03:31:23,089 INFO L409 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-01-30 03:31:23,089 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-01-30 03:31:23,089 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1485, Invalid=1485, Unknown=0, NotChecked=0, Total=2970 [2018-01-30 03:31:23,090 INFO L87 Difference]: Start difference. First operand 230 states and 232 transitions. Second operand 55 states. [2018-01-30 03:31:24,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:24,458 INFO L93 Difference]: Finished difference Result 250 states and 254 transitions. [2018-01-30 03:31:24,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-01-30 03:31:24,458 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 224 [2018-01-30 03:31:24,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:24,459 INFO L225 Difference]: With dead ends: 250 [2018-01-30 03:31:24,459 INFO L226 Difference]: Without dead ends: 236 [2018-01-30 03:31:24,459 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 278 GetRequests, 225 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1485, Invalid=1485, Unknown=0, NotChecked=0, Total=2970 [2018-01-30 03:31:24,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-01-30 03:31:24,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 234. [2018-01-30 03:31:24,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234 states. [2018-01-30 03:31:24,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234 states to 234 states and 236 transitions. [2018-01-30 03:31:24,461 INFO L78 Accepts]: Start accepts. Automaton has 234 states and 236 transitions. Word has length 224 [2018-01-30 03:31:24,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:24,461 INFO L432 AbstractCegarLoop]: Abstraction has 234 states and 236 transitions. [2018-01-30 03:31:24,461 INFO L433 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-01-30 03:31:24,461 INFO L276 IsEmpty]: Start isEmpty. Operand 234 states and 236 transitions. [2018-01-30 03:31:24,462 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 229 [2018-01-30 03:31:24,462 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:24,462 INFO L350 BasicCegarLoop]: trace histogram [54, 53, 53, 53, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:24,462 INFO L371 AbstractCegarLoop]: === Iteration 55 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:24,462 INFO L82 PathProgramCache]: Analyzing trace with hash 1579545725, now seen corresponding path program 53 times [2018-01-30 03:31:24,462 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:24,462 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:24,463 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:24,463 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:24,463 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:24,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:24,469 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:25,297 INFO L134 CoverageAnalysis]: Checked inductivity of 5618 backedges. 0 proven. 5618 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:25,298 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:25,298 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:25,302 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 03:31:25,307 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,308 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,309 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,310 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,310 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,311 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,312 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,313 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,314 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,315 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,317 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,318 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,320 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,322 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,324 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,327 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,329 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,332 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,336 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,339 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,343 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,348 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,353 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,359 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,365 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,372 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,380 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,389 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,399 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,409 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,420 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,433 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,447 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,462 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,478 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,496 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,516 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,537 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,561 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,586 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,613 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,642 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,671 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,703 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,738 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,775 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,815 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,858 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,905 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:25,953 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:26,004 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:26,060 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:26,119 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:26,183 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:26,185 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:26,188 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:26,214 INFO L134 CoverageAnalysis]: Checked inductivity of 5618 backedges. 0 proven. 5618 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:26,233 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:26,233 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 56] total 56 [2018-01-30 03:31:26,233 INFO L409 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-01-30 03:31:26,233 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-01-30 03:31:26,233 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-30 03:31:26,233 INFO L87 Difference]: Start difference. First operand 234 states and 236 transitions. Second operand 56 states. [2018-01-30 03:31:26,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:26,356 INFO L93 Difference]: Finished difference Result 254 states and 258 transitions. [2018-01-30 03:31:26,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-01-30 03:31:26,356 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 228 [2018-01-30 03:31:26,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:26,357 INFO L225 Difference]: With dead ends: 254 [2018-01-30 03:31:26,357 INFO L226 Difference]: Without dead ends: 240 [2018-01-30 03:31:26,357 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 283 GetRequests, 229 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-30 03:31:26,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240 states. [2018-01-30 03:31:26,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240 to 238. [2018-01-30 03:31:26,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-01-30 03:31:26,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 240 transitions. [2018-01-30 03:31:26,359 INFO L78 Accepts]: Start accepts. Automaton has 238 states and 240 transitions. Word has length 228 [2018-01-30 03:31:26,359 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:26,359 INFO L432 AbstractCegarLoop]: Abstraction has 238 states and 240 transitions. [2018-01-30 03:31:26,360 INFO L433 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-01-30 03:31:26,360 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 240 transitions. [2018-01-30 03:31:26,360 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 233 [2018-01-30 03:31:26,360 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:26,360 INFO L350 BasicCegarLoop]: trace histogram [55, 54, 54, 54, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:26,360 INFO L371 AbstractCegarLoop]: === Iteration 56 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:26,360 INFO L82 PathProgramCache]: Analyzing trace with hash 567676834, now seen corresponding path program 54 times [2018-01-30 03:31:26,360 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:26,360 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:26,361 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:26,361 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:26,361 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:26,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:26,367 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:27,310 INFO L134 CoverageAnalysis]: Checked inductivity of 5832 backedges. 0 proven. 5832 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:27,311 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:27,311 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:27,316 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 03:31:27,326 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,344 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,345 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,345 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,346 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,347 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,347 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,348 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,349 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,350 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,351 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,352 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,353 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,354 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,356 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,357 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,359 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,360 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,362 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,364 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,366 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,368 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,370 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,372 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,375 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,377 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,380 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,383 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,387 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,390 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,394 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,397 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,401 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,406 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,410 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,415 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,420 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,426 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,432 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,437 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,444 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,451 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,459 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,466 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,474 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,482 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,491 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,500 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,511 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,521 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,532 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,544 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,557 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,569 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,617 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:27,618 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:27,621 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:27,650 INFO L134 CoverageAnalysis]: Checked inductivity of 5832 backedges. 0 proven. 5832 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:27,668 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:27,668 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57] total 57 [2018-01-30 03:31:27,668 INFO L409 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-01-30 03:31:27,668 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-01-30 03:31:27,669 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1596, Invalid=1596, Unknown=0, NotChecked=0, Total=3192 [2018-01-30 03:31:27,669 INFO L87 Difference]: Start difference. First operand 238 states and 240 transitions. Second operand 57 states. [2018-01-30 03:31:27,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:27,815 INFO L93 Difference]: Finished difference Result 258 states and 262 transitions. [2018-01-30 03:31:27,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-01-30 03:31:27,816 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 232 [2018-01-30 03:31:27,816 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:27,816 INFO L225 Difference]: With dead ends: 258 [2018-01-30 03:31:27,816 INFO L226 Difference]: Without dead ends: 244 [2018-01-30 03:31:27,817 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 288 GetRequests, 233 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1596, Invalid=1596, Unknown=0, NotChecked=0, Total=3192 [2018-01-30 03:31:27,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 244 states. [2018-01-30 03:31:27,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 244 to 242. [2018-01-30 03:31:27,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 242 states. [2018-01-30 03:31:27,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242 states to 242 states and 244 transitions. [2018-01-30 03:31:27,819 INFO L78 Accepts]: Start accepts. Automaton has 242 states and 244 transitions. Word has length 232 [2018-01-30 03:31:27,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:27,819 INFO L432 AbstractCegarLoop]: Abstraction has 242 states and 244 transitions. [2018-01-30 03:31:27,819 INFO L433 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-01-30 03:31:27,819 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 244 transitions. [2018-01-30 03:31:27,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 237 [2018-01-30 03:31:27,820 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:27,820 INFO L350 BasicCegarLoop]: trace histogram [56, 55, 55, 55, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:27,820 INFO L371 AbstractCegarLoop]: === Iteration 57 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:27,820 INFO L82 PathProgramCache]: Analyzing trace with hash 201986119, now seen corresponding path program 55 times [2018-01-30 03:31:27,820 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:27,820 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:27,820 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:27,820 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:27,820 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:27,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:27,827 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:28,697 INFO L134 CoverageAnalysis]: Checked inductivity of 6050 backedges. 0 proven. 6050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:28,697 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:28,697 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:28,702 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:31:28,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:28,722 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:28,751 INFO L134 CoverageAnalysis]: Checked inductivity of 6050 backedges. 0 proven. 6050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:28,768 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:28,768 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 58] total 58 [2018-01-30 03:31:28,768 INFO L409 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-01-30 03:31:28,769 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-01-30 03:31:28,769 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-30 03:31:28,769 INFO L87 Difference]: Start difference. First operand 242 states and 244 transitions. Second operand 58 states. [2018-01-30 03:31:29,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:29,305 INFO L93 Difference]: Finished difference Result 262 states and 266 transitions. [2018-01-30 03:31:29,305 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-01-30 03:31:29,305 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 236 [2018-01-30 03:31:29,305 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:29,306 INFO L225 Difference]: With dead ends: 262 [2018-01-30 03:31:29,306 INFO L226 Difference]: Without dead ends: 248 [2018-01-30 03:31:29,306 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 293 GetRequests, 237 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-30 03:31:29,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248 states. [2018-01-30 03:31:29,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248 to 246. [2018-01-30 03:31:29,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 246 states. [2018-01-30 03:31:29,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 246 states to 246 states and 248 transitions. [2018-01-30 03:31:29,308 INFO L78 Accepts]: Start accepts. Automaton has 246 states and 248 transitions. Word has length 236 [2018-01-30 03:31:29,309 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:29,309 INFO L432 AbstractCegarLoop]: Abstraction has 246 states and 248 transitions. [2018-01-30 03:31:29,309 INFO L433 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-01-30 03:31:29,309 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 248 transitions. [2018-01-30 03:31:29,309 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 241 [2018-01-30 03:31:29,309 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:29,309 INFO L350 BasicCegarLoop]: trace histogram [57, 56, 56, 56, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:29,309 INFO L371 AbstractCegarLoop]: === Iteration 58 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:29,310 INFO L82 PathProgramCache]: Analyzing trace with hash -984402324, now seen corresponding path program 56 times [2018-01-30 03:31:29,310 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:29,310 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:29,310 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:29,310 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:31:29,310 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:29,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:29,317 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:30,225 INFO L134 CoverageAnalysis]: Checked inductivity of 6272 backedges. 0 proven. 6272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:30,226 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:30,226 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:30,231 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 03:31:30,237 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:30,248 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:30,250 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:30,252 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:30,281 INFO L134 CoverageAnalysis]: Checked inductivity of 6272 backedges. 0 proven. 6272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:30,297 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:30,297 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59] total 59 [2018-01-30 03:31:30,297 INFO L409 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-01-30 03:31:30,298 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-01-30 03:31:30,298 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1711, Invalid=1711, Unknown=0, NotChecked=0, Total=3422 [2018-01-30 03:31:30,298 INFO L87 Difference]: Start difference. First operand 246 states and 248 transitions. Second operand 59 states. [2018-01-30 03:31:30,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:30,528 INFO L93 Difference]: Finished difference Result 266 states and 270 transitions. [2018-01-30 03:31:30,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-01-30 03:31:30,528 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 240 [2018-01-30 03:31:30,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:30,529 INFO L225 Difference]: With dead ends: 266 [2018-01-30 03:31:30,529 INFO L226 Difference]: Without dead ends: 252 [2018-01-30 03:31:30,529 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 298 GetRequests, 241 SyntacticMatches, 0 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1711, Invalid=1711, Unknown=0, NotChecked=0, Total=3422 [2018-01-30 03:31:30,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252 states. [2018-01-30 03:31:30,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 252 to 250. [2018-01-30 03:31:30,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-01-30 03:31:30,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 252 transitions. [2018-01-30 03:31:30,531 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 252 transitions. Word has length 240 [2018-01-30 03:31:30,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:30,531 INFO L432 AbstractCegarLoop]: Abstraction has 250 states and 252 transitions. [2018-01-30 03:31:30,531 INFO L433 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-01-30 03:31:30,531 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 252 transitions. [2018-01-30 03:31:30,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 245 [2018-01-30 03:31:30,532 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:30,532 INFO L350 BasicCegarLoop]: trace histogram [58, 57, 57, 57, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:30,532 INFO L371 AbstractCegarLoop]: === Iteration 59 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:30,532 INFO L82 PathProgramCache]: Analyzing trace with hash -878525935, now seen corresponding path program 57 times [2018-01-30 03:31:30,532 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:30,532 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:30,533 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:30,533 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:30,533 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:30,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:30,540 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:31,496 INFO L134 CoverageAnalysis]: Checked inductivity of 6498 backedges. 0 proven. 6498 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:31,496 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:31,496 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:31,500 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 03:31:31,505 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,518 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,528 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,538 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,548 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,558 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,568 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,578 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,586 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,587 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,588 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,590 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,591 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,592 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,594 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,596 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,598 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,600 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,603 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,605 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,608 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,611 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,615 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,618 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,622 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,626 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,631 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,636 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,642 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,647 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,654 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,661 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,668 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,677 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,686 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,696 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,705 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,716 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,728 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,741 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,754 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,769 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,784 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,801 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,819 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,837 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,858 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,880 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,902 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,927 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,953 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:31,982 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:32,010 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:32,040 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:32,072 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:32,106 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:32,142 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:32,179 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:32,180 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:32,182 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:32,213 INFO L134 CoverageAnalysis]: Checked inductivity of 6498 backedges. 0 proven. 6498 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:32,231 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:32,232 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 60] total 60 [2018-01-30 03:31:32,232 INFO L409 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-01-30 03:31:32,232 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-01-30 03:31:32,232 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-01-30 03:31:32,232 INFO L87 Difference]: Start difference. First operand 250 states and 252 transitions. Second operand 60 states. [2018-01-30 03:31:32,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:32,411 INFO L93 Difference]: Finished difference Result 270 states and 274 transitions. [2018-01-30 03:31:32,411 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-01-30 03:31:32,411 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 244 [2018-01-30 03:31:32,411 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:32,412 INFO L225 Difference]: With dead ends: 270 [2018-01-30 03:31:32,412 INFO L226 Difference]: Without dead ends: 256 [2018-01-30 03:31:32,412 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 303 GetRequests, 245 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-01-30 03:31:32,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-01-30 03:31:32,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 254. [2018-01-30 03:31:32,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 254 states. [2018-01-30 03:31:32,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254 states to 254 states and 256 transitions. [2018-01-30 03:31:32,414 INFO L78 Accepts]: Start accepts. Automaton has 254 states and 256 transitions. Word has length 244 [2018-01-30 03:31:32,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:32,414 INFO L432 AbstractCegarLoop]: Abstraction has 254 states and 256 transitions. [2018-01-30 03:31:32,414 INFO L433 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-01-30 03:31:32,414 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 256 transitions. [2018-01-30 03:31:32,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 249 [2018-01-30 03:31:32,415 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:32,415 INFO L350 BasicCegarLoop]: trace histogram [59, 58, 58, 58, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:32,415 INFO L371 AbstractCegarLoop]: === Iteration 60 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:32,415 INFO L82 PathProgramCache]: Analyzing trace with hash -1035341002, now seen corresponding path program 58 times [2018-01-30 03:31:32,415 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:32,415 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:32,416 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:32,416 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:32,416 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:32,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:32,423 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:33,398 INFO L134 CoverageAnalysis]: Checked inductivity of 6728 backedges. 0 proven. 6728 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:33,399 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:33,399 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:33,405 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 03:31:33,424 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:33,426 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:33,457 INFO L134 CoverageAnalysis]: Checked inductivity of 6728 backedges. 0 proven. 6728 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:33,475 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:33,475 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61] total 61 [2018-01-30 03:31:33,475 INFO L409 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-01-30 03:31:33,475 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-01-30 03:31:33,476 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1830, Invalid=1830, Unknown=0, NotChecked=0, Total=3660 [2018-01-30 03:31:33,476 INFO L87 Difference]: Start difference. First operand 254 states and 256 transitions. Second operand 61 states. [2018-01-30 03:31:33,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:33,616 INFO L93 Difference]: Finished difference Result 274 states and 278 transitions. [2018-01-30 03:31:33,616 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-01-30 03:31:33,616 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 248 [2018-01-30 03:31:33,616 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:33,617 INFO L225 Difference]: With dead ends: 274 [2018-01-30 03:31:33,617 INFO L226 Difference]: Without dead ends: 260 [2018-01-30 03:31:33,617 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 308 GetRequests, 249 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1830, Invalid=1830, Unknown=0, NotChecked=0, Total=3660 [2018-01-30 03:31:33,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 260 states. [2018-01-30 03:31:33,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 260 to 258. [2018-01-30 03:31:33,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 258 states. [2018-01-30 03:31:33,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 258 states to 258 states and 260 transitions. [2018-01-30 03:31:33,619 INFO L78 Accepts]: Start accepts. Automaton has 258 states and 260 transitions. Word has length 248 [2018-01-30 03:31:33,619 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:33,619 INFO L432 AbstractCegarLoop]: Abstraction has 258 states and 260 transitions. [2018-01-30 03:31:33,619 INFO L433 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-01-30 03:31:33,619 INFO L276 IsEmpty]: Start isEmpty. Operand 258 states and 260 transitions. [2018-01-30 03:31:33,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 253 [2018-01-30 03:31:33,620 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:33,620 INFO L350 BasicCegarLoop]: trace histogram [60, 59, 59, 59, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:33,620 INFO L371 AbstractCegarLoop]: === Iteration 61 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:33,620 INFO L82 PathProgramCache]: Analyzing trace with hash -1040578085, now seen corresponding path program 59 times [2018-01-30 03:31:33,620 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:33,620 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:33,621 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:33,621 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:33,621 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:33,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:33,628 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:34,648 INFO L134 CoverageAnalysis]: Checked inductivity of 6962 backedges. 0 proven. 6962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:34,648 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:34,648 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:34,653 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 03:31:34,657 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,657 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,658 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,659 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,659 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,660 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,661 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,662 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,663 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,665 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,666 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,667 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,669 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,671 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,673 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,676 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,678 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,681 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,685 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,688 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,692 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,697 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,702 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,708 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,714 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,721 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,729 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,737 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,747 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,757 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,768 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,780 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,794 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,809 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,825 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,843 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,862 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,883 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,907 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,932 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,958 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:34,986 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,016 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,048 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,082 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,119 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,159 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,202 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,247 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,296 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,347 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,402 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,461 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,523 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,590 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,660 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,735 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,812 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,894 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,979 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:35,980 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:35,983 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:36,019 INFO L134 CoverageAnalysis]: Checked inductivity of 6962 backedges. 0 proven. 6962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:36,039 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:36,039 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 62] total 62 [2018-01-30 03:31:36,039 INFO L409 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-01-30 03:31:36,040 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-01-30 03:31:36,040 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-30 03:31:36,040 INFO L87 Difference]: Start difference. First operand 258 states and 260 transitions. Second operand 62 states. [2018-01-30 03:31:36,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:36,205 INFO L93 Difference]: Finished difference Result 278 states and 282 transitions. [2018-01-30 03:31:36,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-01-30 03:31:36,206 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 252 [2018-01-30 03:31:36,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:36,206 INFO L225 Difference]: With dead ends: 278 [2018-01-30 03:31:36,206 INFO L226 Difference]: Without dead ends: 264 [2018-01-30 03:31:36,206 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 313 GetRequests, 253 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-30 03:31:36,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 264 states. [2018-01-30 03:31:36,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 264 to 262. [2018-01-30 03:31:36,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 262 states. [2018-01-30 03:31:36,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 264 transitions. [2018-01-30 03:31:36,208 INFO L78 Accepts]: Start accepts. Automaton has 262 states and 264 transitions. Word has length 252 [2018-01-30 03:31:36,209 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:36,209 INFO L432 AbstractCegarLoop]: Abstraction has 262 states and 264 transitions. [2018-01-30 03:31:36,209 INFO L433 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-01-30 03:31:36,209 INFO L276 IsEmpty]: Start isEmpty. Operand 262 states and 264 transitions. [2018-01-30 03:31:36,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 257 [2018-01-30 03:31:36,209 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:36,209 INFO L350 BasicCegarLoop]: trace histogram [61, 60, 60, 60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:36,209 INFO L371 AbstractCegarLoop]: === Iteration 62 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:36,210 INFO L82 PathProgramCache]: Analyzing trace with hash -1463532032, now seen corresponding path program 60 times [2018-01-30 03:31:36,210 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:36,210 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:36,210 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:36,210 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:36,210 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:36,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:36,218 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:37,225 INFO L134 CoverageAnalysis]: Checked inductivity of 7200 backedges. 0 proven. 7200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:37,225 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:37,226 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:37,230 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 03:31:37,236 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,237 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,237 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,238 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,239 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,239 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,240 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,241 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,242 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,243 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,243 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,245 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,246 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,247 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,248 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,250 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,251 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,253 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,255 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,256 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,259 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,261 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,263 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,265 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,268 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,270 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,273 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,276 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,280 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,283 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,287 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,290 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,294 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,298 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,303 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,308 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,313 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,319 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,325 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,331 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,337 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,344 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,351 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,358 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,366 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,375 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,384 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,392 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,402 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,413 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,425 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,436 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,449 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,462 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,476 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,490 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,506 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,522 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,541 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,560 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,593 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:37,594 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:37,597 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:37,629 INFO L134 CoverageAnalysis]: Checked inductivity of 7200 backedges. 0 proven. 7200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:37,647 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:37,647 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 63] total 63 [2018-01-30 03:31:37,648 INFO L409 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-01-30 03:31:37,648 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-01-30 03:31:37,648 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1953, Invalid=1953, Unknown=0, NotChecked=0, Total=3906 [2018-01-30 03:31:37,648 INFO L87 Difference]: Start difference. First operand 262 states and 264 transitions. Second operand 63 states. [2018-01-30 03:31:37,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:37,787 INFO L93 Difference]: Finished difference Result 282 states and 286 transitions. [2018-01-30 03:31:37,788 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-01-30 03:31:37,788 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 256 [2018-01-30 03:31:37,788 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:37,788 INFO L225 Difference]: With dead ends: 282 [2018-01-30 03:31:37,788 INFO L226 Difference]: Without dead ends: 268 [2018-01-30 03:31:37,789 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 318 GetRequests, 257 SyntacticMatches, 0 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1953, Invalid=1953, Unknown=0, NotChecked=0, Total=3906 [2018-01-30 03:31:37,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 268 states. [2018-01-30 03:31:37,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 268 to 266. [2018-01-30 03:31:37,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 266 states. [2018-01-30 03:31:37,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 266 states to 266 states and 268 transitions. [2018-01-30 03:31:37,791 INFO L78 Accepts]: Start accepts. Automaton has 266 states and 268 transitions. Word has length 256 [2018-01-30 03:31:37,791 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:37,791 INFO L432 AbstractCegarLoop]: Abstraction has 266 states and 268 transitions. [2018-01-30 03:31:37,791 INFO L433 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-01-30 03:31:37,791 INFO L276 IsEmpty]: Start isEmpty. Operand 266 states and 268 transitions. [2018-01-30 03:31:37,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 261 [2018-01-30 03:31:37,791 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:37,792 INFO L350 BasicCegarLoop]: trace histogram [62, 61, 61, 61, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:37,792 INFO L371 AbstractCegarLoop]: === Iteration 63 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:37,792 INFO L82 PathProgramCache]: Analyzing trace with hash 1780082597, now seen corresponding path program 61 times [2018-01-30 03:31:37,792 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:37,792 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:37,792 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:37,792 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:37,792 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:37,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:37,800 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:38,833 INFO L134 CoverageAnalysis]: Checked inductivity of 7442 backedges. 0 proven. 7442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:38,833 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:38,833 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:38,839 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:31:38,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:38,859 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:38,903 INFO L134 CoverageAnalysis]: Checked inductivity of 7442 backedges. 0 proven. 7442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:38,920 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:38,920 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 64] total 64 [2018-01-30 03:31:38,920 INFO L409 AbstractCegarLoop]: Interpolant automaton has 64 states [2018-01-30 03:31:38,920 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2018-01-30 03:31:38,920 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-30 03:31:38,920 INFO L87 Difference]: Start difference. First operand 266 states and 268 transitions. Second operand 64 states. [2018-01-30 03:31:39,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:39,073 INFO L93 Difference]: Finished difference Result 286 states and 290 transitions. [2018-01-30 03:31:39,073 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2018-01-30 03:31:39,073 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 260 [2018-01-30 03:31:39,073 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:39,074 INFO L225 Difference]: With dead ends: 286 [2018-01-30 03:31:39,074 INFO L226 Difference]: Without dead ends: 272 [2018-01-30 03:31:39,074 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 323 GetRequests, 261 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-30 03:31:39,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272 states. [2018-01-30 03:31:39,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272 to 270. [2018-01-30 03:31:39,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2018-01-30 03:31:39,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 272 transitions. [2018-01-30 03:31:39,076 INFO L78 Accepts]: Start accepts. Automaton has 270 states and 272 transitions. Word has length 260 [2018-01-30 03:31:39,076 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:39,076 INFO L432 AbstractCegarLoop]: Abstraction has 270 states and 272 transitions. [2018-01-30 03:31:39,076 INFO L433 AbstractCegarLoop]: Interpolant automaton has 64 states. [2018-01-30 03:31:39,076 INFO L276 IsEmpty]: Start isEmpty. Operand 270 states and 272 transitions. [2018-01-30 03:31:39,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 265 [2018-01-30 03:31:39,077 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:39,077 INFO L350 BasicCegarLoop]: trace histogram [63, 62, 62, 62, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:39,077 INFO L371 AbstractCegarLoop]: === Iteration 64 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:39,077 INFO L82 PathProgramCache]: Analyzing trace with hash 1590439626, now seen corresponding path program 62 times [2018-01-30 03:31:39,077 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:39,077 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:39,078 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:39,078 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 03:31:39,078 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:39,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:39,096 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:40,258 INFO L134 CoverageAnalysis]: Checked inductivity of 7688 backedges. 0 proven. 7688 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:40,259 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:40,259 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:40,264 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 03:31:40,269 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:40,281 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:40,284 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:40,286 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:40,327 INFO L134 CoverageAnalysis]: Checked inductivity of 7688 backedges. 0 proven. 7688 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:40,346 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:40,346 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 65] total 65 [2018-01-30 03:31:40,346 INFO L409 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-01-30 03:31:40,347 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-01-30 03:31:40,347 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2080, Invalid=2080, Unknown=0, NotChecked=0, Total=4160 [2018-01-30 03:31:40,347 INFO L87 Difference]: Start difference. First operand 270 states and 272 transitions. Second operand 65 states. [2018-01-30 03:31:40,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:40,507 INFO L93 Difference]: Finished difference Result 290 states and 294 transitions. [2018-01-30 03:31:40,507 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-01-30 03:31:40,507 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 264 [2018-01-30 03:31:40,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:40,508 INFO L225 Difference]: With dead ends: 290 [2018-01-30 03:31:40,508 INFO L226 Difference]: Without dead ends: 276 [2018-01-30 03:31:40,508 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 328 GetRequests, 265 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2080, Invalid=2080, Unknown=0, NotChecked=0, Total=4160 [2018-01-30 03:31:40,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states. [2018-01-30 03:31:40,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 274. [2018-01-30 03:31:40,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 274 states. [2018-01-30 03:31:40,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 274 states to 274 states and 276 transitions. [2018-01-30 03:31:40,510 INFO L78 Accepts]: Start accepts. Automaton has 274 states and 276 transitions. Word has length 264 [2018-01-30 03:31:40,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:40,510 INFO L432 AbstractCegarLoop]: Abstraction has 274 states and 276 transitions. [2018-01-30 03:31:40,510 INFO L433 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-01-30 03:31:40,510 INFO L276 IsEmpty]: Start isEmpty. Operand 274 states and 276 transitions. [2018-01-30 03:31:40,511 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 269 [2018-01-30 03:31:40,511 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:40,513 INFO L350 BasicCegarLoop]: trace histogram [64, 63, 63, 63, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:40,513 INFO L371 AbstractCegarLoop]: === Iteration 65 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:40,513 INFO L82 PathProgramCache]: Analyzing trace with hash -1794352273, now seen corresponding path program 63 times [2018-01-30 03:31:40,513 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:40,513 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:40,513 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:40,513 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:40,513 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:40,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:40,532 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:41,674 INFO L134 CoverageAnalysis]: Checked inductivity of 7938 backedges. 0 proven. 7938 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:41,675 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:41,675 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:41,679 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 03:31:41,685 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,686 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,686 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,687 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,688 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,689 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,689 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,690 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,692 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,693 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,694 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,695 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,696 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,698 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,700 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,702 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,703 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,705 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,708 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,711 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,713 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,716 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,720 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,724 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,728 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,732 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,737 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,742 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,747 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,753 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,760 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,767 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,775 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,783 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,792 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,802 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,812 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,823 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,835 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,848 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,861 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,876 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,892 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,909 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,927 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,946 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,967 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:41,989 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,012 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,036 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,063 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,091 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,118 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,148 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,180 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,214 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,249 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,286 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,326 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,369 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,413 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,459 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,508 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,559 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 03:31:42,561 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:42,564 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:42,615 INFO L134 CoverageAnalysis]: Checked inductivity of 7938 backedges. 0 proven. 7938 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:42,633 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:42,633 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 66] total 66 [2018-01-30 03:31:42,634 INFO L409 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-01-30 03:31:42,634 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-01-30 03:31:42,634 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-01-30 03:31:42,634 INFO L87 Difference]: Start difference. First operand 274 states and 276 transitions. Second operand 66 states. [2018-01-30 03:31:42,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:42,802 INFO L93 Difference]: Finished difference Result 294 states and 298 transitions. [2018-01-30 03:31:42,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-01-30 03:31:42,802 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 268 [2018-01-30 03:31:42,802 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:42,803 INFO L225 Difference]: With dead ends: 294 [2018-01-30 03:31:42,803 INFO L226 Difference]: Without dead ends: 280 [2018-01-30 03:31:42,803 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 333 GetRequests, 269 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-01-30 03:31:42,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 280 states. [2018-01-30 03:31:42,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 280 to 278. [2018-01-30 03:31:42,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 278 states. [2018-01-30 03:31:42,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 278 states to 278 states and 280 transitions. [2018-01-30 03:31:42,805 INFO L78 Accepts]: Start accepts. Automaton has 278 states and 280 transitions. Word has length 268 [2018-01-30 03:31:42,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:42,805 INFO L432 AbstractCegarLoop]: Abstraction has 278 states and 280 transitions. [2018-01-30 03:31:42,805 INFO L433 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-01-30 03:31:42,805 INFO L276 IsEmpty]: Start isEmpty. Operand 278 states and 280 transitions. [2018-01-30 03:31:42,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 273 [2018-01-30 03:31:42,806 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:42,806 INFO L350 BasicCegarLoop]: trace histogram [65, 64, 64, 64, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:42,806 INFO L371 AbstractCegarLoop]: === Iteration 66 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:42,806 INFO L82 PathProgramCache]: Analyzing trace with hash 543927700, now seen corresponding path program 64 times [2018-01-30 03:31:42,806 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:42,806 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:42,807 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:42,807 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:42,807 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:42,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:42,815 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:43,992 INFO L134 CoverageAnalysis]: Checked inductivity of 8192 backedges. 0 proven. 8192 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:43,993 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:43,993 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:43,997 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 03:31:44,018 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:44,020 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:44,065 INFO L134 CoverageAnalysis]: Checked inductivity of 8192 backedges. 0 proven. 8192 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:44,083 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:44,083 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [67, 67] total 67 [2018-01-30 03:31:44,083 INFO L409 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-01-30 03:31:44,083 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-01-30 03:31:44,083 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2211, Invalid=2211, Unknown=0, NotChecked=0, Total=4422 [2018-01-30 03:31:44,084 INFO L87 Difference]: Start difference. First operand 278 states and 280 transitions. Second operand 67 states. [2018-01-30 03:31:44,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:44,287 INFO L93 Difference]: Finished difference Result 298 states and 302 transitions. [2018-01-30 03:31:44,287 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-01-30 03:31:44,287 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 272 [2018-01-30 03:31:44,287 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:44,288 INFO L225 Difference]: With dead ends: 298 [2018-01-30 03:31:44,288 INFO L226 Difference]: Without dead ends: 284 [2018-01-30 03:31:44,288 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 273 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2211, Invalid=2211, Unknown=0, NotChecked=0, Total=4422 [2018-01-30 03:31:44,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states. [2018-01-30 03:31:44,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 282. [2018-01-30 03:31:44,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 282 states. [2018-01-30 03:31:44,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 282 states to 282 states and 284 transitions. [2018-01-30 03:31:44,290 INFO L78 Accepts]: Start accepts. Automaton has 282 states and 284 transitions. Word has length 272 [2018-01-30 03:31:44,290 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:44,290 INFO L432 AbstractCegarLoop]: Abstraction has 282 states and 284 transitions. [2018-01-30 03:31:44,290 INFO L433 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-01-30 03:31:44,290 INFO L276 IsEmpty]: Start isEmpty. Operand 282 states and 284 transitions. [2018-01-30 03:31:44,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 277 [2018-01-30 03:31:44,291 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:44,291 INFO L350 BasicCegarLoop]: trace histogram [66, 65, 65, 65, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:44,291 INFO L371 AbstractCegarLoop]: === Iteration 67 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:44,291 INFO L82 PathProgramCache]: Analyzing trace with hash 1775985977, now seen corresponding path program 65 times [2018-01-30 03:31:44,291 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:44,291 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:44,292 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:44,292 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:44,292 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:44,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:44,300 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:45,466 INFO L134 CoverageAnalysis]: Checked inductivity of 8450 backedges. 0 proven. 8450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:45,466 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:45,466 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:45,470 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 03:31:45,475 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,476 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,476 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,477 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,478 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,479 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,480 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,481 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,482 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,483 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,485 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,486 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,488 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,490 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,492 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,495 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,497 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,500 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,504 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,508 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,512 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,522 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,527 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,533 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,539 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,546 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,554 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,563 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,572 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,583 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,594 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,606 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,620 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,635 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,651 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,669 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,688 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,710 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,733 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,758 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,785 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,813 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,842 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,874 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,909 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,946 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:45,985 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,028 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,074 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,122 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,173 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,228 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,287 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,348 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,415 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,486 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,562 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,641 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,723 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,808 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,897 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:46,990 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:47,089 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:47,192 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:47,301 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:47,414 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 03:31:47,417 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:47,421 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:47,457 INFO L134 CoverageAnalysis]: Checked inductivity of 8450 backedges. 0 proven. 8450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:47,477 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:47,477 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 68] total 68 [2018-01-30 03:31:47,477 INFO L409 AbstractCegarLoop]: Interpolant automaton has 68 states [2018-01-30 03:31:47,478 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2018-01-30 03:31:47,478 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-01-30 03:31:47,478 INFO L87 Difference]: Start difference. First operand 282 states and 284 transitions. Second operand 68 states. [2018-01-30 03:31:47,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:47,641 INFO L93 Difference]: Finished difference Result 302 states and 306 transitions. [2018-01-30 03:31:47,641 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-01-30 03:31:47,641 INFO L78 Accepts]: Start accepts. Automaton has 68 states. Word has length 276 [2018-01-30 03:31:47,641 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:47,642 INFO L225 Difference]: With dead ends: 302 [2018-01-30 03:31:47,642 INFO L226 Difference]: Without dead ends: 288 [2018-01-30 03:31:47,642 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 277 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-01-30 03:31:47,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states. [2018-01-30 03:31:47,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 286. [2018-01-30 03:31:47,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 286 states. [2018-01-30 03:31:47,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 286 states to 286 states and 288 transitions. [2018-01-30 03:31:47,644 INFO L78 Accepts]: Start accepts. Automaton has 286 states and 288 transitions. Word has length 276 [2018-01-30 03:31:47,644 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:47,644 INFO L432 AbstractCegarLoop]: Abstraction has 286 states and 288 transitions. [2018-01-30 03:31:47,644 INFO L433 AbstractCegarLoop]: Interpolant automaton has 68 states. [2018-01-30 03:31:47,644 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 288 transitions. [2018-01-30 03:31:47,645 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 281 [2018-01-30 03:31:47,645 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:47,645 INFO L350 BasicCegarLoop]: trace histogram [67, 66, 66, 66, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:47,645 INFO L371 AbstractCegarLoop]: === Iteration 68 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:47,645 INFO L82 PathProgramCache]: Analyzing trace with hash 2142028382, now seen corresponding path program 66 times [2018-01-30 03:31:47,645 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:47,645 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:47,646 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:47,646 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:47,646 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:47,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:47,654 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 03:31:48,856 INFO L134 CoverageAnalysis]: Checked inductivity of 8712 backedges. 0 proven. 8712 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:48,856 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 03:31:48,857 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 03:31:48,866 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 03:31:48,872 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,873 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,873 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,874 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,875 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,875 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,876 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,877 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,878 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,879 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,880 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,881 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,882 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,883 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,884 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,886 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,887 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,889 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,891 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,893 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,895 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,897 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,899 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,901 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,904 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,906 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,909 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,912 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,915 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,919 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,923 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,926 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,930 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,935 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,939 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,944 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,949 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,955 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,961 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,966 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,974 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,981 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,989 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:48,996 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,005 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,014 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,023 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,032 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,042 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,053 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,065 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,077 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,090 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,103 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,118 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,132 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,148 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,165 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,182 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,200 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,220 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,239 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,261 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,281 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,323 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,362 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,404 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 03:31:49,405 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 03:31:49,409 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 03:31:49,447 INFO L134 CoverageAnalysis]: Checked inductivity of 8712 backedges. 0 proven. 8712 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 03:31:49,465 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 03:31:49,465 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [69, 69] total 69 [2018-01-30 03:31:49,465 INFO L409 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-01-30 03:31:49,465 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-01-30 03:31:49,466 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2346, Invalid=2346, Unknown=0, NotChecked=0, Total=4692 [2018-01-30 03:31:49,466 INFO L87 Difference]: Start difference. First operand 286 states and 288 transitions. Second operand 69 states. [2018-01-30 03:31:49,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 03:31:49,595 INFO L93 Difference]: Finished difference Result 306 states and 310 transitions. [2018-01-30 03:31:49,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-01-30 03:31:49,595 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 280 [2018-01-30 03:31:49,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 03:31:49,596 INFO L225 Difference]: With dead ends: 306 [2018-01-30 03:31:49,596 INFO L226 Difference]: Without dead ends: 292 [2018-01-30 03:31:49,596 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 348 GetRequests, 281 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2346, Invalid=2346, Unknown=0, NotChecked=0, Total=4692 [2018-01-30 03:31:49,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 292 states. [2018-01-30 03:31:49,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 292 to 290. [2018-01-30 03:31:49,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 290 states. [2018-01-30 03:31:49,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 290 states to 290 states and 292 transitions. [2018-01-30 03:31:49,598 INFO L78 Accepts]: Start accepts. Automaton has 290 states and 292 transitions. Word has length 280 [2018-01-30 03:31:49,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 03:31:49,598 INFO L432 AbstractCegarLoop]: Abstraction has 290 states and 292 transitions. [2018-01-30 03:31:49,598 INFO L433 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-01-30 03:31:49,598 INFO L276 IsEmpty]: Start isEmpty. Operand 290 states and 292 transitions. [2018-01-30 03:31:49,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 285 [2018-01-30 03:31:49,599 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 03:31:49,599 INFO L350 BasicCegarLoop]: trace histogram [68, 67, 67, 67, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 03:31:49,599 INFO L371 AbstractCegarLoop]: === Iteration 69 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 03:31:49,599 INFO L82 PathProgramCache]: Analyzing trace with hash 1704002819, now seen corresponding path program 67 times [2018-01-30 03:31:49,599 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 03:31:49,599 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 03:31:49,600 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:49,600 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 03:31:49,600 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 03:31:49,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 03:31:49,609 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. Received shutdown request... [2018-01-30 03:31:50,346 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-30 03:31:50,350 WARN L185 ceAbstractionStarter]: Timeout [2018-01-30 03:31:50,350 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 30.01 03:31:50 BasicIcfg [2018-01-30 03:31:50,350 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-30 03:31:50,351 INFO L168 Benchmark]: Toolchain (without parser) took 65958.75 ms. Allocated memory was 151.0 MB in the beginning and 872.4 MB in the end (delta: 721.4 MB). Free memory was 116.0 MB in the beginning and 396.9 MB in the end (delta: -280.9 MB). Peak memory consumption was 440.5 MB. Max. memory is 5.3 GB. [2018-01-30 03:31:50,351 INFO L168 Benchmark]: CDTParser took 0.10 ms. Allocated memory is still 151.0 MB. Free memory is still 120.8 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-30 03:31:50,352 INFO L168 Benchmark]: CACSL2BoogieTranslator took 103.23 ms. Allocated memory is still 151.0 MB. Free memory was 115.8 MB in the beginning and 107.9 MB in the end (delta: 7.9 MB). Peak memory consumption was 7.9 MB. Max. memory is 5.3 GB. [2018-01-30 03:31:50,352 INFO L168 Benchmark]: Boogie Preprocessor took 17.27 ms. Allocated memory is still 151.0 MB. Free memory was 107.9 MB in the beginning and 106.3 MB in the end (delta: 1.6 MB). Peak memory consumption was 1.6 MB. Max. memory is 5.3 GB. [2018-01-30 03:31:50,352 INFO L168 Benchmark]: RCFGBuilder took 266.71 ms. Allocated memory is still 151.0 MB. Free memory was 106.3 MB in the beginning and 95.5 MB in the end (delta: 10.9 MB). Peak memory consumption was 10.9 MB. Max. memory is 5.3 GB. [2018-01-30 03:31:50,352 INFO L168 Benchmark]: IcfgTransformer took 11.28 ms. Allocated memory is still 151.0 MB. Free memory was 95.5 MB in the beginning and 94.3 MB in the end (delta: 1.2 MB). Peak memory consumption was 1.2 MB. Max. memory is 5.3 GB. [2018-01-30 03:31:50,352 INFO L168 Benchmark]: TraceAbstraction took 65557.69 ms. Allocated memory was 151.0 MB in the beginning and 872.4 MB in the end (delta: 721.4 MB). Free memory was 94.1 MB in the beginning and 396.9 MB in the end (delta: -302.8 MB). Peak memory consumption was 418.6 MB. Max. memory is 5.3 GB. [2018-01-30 03:31:50,353 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10 ms. Allocated memory is still 151.0 MB. Free memory is still 120.8 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 103.23 ms. Allocated memory is still 151.0 MB. Free memory was 115.8 MB in the beginning and 107.9 MB in the end (delta: 7.9 MB). Peak memory consumption was 7.9 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 17.27 ms. Allocated memory is still 151.0 MB. Free memory was 107.9 MB in the beginning and 106.3 MB in the end (delta: 1.6 MB). Peak memory consumption was 1.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 266.71 ms. Allocated memory is still 151.0 MB. Free memory was 106.3 MB in the beginning and 95.5 MB in the end (delta: 10.9 MB). Peak memory consumption was 10.9 MB. Max. memory is 5.3 GB. * IcfgTransformer took 11.28 ms. Allocated memory is still 151.0 MB. Free memory was 95.5 MB in the beginning and 94.3 MB in the end (delta: 1.2 MB). Peak memory consumption was 1.2 MB. Max. memory is 5.3 GB. * TraceAbstraction took 65557.69 ms. Allocated memory was 151.0 MB in the beginning and 872.4 MB in the end (delta: 721.4 MB). Free memory was 94.1 MB in the beginning and 396.9 MB in the end (delta: -302.8 MB). Peak memory consumption was 418.6 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 2]: Timeout (TraceAbstraction) Unable to prove that call of __VERIFIER_error() unreachable (line 2). Cancelled while BasicCegarLoop was analyzing trace of length 285 with TraceHistMax 68, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 46 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 29 locations, 1 error locations. TIMEOUT Result, 65.5s OverallTime, 69 OverallIterations, 68 TraceHistogramMax, 11.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1572 SDtfs, 4556 SDslu, 35798 SDs, 0 SdLazy, 8711 SolverSat, 100 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 9.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 12248 GetRequests, 9970 SyntacticMatches, 0 SemanticMatches, 2278 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 31.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=290occurred in iteration=68, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 68 MinimizatonAttempts, 134 StatesRemovedByMinimization, 67 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 10.9s SatisfiabilityAnalysisTime, 39.0s InterpolantComputationTime, 19831 NumberOfCodeBlocks, 19831 NumberOfCodeBlocksAsserted, 1300 NumberOfCheckSat, 19697 ConstructedInterpolants, 0 QuantifiedInterpolants, 10580149 SizeOfPredicates, 66 NumberOfNonLiveVariables, 12969 ConjunctsInSsa, 2343 ConjunctsInUnsatCore, 134 InterpolantComputations, 2 PerfectInterpolantSequences, 0/392084 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_init1_true-unreach-call_ground.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-Benchmark-0-2018-01-30_03-31-50-358.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_init1_true-unreach-call_ground.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-30_03-31-50-358.csv Completed graceful shutdown