java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/reducercommutativity/rangesum20_false-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-5f7ec6e-m [2018-01-31 10:12:27,568 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-31 10:12:27,569 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-31 10:12:27,578 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-31 10:12:27,578 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-31 10:12:27,578 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-31 10:12:27,579 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-31 10:12:27,580 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-31 10:12:27,581 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-31 10:12:27,582 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-31 10:12:27,582 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-31 10:12:27,582 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-31 10:12:27,583 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-31 10:12:27,583 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-31 10:12:27,584 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-31 10:12:27,585 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-31 10:12:27,586 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-31 10:12:27,587 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-31 10:12:27,588 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-31 10:12:27,588 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-31 10:12:27,590 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-31 10:12:27,590 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-31 10:12:27,590 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-31 10:12:27,590 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-31 10:12:27,591 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-31 10:12:27,592 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-31 10:12:27,592 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-31 10:12:27,592 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-31 10:12:27,592 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-31 10:12:27,592 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-31 10:12:27,593 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-31 10:12:27,593 INFO L98 SettingsManager]: Beginning loading settings from /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf [2018-01-31 10:12:27,598 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-31 10:12:27,599 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-31 10:12:27,599 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-31 10:12:27,599 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-31 10:12:27,599 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-31 10:12:27,599 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-31 10:12:27,599 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-31 10:12:27,600 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-31 10:12:27,600 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-31 10:12:27,600 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-31 10:12:27,600 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-31 10:12:27,600 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-31 10:12:27,600 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-01-31 10:12:27,600 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-31 10:12:27,600 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-01-31 10:12:27,601 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-31 10:12:27,601 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-01-31 10:12:27,601 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-01-31 10:12:27,601 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-31 10:12:27,601 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-01-31 10:12:27,601 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-31 10:12:27,601 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-31 10:12:27,601 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-31 10:12:27,601 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-31 10:12:27,601 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-31 10:12:27,601 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-31 10:12:27,602 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-31 10:12:27,602 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-31 10:12:27,602 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-31 10:12:27,602 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-31 10:12:27,602 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-31 10:12:27,602 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-31 10:12:27,602 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-31 10:12:27,602 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-31 10:12:27,621 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-31 10:12:27,627 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-31 10:12:27,629 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-31 10:12:27,630 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-31 10:12:27,630 INFO L276 PluginConnector]: CDTParser initialized [2018-01-31 10:12:27,631 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/rangesum20_false-unreach-call.i [2018-01-31 10:12:27,697 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-31 10:12:27,698 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-01-31 10:12:27,699 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-31 10:12:27,699 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-31 10:12:27,702 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-31 10:12:27,703 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.01 10:12:27" (1/1) ... [2018-01-31 10:12:27,705 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2bfc5e08 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:27, skipping insertion in model container [2018-01-31 10:12:27,705 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.01 10:12:27" (1/1) ... [2018-01-31 10:12:27,714 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-31 10:12:27,723 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-31 10:12:27,795 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-31 10:12:27,808 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-31 10:12:27,812 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:27 WrapperNode [2018-01-31 10:12:27,812 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-31 10:12:27,812 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-31 10:12:27,812 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-31 10:12:27,813 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-31 10:12:27,821 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:27" (1/1) ... [2018-01-31 10:12:27,821 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:27" (1/1) ... [2018-01-31 10:12:27,827 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:27" (1/1) ... [2018-01-31 10:12:27,827 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:27" (1/1) ... [2018-01-31 10:12:27,829 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:27" (1/1) ... [2018-01-31 10:12:27,831 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:27" (1/1) ... [2018-01-31 10:12:27,832 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:27" (1/1) ... [2018-01-31 10:12:27,833 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-31 10:12:27,833 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-31 10:12:27,833 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-31 10:12:27,833 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-31 10:12:27,834 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:27" (1/1) ... No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-31 10:12:27,876 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-31 10:12:27,876 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-31 10:12:27,876 INFO L136 BoogieDeclarations]: Found implementation of procedure init_nondet [2018-01-31 10:12:27,876 INFO L136 BoogieDeclarations]: Found implementation of procedure rangesum [2018-01-31 10:12:27,876 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-31 10:12:27,876 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-31 10:12:27,876 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-31 10:12:27,876 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-31 10:12:27,876 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-31 10:12:27,876 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-31 10:12:27,877 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-31 10:12:27,877 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-31 10:12:27,877 INFO L128 BoogieDeclarations]: Found specification of procedure init_nondet [2018-01-31 10:12:27,877 INFO L128 BoogieDeclarations]: Found specification of procedure rangesum [2018-01-31 10:12:27,877 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-31 10:12:27,877 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-31 10:12:27,877 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-31 10:12:28,218 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-31 10:12:28,218 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:12:28 BoogieIcfgContainer [2018-01-31 10:12:28,218 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-31 10:12:28,218 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2018-01-31 10:12:28,218 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2018-01-31 10:12:28,219 INFO L276 PluginConnector]: IcfgTransformer initialized [2018-01-31 10:12:28,221 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:12:28" (1/1) ... [2018-01-31 10:12:28,226 INFO L103 apSepIcfgTransformer]: HeapSepIcfgTransformer: Starting heap partitioning [2018-01-31 10:12:28,226 INFO L104 apSepIcfgTransformer]: To be partitioned heap arrays found [#memory_int] [2018-01-31 10:12:28,226 INFO L150 apSepIcfgTransformer]: starting freeze-var-style preprocessing [2018-01-31 10:12:28,253 INFO L162 apSepIcfgTransformer]: finished StoreIndexFreezer, created 13 freeze vars and freeze var literals (each corresponds to one heap write) [2018-01-31 10:12:28,271 INFO L221 apSepIcfgTransformer]: finished preprocessing for the equality analysis [2018-01-31 10:12:28,307 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-31 10:12:35,170 INFO L314 AbstractInterpreter]: Visited 104 different actions 756 times. Merged at 73 different actions 393 times. Never widened. Found 75 fixpoints after 15 different actions. Largest state had 65 variables. [2018-01-31 10:12:35,172 INFO L229 apSepIcfgTransformer]: finished equality analysis [2018-01-31 10:12:35,177 INFO L244 HeapSepPreAnalysis]: Number of read from array group [#memory_int] : 10 [2018-01-31 10:12:35,178 INFO L241 apSepIcfgTransformer]: Finished pre analysis before partitioning [2018-01-31 10:12:35,178 INFO L242 apSepIcfgTransformer]: array groups: Set: [#memory_int] [2018-01-31 10:12:35,178 INFO L244 apSepIcfgTransformer]: select infos: Set: ((select |v_#memory_int_19| v_init_nondet_~x.base_2), at (SUMMARY for call write~int(#t~nondet1, ~x.base, ~x.offset + ~i~3 * 4, 4); srcloc: L7')) ((select (select |v_#memory_int_11| |v_main_~#x~8.base_11|) |v_main_~#x~8.offset_11|), at (SUMMARY for call #t~mem11 := read~int(~#x~8.base, ~#x~8.offset + 0, 4); srcloc: L42)) ((select (select |v_#memory_int_12| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4)), at (SUMMARY for call #t~mem14 := read~int(~#x~8.base, ~#x~8.offset + (~i~9 + 1) * 4, 4); srcloc: L44)) ((select |v_#memory_int_10| |v_main_~#x~8.base_9|), at (SUMMARY for call write~int(~temp~8, ~#x~8.base, ~#x~8.offset + 4, 4); srcloc: L40'''''')) ((select (select |v_#memory_int_5| |v_main_~#x~8.base_6|) |v_main_~#x~8.offset_6|), at (SUMMARY for call #t~mem6 := read~int(~#x~8.base, ~#x~8.offset + 0, 4); srcloc: L40)) ((select |v_#memory_int_8| |v_main_~#x~8.base_8|), at (SUMMARY for call write~int(#t~mem8, ~#x~8.base, ~#x~8.offset + 0, 4); srcloc: L40'''')) ((select (select |v_#memory_int_17| v_rangesum_~x.base_2) (+ v_rangesum_~x.offset_2 (* 4 v_rangesum_~i~5_6))), at (SUMMARY for call #t~mem4 := read~int(~x.base, ~x.offset + ~i~5 * 4, 4); srcloc: L19)) ((select |v_#memory_int_16| |v_main_~#x~8.base_14|), at (SUMMARY for call write~int(~temp~8, ~#x~8.base, ~#x~8.offset + 76, 4); srcloc: L43''''''')) ((select |v_#memory_int_14| |v_main_~#x~8.base_13|), at (SUMMARY for call write~int(#t~mem14, ~#x~8.base, ~#x~8.offset + ~i~9 * 4, 4); srcloc: L44')) ((select (select |v_#memory_int_6| |v_main_~#x~8.base_7|) (+ |v_main_~#x~8.offset_7| 4)), at (SUMMARY for call #t~mem8 := read~int(~#x~8.base, ~#x~8.offset + 4, 4); srcloc: L40''')) [2018-01-31 10:12:35,188 INFO L547 PartitionManager]: partitioning result: [2018-01-31 10:12:35,188 INFO L552 PartitionManager]: location blocks for array group [#memory_int] [2018-01-31 10:12:35,189 INFO L562 PartitionManager]: at dimension 0 [2018-01-31 10:12:35,189 INFO L563 PartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 6 [2018-01-31 10:12:35,189 INFO L564 PartitionManager]: # location blocks :3 [2018-01-31 10:12:35,189 INFO L562 PartitionManager]: at dimension 1 [2018-01-31 10:12:35,189 INFO L563 PartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 6 [2018-01-31 10:12:35,189 INFO L564 PartitionManager]: # location blocks :2 [2018-01-31 10:12:35,189 INFO L86 ransitionTransformer]: executing heap partitioning transformation [2018-01-31 10:12:35,207 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 31.01 10:12:35 BasicIcfg [2018-01-31 10:12:35,207 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2018-01-31 10:12:35,208 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-31 10:12:35,208 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-31 10:12:35,209 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-31 10:12:35,210 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 31.01 10:12:27" (1/4) ... [2018-01-31 10:12:35,211 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@579bd530 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 31.01 10:12:35, skipping insertion in model container [2018-01-31 10:12:35,211 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:27" (2/4) ... [2018-01-31 10:12:35,217 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@579bd530 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 31.01 10:12:35, skipping insertion in model container [2018-01-31 10:12:35,217 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:12:28" (3/4) ... [2018-01-31 10:12:35,217 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@579bd530 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 31.01 10:12:35, skipping insertion in model container [2018-01-31 10:12:35,217 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 31.01 10:12:35" (4/4) ... [2018-01-31 10:12:35,218 INFO L107 eAbstractionObserver]: Analyzing ICFG HeapSeparatedIcfg [2018-01-31 10:12:35,223 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-31 10:12:35,227 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-01-31 10:12:35,309 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-31 10:12:35,309 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-31 10:12:35,310 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-31 10:12:35,310 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-31 10:12:35,310 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-31 10:12:35,310 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-31 10:12:35,310 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-31 10:12:35,310 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-31 10:12:35,310 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-31 10:12:35,317 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states. [2018-01-31 10:12:35,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-01-31 10:12:35,322 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:35,322 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:35,322 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation]=== [2018-01-31 10:12:35,325 INFO L82 PathProgramCache]: Analyzing trace with hash -1073882414, now seen corresponding path program 1 times [2018-01-31 10:12:35,326 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:35,326 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:35,354 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:35,354 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:35,354 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:35,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:35,388 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:35,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:35,419 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-31 10:12:35,419 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-31 10:12:35,420 INFO L409 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-01-31 10:12:35,427 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-01-31 10:12:35,427 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-31 10:12:35,428 INFO L87 Difference]: Start difference. First operand 88 states. Second operand 2 states. [2018-01-31 10:12:35,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:35,446 INFO L93 Difference]: Finished difference Result 157 states and 187 transitions. [2018-01-31 10:12:35,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-01-31 10:12:35,447 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 35 [2018-01-31 10:12:35,449 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:35,455 INFO L225 Difference]: With dead ends: 157 [2018-01-31 10:12:35,455 INFO L226 Difference]: Without dead ends: 81 [2018-01-31 10:12:35,458 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-31 10:12:35,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-01-31 10:12:35,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2018-01-31 10:12:35,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-01-31 10:12:35,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 92 transitions. [2018-01-31 10:12:35,481 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 92 transitions. Word has length 35 [2018-01-31 10:12:35,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:35,481 INFO L432 AbstractCegarLoop]: Abstraction has 81 states and 92 transitions. [2018-01-31 10:12:35,481 INFO L433 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-01-31 10:12:35,481 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 92 transitions. [2018-01-31 10:12:35,483 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-31 10:12:35,483 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:35,483 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:35,483 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation]=== [2018-01-31 10:12:35,483 INFO L82 PathProgramCache]: Analyzing trace with hash -173460809, now seen corresponding path program 1 times [2018-01-31 10:12:35,483 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:35,483 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:35,484 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:35,484 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:35,484 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:35,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:35,499 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:35,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:35,619 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-31 10:12:35,619 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-31 10:12:35,620 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-31 10:12:35,620 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-31 10:12:35,620 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-31 10:12:35,621 INFO L87 Difference]: Start difference. First operand 81 states and 92 transitions. Second operand 4 states. [2018-01-31 10:12:35,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:35,794 INFO L93 Difference]: Finished difference Result 117 states and 132 transitions. [2018-01-31 10:12:35,794 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-31 10:12:35,794 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2018-01-31 10:12:35,794 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:35,795 INFO L225 Difference]: With dead ends: 117 [2018-01-31 10:12:35,795 INFO L226 Difference]: Without dead ends: 88 [2018-01-31 10:12:35,796 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-31 10:12:35,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-01-31 10:12:35,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 83. [2018-01-31 10:12:35,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2018-01-31 10:12:35,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 94 transitions. [2018-01-31 10:12:35,800 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 94 transitions. Word has length 36 [2018-01-31 10:12:35,800 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:35,801 INFO L432 AbstractCegarLoop]: Abstraction has 83 states and 94 transitions. [2018-01-31 10:12:35,801 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-31 10:12:35,801 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 94 transitions. [2018-01-31 10:12:35,801 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-31 10:12:35,801 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:35,802 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:35,802 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation]=== [2018-01-31 10:12:35,802 INFO L82 PathProgramCache]: Analyzing trace with hash 858737893, now seen corresponding path program 1 times [2018-01-31 10:12:35,802 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:35,802 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:35,803 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:35,803 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:35,803 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:35,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:35,813 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:36,007 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:36,008 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:36,008 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:36,024 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:36,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:36,057 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:36,110 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:36,132 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:36,132 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5] total 9 [2018-01-31 10:12:36,132 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-31 10:12:36,132 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-31 10:12:36,132 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2018-01-31 10:12:36,133 INFO L87 Difference]: Start difference. First operand 83 states and 94 transitions. Second operand 9 states. [2018-01-31 10:12:36,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:36,278 INFO L93 Difference]: Finished difference Result 125 states and 140 transitions. [2018-01-31 10:12:36,281 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-31 10:12:36,281 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 44 [2018-01-31 10:12:36,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:36,282 INFO L225 Difference]: With dead ends: 125 [2018-01-31 10:12:36,282 INFO L226 Difference]: Without dead ends: 96 [2018-01-31 10:12:36,282 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 42 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2018-01-31 10:12:36,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-01-31 10:12:36,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 91. [2018-01-31 10:12:36,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-01-31 10:12:36,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 102 transitions. [2018-01-31 10:12:36,290 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 102 transitions. Word has length 44 [2018-01-31 10:12:36,290 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:36,290 INFO L432 AbstractCegarLoop]: Abstraction has 91 states and 102 transitions. [2018-01-31 10:12:36,290 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-31 10:12:36,290 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 102 transitions. [2018-01-31 10:12:36,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-31 10:12:36,291 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:36,291 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:36,291 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation]=== [2018-01-31 10:12:36,291 INFO L82 PathProgramCache]: Analyzing trace with hash 575101203, now seen corresponding path program 2 times [2018-01-31 10:12:36,291 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:36,291 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:36,292 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:36,292 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:36,292 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:36,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:36,302 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:36,393 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:36,393 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:36,393 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:36,411 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-31 10:12:36,423 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:36,433 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:36,434 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:36,435 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:36,592 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:36,610 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:36,610 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7] total 13 [2018-01-31 10:12:36,610 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-31 10:12:36,610 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-31 10:12:36,610 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2018-01-31 10:12:36,611 INFO L87 Difference]: Start difference. First operand 91 states and 102 transitions. Second operand 13 states. [2018-01-31 10:12:37,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:37,011 INFO L93 Difference]: Finished difference Result 133 states and 148 transitions. [2018-01-31 10:12:37,012 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-31 10:12:37,012 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 52 [2018-01-31 10:12:37,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:37,013 INFO L225 Difference]: With dead ends: 133 [2018-01-31 10:12:37,013 INFO L226 Difference]: Without dead ends: 104 [2018-01-31 10:12:37,013 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 48 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=91, Invalid=181, Unknown=0, NotChecked=0, Total=272 [2018-01-31 10:12:37,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-01-31 10:12:37,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 99. [2018-01-31 10:12:37,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-01-31 10:12:37,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 110 transitions. [2018-01-31 10:12:37,017 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 110 transitions. Word has length 52 [2018-01-31 10:12:37,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:37,017 INFO L432 AbstractCegarLoop]: Abstraction has 99 states and 110 transitions. [2018-01-31 10:12:37,017 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-31 10:12:37,017 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 110 transitions. [2018-01-31 10:12:37,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-01-31 10:12:37,018 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:37,018 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:37,019 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation]=== [2018-01-31 10:12:37,019 INFO L82 PathProgramCache]: Analyzing trace with hash 1390368577, now seen corresponding path program 3 times [2018-01-31 10:12:37,019 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:37,019 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:37,019 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:37,019 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:37,019 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:37,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:37,032 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:37,169 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:37,169 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:37,169 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:37,176 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-31 10:12:37,201 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:37,206 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:37,208 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:37,211 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:37,211 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:37,213 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:37,320 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:37,337 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:37,337 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 17 [2018-01-31 10:12:37,337 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-31 10:12:37,337 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-31 10:12:37,337 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=200, Unknown=0, NotChecked=0, Total=272 [2018-01-31 10:12:37,338 INFO L87 Difference]: Start difference. First operand 99 states and 110 transitions. Second operand 17 states. [2018-01-31 10:12:37,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:37,509 INFO L93 Difference]: Finished difference Result 141 states and 156 transitions. [2018-01-31 10:12:37,510 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-31 10:12:37,510 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 60 [2018-01-31 10:12:37,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:37,510 INFO L225 Difference]: With dead ends: 141 [2018-01-31 10:12:37,510 INFO L226 Difference]: Without dead ends: 112 [2018-01-31 10:12:37,511 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 54 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=159, Invalid=347, Unknown=0, NotChecked=0, Total=506 [2018-01-31 10:12:37,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-01-31 10:12:37,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 107. [2018-01-31 10:12:37,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-01-31 10:12:37,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 118 transitions. [2018-01-31 10:12:37,514 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 118 transitions. Word has length 60 [2018-01-31 10:12:37,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:37,514 INFO L432 AbstractCegarLoop]: Abstraction has 107 states and 118 transitions. [2018-01-31 10:12:37,515 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-31 10:12:37,515 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 118 transitions. [2018-01-31 10:12:37,516 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-01-31 10:12:37,516 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:37,516 INFO L351 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:37,516 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation]=== [2018-01-31 10:12:37,516 INFO L82 PathProgramCache]: Analyzing trace with hash -2031794321, now seen corresponding path program 4 times [2018-01-31 10:12:37,516 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:37,516 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:37,516 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:37,517 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:37,517 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:37,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:37,526 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:37,674 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:37,674 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:37,674 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:37,679 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-31 10:12:37,714 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:37,715 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:37,889 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:37,905 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:37,905 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11] total 21 [2018-01-31 10:12:37,906 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-31 10:12:37,906 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-31 10:12:37,906 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=315, Unknown=0, NotChecked=0, Total=420 [2018-01-31 10:12:37,906 INFO L87 Difference]: Start difference. First operand 107 states and 118 transitions. Second operand 21 states. [2018-01-31 10:12:38,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:38,151 INFO L93 Difference]: Finished difference Result 149 states and 164 transitions. [2018-01-31 10:12:38,151 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-31 10:12:38,151 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 68 [2018-01-31 10:12:38,151 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:38,152 INFO L225 Difference]: With dead ends: 149 [2018-01-31 10:12:38,152 INFO L226 Difference]: Without dead ends: 120 [2018-01-31 10:12:38,153 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 60 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 181 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=245, Invalid=567, Unknown=0, NotChecked=0, Total=812 [2018-01-31 10:12:38,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-01-31 10:12:38,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 115. [2018-01-31 10:12:38,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-01-31 10:12:38,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 126 transitions. [2018-01-31 10:12:38,157 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 126 transitions. Word has length 68 [2018-01-31 10:12:38,157 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:38,157 INFO L432 AbstractCegarLoop]: Abstraction has 115 states and 126 transitions. [2018-01-31 10:12:38,157 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-31 10:12:38,157 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 126 transitions. [2018-01-31 10:12:38,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-01-31 10:12:38,158 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:38,158 INFO L351 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:38,158 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation]=== [2018-01-31 10:12:38,158 INFO L82 PathProgramCache]: Analyzing trace with hash -1303959139, now seen corresponding path program 5 times [2018-01-31 10:12:38,158 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:38,158 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:38,159 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:38,159 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:38,159 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:38,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:38,168 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:38,515 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:38,516 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:38,516 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:38,522 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-31 10:12:38,528 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:38,530 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:38,532 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:38,539 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:38,542 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:38,547 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:38,548 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:38,549 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:38,641 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:38,660 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:38,660 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13] total 25 [2018-01-31 10:12:38,661 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-31 10:12:38,661 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-31 10:12:38,661 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=456, Unknown=0, NotChecked=0, Total=600 [2018-01-31 10:12:38,661 INFO L87 Difference]: Start difference. First operand 115 states and 126 transitions. Second operand 25 states. [2018-01-31 10:12:38,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:38,913 INFO L93 Difference]: Finished difference Result 157 states and 172 transitions. [2018-01-31 10:12:38,913 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-31 10:12:38,913 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 76 [2018-01-31 10:12:38,913 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:38,914 INFO L225 Difference]: With dead ends: 157 [2018-01-31 10:12:38,914 INFO L226 Difference]: Without dead ends: 128 [2018-01-31 10:12:38,914 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 66 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 281 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=349, Invalid=841, Unknown=0, NotChecked=0, Total=1190 [2018-01-31 10:12:38,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-01-31 10:12:38,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 123. [2018-01-31 10:12:38,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123 states. [2018-01-31 10:12:38,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 134 transitions. [2018-01-31 10:12:38,918 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 134 transitions. Word has length 76 [2018-01-31 10:12:38,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:38,918 INFO L432 AbstractCegarLoop]: Abstraction has 123 states and 134 transitions. [2018-01-31 10:12:38,918 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-31 10:12:38,918 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 134 transitions. [2018-01-31 10:12:38,919 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-01-31 10:12:38,919 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:38,919 INFO L351 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:38,919 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation]=== [2018-01-31 10:12:38,919 INFO L82 PathProgramCache]: Analyzing trace with hash -84738613, now seen corresponding path program 6 times [2018-01-31 10:12:38,919 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:38,919 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:38,920 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:38,920 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:38,920 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:38,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:38,929 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:39,103 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:39,103 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:39,104 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:39,110 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-31 10:12:39,119 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:39,130 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:39,132 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:39,134 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:39,138 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:39,146 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:39,150 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:39,150 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:39,152 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:39,256 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:39,275 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:39,275 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15] total 29 [2018-01-31 10:12:39,275 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-31 10:12:39,276 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-31 10:12:39,276 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=189, Invalid=623, Unknown=0, NotChecked=0, Total=812 [2018-01-31 10:12:39,276 INFO L87 Difference]: Start difference. First operand 123 states and 134 transitions. Second operand 29 states. [2018-01-31 10:12:39,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:39,549 INFO L93 Difference]: Finished difference Result 165 states and 180 transitions. [2018-01-31 10:12:39,549 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-31 10:12:39,549 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 84 [2018-01-31 10:12:39,550 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:39,550 INFO L225 Difference]: With dead ends: 165 [2018-01-31 10:12:39,550 INFO L226 Difference]: Without dead ends: 136 [2018-01-31 10:12:39,551 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 72 SyntacticMatches, 1 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 403 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=471, Invalid=1169, Unknown=0, NotChecked=0, Total=1640 [2018-01-31 10:12:39,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-01-31 10:12:39,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 131. [2018-01-31 10:12:39,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-01-31 10:12:39,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 142 transitions. [2018-01-31 10:12:39,557 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 142 transitions. Word has length 84 [2018-01-31 10:12:39,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:39,557 INFO L432 AbstractCegarLoop]: Abstraction has 131 states and 142 transitions. [2018-01-31 10:12:39,557 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-31 10:12:39,558 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 142 transitions. [2018-01-31 10:12:39,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-31 10:12:39,558 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:39,558 INFO L351 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:39,558 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation]=== [2018-01-31 10:12:39,558 INFO L82 PathProgramCache]: Analyzing trace with hash -1193884679, now seen corresponding path program 7 times [2018-01-31 10:12:39,559 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:39,559 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:39,559 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:39,559 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:39,559 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:39,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:39,575 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:39,790 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:39,791 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:39,791 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:39,795 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:39,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:39,819 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:39,947 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:39,966 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:39,966 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17] total 33 [2018-01-31 10:12:39,966 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-31 10:12:39,966 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-31 10:12:39,967 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=240, Invalid=816, Unknown=0, NotChecked=0, Total=1056 [2018-01-31 10:12:39,967 INFO L87 Difference]: Start difference. First operand 131 states and 142 transitions. Second operand 33 states. [2018-01-31 10:12:40,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:40,356 INFO L93 Difference]: Finished difference Result 173 states and 188 transitions. [2018-01-31 10:12:40,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-31 10:12:40,356 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 92 [2018-01-31 10:12:40,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:40,357 INFO L225 Difference]: With dead ends: 173 [2018-01-31 10:12:40,357 INFO L226 Difference]: Without dead ends: 144 [2018-01-31 10:12:40,358 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 124 GetRequests, 78 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 547 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=611, Invalid=1551, Unknown=0, NotChecked=0, Total=2162 [2018-01-31 10:12:40,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-01-31 10:12:40,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 139. [2018-01-31 10:12:40,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-01-31 10:12:40,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 150 transitions. [2018-01-31 10:12:40,361 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 150 transitions. Word has length 92 [2018-01-31 10:12:40,361 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:40,361 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 150 transitions. [2018-01-31 10:12:40,361 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-31 10:12:40,361 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 150 transitions. [2018-01-31 10:12:40,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-01-31 10:12:40,362 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:40,362 INFO L351 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:40,362 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation]=== [2018-01-31 10:12:40,362 INFO L82 PathProgramCache]: Analyzing trace with hash 1977646119, now seen corresponding path program 8 times [2018-01-31 10:12:40,362 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:40,362 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:40,362 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:40,362 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:40,362 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:40,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:40,371 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:40,596 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:40,596 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:40,596 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:40,603 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-31 10:12:40,614 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:40,621 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:40,623 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:40,624 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:40,774 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:40,794 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:40,794 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 19] total 37 [2018-01-31 10:12:40,794 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-01-31 10:12:40,794 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-01-31 10:12:40,795 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=297, Invalid=1035, Unknown=0, NotChecked=0, Total=1332 [2018-01-31 10:12:40,795 INFO L87 Difference]: Start difference. First operand 139 states and 150 transitions. Second operand 37 states. [2018-01-31 10:12:41,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:41,199 INFO L93 Difference]: Finished difference Result 181 states and 196 transitions. [2018-01-31 10:12:41,200 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-31 10:12:41,200 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 100 [2018-01-31 10:12:41,200 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:41,201 INFO L225 Difference]: With dead ends: 181 [2018-01-31 10:12:41,201 INFO L226 Difference]: Without dead ends: 152 [2018-01-31 10:12:41,201 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 84 SyntacticMatches, 1 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 713 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=769, Invalid=1987, Unknown=0, NotChecked=0, Total=2756 [2018-01-31 10:12:41,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-01-31 10:12:41,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 147. [2018-01-31 10:12:41,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-01-31 10:12:41,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 158 transitions. [2018-01-31 10:12:41,205 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 158 transitions. Word has length 100 [2018-01-31 10:12:41,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:41,205 INFO L432 AbstractCegarLoop]: Abstraction has 147 states and 158 transitions. [2018-01-31 10:12:41,205 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-01-31 10:12:41,205 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 158 transitions. [2018-01-31 10:12:41,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-01-31 10:12:41,206 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:41,206 INFO L351 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:41,206 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation]=== [2018-01-31 10:12:41,206 INFO L82 PathProgramCache]: Analyzing trace with hash -302111147, now seen corresponding path program 9 times [2018-01-31 10:12:41,206 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:41,206 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:41,207 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:41,207 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:41,207 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:41,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:41,215 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:42,077 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:42,078 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:42,078 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:42,082 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-31 10:12:42,092 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:42,094 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:42,097 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:42,100 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:42,108 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:42,112 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:42,121 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:42,126 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:42,137 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:42,166 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:42,167 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:42,169 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:42,343 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:42,360 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:42,360 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21] total 41 [2018-01-31 10:12:42,360 INFO L409 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-01-31 10:12:42,361 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-01-31 10:12:42,361 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=360, Invalid=1280, Unknown=0, NotChecked=0, Total=1640 [2018-01-31 10:12:42,361 INFO L87 Difference]: Start difference. First operand 147 states and 158 transitions. Second operand 41 states. [2018-01-31 10:12:42,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:42,781 INFO L93 Difference]: Finished difference Result 189 states and 204 transitions. [2018-01-31 10:12:42,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-31 10:12:42,782 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 108 [2018-01-31 10:12:42,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:42,783 INFO L225 Difference]: With dead ends: 189 [2018-01-31 10:12:42,783 INFO L226 Difference]: Without dead ends: 160 [2018-01-31 10:12:42,784 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 90 SyntacticMatches, 1 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 901 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=945, Invalid=2477, Unknown=0, NotChecked=0, Total=3422 [2018-01-31 10:12:42,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-01-31 10:12:42,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 155. [2018-01-31 10:12:42,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 155 states. [2018-01-31 10:12:42,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 166 transitions. [2018-01-31 10:12:42,786 INFO L78 Accepts]: Start accepts. Automaton has 155 states and 166 transitions. Word has length 108 [2018-01-31 10:12:42,786 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:42,786 INFO L432 AbstractCegarLoop]: Abstraction has 155 states and 166 transitions. [2018-01-31 10:12:42,787 INFO L433 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-01-31 10:12:42,787 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 166 transitions. [2018-01-31 10:12:42,787 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-01-31 10:12:42,787 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:42,787 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:42,787 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation]=== [2018-01-31 10:12:42,787 INFO L82 PathProgramCache]: Analyzing trace with hash 253608579, now seen corresponding path program 10 times [2018-01-31 10:12:42,788 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:42,788 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:42,788 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:42,788 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:42,788 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:42,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:42,796 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:43,117 INFO L134 CoverageAnalysis]: Checked inductivity of 380 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:43,117 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:43,117 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:43,122 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-31 10:12:43,149 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:43,151 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:43,599 INFO L134 CoverageAnalysis]: Checked inductivity of 380 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:43,616 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:43,616 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 23] total 45 [2018-01-31 10:12:43,616 INFO L409 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-01-31 10:12:43,616 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-01-31 10:12:43,617 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=429, Invalid=1551, Unknown=0, NotChecked=0, Total=1980 [2018-01-31 10:12:43,617 INFO L87 Difference]: Start difference. First operand 155 states and 166 transitions. Second operand 45 states. [2018-01-31 10:12:44,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:44,363 INFO L93 Difference]: Finished difference Result 197 states and 212 transitions. [2018-01-31 10:12:44,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-01-31 10:12:44,365 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 116 [2018-01-31 10:12:44,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:44,366 INFO L225 Difference]: With dead ends: 197 [2018-01-31 10:12:44,366 INFO L226 Difference]: Without dead ends: 168 [2018-01-31 10:12:44,367 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 160 GetRequests, 96 SyntacticMatches, 1 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1111 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1139, Invalid=3021, Unknown=0, NotChecked=0, Total=4160 [2018-01-31 10:12:44,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168 states. [2018-01-31 10:12:44,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168 to 163. [2018-01-31 10:12:44,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 163 states. [2018-01-31 10:12:44,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 174 transitions. [2018-01-31 10:12:44,370 INFO L78 Accepts]: Start accepts. Automaton has 163 states and 174 transitions. Word has length 116 [2018-01-31 10:12:44,370 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:44,370 INFO L432 AbstractCegarLoop]: Abstraction has 163 states and 174 transitions. [2018-01-31 10:12:44,370 INFO L433 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-01-31 10:12:44,370 INFO L276 IsEmpty]: Start isEmpty. Operand 163 states and 174 transitions. [2018-01-31 10:12:44,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2018-01-31 10:12:44,373 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:44,373 INFO L351 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:44,373 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation]=== [2018-01-31 10:12:44,373 INFO L82 PathProgramCache]: Analyzing trace with hash -114470735, now seen corresponding path program 11 times [2018-01-31 10:12:44,373 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:44,373 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:44,373 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:44,374 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:44,374 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:44,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:44,383 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:44,697 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 0 proven. 462 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:44,697 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:44,697 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:44,702 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-31 10:12:44,709 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:44,711 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:44,712 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:44,714 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:44,716 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:44,719 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:44,722 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:44,726 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:44,731 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:44,740 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:44,748 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:44,756 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:44,757 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:44,759 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:45,027 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 0 proven. 462 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:45,044 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:45,044 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 25] total 49 [2018-01-31 10:12:45,044 INFO L409 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-01-31 10:12:45,044 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-01-31 10:12:45,045 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=504, Invalid=1848, Unknown=0, NotChecked=0, Total=2352 [2018-01-31 10:12:45,045 INFO L87 Difference]: Start difference. First operand 163 states and 174 transitions. Second operand 49 states. [2018-01-31 10:12:45,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:45,632 INFO L93 Difference]: Finished difference Result 205 states and 220 transitions. [2018-01-31 10:12:45,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-01-31 10:12:45,632 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 124 [2018-01-31 10:12:45,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:45,633 INFO L225 Difference]: With dead ends: 205 [2018-01-31 10:12:45,633 INFO L226 Difference]: Without dead ends: 176 [2018-01-31 10:12:45,634 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 172 GetRequests, 102 SyntacticMatches, 1 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1343 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1351, Invalid=3619, Unknown=0, NotChecked=0, Total=4970 [2018-01-31 10:12:45,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-01-31 10:12:45,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 171. [2018-01-31 10:12:45,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-01-31 10:12:45,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 182 transitions. [2018-01-31 10:12:45,637 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 182 transitions. Word has length 124 [2018-01-31 10:12:45,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:45,637 INFO L432 AbstractCegarLoop]: Abstraction has 171 states and 182 transitions. [2018-01-31 10:12:45,637 INFO L433 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-01-31 10:12:45,637 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 182 transitions. [2018-01-31 10:12:45,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-01-31 10:12:45,638 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:45,638 INFO L351 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:45,638 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation]=== [2018-01-31 10:12:45,638 INFO L82 PathProgramCache]: Analyzing trace with hash -31797025, now seen corresponding path program 12 times [2018-01-31 10:12:45,638 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:45,638 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:45,638 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:45,638 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:45,638 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:45,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:45,646 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:46,118 INFO L134 CoverageAnalysis]: Checked inductivity of 552 backedges. 0 proven. 552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:46,118 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:46,118 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:46,125 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-31 10:12:46,136 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:46,138 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:46,141 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:46,144 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:46,153 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:46,166 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:46,186 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:46,203 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:46,239 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:46,279 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:46,309 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:46,337 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:46,347 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:46,348 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:46,350 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:46,697 INFO L134 CoverageAnalysis]: Checked inductivity of 552 backedges. 0 proven. 552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:46,715 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:46,715 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 27] total 53 [2018-01-31 10:12:46,717 INFO L409 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-01-31 10:12:46,718 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-01-31 10:12:46,718 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=585, Invalid=2171, Unknown=0, NotChecked=0, Total=2756 [2018-01-31 10:12:46,718 INFO L87 Difference]: Start difference. First operand 171 states and 182 transitions. Second operand 53 states. [2018-01-31 10:12:47,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:47,312 INFO L93 Difference]: Finished difference Result 213 states and 228 transitions. [2018-01-31 10:12:47,313 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-01-31 10:12:47,313 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 132 [2018-01-31 10:12:47,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:47,314 INFO L225 Difference]: With dead ends: 213 [2018-01-31 10:12:47,314 INFO L226 Difference]: Without dead ends: 184 [2018-01-31 10:12:47,315 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 108 SyntacticMatches, 1 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1597 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1581, Invalid=4271, Unknown=0, NotChecked=0, Total=5852 [2018-01-31 10:12:47,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-01-31 10:12:47,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 179. [2018-01-31 10:12:47,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179 states. [2018-01-31 10:12:47,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 190 transitions. [2018-01-31 10:12:47,318 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 190 transitions. Word has length 132 [2018-01-31 10:12:47,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:47,318 INFO L432 AbstractCegarLoop]: Abstraction has 179 states and 190 transitions. [2018-01-31 10:12:47,318 INFO L433 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-01-31 10:12:47,318 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 190 transitions. [2018-01-31 10:12:47,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-01-31 10:12:47,319 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:47,319 INFO L351 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:47,319 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation]=== [2018-01-31 10:12:47,319 INFO L82 PathProgramCache]: Analyzing trace with hash -1579924723, now seen corresponding path program 13 times [2018-01-31 10:12:47,319 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:47,319 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:47,320 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:47,320 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:47,320 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:47,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:47,328 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:48,038 INFO L134 CoverageAnalysis]: Checked inductivity of 650 backedges. 0 proven. 650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:48,039 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:48,039 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:48,043 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:48,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:48,066 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:48,366 INFO L134 CoverageAnalysis]: Checked inductivity of 650 backedges. 0 proven. 650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:48,385 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:48,385 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 29] total 57 [2018-01-31 10:12:48,385 INFO L409 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-01-31 10:12:48,386 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-01-31 10:12:48,386 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=672, Invalid=2520, Unknown=0, NotChecked=0, Total=3192 [2018-01-31 10:12:48,386 INFO L87 Difference]: Start difference. First operand 179 states and 190 transitions. Second operand 57 states. [2018-01-31 10:12:49,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:49,287 INFO L93 Difference]: Finished difference Result 221 states and 236 transitions. [2018-01-31 10:12:49,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-01-31 10:12:49,288 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 140 [2018-01-31 10:12:49,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:49,289 INFO L225 Difference]: With dead ends: 221 [2018-01-31 10:12:49,289 INFO L226 Difference]: Without dead ends: 192 [2018-01-31 10:12:49,290 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 114 SyntacticMatches, 1 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1873 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1829, Invalid=4977, Unknown=0, NotChecked=0, Total=6806 [2018-01-31 10:12:49,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 192 states. [2018-01-31 10:12:49,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 192 to 187. [2018-01-31 10:12:49,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 187 states. [2018-01-31 10:12:49,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 198 transitions. [2018-01-31 10:12:49,294 INFO L78 Accepts]: Start accepts. Automaton has 187 states and 198 transitions. Word has length 140 [2018-01-31 10:12:49,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:49,294 INFO L432 AbstractCegarLoop]: Abstraction has 187 states and 198 transitions. [2018-01-31 10:12:49,294 INFO L433 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-01-31 10:12:49,294 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 198 transitions. [2018-01-31 10:12:49,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-01-31 10:12:49,295 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:49,295 INFO L351 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:49,295 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation]=== [2018-01-31 10:12:49,295 INFO L82 PathProgramCache]: Analyzing trace with hash -1706580165, now seen corresponding path program 14 times [2018-01-31 10:12:49,295 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:49,295 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:49,295 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:49,296 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:49,296 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:49,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:49,305 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:50,106 INFO L134 CoverageAnalysis]: Checked inductivity of 756 backedges. 0 proven. 756 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:50,106 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:50,106 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:50,112 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-31 10:12:50,123 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:50,134 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:50,136 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:50,138 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:50,496 INFO L134 CoverageAnalysis]: Checked inductivity of 756 backedges. 0 proven. 756 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:50,513 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:50,514 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 31] total 61 [2018-01-31 10:12:50,514 INFO L409 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-01-31 10:12:50,514 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-01-31 10:12:50,515 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=765, Invalid=2895, Unknown=0, NotChecked=0, Total=3660 [2018-01-31 10:12:50,515 INFO L87 Difference]: Start difference. First operand 187 states and 198 transitions. Second operand 61 states. [2018-01-31 10:12:51,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:51,378 INFO L93 Difference]: Finished difference Result 229 states and 244 transitions. [2018-01-31 10:12:51,378 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-01-31 10:12:51,378 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 148 [2018-01-31 10:12:51,378 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:51,379 INFO L225 Difference]: With dead ends: 229 [2018-01-31 10:12:51,379 INFO L226 Difference]: Without dead ends: 200 [2018-01-31 10:12:51,380 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 208 GetRequests, 120 SyntacticMatches, 1 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2171 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2095, Invalid=5737, Unknown=0, NotChecked=0, Total=7832 [2018-01-31 10:12:51,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states. [2018-01-31 10:12:51,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 195. [2018-01-31 10:12:51,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 195 states. [2018-01-31 10:12:51,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 206 transitions. [2018-01-31 10:12:51,383 INFO L78 Accepts]: Start accepts. Automaton has 195 states and 206 transitions. Word has length 148 [2018-01-31 10:12:51,383 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:51,383 INFO L432 AbstractCegarLoop]: Abstraction has 195 states and 206 transitions. [2018-01-31 10:12:51,383 INFO L433 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-01-31 10:12:51,383 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 206 transitions. [2018-01-31 10:12:51,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2018-01-31 10:12:51,384 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:51,384 INFO L351 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:51,384 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation]=== [2018-01-31 10:12:51,384 INFO L82 PathProgramCache]: Analyzing trace with hash -815596183, now seen corresponding path program 15 times [2018-01-31 10:12:51,384 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:51,384 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:51,384 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:51,385 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:51,385 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:51,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:51,393 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:52,096 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 0 proven. 870 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:52,096 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:52,096 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:52,101 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-31 10:12:52,112 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,114 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,117 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,119 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,128 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,132 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,140 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,149 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,163 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,170 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,219 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,248 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,272 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,304 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,327 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,367 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:52,368 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:52,370 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:52,786 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 0 proven. 870 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:52,804 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:52,804 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 33] total 65 [2018-01-31 10:12:52,804 INFO L409 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-01-31 10:12:52,804 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-01-31 10:12:52,805 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=864, Invalid=3296, Unknown=0, NotChecked=0, Total=4160 [2018-01-31 10:12:52,805 INFO L87 Difference]: Start difference. First operand 195 states and 206 transitions. Second operand 65 states. [2018-01-31 10:12:53,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:53,765 INFO L93 Difference]: Finished difference Result 237 states and 252 transitions. [2018-01-31 10:12:53,765 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-01-31 10:12:53,765 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 156 [2018-01-31 10:12:53,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:53,766 INFO L225 Difference]: With dead ends: 237 [2018-01-31 10:12:53,766 INFO L226 Difference]: Without dead ends: 208 [2018-01-31 10:12:53,767 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 220 GetRequests, 126 SyntacticMatches, 1 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2491 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2379, Invalid=6551, Unknown=0, NotChecked=0, Total=8930 [2018-01-31 10:12:53,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states. [2018-01-31 10:12:53,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 203. [2018-01-31 10:12:53,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-01-31 10:12:53,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 214 transitions. [2018-01-31 10:12:53,769 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 214 transitions. Word has length 156 [2018-01-31 10:12:53,770 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:53,770 INFO L432 AbstractCegarLoop]: Abstraction has 203 states and 214 transitions. [2018-01-31 10:12:53,770 INFO L433 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-01-31 10:12:53,770 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 214 transitions. [2018-01-31 10:12:53,771 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-01-31 10:12:53,771 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:53,771 INFO L351 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:53,771 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation]=== [2018-01-31 10:12:53,771 INFO L82 PathProgramCache]: Analyzing trace with hash 1528055191, now seen corresponding path program 16 times [2018-01-31 10:12:53,771 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:53,771 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:53,772 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:53,772 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:53,772 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:53,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:53,781 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:54,546 INFO L134 CoverageAnalysis]: Checked inductivity of 992 backedges. 0 proven. 992 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:54,546 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:54,546 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:54,551 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-31 10:12:54,617 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:54,619 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:55,041 INFO L134 CoverageAnalysis]: Checked inductivity of 992 backedges. 0 proven. 992 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:55,058 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:55,059 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 35] total 69 [2018-01-31 10:12:55,059 INFO L409 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-01-31 10:12:55,059 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-01-31 10:12:55,059 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=969, Invalid=3723, Unknown=0, NotChecked=0, Total=4692 [2018-01-31 10:12:55,060 INFO L87 Difference]: Start difference. First operand 203 states and 214 transitions. Second operand 69 states. [2018-01-31 10:12:56,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:56,051 INFO L93 Difference]: Finished difference Result 245 states and 260 transitions. [2018-01-31 10:12:56,051 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-01-31 10:12:56,051 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 164 [2018-01-31 10:12:56,051 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:56,052 INFO L225 Difference]: With dead ends: 245 [2018-01-31 10:12:56,052 INFO L226 Difference]: Without dead ends: 216 [2018-01-31 10:12:56,053 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 232 GetRequests, 132 SyntacticMatches, 1 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2833 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2681, Invalid=7419, Unknown=0, NotChecked=0, Total=10100 [2018-01-31 10:12:56,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-01-31 10:12:56,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 211. [2018-01-31 10:12:56,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 211 states. [2018-01-31 10:12:56,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 211 states to 211 states and 222 transitions. [2018-01-31 10:12:56,056 INFO L78 Accepts]: Start accepts. Automaton has 211 states and 222 transitions. Word has length 164 [2018-01-31 10:12:56,056 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:56,056 INFO L432 AbstractCegarLoop]: Abstraction has 211 states and 222 transitions. [2018-01-31 10:12:56,056 INFO L433 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-01-31 10:12:56,056 INFO L276 IsEmpty]: Start isEmpty. Operand 211 states and 222 transitions. [2018-01-31 10:12:56,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2018-01-31 10:12:56,058 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:56,058 INFO L351 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:56,059 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation]=== [2018-01-31 10:12:56,059 INFO L82 PathProgramCache]: Analyzing trace with hash -1991671867, now seen corresponding path program 17 times [2018-01-31 10:12:56,059 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:56,059 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:56,059 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:56,059 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:56,059 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:56,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:56,069 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:56,766 INFO L134 CoverageAnalysis]: Checked inductivity of 1122 backedges. 0 proven. 1122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:56,766 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:56,766 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:56,770 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-31 10:12:56,780 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,782 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,783 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,787 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,789 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,792 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,796 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,800 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,805 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,813 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,818 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,825 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,834 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,842 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,855 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,867 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,886 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,935 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:56,936 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:56,939 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:57,427 INFO L134 CoverageAnalysis]: Checked inductivity of 1122 backedges. 0 proven. 1122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:57,444 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:57,444 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 37] total 73 [2018-01-31 10:12:57,445 INFO L409 AbstractCegarLoop]: Interpolant automaton has 73 states [2018-01-31 10:12:57,445 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2018-01-31 10:12:57,445 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1080, Invalid=4176, Unknown=0, NotChecked=0, Total=5256 [2018-01-31 10:12:57,445 INFO L87 Difference]: Start difference. First operand 211 states and 222 transitions. Second operand 73 states. [2018-01-31 10:12:58,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:58,897 INFO L93 Difference]: Finished difference Result 253 states and 268 transitions. [2018-01-31 10:12:58,897 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-01-31 10:12:58,897 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 172 [2018-01-31 10:12:58,897 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:58,898 INFO L225 Difference]: With dead ends: 253 [2018-01-31 10:12:58,898 INFO L226 Difference]: Without dead ends: 224 [2018-01-31 10:12:58,899 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 244 GetRequests, 138 SyntacticMatches, 1 SemanticMatches, 105 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3197 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=3001, Invalid=8341, Unknown=0, NotChecked=0, Total=11342 [2018-01-31 10:12:58,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-01-31 10:12:58,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 219. [2018-01-31 10:12:58,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 219 states. [2018-01-31 10:12:58,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 230 transitions. [2018-01-31 10:12:58,901 INFO L78 Accepts]: Start accepts. Automaton has 219 states and 230 transitions. Word has length 172 [2018-01-31 10:12:58,902 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:58,902 INFO L432 AbstractCegarLoop]: Abstraction has 219 states and 230 transitions. [2018-01-31 10:12:58,902 INFO L433 AbstractCegarLoop]: Interpolant automaton has 73 states. [2018-01-31 10:12:58,902 INFO L276 IsEmpty]: Start isEmpty. Operand 219 states and 230 transitions. [2018-01-31 10:12:58,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2018-01-31 10:12:58,902 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:58,902 INFO L351 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:58,902 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation]=== [2018-01-31 10:12:58,902 INFO L82 PathProgramCache]: Analyzing trace with hash -672093197, now seen corresponding path program 18 times [2018-01-31 10:12:58,903 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:58,903 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:58,903 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:58,903 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:58,903 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:58,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:58,912 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:59,762 INFO L134 CoverageAnalysis]: Checked inductivity of 1260 backedges. 0 proven. 1260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:59,763 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:59,763 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:59,767 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-31 10:12:59,780 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:59,782 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:59,784 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:59,787 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:59,796 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:59,815 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:59,836 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:59,859 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:59,890 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:59,928 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:59,987 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:13:00,041 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:13:00,063 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:13:00,191 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:13:00,369 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:13:00,449 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:13:00,605 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:13:01,031 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:13:01,294 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:13:01,295 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:13:01,298 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:13:01,823 INFO L134 CoverageAnalysis]: Checked inductivity of 1260 backedges. 0 proven. 1260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:13:01,840 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:13:01,841 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 39] total 77 [2018-01-31 10:13:01,841 INFO L409 AbstractCegarLoop]: Interpolant automaton has 77 states [2018-01-31 10:13:01,841 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2018-01-31 10:13:01,842 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1197, Invalid=4655, Unknown=0, NotChecked=0, Total=5852 [2018-01-31 10:13:01,842 INFO L87 Difference]: Start difference. First operand 219 states and 230 transitions. Second operand 77 states. [2018-01-31 10:13:03,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:13:03,042 INFO L93 Difference]: Finished difference Result 256 states and 271 transitions. [2018-01-31 10:13:03,043 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-01-31 10:13:03,043 INFO L78 Accepts]: Start accepts. Automaton has 77 states. Word has length 180 [2018-01-31 10:13:03,043 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:13:03,043 INFO L225 Difference]: With dead ends: 256 [2018-01-31 10:13:03,043 INFO L226 Difference]: Without dead ends: 227 [2018-01-31 10:13:03,044 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 256 GetRequests, 144 SyntacticMatches, 1 SemanticMatches, 111 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3583 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=3339, Invalid=9317, Unknown=0, NotChecked=0, Total=12656 [2018-01-31 10:13:03,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227 states. [2018-01-31 10:13:03,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227 to 227. [2018-01-31 10:13:03,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227 states. [2018-01-31 10:13:03,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227 states to 227 states and 238 transitions. [2018-01-31 10:13:03,047 INFO L78 Accepts]: Start accepts. Automaton has 227 states and 238 transitions. Word has length 180 [2018-01-31 10:13:03,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:13:03,047 INFO L432 AbstractCegarLoop]: Abstraction has 227 states and 238 transitions. [2018-01-31 10:13:03,047 INFO L433 AbstractCegarLoop]: Interpolant automaton has 77 states. [2018-01-31 10:13:03,047 INFO L276 IsEmpty]: Start isEmpty. Operand 227 states and 238 transitions. [2018-01-31 10:13:03,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 189 [2018-01-31 10:13:03,048 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:13:03,048 INFO L351 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:13:03,048 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation]=== [2018-01-31 10:13:03,048 INFO L82 PathProgramCache]: Analyzing trace with hash -151533023, now seen corresponding path program 19 times [2018-01-31 10:13:03,048 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:13:03,048 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:13:03,048 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:13:03,048 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:13:03,048 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:13:03,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-01-31 10:13:03,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-01-31 10:13:03,102 INFO L410 BasicCegarLoop]: Counterexample might be feasible [2018-01-31 10:13:03,103 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] ULTIMATE.startENTRY-->L1: Formula: true InVars {} OutVars{#NULL.offset=|v_#NULL.offset_2|, #NULL.base=|v_#NULL.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[#valid, #NULL.offset, #NULL.base] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] mainENTRY-->L31: Formula: (and (= (select |v_#valid_10| |v_main_~#x~8.base_3|) 0) (= |v_main_~#x~8.offset_3| 0) (not (= |v_main_~#x~8.base_3| 0)) (= |v_#valid_9| (store |v_#valid_10| |v_main_~#x~8.base_3| 1)) (= |v_#length_3| (store |v_#length_4| |v_main_~#x~8.base_3| 80))) InVars {#length=|v_#length_4|, #valid=|v_#valid_10|} OutVars{#length=|v_#length_3|, main_~#x~8.base=|v_main_~#x~8.base_3|, main_~#x~8.offset=|v_main_~#x~8.offset_3|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid, #length, main_~#x~8.base, main_~#x~8.offset] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [433] [433] L31-->L32: Formula: true InVars {} OutVars{#memory_int=|v_#memory_int_3|} AuxVars[] AssignedVars[#memory_int] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [439] [439] L32-->L34: Formula: true InVars {} OutVars{main_~temp~8=v_main_~temp~8_1} AuxVars[] AssignedVars[main_~temp~8] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [443] [443] L34-->L35: Formula: true InVars {} OutVars{main_~ret~8=v_main_~ret~8_1} AuxVars[] AssignedVars[main_~ret~8] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L35-->L36: Formula: true InVars {} OutVars{main_~ret2~8=v_main_~ret2~8_1} AuxVars[] AssignedVars[main_~ret2~8] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [451] [451] L36-->L38: Formula: true InVars {} OutVars{main_~ret5~8=v_main_~ret5~8_1} AuxVars[] AssignedVars[main_~ret5~8] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [457] [457] L38-->L38': Formula: true InVars {} OutVars{main_#t~ret5=|v_main_#t~ret5_1|} AuxVars[] AssignedVars[main_#t~ret5] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [467] [467] L38'-->L38'': Formula: (and (<= 0 (+ |v_main_#t~ret5_2| 2147483648)) (<= |v_main_#t~ret5_2| 2147483647)) InVars {main_#t~ret5=|v_main_#t~ret5_2|} OutVars{main_#t~ret5=|v_main_#t~ret5_2|} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [473] [473] L38''-->L38''': Formula: (= v_main_~ret~8_2 |v_main_#t~ret5_3|) InVars {main_#t~ret5=|v_main_#t~ret5_3|} OutVars{main_~ret~8=v_main_~ret~8_2, main_#t~ret5=|v_main_#t~ret5_3|} AuxVars[] AssignedVars[main_~ret~8] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [479] [479] L38'''-->L40: Formula: true InVars {} OutVars{main_#t~ret5=|v_main_#t~ret5_4|} AuxVars[] AssignedVars[main_#t~ret5] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [485] [485] L40-->L40': Formula: (= (select (select |v_#memory_int_part_locs_30_locs_30_3| |v_main_~#x~8.base_6|) |v_main_~#x~8.offset_6|) |v_main_#t~mem6_1|) InVars {#memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_3|, main_~#x~8.base=|v_main_~#x~8.base_6|, main_~#x~8.offset=|v_main_~#x~8.offset_6|} OutVars{main_#t~mem6=|v_main_#t~mem6_1|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_3|, main_~#x~8.base=|v_main_~#x~8.base_6|, main_~#x~8.offset=|v_main_~#x~8.offset_6|} AuxVars[] AssignedVars[main_#t~mem6] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [491] [491] L40'-->L40'': Formula: (= v_main_~temp~8_2 |v_main_#t~mem6_2|) InVars {main_#t~mem6=|v_main_#t~mem6_2|} OutVars{main_~temp~8=v_main_~temp~8_2, main_#t~mem6=|v_main_#t~mem6_2|} AuxVars[] AssignedVars[main_~temp~8] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [497] [497] L40''-->L40''': Formula: true InVars {} OutVars{main_#t~mem6=|v_main_#t~mem6_3|} AuxVars[] AssignedVars[main_#t~mem6] [2018-01-31 10:13:03,104 INFO L84 mationBacktranslator]: Skipped ATE [503] [503] L40'''-->L40'''': Formula: (= |v_main_#t~mem8_1| (select (select |v_#memory_int_part_locs_30_locs_92_3| |v_main_~#x~8.base_7|) (+ |v_main_~#x~8.offset_7| 4))) InVars {#memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_3|, main_~#x~8.base=|v_main_~#x~8.base_7|, main_~#x~8.offset=|v_main_~#x~8.offset_7|} OutVars{main_#t~mem8=|v_main_#t~mem8_1|, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_3|, main_~#x~8.base=|v_main_~#x~8.base_7|, main_~#x~8.offset=|v_main_~#x~8.offset_7|} AuxVars[] AssignedVars[main_#t~mem8] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [509] [509] L40''''-->L40''''': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_4| |v_#memory_int_part_locs_30_locs_30_5|) (= |v_#memory_int_part_locs_30_locs_92_4| |v_#memory_int_part_locs_30_locs_92_5|) (= |v_#memory_int_part_locs_54_locs_92_3| (store |v_#memory_int_part_locs_54_locs_92_4| |v_main_~#x~8.base_8| (store (select |v_#memory_int_part_locs_30_locs_92_5| |v_main_~#x~8.base_8|) |v_main_~#x~8.offset_8| |v_main_#t~mem8_2|))) (= |v_#memory_int_part_locs_33_locs_30_3| |v_#memory_int_part_locs_33_locs_30_4|) (= |v_#memory_int_part_locs_33_locs_92_3| |v_#memory_int_part_locs_33_locs_92_4|) (= |v_#memory_int_part_locs_54_locs_30_3| (store |v_#memory_int_part_locs_54_locs_30_4| |v_main_~#x~8.base_8| (select |v_#memory_int_part_locs_30_locs_30_5| |v_main_~#x~8.base_8|)))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_4|, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_5|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_4|, main_#t~mem8=|v_main_#t~mem8_2|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_4|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_5|, main_~#x~8.base=|v_main_~#x~8.base_8|, main_~#x~8.offset=|v_main_~#x~8.offset_8|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_4|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_3|, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_4|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_3|, #memory_int=|v_#memory_int_7|, main_#t~mem8=|v_main_#t~mem8_2|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_3|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_4|, main_~#x~8.base=|v_main_~#x~8.base_8|, main_~#x~8.offset=|v_main_~#x~8.offset_8|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_3|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [519] [519] L40'''''-->L40'''''': Formula: true InVars {} OutVars{main_#t~mem8=|v_main_#t~mem8_3|} AuxVars[] AssignedVars[main_#t~mem8] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [529] [529] L40''''''-->L40''''''': Formula: (and (= |v_#memory_int_part_locs_33_locs_92_5| |v_#memory_int_part_locs_33_locs_92_6|) (= |v_#memory_int_part_locs_30_locs_30_6| |v_#memory_int_part_locs_30_locs_30_7|) (= |v_#memory_int_part_locs_54_locs_92_5| (store |v_#memory_int_part_locs_54_locs_92_6| |v_main_~#x~8.base_9| (store (select |v_#memory_int_part_locs_54_locs_92_6| |v_main_~#x~8.base_9|) (+ |v_main_~#x~8.offset_9| 4) v_main_~temp~8_3))) (= |v_#memory_int_part_locs_54_locs_30_5| (store |v_#memory_int_part_locs_54_locs_30_6| |v_main_~#x~8.base_9| (select |v_#memory_int_part_locs_54_locs_30_6| |v_main_~#x~8.base_9|))) (= |v_#memory_int_part_locs_30_locs_92_6| |v_#memory_int_part_locs_30_locs_92_7|) (= |v_#memory_int_part_locs_33_locs_30_5| |v_#memory_int_part_locs_33_locs_30_6|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_6|, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_7|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_6|, main_~temp~8=v_main_~temp~8_3, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_6|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_7|, main_~#x~8.base=|v_main_~#x~8.base_9|, main_~#x~8.offset=|v_main_~#x~8.offset_9|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_6|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_5|, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_6|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_5|, #memory_int=|v_#memory_int_9|, main_~temp~8=v_main_~temp~8_3, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_5|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_6|, main_~#x~8.base=|v_main_~#x~8.base_9|, main_~#x~8.offset=|v_main_~#x~8.offset_9|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_5|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [537] [537] L40'''''''-->L41: Formula: true InVars {} OutVars{main_#t~ret10=|v_main_#t~ret10_1|} AuxVars[] AssignedVars[main_#t~ret10] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L41-->L41': Formula: (and (<= |v_main_#t~ret10_2| 2147483647) (<= 0 (+ |v_main_#t~ret10_2| 2147483648))) InVars {main_#t~ret10=|v_main_#t~ret10_2|} OutVars{main_#t~ret10=|v_main_#t~ret10_2|} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L41'-->L41'': Formula: (= v_main_~ret2~8_2 |v_main_#t~ret10_3|) InVars {main_#t~ret10=|v_main_#t~ret10_3|} OutVars{main_#t~ret10=|v_main_#t~ret10_3|, main_~ret2~8=v_main_~ret2~8_2} AuxVars[] AssignedVars[main_~ret2~8] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [559] [559] L41''-->L42: Formula: true InVars {} OutVars{main_#t~ret10=|v_main_#t~ret10_4|} AuxVars[] AssignedVars[main_#t~ret10] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L42-->L42': Formula: (= (select (select |v_#memory_int_part_locs_54_locs_92_8| |v_main_~#x~8.base_11|) |v_main_~#x~8.offset_11|) |v_main_#t~mem11_1|) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_8|, main_~#x~8.base=|v_main_~#x~8.base_11|, main_~#x~8.offset=|v_main_~#x~8.offset_11|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_8|, main_~#x~8.base=|v_main_~#x~8.base_11|, main_~#x~8.offset=|v_main_~#x~8.offset_11|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L42'-->L42'': Formula: (= v_main_~temp~8_4 |v_main_#t~mem11_2|) InVars {main_#t~mem11=|v_main_#t~mem11_2|} OutVars{main_~temp~8=v_main_~temp~8_4, main_#t~mem11=|v_main_#t~mem11_2|} AuxVars[] AssignedVars[main_~temp~8] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [577] [577] L42''-->L43: Formula: true InVars {} OutVars{main_#t~mem11=|v_main_#t~mem11_3|} AuxVars[] AssignedVars[main_#t~mem11] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [581] [581] L43-->L43'''''': Formula: (= v_main_~i~9_1 0) InVars {} OutVars{main_~i~9=v_main_~i~9_1} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,105 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,106 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,107 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,108 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,109 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,110 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,111 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,112 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,113 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 19) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:13:03,114 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,115 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:13:03,115 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:13:03,115 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,115 INFO L84 mationBacktranslator]: Skipped ATE [591] [591] L43'-->L43''''''': Formula: (not (< v_main_~i~9_2 19)) InVars {main_~i~9=v_main_~i~9_2} OutVars{main_~i~9=v_main_~i~9_2} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,115 INFO L84 mationBacktranslator]: Skipped ATE [595] [595] L43'''''''-->L46: Formula: (and (= |v_#memory_int_part_locs_33_locs_30_7| |v_#memory_int_part_locs_33_locs_30_8|) (= |v_#memory_int_part_locs_54_locs_92_9| (store |v_#memory_int_part_locs_54_locs_92_10| |v_main_~#x~8.base_14| (store (select |v_#memory_int_part_locs_54_locs_92_10| |v_main_~#x~8.base_14|) (+ |v_main_~#x~8.offset_14| 76) v_main_~temp~8_5))) (= |v_#memory_int_part_locs_54_locs_30_7| (store |v_#memory_int_part_locs_54_locs_30_8| |v_main_~#x~8.base_14| (select |v_#memory_int_part_locs_54_locs_30_8| |v_main_~#x~8.base_14|))) (= |v_#memory_int_part_locs_30_locs_92_8| |v_#memory_int_part_locs_30_locs_92_9|) (= |v_#memory_int_part_locs_33_locs_92_7| |v_#memory_int_part_locs_33_locs_92_8|) (= |v_#memory_int_part_locs_30_locs_30_8| |v_#memory_int_part_locs_30_locs_30_9|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_10|, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_9|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_8|, main_~temp~8=v_main_~temp~8_5, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_8|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_9|, main_~#x~8.base=|v_main_~#x~8.base_14|, main_~#x~8.offset=|v_main_~#x~8.offset_14|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_8|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_9|, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_8|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_7|, #memory_int=|v_#memory_int_15|, main_~temp~8=v_main_~temp~8_5, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_7|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_8|, main_~#x~8.base=|v_main_~#x~8.base_14|, main_~#x~8.offset=|v_main_~#x~8.offset_14|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_7|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:13:03,115 INFO L84 mationBacktranslator]: Skipped ATE [599] [599] L46-->L47: Formula: true InVars {} OutVars{main_#t~ret16=|v_main_#t~ret16_1|} AuxVars[] AssignedVars[main_#t~ret16] [2018-01-31 10:13:03,115 INFO L84 mationBacktranslator]: Skipped ATE [551] [551] L47-->L47': Formula: (and (<= 0 (+ |v_main_#t~ret16_2| 2147483648)) (<= |v_main_#t~ret16_2| 2147483647)) InVars {main_#t~ret16=|v_main_#t~ret16_2|} OutVars{main_#t~ret16=|v_main_#t~ret16_2|} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,115 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L47'-->L47'': Formula: (= v_main_~ret5~8_2 |v_main_#t~ret16_3|) InVars {main_#t~ret16=|v_main_#t~ret16_3|} OutVars{main_#t~ret16=|v_main_#t~ret16_3|, main_~ret5~8=v_main_~ret5~8_2} AuxVars[] AssignedVars[main_~ret5~8] [2018-01-31 10:13:03,115 INFO L84 mationBacktranslator]: Skipped ATE [561] [561] L47''-->L49: Formula: true InVars {} OutVars{main_#t~ret16=|v_main_#t~ret16_4|} AuxVars[] AssignedVars[main_#t~ret16] [2018-01-31 10:13:03,115 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L49-->L50: Formula: (or (not (= v_main_~ret2~8_3 v_main_~ret~8_3)) (not (= v_main_~ret5~8_3 v_main_~ret~8_3))) InVars {main_~ret5~8=v_main_~ret5~8_3, main_~ret~8=v_main_~ret~8_3, main_~ret2~8=v_main_~ret2~8_3} OutVars{main_~ret5~8=v_main_~ret5~8_3, main_~ret~8=v_main_~ret~8_3, main_~ret2~8=v_main_~ret2~8_3} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,115 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L50-->mainErr0AssertViolation: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:13:03,118 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 31.01 10:13:03 BasicIcfg [2018-01-31 10:13:03,118 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-31 10:13:03,119 INFO L168 Benchmark]: Toolchain (without parser) took 35420.96 ms. Allocated memory was 151.5 MB in the beginning and 1.3 GB in the end (delta: 1.2 GB). Free memory was 115.9 MB in the beginning and 1.1 GB in the end (delta: -959.1 MB). Peak memory consumption was 193.3 MB. Max. memory is 5.3 GB. [2018-01-31 10:13:03,119 INFO L168 Benchmark]: CDTParser took 0.09 ms. Allocated memory is still 151.5 MB. Free memory is still 121.2 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-31 10:13:03,119 INFO L168 Benchmark]: CACSL2BoogieTranslator took 113.24 ms. Allocated memory is still 151.5 MB. Free memory was 115.9 MB in the beginning and 107.1 MB in the end (delta: 8.9 MB). Peak memory consumption was 8.9 MB. Max. memory is 5.3 GB. [2018-01-31 10:13:03,119 INFO L168 Benchmark]: Boogie Preprocessor took 20.47 ms. Allocated memory is still 151.5 MB. Free memory was 107.1 MB in the beginning and 105.3 MB in the end (delta: 1.8 MB). Peak memory consumption was 1.8 MB. Max. memory is 5.3 GB. [2018-01-31 10:13:03,119 INFO L168 Benchmark]: RCFGBuilder took 385.17 ms. Allocated memory is still 151.5 MB. Free memory was 105.3 MB in the beginning and 85.1 MB in the end (delta: 20.2 MB). Peak memory consumption was 20.2 MB. Max. memory is 5.3 GB. [2018-01-31 10:13:03,120 INFO L168 Benchmark]: IcfgTransformer took 6988.78 ms. Allocated memory was 151.5 MB in the beginning and 856.2 MB in the end (delta: 704.6 MB). Free memory was 85.1 MB in the beginning and 175.0 MB in the end (delta: -90.0 MB). Peak memory consumption was 614.7 MB. Max. memory is 5.3 GB. [2018-01-31 10:13:03,120 INFO L168 Benchmark]: TraceAbstraction took 27910.74 ms. Allocated memory was 856.2 MB in the beginning and 1.3 GB in the end (delta: 447.7 MB). Free memory was 175.0 MB in the beginning and 1.1 GB in the end (delta: -900.0 MB). There was no memory consumed. Max. memory is 5.3 GB. [2018-01-31 10:13:03,121 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.09 ms. Allocated memory is still 151.5 MB. Free memory is still 121.2 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 113.24 ms. Allocated memory is still 151.5 MB. Free memory was 115.9 MB in the beginning and 107.1 MB in the end (delta: 8.9 MB). Peak memory consumption was 8.9 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 20.47 ms. Allocated memory is still 151.5 MB. Free memory was 107.1 MB in the beginning and 105.3 MB in the end (delta: 1.8 MB). Peak memory consumption was 1.8 MB. Max. memory is 5.3 GB. * RCFGBuilder took 385.17 ms. Allocated memory is still 151.5 MB. Free memory was 105.3 MB in the beginning and 85.1 MB in the end (delta: 20.2 MB). Peak memory consumption was 20.2 MB. Max. memory is 5.3 GB. * IcfgTransformer took 6988.78 ms. Allocated memory was 151.5 MB in the beginning and 856.2 MB in the end (delta: 704.6 MB). Free memory was 85.1 MB in the beginning and 175.0 MB in the end (delta: -90.0 MB). Peak memory consumption was 614.7 MB. Max. memory is 5.3 GB. * TraceAbstraction took 27910.74 ms. Allocated memory was 856.2 MB in the beginning and 1.3 GB in the end (delta: 447.7 MB). Free memory was 175.0 MB in the beginning and 1.1 GB in the end (delta: -900.0 MB). There was no memory consumed. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 87 LocStat_MAX_WEQGRAPH_SIZE : 2 LocStat_MAX_SIZEOF_WEQEDGELABEL : 1 LocStat_NO_SUPPORTING_EQUALITIES : 1657 LocStat_NO_SUPPORTING_DISEQUALITIES : 2978 LocStat_NO_DISJUNCTIONS : -174 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 118 TransStat_MAX_WEQGRAPH_SIZE : 2 TransStat_MAX_SIZEOF_WEQEDGELABEL : 1 TransStat_NO_SUPPORTING_EQUALITIES : 175 TransStat_NO_SUPPORTING_DISEQUALITIES : 7 TransStat_NO_DISJUNCTIONS : 116 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.291314 RENAME_VARIABLES(MILLISECONDS) : 0.198985 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.279069 PROJECTAWAY(MILLISECONDS) : 0.085340 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.036200 DISJOIN(MILLISECONDS) : 0.490925 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.211239 ADD_EQUALITY(MILLISECONDS) : 0.004264 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.004979 #CONJOIN_DISJUNCTIVE : 1043 #RENAME_VARIABLES : 2297 #UNFREEZE : 0 #CONJOIN : 1493 #PROJECTAWAY : 1424 #ADD_WEAK_EQUALITY : 14 #DISJOIN : 225 #RENAME_VARIABLES_DISJUNCTIVE : 2331 #ADD_EQUALITY : 180 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 4 * Results from de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: - StatisticsResult: HeapSeparatorStatistics #COUNT_NEW_ARRAY_VARS_[#memory_int] : 6 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_0 : 6 COUNT_BLOCKS_for_[#memory_int]_at_dim_0 : 3 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_1 : 6 COUNT_BLOCKS_for_[#memory_int]_at_dim_1 : 2 COUNT_ARRAY_READS for [#memory_int] : 10 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 50]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 88 locations, 1 error locations. UNSAFE Result, 27.8s OverallTime, 21 OverallIterations, 20 TraceHistogramMax, 11.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1641 SDtfs, 3065 SDslu, 13455 SDs, 0 SdLazy, 3802 SolverSat, 600 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2779 GetRequests, 1678 SyntacticMatches, 19 SemanticMatches, 1082 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23388 ImplicationChecksByTransitivity, 18.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=227occurred in iteration=20, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 20 MinimizatonAttempts, 90 StatesRemovedByMinimization, 18 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 2.7s SatisfiabilityAnalysisTime, 12.7s InterpolantComputationTime, 4291 NumberOfCodeBlocks, 4291 NumberOfCodeBlocksAsserted, 141 NumberOfCheckSat, 4065 ConstructedInterpolants, 0 QuantifiedInterpolants, 2446505 SizeOfPredicates, 365 NumberOfNonLiveVariables, 4122 ConjunctsInSsa, 388 ConjunctsInUnsatCore, 38 InterpolantComputations, 2 PerfectInterpolantSequences, 0/16188 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/rangesum20_false-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-Benchmark-0-2018-01-31_10-13-03-126.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/rangesum20_false-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-VPDomainBenchmark-0-2018-01-31_10-13-03-126.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/rangesum20_false-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-0-2018-01-31_10-13-03-126.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/rangesum20_false-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-HeapSeparatorBenchmark-0-2018-01-31_10-13-03-126.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/rangesum20_false-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-31_10-13-03-126.csv Received shutdown request...