java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/reducercommutativity/sum10_true-unreach-call_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-5f7ec6e-m [2018-01-31 10:29:18,287 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-31 10:29:18,288 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-31 10:29:18,296 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-31 10:29:18,297 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-31 10:29:18,297 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-31 10:29:18,298 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-31 10:29:18,298 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-31 10:29:18,299 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-31 10:29:18,300 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-31 10:29:18,300 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-31 10:29:18,300 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-31 10:29:18,301 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-31 10:29:18,302 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-31 10:29:18,302 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-31 10:29:18,303 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-31 10:29:18,304 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-31 10:29:18,305 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-31 10:29:18,306 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-31 10:29:18,307 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-31 10:29:18,308 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-31 10:29:18,308 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-31 10:29:18,308 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-31 10:29:18,308 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-31 10:29:18,309 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-31 10:29:18,310 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-31 10:29:18,310 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-31 10:29:18,310 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-31 10:29:18,310 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-31 10:29:18,310 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-31 10:29:18,311 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-31 10:29:18,311 INFO L98 SettingsManager]: Beginning loading settings from /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf [2018-01-31 10:29:18,315 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-31 10:29:18,316 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-31 10:29:18,316 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-31 10:29:18,316 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-31 10:29:18,316 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-31 10:29:18,316 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-31 10:29:18,316 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-31 10:29:18,317 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-31 10:29:18,317 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-31 10:29:18,317 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-31 10:29:18,317 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-31 10:29:18,317 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-31 10:29:18,317 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-01-31 10:29:18,317 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-31 10:29:18,317 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-01-31 10:29:18,317 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-31 10:29:18,318 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-01-31 10:29:18,318 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-01-31 10:29:18,318 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-31 10:29:18,318 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-01-31 10:29:18,318 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-31 10:29:18,318 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-31 10:29:18,318 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-31 10:29:18,318 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-31 10:29:18,318 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-31 10:29:18,318 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-31 10:29:18,319 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-31 10:29:18,319 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-31 10:29:18,319 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-31 10:29:18,319 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-31 10:29:18,319 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-31 10:29:18,319 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-31 10:29:18,319 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-31 10:29:18,320 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-31 10:29:18,338 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-31 10:29:18,346 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-31 10:29:18,348 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-31 10:29:18,349 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-31 10:29:18,349 INFO L276 PluginConnector]: CDTParser initialized [2018-01-31 10:29:18,349 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/sum10_true-unreach-call_true-termination.i [2018-01-31 10:29:18,413 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-31 10:29:18,413 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-01-31 10:29:18,414 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-31 10:29:18,414 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-31 10:29:18,423 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-31 10:29:18,423 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.01 10:29:18" (1/1) ... [2018-01-31 10:29:18,425 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@468012d3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:29:18, skipping insertion in model container [2018-01-31 10:29:18,425 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.01 10:29:18" (1/1) ... [2018-01-31 10:29:18,434 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-31 10:29:18,443 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-31 10:29:18,517 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-31 10:29:18,529 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-31 10:29:18,533 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:29:18 WrapperNode [2018-01-31 10:29:18,533 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-31 10:29:18,534 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-31 10:29:18,534 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-31 10:29:18,534 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-31 10:29:18,542 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:29:18" (1/1) ... [2018-01-31 10:29:18,542 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:29:18" (1/1) ... [2018-01-31 10:29:18,548 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:29:18" (1/1) ... [2018-01-31 10:29:18,548 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:29:18" (1/1) ... [2018-01-31 10:29:18,550 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:29:18" (1/1) ... [2018-01-31 10:29:18,552 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:29:18" (1/1) ... [2018-01-31 10:29:18,553 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:29:18" (1/1) ... [2018-01-31 10:29:18,554 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-31 10:29:18,554 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-31 10:29:18,554 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-31 10:29:18,554 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-31 10:29:18,555 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:29:18" (1/1) ... No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-31 10:29:18,596 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-31 10:29:18,596 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-31 10:29:18,596 INFO L136 BoogieDeclarations]: Found implementation of procedure sum [2018-01-31 10:29:18,596 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-31 10:29:18,596 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-31 10:29:18,596 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-31 10:29:18,596 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-31 10:29:18,597 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-31 10:29:18,597 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-31 10:29:18,597 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-31 10:29:18,597 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-31 10:29:18,597 INFO L128 BoogieDeclarations]: Found specification of procedure sum [2018-01-31 10:29:18,597 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-31 10:29:18,597 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-31 10:29:18,597 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-31 10:29:18,954 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-31 10:29:18,954 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:29:18 BoogieIcfgContainer [2018-01-31 10:29:18,955 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-31 10:29:18,955 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2018-01-31 10:29:18,955 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2018-01-31 10:29:18,955 INFO L276 PluginConnector]: IcfgTransformer initialized [2018-01-31 10:29:18,957 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:29:18" (1/1) ... [2018-01-31 10:29:18,962 INFO L103 apSepIcfgTransformer]: HeapSepIcfgTransformer: Starting heap partitioning [2018-01-31 10:29:18,962 INFO L104 apSepIcfgTransformer]: To be partitioned heap arrays found [#memory_int] [2018-01-31 10:29:18,963 INFO L150 apSepIcfgTransformer]: starting freeze-var-style preprocessing [2018-01-31 10:29:18,987 INFO L162 apSepIcfgTransformer]: finished StoreIndexFreezer, created 13 freeze vars and freeze var literals (each corresponds to one heap write) [2018-01-31 10:29:19,005 INFO L221 apSepIcfgTransformer]: finished preprocessing for the equality analysis [2018-01-31 10:29:19,038 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-31 10:30:47,865 INFO L314 AbstractInterpreter]: Visited 91 different actions 690 times. Merged at 63 different actions 327 times. Widened at 1 different actions 1 times. Found 48 fixpoints after 13 different actions. Largest state had 68 variables. [2018-01-31 10:30:47,866 INFO L229 apSepIcfgTransformer]: finished equality analysis [2018-01-31 10:30:47,872 INFO L244 HeapSepPreAnalysis]: Number of read from array group [#memory_int] : 10 [2018-01-31 10:30:47,872 INFO L241 apSepIcfgTransformer]: Finished pre analysis before partitioning [2018-01-31 10:30:47,873 INFO L242 apSepIcfgTransformer]: array groups: Set: [#memory_int] [2018-01-31 10:30:47,873 INFO L244 apSepIcfgTransformer]: select infos: Set: ((select |v_#memory_int_11| |v_main_~#x~5.base_7|), at (SUMMARY for call write~int(~temp~5, ~#x~5.base, ~#x~5.offset + 4, 4); srcloc: L29'''''')) ((select (select |v_#memory_int_12| |v_main_~#x~5.base_9|) |v_main_~#x~5.offset_9|), at (SUMMARY for call #t~mem11 := read~int(~#x~5.base, ~#x~5.offset + 0, 4); srcloc: L31)) ((select (select |v_#memory_int_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4)), at (SUMMARY for call #t~mem14 := read~int(~#x~5.base, ~#x~5.offset + (~i~7 + 1) * 4, 4); srcloc: L33)) ((select (select |v_#memory_int_7| |v_main_~#x~5.base_5|) (+ |v_main_~#x~5.offset_5| 4)), at (SUMMARY for call #t~mem8 := read~int(~#x~5.base, ~#x~5.offset + 4, 4); srcloc: L29''')) ((select (select |v_#memory_int_3| v_sum_~x.base_2) (+ (* 4 v_sum_~i~3_5) v_sum_~x.offset_2)), at (SUMMARY for call #t~mem1 := read~int(~x.base, ~x.offset + ~i~3 * 4, 4); srcloc: L10)) ((select |v_#memory_int_15| |v_main_~#x~5.base_11|), at (SUMMARY for call write~int(#t~mem14, ~#x~5.base, ~#x~5.offset + ~i~7 * 4, 4); srcloc: L33')) ((select |v_#memory_int_9| |v_main_~#x~5.base_6|), at (SUMMARY for call write~int(#t~mem8, ~#x~5.base, ~#x~5.offset + 0, 4); srcloc: L29'''')) ((select |v_#memory_int_17| |v_main_~#x~5.base_12|), at (SUMMARY for call write~int(~temp~5, ~#x~5.base, ~#x~5.offset + 36, 4); srcloc: L32''''''')) ((select |v_#memory_int_5| |v_main_~#x~5.base_2|), at (SUMMARY for call write~int(#t~nondet3, ~#x~5.base, ~#x~5.offset + ~i~6 * 4, 4); srcloc: L24')) ((select (select |v_#memory_int_6| |v_main_~#x~5.base_4|) |v_main_~#x~5.offset_4|), at (SUMMARY for call #t~mem6 := read~int(~#x~5.base, ~#x~5.offset + 0, 4); srcloc: L29)) [2018-01-31 10:30:47,891 INFO L547 PartitionManager]: partitioning result: [2018-01-31 10:30:47,892 INFO L552 PartitionManager]: location blocks for array group [#memory_int] [2018-01-31 10:30:47,892 INFO L562 PartitionManager]: at dimension 0 [2018-01-31 10:30:47,892 INFO L563 PartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 5 [2018-01-31 10:30:47,892 INFO L564 PartitionManager]: # location blocks :1 [2018-01-31 10:30:47,892 INFO L562 PartitionManager]: at dimension 1 [2018-01-31 10:30:47,892 INFO L563 PartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 5 [2018-01-31 10:30:47,892 INFO L564 PartitionManager]: # location blocks :1 [2018-01-31 10:30:47,893 INFO L86 ransitionTransformer]: executing heap partitioning transformation [2018-01-31 10:30:47,908 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 31.01 10:30:47 BasicIcfg [2018-01-31 10:30:47,908 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2018-01-31 10:30:47,908 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-31 10:30:47,908 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-31 10:30:47,910 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-31 10:30:47,910 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 31.01 10:29:18" (1/4) ... [2018-01-31 10:30:47,911 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@58bcabb9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 31.01 10:30:47, skipping insertion in model container [2018-01-31 10:30:47,911 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:29:18" (2/4) ... [2018-01-31 10:30:47,911 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@58bcabb9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 31.01 10:30:47, skipping insertion in model container [2018-01-31 10:30:47,911 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:29:18" (3/4) ... [2018-01-31 10:30:47,911 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@58bcabb9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 31.01 10:30:47, skipping insertion in model container [2018-01-31 10:30:47,912 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 31.01 10:30:47" (4/4) ... [2018-01-31 10:30:47,913 INFO L107 eAbstractionObserver]: Analyzing ICFG HeapSeparatedIcfg [2018-01-31 10:30:47,919 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-31 10:30:47,924 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-01-31 10:30:47,944 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-31 10:30:47,944 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-31 10:30:47,944 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-31 10:30:47,944 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-31 10:30:47,944 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-31 10:30:47,944 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-31 10:30:47,944 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-31 10:30:47,944 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-31 10:30:47,945 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-31 10:30:47,951 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states. [2018-01-31 10:30:47,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-31 10:30:47,956 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:47,957 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:47,957 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation]=== [2018-01-31 10:30:47,959 INFO L82 PathProgramCache]: Analyzing trace with hash 119124891, now seen corresponding path program 1 times [2018-01-31 10:30:47,960 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:47,960 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:47,991 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:47,991 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:30:47,991 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:48,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:48,013 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:30:48,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:30:48,033 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-31 10:30:48,033 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-31 10:30:48,034 INFO L409 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-01-31 10:30:48,039 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-01-31 10:30:48,040 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-31 10:30:48,041 INFO L87 Difference]: Start difference. First operand 78 states. Second operand 2 states. [2018-01-31 10:30:48,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:30:48,056 INFO L93 Difference]: Finished difference Result 136 states and 161 transitions. [2018-01-31 10:30:48,056 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-01-31 10:30:48,056 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 36 [2018-01-31 10:30:48,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:30:48,061 INFO L225 Difference]: With dead ends: 136 [2018-01-31 10:30:48,062 INFO L226 Difference]: Without dead ends: 71 [2018-01-31 10:30:48,064 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-31 10:30:48,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-01-31 10:30:48,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 71. [2018-01-31 10:30:48,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-01-31 10:30:48,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 79 transitions. [2018-01-31 10:30:48,087 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 79 transitions. Word has length 36 [2018-01-31 10:30:48,087 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:30:48,088 INFO L432 AbstractCegarLoop]: Abstraction has 71 states and 79 transitions. [2018-01-31 10:30:48,088 INFO L433 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-01-31 10:30:48,088 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 79 transitions. [2018-01-31 10:30:48,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-01-31 10:30:48,089 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:48,089 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:48,089 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation]=== [2018-01-31 10:30:48,090 INFO L82 PathProgramCache]: Analyzing trace with hash 320115213, now seen corresponding path program 1 times [2018-01-31 10:30:48,090 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:48,090 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:48,090 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:48,091 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:30:48,091 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:48,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:48,098 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:30:48,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:30:48,153 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-31 10:30:48,153 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-31 10:30:48,154 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-31 10:30:48,154 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-31 10:30:48,154 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-31 10:30:48,154 INFO L87 Difference]: Start difference. First operand 71 states and 79 transitions. Second operand 3 states. [2018-01-31 10:30:48,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:30:48,193 INFO L93 Difference]: Finished difference Result 129 states and 144 transitions. [2018-01-31 10:30:48,197 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-31 10:30:48,197 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 38 [2018-01-31 10:30:48,197 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:30:48,198 INFO L225 Difference]: With dead ends: 129 [2018-01-31 10:30:48,198 INFO L226 Difference]: Without dead ends: 78 [2018-01-31 10:30:48,199 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-31 10:30:48,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2018-01-31 10:30:48,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 73. [2018-01-31 10:30:48,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-01-31 10:30:48,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 81 transitions. [2018-01-31 10:30:48,207 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 81 transitions. Word has length 38 [2018-01-31 10:30:48,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:30:48,208 INFO L432 AbstractCegarLoop]: Abstraction has 73 states and 81 transitions. [2018-01-31 10:30:48,208 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-31 10:30:48,208 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 81 transitions. [2018-01-31 10:30:48,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-01-31 10:30:48,209 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:48,209 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:48,209 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation]=== [2018-01-31 10:30:48,209 INFO L82 PathProgramCache]: Analyzing trace with hash 1650744741, now seen corresponding path program 1 times [2018-01-31 10:30:48,209 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:48,209 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:48,210 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:48,210 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:30:48,210 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:48,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:48,222 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:30:48,330 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:30:48,330 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:30:48,330 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:30:48,357 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:30:48,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:48,392 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:30:48,462 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-31 10:30:48,479 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-01-31 10:30:48,479 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-01-31 10:30:48,479 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-31 10:30:48,479 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-31 10:30:48,480 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-01-31 10:30:48,480 INFO L87 Difference]: Start difference. First operand 73 states and 81 transitions. Second operand 6 states. [2018-01-31 10:30:48,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:30:48,590 INFO L93 Difference]: Finished difference Result 144 states and 160 transitions. [2018-01-31 10:30:48,590 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-31 10:30:48,590 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 46 [2018-01-31 10:30:48,590 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:30:48,591 INFO L225 Difference]: With dead ends: 144 [2018-01-31 10:30:48,591 INFO L226 Difference]: Without dead ends: 93 [2018-01-31 10:30:48,591 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-01-31 10:30:48,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-01-31 10:30:48,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 83. [2018-01-31 10:30:48,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2018-01-31 10:30:48,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 91 transitions. [2018-01-31 10:30:48,595 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 91 transitions. Word has length 46 [2018-01-31 10:30:48,596 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:30:48,596 INFO L432 AbstractCegarLoop]: Abstraction has 83 states and 91 transitions. [2018-01-31 10:30:48,596 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-31 10:30:48,596 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 91 transitions. [2018-01-31 10:30:48,597 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-31 10:30:48,597 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:48,597 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:48,597 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation]=== [2018-01-31 10:30:48,597 INFO L82 PathProgramCache]: Analyzing trace with hash -621479573, now seen corresponding path program 1 times [2018-01-31 10:30:48,597 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:48,597 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:48,598 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:48,598 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:30:48,598 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:48,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:48,609 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:30:48,662 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-01-31 10:30:48,662 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:30:48,662 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:30:48,677 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:30:48,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:48,702 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:30:48,787 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-31 10:30:48,804 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:30:48,804 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 7] total 10 [2018-01-31 10:30:48,804 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-31 10:30:48,804 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-31 10:30:48,804 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2018-01-31 10:30:48,804 INFO L87 Difference]: Start difference. First operand 83 states and 91 transitions. Second operand 10 states. [2018-01-31 10:30:49,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:30:49,162 INFO L93 Difference]: Finished difference Result 162 states and 178 transitions. [2018-01-31 10:30:49,162 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-31 10:30:49,162 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 62 [2018-01-31 10:30:49,162 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:30:49,163 INFO L225 Difference]: With dead ends: 162 [2018-01-31 10:30:49,163 INFO L226 Difference]: Without dead ends: 109 [2018-01-31 10:30:49,163 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 58 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=180, Unknown=0, NotChecked=0, Total=240 [2018-01-31 10:30:49,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-01-31 10:30:49,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 99. [2018-01-31 10:30:49,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-01-31 10:30:49,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 107 transitions. [2018-01-31 10:30:49,169 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 107 transitions. Word has length 62 [2018-01-31 10:30:49,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:30:49,170 INFO L432 AbstractCegarLoop]: Abstraction has 99 states and 107 transitions. [2018-01-31 10:30:49,170 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-31 10:30:49,170 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 107 transitions. [2018-01-31 10:30:49,173 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-31 10:30:49,173 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:49,173 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:49,173 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation]=== [2018-01-31 10:30:49,173 INFO L82 PathProgramCache]: Analyzing trace with hash -1813102799, now seen corresponding path program 2 times [2018-01-31 10:30:49,173 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:49,173 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:49,174 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:49,174 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:30:49,174 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:49,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:49,199 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:30:49,512 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-01-31 10:30:49,512 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:30:49,512 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:30:49,516 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-31 10:30:49,533 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:49,545 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:49,550 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:30:49,552 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:30:49,672 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-01-31 10:30:49,689 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:30:49,689 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 9] total 14 [2018-01-31 10:30:49,689 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-31 10:30:49,689 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-31 10:30:49,690 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=144, Unknown=0, NotChecked=0, Total=182 [2018-01-31 10:30:49,690 INFO L87 Difference]: Start difference. First operand 99 states and 107 transitions. Second operand 14 states. [2018-01-31 10:30:50,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:30:50,057 INFO L93 Difference]: Finished difference Result 186 states and 202 transitions. [2018-01-31 10:30:50,058 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-31 10:30:50,058 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 78 [2018-01-31 10:30:50,058 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:30:50,059 INFO L225 Difference]: With dead ends: 186 [2018-01-31 10:30:50,059 INFO L226 Difference]: Without dead ends: 125 [2018-01-31 10:30:50,060 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 72 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 74 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=120, Invalid=432, Unknown=0, NotChecked=0, Total=552 [2018-01-31 10:30:50,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2018-01-31 10:30:50,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 115. [2018-01-31 10:30:50,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-01-31 10:30:50,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 123 transitions. [2018-01-31 10:30:50,067 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 123 transitions. Word has length 78 [2018-01-31 10:30:50,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:30:50,067 INFO L432 AbstractCegarLoop]: Abstraction has 115 states and 123 transitions. [2018-01-31 10:30:50,067 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-31 10:30:50,067 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 123 transitions. [2018-01-31 10:30:50,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-01-31 10:30:50,068 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:50,068 INFO L351 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:50,068 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation]=== [2018-01-31 10:30:50,069 INFO L82 PathProgramCache]: Analyzing trace with hash -244961545, now seen corresponding path program 3 times [2018-01-31 10:30:50,069 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:50,069 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:50,069 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:50,069 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:30:50,069 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:50,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:50,080 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:30:50,151 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-01-31 10:30:50,151 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:30:50,152 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:30:50,156 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-31 10:30:50,182 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:30:50,184 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:30:50,190 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:30:50,199 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:30:50,200 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:30:50,201 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:30:50,265 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-01-31 10:30:50,282 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:30:50,282 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 9] total 18 [2018-01-31 10:30:50,283 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-31 10:30:50,283 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-31 10:30:50,283 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=248, Unknown=0, NotChecked=0, Total=306 [2018-01-31 10:30:50,283 INFO L87 Difference]: Start difference. First operand 115 states and 123 transitions. Second operand 18 states. [2018-01-31 10:30:50,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:30:50,562 INFO L93 Difference]: Finished difference Result 210 states and 226 transitions. [2018-01-31 10:30:50,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-31 10:30:50,562 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 94 [2018-01-31 10:30:50,563 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:30:50,563 INFO L225 Difference]: With dead ends: 210 [2018-01-31 10:30:50,563 INFO L226 Difference]: Without dead ends: 141 [2018-01-31 10:30:50,564 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 158 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=200, Invalid=792, Unknown=0, NotChecked=0, Total=992 [2018-01-31 10:30:50,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-01-31 10:30:50,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 131. [2018-01-31 10:30:50,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-01-31 10:30:50,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 139 transitions. [2018-01-31 10:30:50,579 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 139 transitions. Word has length 94 [2018-01-31 10:30:50,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:30:50,579 INFO L432 AbstractCegarLoop]: Abstraction has 131 states and 139 transitions. [2018-01-31 10:30:50,579 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-31 10:30:50,579 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 139 transitions. [2018-01-31 10:30:50,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-01-31 10:30:50,586 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:50,586 INFO L351 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:50,586 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation]=== [2018-01-31 10:30:50,586 INFO L82 PathProgramCache]: Analyzing trace with hash 561170621, now seen corresponding path program 4 times [2018-01-31 10:30:50,586 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:50,586 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:50,587 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:50,587 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:30:50,587 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:50,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:50,613 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:30:50,778 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-01-31 10:30:50,778 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:30:50,778 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:30:50,783 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-31 10:30:50,807 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:30:50,809 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:30:51,021 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-01-31 10:30:51,040 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:30:51,041 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 15 [2018-01-31 10:30:51,041 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-31 10:30:51,041 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-31 10:30:51,041 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=147, Unknown=0, NotChecked=0, Total=210 [2018-01-31 10:30:51,041 INFO L87 Difference]: Start difference. First operand 131 states and 139 transitions. Second operand 15 states. [2018-01-31 10:30:51,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:30:51,162 INFO L93 Difference]: Finished difference Result 221 states and 236 transitions. [2018-01-31 10:30:51,162 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-31 10:30:51,162 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 110 [2018-01-31 10:30:51,163 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:30:51,163 INFO L225 Difference]: With dead ends: 221 [2018-01-31 10:30:51,163 INFO L226 Difference]: Without dead ends: 144 [2018-01-31 10:30:51,164 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 132 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=196, Invalid=404, Unknown=0, NotChecked=0, Total=600 [2018-01-31 10:30:51,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-01-31 10:30:51,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 139. [2018-01-31 10:30:51,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-01-31 10:30:51,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 147 transitions. [2018-01-31 10:30:51,172 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 147 transitions. Word has length 110 [2018-01-31 10:30:51,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:30:51,173 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 147 transitions. [2018-01-31 10:30:51,173 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-31 10:30:51,173 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 147 transitions. [2018-01-31 10:30:51,173 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-01-31 10:30:51,173 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:51,174 INFO L351 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 6, 6, 5, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:51,174 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation]=== [2018-01-31 10:30:51,174 INFO L82 PathProgramCache]: Analyzing trace with hash 1493220437, now seen corresponding path program 5 times [2018-01-31 10:30:51,174 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:51,174 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:51,174 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:51,174 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:30:51,174 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:51,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:51,185 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:30:51,308 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-01-31 10:30:51,308 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:30:51,308 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:30:51,313 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-31 10:30:51,323 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:51,324 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:51,325 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:51,328 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:51,332 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:51,351 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:51,368 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:51,369 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:30:51,371 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:30:51,488 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:30:51,507 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:30:51,507 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 11] total 24 [2018-01-31 10:30:51,508 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-31 10:30:51,508 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-31 10:30:51,508 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=455, Unknown=0, NotChecked=0, Total=552 [2018-01-31 10:30:51,508 INFO L87 Difference]: Start difference. First operand 139 states and 147 transitions. Second operand 24 states. [2018-01-31 10:30:51,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:30:51,876 INFO L93 Difference]: Finished difference Result 242 states and 258 transitions. [2018-01-31 10:30:51,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-01-31 10:30:51,879 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 118 [2018-01-31 10:30:51,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:30:51,880 INFO L225 Difference]: With dead ends: 242 [2018-01-31 10:30:51,880 INFO L226 Difference]: Without dead ends: 165 [2018-01-31 10:30:51,881 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 152 GetRequests, 110 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 331 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=365, Invalid=1527, Unknown=0, NotChecked=0, Total=1892 [2018-01-31 10:30:51,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-01-31 10:30:51,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 155. [2018-01-31 10:30:51,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 155 states. [2018-01-31 10:30:51,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 163 transitions. [2018-01-31 10:30:51,892 INFO L78 Accepts]: Start accepts. Automaton has 155 states and 163 transitions. Word has length 118 [2018-01-31 10:30:51,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:30:51,892 INFO L432 AbstractCegarLoop]: Abstraction has 155 states and 163 transitions. [2018-01-31 10:30:51,892 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-31 10:30:51,893 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 163 transitions. [2018-01-31 10:30:51,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-01-31 10:30:51,893 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:51,893 INFO L351 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 7, 7, 6, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:51,894 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation]=== [2018-01-31 10:30:51,894 INFO L82 PathProgramCache]: Analyzing trace with hash -1135751141, now seen corresponding path program 6 times [2018-01-31 10:30:51,894 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:51,894 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:51,894 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:51,894 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:30:51,894 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:51,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:51,914 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:30:52,098 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-01-31 10:30:52,098 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:30:52,098 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:30:52,104 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-31 10:30:52,113 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:30:52,114 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:30:52,117 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:30:52,119 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:30:52,124 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:30:52,130 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:30:52,137 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:30:52,167 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:30:52,168 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:30:52,169 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:30:52,296 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2018-01-31 10:30:52,313 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:30:52,314 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 13] total 28 [2018-01-31 10:30:52,314 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-31 10:30:52,314 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-31 10:30:52,314 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=629, Unknown=0, NotChecked=0, Total=756 [2018-01-31 10:30:52,315 INFO L87 Difference]: Start difference. First operand 155 states and 163 transitions. Second operand 28 states. [2018-01-31 10:30:52,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:30:52,926 INFO L93 Difference]: Finished difference Result 266 states and 282 transitions. [2018-01-31 10:30:52,928 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-01-31 10:30:52,928 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 134 [2018-01-31 10:30:52,928 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:30:52,928 INFO L225 Difference]: With dead ends: 266 [2018-01-31 10:30:52,928 INFO L226 Difference]: Without dead ends: 181 [2018-01-31 10:30:52,930 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 174 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 481 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=495, Invalid=2157, Unknown=0, NotChecked=0, Total=2652 [2018-01-31 10:30:52,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2018-01-31 10:30:52,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 171. [2018-01-31 10:30:52,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-01-31 10:30:52,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 179 transitions. [2018-01-31 10:30:52,933 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 179 transitions. Word has length 134 [2018-01-31 10:30:52,933 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:30:52,933 INFO L432 AbstractCegarLoop]: Abstraction has 171 states and 179 transitions. [2018-01-31 10:30:52,943 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-31 10:30:52,943 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 179 transitions. [2018-01-31 10:30:52,944 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-01-31 10:30:52,944 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:52,944 INFO L351 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 8, 8, 8, 7, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:52,944 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation]=== [2018-01-31 10:30:52,944 INFO L82 PathProgramCache]: Analyzing trace with hash -423916063, now seen corresponding path program 7 times [2018-01-31 10:30:52,944 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:52,944 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:52,945 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:52,945 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:30:52,945 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:52,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:52,970 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:30:53,163 INFO L134 CoverageAnalysis]: Checked inductivity of 372 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:30:53,164 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:30:53,164 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:30:53,191 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:30:53,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:53,210 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:30:53,236 INFO L134 CoverageAnalysis]: Checked inductivity of 372 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:30:53,253 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:30:53,253 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 21 [2018-01-31 10:30:53,253 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-31 10:30:53,253 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-31 10:30:53,253 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-01-31 10:30:53,253 INFO L87 Difference]: Start difference. First operand 171 states and 179 transitions. Second operand 21 states. [2018-01-31 10:30:53,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:30:53,498 INFO L93 Difference]: Finished difference Result 277 states and 292 transitions. [2018-01-31 10:30:53,500 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-31 10:30:53,500 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 150 [2018-01-31 10:30:53,501 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:30:53,501 INFO L225 Difference]: With dead ends: 277 [2018-01-31 10:30:53,501 INFO L226 Difference]: Without dead ends: 184 [2018-01-31 10:30:53,502 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 149 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 244 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=427, Invalid=905, Unknown=0, NotChecked=0, Total=1332 [2018-01-31 10:30:53,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-01-31 10:30:53,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 179. [2018-01-31 10:30:53,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179 states. [2018-01-31 10:30:53,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 187 transitions. [2018-01-31 10:30:53,505 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 187 transitions. Word has length 150 [2018-01-31 10:30:53,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:30:53,505 INFO L432 AbstractCegarLoop]: Abstraction has 179 states and 187 transitions. [2018-01-31 10:30:53,505 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-31 10:30:53,505 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 187 transitions. [2018-01-31 10:30:53,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-01-31 10:30:53,506 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:53,506 INFO L351 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 9, 9, 9, 7, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:53,506 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation]=== [2018-01-31 10:30:53,507 INFO L82 PathProgramCache]: Analyzing trace with hash 1429473657, now seen corresponding path program 8 times [2018-01-31 10:30:53,507 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:53,507 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:53,507 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:53,507 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:30:53,507 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:53,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:53,517 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:30:53,900 INFO L134 CoverageAnalysis]: Checked inductivity of 438 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:30:53,900 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:30:53,900 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:30:53,905 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-31 10:30:53,912 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:53,926 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:53,928 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:30:53,930 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:30:53,972 INFO L134 CoverageAnalysis]: Checked inductivity of 438 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:30:53,989 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:30:53,989 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 23 [2018-01-31 10:30:53,990 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-31 10:30:53,990 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-31 10:30:53,990 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=363, Unknown=0, NotChecked=0, Total=506 [2018-01-31 10:30:53,990 INFO L87 Difference]: Start difference. First operand 179 states and 187 transitions. Second operand 23 states. [2018-01-31 10:30:54,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:30:54,249 INFO L93 Difference]: Finished difference Result 280 states and 295 transitions. [2018-01-31 10:30:54,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-31 10:30:54,249 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 158 [2018-01-31 10:30:54,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:30:54,250 INFO L225 Difference]: With dead ends: 280 [2018-01-31 10:30:54,250 INFO L226 Difference]: Without dead ends: 187 [2018-01-31 10:30:54,251 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 157 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 303 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=524, Invalid=1116, Unknown=0, NotChecked=0, Total=1640 [2018-01-31 10:30:54,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2018-01-31 10:30:54,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 187. [2018-01-31 10:30:54,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 187 states. [2018-01-31 10:30:54,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 195 transitions. [2018-01-31 10:30:54,254 INFO L78 Accepts]: Start accepts. Automaton has 187 states and 195 transitions. Word has length 158 [2018-01-31 10:30:54,254 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:30:54,254 INFO L432 AbstractCegarLoop]: Abstraction has 187 states and 195 transitions. [2018-01-31 10:30:54,254 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-31 10:30:54,254 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 195 transitions. [2018-01-31 10:30:54,255 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2018-01-31 10:30:54,255 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:54,255 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 10, 10, 7, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:54,255 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation]=== [2018-01-31 10:30:54,255 INFO L82 PathProgramCache]: Analyzing trace with hash -1247580911, now seen corresponding path program 9 times [2018-01-31 10:30:54,255 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:54,255 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:54,256 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:54,256 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:30:54,256 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:54,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:54,265 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:30:54,412 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-01-31 10:30:54,412 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:30:54,412 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:30:54,439 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-31 10:30:54,447 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:30:54,449 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:30:54,452 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:30:54,467 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:30:54,488 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:30:54,527 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:30:54,623 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:30:54,624 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:30:54,627 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:30:54,653 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-01-31 10:30:54,671 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:30:54,671 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 17 [2018-01-31 10:30:54,671 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-31 10:30:54,671 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-31 10:30:54,671 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=192, Unknown=0, NotChecked=0, Total=272 [2018-01-31 10:30:54,671 INFO L87 Difference]: Start difference. First operand 187 states and 195 transitions. Second operand 17 states. [2018-01-31 10:30:54,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:30:54,818 INFO L93 Difference]: Finished difference Result 224 states and 234 transitions. [2018-01-31 10:30:54,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-31 10:30:54,818 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 166 [2018-01-31 10:30:54,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:30:54,819 INFO L225 Difference]: With dead ends: 224 [2018-01-31 10:30:54,819 INFO L226 Difference]: Without dead ends: 200 [2018-01-31 10:30:54,819 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 192 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 144 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=263, Invalid=549, Unknown=0, NotChecked=0, Total=812 [2018-01-31 10:30:54,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states. [2018-01-31 10:30:54,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 195. [2018-01-31 10:30:54,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 195 states. [2018-01-31 10:30:54,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 203 transitions. [2018-01-31 10:30:54,822 INFO L78 Accepts]: Start accepts. Automaton has 195 states and 203 transitions. Word has length 166 [2018-01-31 10:30:54,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:30:54,822 INFO L432 AbstractCegarLoop]: Abstraction has 195 states and 203 transitions. [2018-01-31 10:30:54,822 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-31 10:30:54,822 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 203 transitions. [2018-01-31 10:30:54,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-01-31 10:30:54,823 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:54,823 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 10, 10, 8, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:54,823 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation]=== [2018-01-31 10:30:54,823 INFO L82 PathProgramCache]: Analyzing trace with hash -1520549569, now seen corresponding path program 10 times [2018-01-31 10:30:54,824 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:54,824 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:54,824 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:54,824 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:30:54,824 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:54,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:54,833 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:30:55,374 INFO L134 CoverageAnalysis]: Checked inductivity of 562 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-01-31 10:30:55,375 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:30:55,375 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:30:55,384 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-31 10:30:55,403 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:30:55,405 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:30:55,435 INFO L134 CoverageAnalysis]: Checked inductivity of 562 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-01-31 10:30:55,467 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:30:55,467 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 19 [2018-01-31 10:30:55,467 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-31 10:30:55,467 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-31 10:30:55,468 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=99, Invalid=243, Unknown=0, NotChecked=0, Total=342 [2018-01-31 10:30:55,468 INFO L87 Difference]: Start difference. First operand 195 states and 203 transitions. Second operand 19 states. [2018-01-31 10:30:55,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:30:55,674 INFO L93 Difference]: Finished difference Result 232 states and 242 transitions. [2018-01-31 10:30:55,674 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-31 10:30:55,675 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 174 [2018-01-31 10:30:55,675 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:30:55,675 INFO L225 Difference]: With dead ends: 232 [2018-01-31 10:30:55,675 INFO L226 Difference]: Without dead ends: 208 [2018-01-31 10:30:55,676 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 204 GetRequests, 173 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 191 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=340, Invalid=716, Unknown=0, NotChecked=0, Total=1056 [2018-01-31 10:30:55,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states. [2018-01-31 10:30:55,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 203. [2018-01-31 10:30:55,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-01-31 10:30:55,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 211 transitions. [2018-01-31 10:30:55,678 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 211 transitions. Word has length 174 [2018-01-31 10:30:55,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:30:55,679 INFO L432 AbstractCegarLoop]: Abstraction has 203 states and 211 transitions. [2018-01-31 10:30:55,679 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-31 10:30:55,679 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 211 transitions. [2018-01-31 10:30:55,679 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-01-31 10:30:55,679 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:55,679 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 10, 10, 9, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:55,680 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation]=== [2018-01-31 10:30:55,680 INFO L82 PathProgramCache]: Analyzing trace with hash -1957623955, now seen corresponding path program 11 times [2018-01-31 10:30:55,680 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:55,680 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:55,680 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:55,680 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:30:55,680 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:55,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:30:55,689 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:30:55,927 INFO L134 CoverageAnalysis]: Checked inductivity of 620 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-01-31 10:30:55,928 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:30:55,928 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-31 10:30:55,940 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:30:55,947 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:55,957 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:55,958 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:55,961 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:55,965 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:55,973 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:56,024 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:56,074 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:56,108 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:56,291 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:56,603 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:30:56,605 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:30:56,608 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:30:56,676 INFO L134 CoverageAnalysis]: Checked inductivity of 620 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-01-31 10:30:56,694 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:30:56,695 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 21 [2018-01-31 10:30:56,695 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-31 10:30:56,695 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-31 10:30:56,695 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-01-31 10:30:56,695 INFO L87 Difference]: Start difference. First operand 203 states and 211 transitions. Second operand 21 states. [2018-01-31 10:30:56,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:30:56,926 INFO L93 Difference]: Finished difference Result 235 states and 245 transitions. [2018-01-31 10:30:56,926 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-31 10:30:56,926 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 182 [2018-01-31 10:30:56,927 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:30:56,927 INFO L225 Difference]: With dead ends: 235 [2018-01-31 10:30:56,927 INFO L226 Difference]: Without dead ends: 211 [2018-01-31 10:30:56,928 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 216 GetRequests, 181 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 244 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=427, Invalid=905, Unknown=0, NotChecked=0, Total=1332 [2018-01-31 10:30:56,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states. [2018-01-31 10:30:56,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 211. [2018-01-31 10:30:56,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 211 states. [2018-01-31 10:30:56,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 211 states to 211 states and 219 transitions. [2018-01-31 10:30:56,930 INFO L78 Accepts]: Start accepts. Automaton has 211 states and 219 transitions. Word has length 182 [2018-01-31 10:30:56,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:30:56,930 INFO L432 AbstractCegarLoop]: Abstraction has 211 states and 219 transitions. [2018-01-31 10:30:56,931 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-31 10:30:56,931 INFO L276 IsEmpty]: Start isEmpty. Operand 211 states and 219 transitions. [2018-01-31 10:30:56,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2018-01-31 10:30:56,931 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:30:56,931 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:30:56,931 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation]=== [2018-01-31 10:30:56,931 INFO L82 PathProgramCache]: Analyzing trace with hash -244727909, now seen corresponding path program 12 times [2018-01-31 10:30:56,931 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:30:56,932 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:30:56,932 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:56,932 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:30:56,932 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:30:56,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-01-31 10:30:56,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-01-31 10:30:57,001 INFO L410 BasicCegarLoop]: Counterexample might be feasible [2018-01-31 10:30:57,002 INFO L84 mationBacktranslator]: Skipped ATE [365] [365] ULTIMATE.startENTRY-->L1: Formula: true InVars {} OutVars{#NULL.offset=|v_#NULL.offset_2|, #NULL.base=|v_#NULL.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[#valid, #NULL.offset, #NULL.base] [2018-01-31 10:30:57,002 INFO L84 mationBacktranslator]: Skipped ATE [371] [371] L1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [377] [377] mainENTRY-->L17: Formula: (and (= |v_#length_3| (store |v_#length_4| |v_main_~#x~5.base_1| 40)) (not (= 0 |v_main_~#x~5.base_1|)) (= |v_main_~#x~5.offset_1| 0) (= (store |v_#valid_8| |v_main_~#x~5.base_1| 1) |v_#valid_7|) (= 0 (select |v_#valid_8| |v_main_~#x~5.base_1|))) InVars {#length=|v_#length_4|, #valid=|v_#valid_8|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_1|, #length=|v_#length_3|, main_~#x~5.offset=|v_main_~#x~5.offset_1|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[main_~#x~5.base, main_~#x~5.offset, #valid, #length] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [381] [381] L17-->L19: Formula: true InVars {} OutVars{main_~temp~5=v_main_~temp~5_1} AuxVars[] AssignedVars[main_~temp~5] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [385] [385] L19-->L20: Formula: true InVars {} OutVars{main_~ret~5=v_main_~ret~5_1} AuxVars[] AssignedVars[main_~ret~5] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [387] [387] L20-->L21: Formula: true InVars {} OutVars{main_~ret2~5=v_main_~ret2~5_1} AuxVars[] AssignedVars[main_~ret2~5] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [389] [389] L21-->L23: Formula: true InVars {} OutVars{main_~ret5~5=v_main_~ret5~5_1} AuxVars[] AssignedVars[main_~ret5~5] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [391] [391] L23-->L23'''''': Formula: (= v_main_~i~6_1 0) InVars {} OutVars{main_~i~6=v_main_~i~6_1} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [393] [393] L23''''''-->L23': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [399] [399] L23'-->L24: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [405] [405] L24-->L24': Formula: (and (<= 0 (+ |v_main_#t~nondet3_1| 2147483648)) (<= |v_main_#t~nondet3_1| 2147483647)) InVars {main_#t~nondet3=|v_main_#t~nondet3_1|} OutVars{main_#t~nondet3=|v_main_#t~nondet3_1|} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [411] [411] L24'-->L24'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet3_2|))) InVars {main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_4|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L24''-->L23''': Formula: true InVars {} OutVars{main_#t~nondet3=|v_main_#t~nondet3_3|} AuxVars[] AssignedVars[main_#t~nondet3] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L23'''-->L23'''': Formula: (= |v_main_#t~post2_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post2=|v_main_#t~post2_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L23''''-->L23''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post2_2| 1)) InVars {main_#t~post2=|v_main_#t~post2_2|} OutVars{main_#t~post2=|v_main_#t~post2_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L23'''''-->L23'''''': Formula: true InVars {} OutVars{main_#t~post2=|v_main_#t~post2_3|} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [393] [393] L23''''''-->L23': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,003 INFO L84 mationBacktranslator]: Skipped ATE [399] [399] L23'-->L24: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [405] [405] L24-->L24': Formula: (and (<= 0 (+ |v_main_#t~nondet3_1| 2147483648)) (<= |v_main_#t~nondet3_1| 2147483647)) InVars {main_#t~nondet3=|v_main_#t~nondet3_1|} OutVars{main_#t~nondet3=|v_main_#t~nondet3_1|} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [411] [411] L24'-->L24'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet3_2|))) InVars {main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_4|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L24''-->L23''': Formula: true InVars {} OutVars{main_#t~nondet3=|v_main_#t~nondet3_3|} AuxVars[] AssignedVars[main_#t~nondet3] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L23'''-->L23'''': Formula: (= |v_main_#t~post2_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post2=|v_main_#t~post2_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L23''''-->L23''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post2_2| 1)) InVars {main_#t~post2=|v_main_#t~post2_2|} OutVars{main_#t~post2=|v_main_#t~post2_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L23'''''-->L23'''''': Formula: true InVars {} OutVars{main_#t~post2=|v_main_#t~post2_3|} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [393] [393] L23''''''-->L23': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [399] [399] L23'-->L24: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [405] [405] L24-->L24': Formula: (and (<= 0 (+ |v_main_#t~nondet3_1| 2147483648)) (<= |v_main_#t~nondet3_1| 2147483647)) InVars {main_#t~nondet3=|v_main_#t~nondet3_1|} OutVars{main_#t~nondet3=|v_main_#t~nondet3_1|} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [411] [411] L24'-->L24'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet3_2|))) InVars {main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_4|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L24''-->L23''': Formula: true InVars {} OutVars{main_#t~nondet3=|v_main_#t~nondet3_3|} AuxVars[] AssignedVars[main_#t~nondet3] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L23'''-->L23'''': Formula: (= |v_main_#t~post2_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post2=|v_main_#t~post2_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L23''''-->L23''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post2_2| 1)) InVars {main_#t~post2=|v_main_#t~post2_2|} OutVars{main_#t~post2=|v_main_#t~post2_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L23'''''-->L23'''''': Formula: true InVars {} OutVars{main_#t~post2=|v_main_#t~post2_3|} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [393] [393] L23''''''-->L23': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,004 INFO L84 mationBacktranslator]: Skipped ATE [399] [399] L23'-->L24: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [405] [405] L24-->L24': Formula: (and (<= 0 (+ |v_main_#t~nondet3_1| 2147483648)) (<= |v_main_#t~nondet3_1| 2147483647)) InVars {main_#t~nondet3=|v_main_#t~nondet3_1|} OutVars{main_#t~nondet3=|v_main_#t~nondet3_1|} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [411] [411] L24'-->L24'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet3_2|))) InVars {main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_4|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L24''-->L23''': Formula: true InVars {} OutVars{main_#t~nondet3=|v_main_#t~nondet3_3|} AuxVars[] AssignedVars[main_#t~nondet3] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L23'''-->L23'''': Formula: (= |v_main_#t~post2_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post2=|v_main_#t~post2_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L23''''-->L23''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post2_2| 1)) InVars {main_#t~post2=|v_main_#t~post2_2|} OutVars{main_#t~post2=|v_main_#t~post2_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L23'''''-->L23'''''': Formula: true InVars {} OutVars{main_#t~post2=|v_main_#t~post2_3|} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [393] [393] L23''''''-->L23': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [399] [399] L23'-->L24: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [405] [405] L24-->L24': Formula: (and (<= 0 (+ |v_main_#t~nondet3_1| 2147483648)) (<= |v_main_#t~nondet3_1| 2147483647)) InVars {main_#t~nondet3=|v_main_#t~nondet3_1|} OutVars{main_#t~nondet3=|v_main_#t~nondet3_1|} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [411] [411] L24'-->L24'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet3_2|))) InVars {main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_4|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L24''-->L23''': Formula: true InVars {} OutVars{main_#t~nondet3=|v_main_#t~nondet3_3|} AuxVars[] AssignedVars[main_#t~nondet3] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L23'''-->L23'''': Formula: (= |v_main_#t~post2_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post2=|v_main_#t~post2_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L23''''-->L23''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post2_2| 1)) InVars {main_#t~post2=|v_main_#t~post2_2|} OutVars{main_#t~post2=|v_main_#t~post2_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L23'''''-->L23'''''': Formula: true InVars {} OutVars{main_#t~post2=|v_main_#t~post2_3|} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [393] [393] L23''''''-->L23': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [399] [399] L23'-->L24: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,005 INFO L84 mationBacktranslator]: Skipped ATE [405] [405] L24-->L24': Formula: (and (<= 0 (+ |v_main_#t~nondet3_1| 2147483648)) (<= |v_main_#t~nondet3_1| 2147483647)) InVars {main_#t~nondet3=|v_main_#t~nondet3_1|} OutVars{main_#t~nondet3=|v_main_#t~nondet3_1|} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [411] [411] L24'-->L24'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet3_2|))) InVars {main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_4|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L24''-->L23''': Formula: true InVars {} OutVars{main_#t~nondet3=|v_main_#t~nondet3_3|} AuxVars[] AssignedVars[main_#t~nondet3] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L23'''-->L23'''': Formula: (= |v_main_#t~post2_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post2=|v_main_#t~post2_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L23''''-->L23''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post2_2| 1)) InVars {main_#t~post2=|v_main_#t~post2_2|} OutVars{main_#t~post2=|v_main_#t~post2_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L23'''''-->L23'''''': Formula: true InVars {} OutVars{main_#t~post2=|v_main_#t~post2_3|} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [393] [393] L23''''''-->L23': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [399] [399] L23'-->L24: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [405] [405] L24-->L24': Formula: (and (<= 0 (+ |v_main_#t~nondet3_1| 2147483648)) (<= |v_main_#t~nondet3_1| 2147483647)) InVars {main_#t~nondet3=|v_main_#t~nondet3_1|} OutVars{main_#t~nondet3=|v_main_#t~nondet3_1|} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [411] [411] L24'-->L24'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet3_2|))) InVars {main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_4|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L24''-->L23''': Formula: true InVars {} OutVars{main_#t~nondet3=|v_main_#t~nondet3_3|} AuxVars[] AssignedVars[main_#t~nondet3] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L23'''-->L23'''': Formula: (= |v_main_#t~post2_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post2=|v_main_#t~post2_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L23''''-->L23''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post2_2| 1)) InVars {main_#t~post2=|v_main_#t~post2_2|} OutVars{main_#t~post2=|v_main_#t~post2_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L23'''''-->L23'''''': Formula: true InVars {} OutVars{main_#t~post2=|v_main_#t~post2_3|} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [393] [393] L23''''''-->L23': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [399] [399] L23'-->L24: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [405] [405] L24-->L24': Formula: (and (<= 0 (+ |v_main_#t~nondet3_1| 2147483648)) (<= |v_main_#t~nondet3_1| 2147483647)) InVars {main_#t~nondet3=|v_main_#t~nondet3_1|} OutVars{main_#t~nondet3=|v_main_#t~nondet3_1|} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,006 INFO L84 mationBacktranslator]: Skipped ATE [411] [411] L24'-->L24'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet3_2|))) InVars {main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_4|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L24''-->L23''': Formula: true InVars {} OutVars{main_#t~nondet3=|v_main_#t~nondet3_3|} AuxVars[] AssignedVars[main_#t~nondet3] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L23'''-->L23'''': Formula: (= |v_main_#t~post2_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post2=|v_main_#t~post2_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L23''''-->L23''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post2_2| 1)) InVars {main_#t~post2=|v_main_#t~post2_2|} OutVars{main_#t~post2=|v_main_#t~post2_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L23'''''-->L23'''''': Formula: true InVars {} OutVars{main_#t~post2=|v_main_#t~post2_3|} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [393] [393] L23''''''-->L23': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [399] [399] L23'-->L24: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [405] [405] L24-->L24': Formula: (and (<= 0 (+ |v_main_#t~nondet3_1| 2147483648)) (<= |v_main_#t~nondet3_1| 2147483647)) InVars {main_#t~nondet3=|v_main_#t~nondet3_1|} OutVars{main_#t~nondet3=|v_main_#t~nondet3_1|} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [411] [411] L24'-->L24'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet3_2|))) InVars {main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_4|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L24''-->L23''': Formula: true InVars {} OutVars{main_#t~nondet3=|v_main_#t~nondet3_3|} AuxVars[] AssignedVars[main_#t~nondet3] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L23'''-->L23'''': Formula: (= |v_main_#t~post2_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post2=|v_main_#t~post2_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L23''''-->L23''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post2_2| 1)) InVars {main_#t~post2=|v_main_#t~post2_2|} OutVars{main_#t~post2=|v_main_#t~post2_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L23'''''-->L23'''''': Formula: true InVars {} OutVars{main_#t~post2=|v_main_#t~post2_3|} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [393] [393] L23''''''-->L23': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [399] [399] L23'-->L24: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [405] [405] L24-->L24': Formula: (and (<= 0 (+ |v_main_#t~nondet3_1| 2147483648)) (<= |v_main_#t~nondet3_1| 2147483647)) InVars {main_#t~nondet3=|v_main_#t~nondet3_1|} OutVars{main_#t~nondet3=|v_main_#t~nondet3_1|} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [411] [411] L24'-->L24'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet3_2|))) InVars {main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_2|, main_#t~nondet3=|v_main_#t~nondet3_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_4|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,007 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L24''-->L23''': Formula: true InVars {} OutVars{main_#t~nondet3=|v_main_#t~nondet3_3|} AuxVars[] AssignedVars[main_#t~nondet3] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L23'''-->L23'''': Formula: (= |v_main_#t~post2_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post2=|v_main_#t~post2_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L23''''-->L23''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post2_2| 1)) InVars {main_#t~post2=|v_main_#t~post2_2|} OutVars{main_#t~post2=|v_main_#t~post2_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L23'''''-->L23'''''': Formula: true InVars {} OutVars{main_#t~post2=|v_main_#t~post2_3|} AuxVars[] AssignedVars[main_#t~post2] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [393] [393] L23''''''-->L23': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [397] [397] L23'-->L23''''''': Formula: (not (< v_main_~i~6_2 10)) InVars {main_~i~6=v_main_~i~6_2} OutVars{main_~i~6=v_main_~i~6_2} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [401] [401] L23'''''''-->L27: Formula: true InVars {} OutVars{main_#t~ret5=|v_main_#t~ret5_1|} AuxVars[] AssignedVars[main_#t~ret5] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [407] [407] L27-->L27': Formula: (and (<= 0 (+ |v_main_#t~ret5_2| 2147483648)) (<= |v_main_#t~ret5_2| 2147483647)) InVars {main_#t~ret5=|v_main_#t~ret5_2|} OutVars{main_#t~ret5=|v_main_#t~ret5_2|} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [413] [413] L27'-->L27'': Formula: (= v_main_~ret~5_2 |v_main_#t~ret5_3|) InVars {main_#t~ret5=|v_main_#t~ret5_3|} OutVars{main_#t~ret5=|v_main_#t~ret5_3|, main_~ret~5=v_main_~ret~5_2} AuxVars[] AssignedVars[main_~ret~5] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [419] [419] L27''-->L29: Formula: true InVars {} OutVars{main_#t~ret5=|v_main_#t~ret5_4|} AuxVars[] AssignedVars[main_#t~ret5] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [425] [425] L29-->L29': Formula: (= |v_main_#t~mem6_1| (select (select |v_#memory_int_part_locs_87_locs_92_3| |v_main_~#x~5.base_4|) |v_main_~#x~5.offset_4|)) InVars {main_~#x~5.base=|v_main_~#x~5.base_4|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_3|, main_~#x~5.offset=|v_main_~#x~5.offset_4|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_4|, main_#t~mem6=|v_main_#t~mem6_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_3|, main_~#x~5.offset=|v_main_~#x~5.offset_4|} AuxVars[] AssignedVars[main_#t~mem6] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [431] [431] L29'-->L29'': Formula: (= v_main_~temp~5_2 |v_main_#t~mem6_2|) InVars {main_#t~mem6=|v_main_#t~mem6_2|} OutVars{main_~temp~5=v_main_~temp~5_2, main_#t~mem6=|v_main_#t~mem6_2|} AuxVars[] AssignedVars[main_~temp~5] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [437] [437] L29''-->L29''': Formula: true InVars {} OutVars{main_#t~mem6=|v_main_#t~mem6_3|} AuxVars[] AssignedVars[main_#t~mem6] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [443] [443] L29'''-->L29'''': Formula: (= (select (select |v_#memory_int_part_locs_87_locs_92_4| |v_main_~#x~5.base_5|) (+ |v_main_~#x~5.offset_5| 4)) |v_main_#t~mem8_1|) InVars {main_~#x~5.base=|v_main_~#x~5.base_5|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_4|, main_~#x~5.offset=|v_main_~#x~5.offset_5|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_5|, main_#t~mem8=|v_main_#t~mem8_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_4|, main_~#x~5.offset=|v_main_~#x~5.offset_5|} AuxVars[] AssignedVars[main_#t~mem8] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [451] [451] L29''''-->L29''''': Formula: (= |v_#memory_int_part_locs_87_locs_92_5| (store |v_#memory_int_part_locs_87_locs_92_6| |v_main_~#x~5.base_6| (store (select |v_#memory_int_part_locs_87_locs_92_6| |v_main_~#x~5.base_6|) |v_main_~#x~5.offset_6| |v_main_#t~mem8_2|))) InVars {main_~#x~5.base=|v_main_~#x~5.base_6|, main_#t~mem8=|v_main_#t~mem8_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_6|, main_~#x~5.offset=|v_main_~#x~5.offset_6|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_6|, #memory_int=|v_#memory_int_8|, main_#t~mem8=|v_main_#t~mem8_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_5|, main_~#x~5.offset=|v_main_~#x~5.offset_6|} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [457] [457] L29'''''-->L29'''''': Formula: true InVars {} OutVars{main_#t~mem8=|v_main_#t~mem8_3|} AuxVars[] AssignedVars[main_#t~mem8] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [461] [461] L29''''''-->L29''''''': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_8| |v_main_~#x~5.base_7| (store (select |v_#memory_int_part_locs_87_locs_92_8| |v_main_~#x~5.base_7|) (+ |v_main_~#x~5.offset_7| 4) v_main_~temp~5_3)) |v_#memory_int_part_locs_87_locs_92_9|) InVars {main_~#x~5.base=|v_main_~#x~5.base_7|, main_~temp~5=v_main_~temp~5_3, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_8|, main_~#x~5.offset=|v_main_~#x~5.offset_7|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_7|, #memory_int=|v_#memory_int_10|, main_~temp~5=v_main_~temp~5_3, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_9|, main_~#x~5.offset=|v_main_~#x~5.offset_7|} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,008 INFO L84 mationBacktranslator]: Skipped ATE [469] [469] L29'''''''-->L30: Formula: true InVars {} OutVars{main_#t~ret10=|v_main_#t~ret10_1|} AuxVars[] AssignedVars[main_#t~ret10] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L30-->L30': Formula: (and (<= |v_main_#t~ret10_2| 2147483647) (<= 0 (+ |v_main_#t~ret10_2| 2147483648))) InVars {main_#t~ret10=|v_main_#t~ret10_2|} OutVars{main_#t~ret10=|v_main_#t~ret10_2|} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [475] [475] L30'-->L30'': Formula: (= v_main_~ret2~5_2 |v_main_#t~ret10_3|) InVars {main_#t~ret10=|v_main_#t~ret10_3|} OutVars{main_#t~ret10=|v_main_#t~ret10_3|, main_~ret2~5=v_main_~ret2~5_2} AuxVars[] AssignedVars[main_~ret2~5] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [481] [481] L30''-->L31: Formula: true InVars {} OutVars{main_#t~ret10=|v_main_#t~ret10_4|} AuxVars[] AssignedVars[main_#t~ret10] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [487] [487] L31-->L31': Formula: (= |v_main_#t~mem11_1| (select (select |v_#memory_int_part_locs_87_locs_92_10| |v_main_~#x~5.base_9|) |v_main_~#x~5.offset_9|)) InVars {main_~#x~5.base=|v_main_~#x~5.base_9|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_10|, main_~#x~5.offset=|v_main_~#x~5.offset_9|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_9|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_10|, main_#t~mem11=|v_main_#t~mem11_1|, main_~#x~5.offset=|v_main_~#x~5.offset_9|} AuxVars[] AssignedVars[main_#t~mem11] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [493] [493] L31'-->L31'': Formula: (= v_main_~temp~5_4 |v_main_#t~mem11_2|) InVars {main_#t~mem11=|v_main_#t~mem11_2|} OutVars{main_~temp~5=v_main_~temp~5_4, main_#t~mem11=|v_main_#t~mem11_2|} AuxVars[] AssignedVars[main_~temp~5] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [501] [501] L31''-->L32: Formula: true InVars {} OutVars{main_#t~mem11=|v_main_#t~mem11_3|} AuxVars[] AssignedVars[main_#t~mem11] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [505] [505] L32-->L32'''''': Formula: (= v_main_~i~7_1 0) InVars {} OutVars{main_~i~7=v_main_~i~7_1} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [509] [509] L32''''''-->L32': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [517] [517] L32'-->L33: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [521] [521] L33-->L33': Formula: (= (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4)) |v_main_#t~mem14_1|) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem14=|v_main_#t~mem14_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [527] [527] L33'-->L33'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_14|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [529] [529] L33''-->L32''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [531] [531] L32'''-->L32'''': Formula: (= |v_main_#t~post12_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [533] [533] L32''''-->L32''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_#t~post12=|v_main_#t~post12_2|, main_~i~7=v_main_~i~7_7} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [535] [535] L32'''''-->L32'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,009 INFO L84 mationBacktranslator]: Skipped ATE [509] [509] L32''''''-->L32': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [517] [517] L32'-->L33: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [521] [521] L33-->L33': Formula: (= (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4)) |v_main_#t~mem14_1|) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem14=|v_main_#t~mem14_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [527] [527] L33'-->L33'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_14|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [529] [529] L33''-->L32''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [531] [531] L32'''-->L32'''': Formula: (= |v_main_#t~post12_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [533] [533] L32''''-->L32''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_#t~post12=|v_main_#t~post12_2|, main_~i~7=v_main_~i~7_7} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [535] [535] L32'''''-->L32'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [509] [509] L32''''''-->L32': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [517] [517] L32'-->L33: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [521] [521] L33-->L33': Formula: (= (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4)) |v_main_#t~mem14_1|) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem14=|v_main_#t~mem14_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [527] [527] L33'-->L33'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_14|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [529] [529] L33''-->L32''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [531] [531] L32'''-->L32'''': Formula: (= |v_main_#t~post12_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [533] [533] L32''''-->L32''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_#t~post12=|v_main_#t~post12_2|, main_~i~7=v_main_~i~7_7} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [535] [535] L32'''''-->L32'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,010 INFO L84 mationBacktranslator]: Skipped ATE [509] [509] L32''''''-->L32': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [517] [517] L32'-->L33: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [521] [521] L33-->L33': Formula: (= (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4)) |v_main_#t~mem14_1|) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem14=|v_main_#t~mem14_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [527] [527] L33'-->L33'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_14|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [529] [529] L33''-->L32''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [531] [531] L32'''-->L32'''': Formula: (= |v_main_#t~post12_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [533] [533] L32''''-->L32''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_#t~post12=|v_main_#t~post12_2|, main_~i~7=v_main_~i~7_7} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [535] [535] L32'''''-->L32'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [509] [509] L32''''''-->L32': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [517] [517] L32'-->L33: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [521] [521] L33-->L33': Formula: (= (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4)) |v_main_#t~mem14_1|) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem14=|v_main_#t~mem14_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [527] [527] L33'-->L33'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_14|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [529] [529] L33''-->L32''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [531] [531] L32'''-->L32'''': Formula: (= |v_main_#t~post12_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [533] [533] L32''''-->L32''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_#t~post12=|v_main_#t~post12_2|, main_~i~7=v_main_~i~7_7} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [535] [535] L32'''''-->L32'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,011 INFO L84 mationBacktranslator]: Skipped ATE [509] [509] L32''''''-->L32': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [517] [517] L32'-->L33: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [521] [521] L33-->L33': Formula: (= (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4)) |v_main_#t~mem14_1|) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem14=|v_main_#t~mem14_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [527] [527] L33'-->L33'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_14|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [529] [529] L33''-->L32''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [531] [531] L32'''-->L32'''': Formula: (= |v_main_#t~post12_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [533] [533] L32''''-->L32''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_#t~post12=|v_main_#t~post12_2|, main_~i~7=v_main_~i~7_7} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [535] [535] L32'''''-->L32'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [509] [509] L32''''''-->L32': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [517] [517] L32'-->L33: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [521] [521] L33-->L33': Formula: (= (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4)) |v_main_#t~mem14_1|) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem14=|v_main_#t~mem14_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [527] [527] L33'-->L33'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_14|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [529] [529] L33''-->L32''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [531] [531] L32'''-->L32'''': Formula: (= |v_main_#t~post12_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [533] [533] L32''''-->L32''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_#t~post12=|v_main_#t~post12_2|, main_~i~7=v_main_~i~7_7} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [535] [535] L32'''''-->L32'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [509] [509] L32''''''-->L32': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,012 INFO L84 mationBacktranslator]: Skipped ATE [517] [517] L32'-->L33: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [521] [521] L33-->L33': Formula: (= (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4)) |v_main_#t~mem14_1|) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem14=|v_main_#t~mem14_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [527] [527] L33'-->L33'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_14|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [529] [529] L33''-->L32''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [531] [531] L32'''-->L32'''': Formula: (= |v_main_#t~post12_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [533] [533] L32''''-->L32''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_#t~post12=|v_main_#t~post12_2|, main_~i~7=v_main_~i~7_7} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [535] [535] L32'''''-->L32'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [509] [509] L32''''''-->L32': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [517] [517] L32'-->L33: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [521] [521] L33-->L33': Formula: (= (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4)) |v_main_#t~mem14_1|) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem14=|v_main_#t~mem14_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [527] [527] L33'-->L33'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem14=|v_main_#t~mem14_2|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_14|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [529] [529] L33''-->L32''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [531] [531] L32'''-->L32'''': Formula: (= |v_main_#t~post12_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [533] [533] L32''''-->L32''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_#t~post12=|v_main_#t~post12_2|, main_~i~7=v_main_~i~7_7} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [535] [535] L32'''''-->L32'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [509] [509] L32''''''-->L32': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [515] [515] L32'-->L32''''''': Formula: (not (< v_main_~i~7_2 9)) InVars {main_~i~7=v_main_~i~7_2} OutVars{main_~i~7=v_main_~i~7_2} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,013 INFO L84 mationBacktranslator]: Skipped ATE [519] [519] L32'''''''-->L35: Formula: (= (store |v_#memory_int_part_locs_87_locs_92_11| |v_main_~#x~5.base_12| (store (select |v_#memory_int_part_locs_87_locs_92_11| |v_main_~#x~5.base_12|) (+ |v_main_~#x~5.offset_12| 36) v_main_~temp~5_5)) |v_#memory_int_part_locs_87_locs_92_12|) InVars {main_~#x~5.base=|v_main_~#x~5.base_12|, main_~temp~5=v_main_~temp~5_5, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_11|, main_~#x~5.offset=|v_main_~#x~5.offset_12|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_12|, #memory_int=|v_#memory_int_16|, main_~temp~5=v_main_~temp~5_5, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_12|, main_~#x~5.offset=|v_main_~#x~5.offset_12|} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:30:57,014 INFO L84 mationBacktranslator]: Skipped ATE [523] [523] L35-->L36: Formula: true InVars {} OutVars{main_#t~ret16=|v_main_#t~ret16_1|} AuxVars[] AssignedVars[main_#t~ret16] [2018-01-31 10:30:57,014 INFO L84 mationBacktranslator]: Skipped ATE [467] [467] L36-->L36': Formula: (and (<= 0 (+ |v_main_#t~ret16_2| 2147483648)) (<= |v_main_#t~ret16_2| 2147483647)) InVars {main_#t~ret16=|v_main_#t~ret16_2|} OutVars{main_#t~ret16=|v_main_#t~ret16_2|} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,014 INFO L84 mationBacktranslator]: Skipped ATE [477] [477] L36'-->L36'': Formula: (= v_main_~ret5~5_2 |v_main_#t~ret16_3|) InVars {main_#t~ret16=|v_main_#t~ret16_3|} OutVars{main_~ret5~5=v_main_~ret5~5_2, main_#t~ret16=|v_main_#t~ret16_3|} AuxVars[] AssignedVars[main_~ret5~5] [2018-01-31 10:30:57,014 INFO L84 mationBacktranslator]: Skipped ATE [483] [483] L36''-->L38: Formula: true InVars {} OutVars{main_#t~ret16=|v_main_#t~ret16_4|} AuxVars[] AssignedVars[main_#t~ret16] [2018-01-31 10:30:57,014 INFO L84 mationBacktranslator]: Skipped ATE [489] [489] L38-->L39: Formula: (or (not (= v_main_~ret2~5_3 v_main_~ret~5_3)) (not (= v_main_~ret5~5_3 v_main_~ret~5_3))) InVars {main_~ret~5=v_main_~ret~5_3, main_~ret5~5=v_main_~ret5~5_3, main_~ret2~5=v_main_~ret2~5_3} OutVars{main_~ret~5=v_main_~ret~5_3, main_~ret5~5=v_main_~ret5~5_3, main_~ret2~5=v_main_~ret2~5_3} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,014 INFO L84 mationBacktranslator]: Skipped ATE [495] [495] L39-->mainErr0AssertViolation: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:30:57,017 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 31.01 10:30:57 BasicIcfg [2018-01-31 10:30:57,017 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-31 10:30:57,017 INFO L168 Benchmark]: Toolchain (without parser) took 98604.37 ms. Allocated memory was 147.8 MB in the beginning and 2.1 GB in the end (delta: 2.0 GB). Free memory was 112.9 MB in the beginning and 1.3 GB in the end (delta: -1.2 GB). Peak memory consumption was 829.5 MB. Max. memory is 5.3 GB. [2018-01-31 10:30:57,018 INFO L168 Benchmark]: CDTParser took 0.09 ms. Allocated memory is still 147.8 MB. Free memory is still 117.8 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-31 10:30:57,018 INFO L168 Benchmark]: CACSL2BoogieTranslator took 119.70 ms. Allocated memory is still 147.8 MB. Free memory was 112.9 MB in the beginning and 104.0 MB in the end (delta: 8.9 MB). Peak memory consumption was 8.9 MB. Max. memory is 5.3 GB. [2018-01-31 10:30:57,018 INFO L168 Benchmark]: Boogie Preprocessor took 19.97 ms. Allocated memory is still 147.8 MB. Free memory was 104.0 MB in the beginning and 102.3 MB in the end (delta: 1.7 MB). Peak memory consumption was 1.7 MB. Max. memory is 5.3 GB. [2018-01-31 10:30:57,018 INFO L168 Benchmark]: RCFGBuilder took 400.48 ms. Allocated memory is still 147.8 MB. Free memory was 102.3 MB in the beginning and 84.0 MB in the end (delta: 18.3 MB). Peak memory consumption was 18.3 MB. Max. memory is 5.3 GB. [2018-01-31 10:30:57,018 INFO L168 Benchmark]: IcfgTransformer took 88953.15 ms. Allocated memory was 147.8 MB in the beginning and 2.1 GB in the end (delta: 2.0 GB). Free memory was 84.0 MB in the beginning and 284.7 MB in the end (delta: -200.7 MB). Peak memory consumption was 1.8 GB. Max. memory is 5.3 GB. [2018-01-31 10:30:57,018 INFO L168 Benchmark]: TraceAbstraction took 9108.58 ms. Allocated memory was 2.1 GB in the beginning and 2.1 GB in the end (delta: 3.7 MB). Free memory was 284.7 MB in the beginning and 1.3 GB in the end (delta: -993.6 MB). There was no memory consumed. Max. memory is 5.3 GB. [2018-01-31 10:30:57,019 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.09 ms. Allocated memory is still 147.8 MB. Free memory is still 117.8 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 119.70 ms. Allocated memory is still 147.8 MB. Free memory was 112.9 MB in the beginning and 104.0 MB in the end (delta: 8.9 MB). Peak memory consumption was 8.9 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 19.97 ms. Allocated memory is still 147.8 MB. Free memory was 104.0 MB in the beginning and 102.3 MB in the end (delta: 1.7 MB). Peak memory consumption was 1.7 MB. Max. memory is 5.3 GB. * RCFGBuilder took 400.48 ms. Allocated memory is still 147.8 MB. Free memory was 102.3 MB in the beginning and 84.0 MB in the end (delta: 18.3 MB). Peak memory consumption was 18.3 MB. Max. memory is 5.3 GB. * IcfgTransformer took 88953.15 ms. Allocated memory was 147.8 MB in the beginning and 2.1 GB in the end (delta: 2.0 GB). Free memory was 84.0 MB in the beginning and 284.7 MB in the end (delta: -200.7 MB). Peak memory consumption was 1.8 GB. Max. memory is 5.3 GB. * TraceAbstraction took 9108.58 ms. Allocated memory was 2.1 GB in the beginning and 2.1 GB in the end (delta: 3.7 MB). Free memory was 284.7 MB in the beginning and 1.3 GB in the end (delta: -993.6 MB). There was no memory consumed. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 77 LocStat_MAX_WEQGRAPH_SIZE : 3 LocStat_MAX_SIZEOF_WEQEDGELABEL : 2 LocStat_NO_SUPPORTING_EQUALITIES : 1471 LocStat_NO_SUPPORTING_DISEQUALITIES : 3216 LocStat_NO_DISJUNCTIONS : -154 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 102 TransStat_MAX_WEQGRAPH_SIZE : 2 TransStat_MAX_SIZEOF_WEQEDGELABEL : 1 TransStat_NO_SUPPORTING_EQUALITIES : 162 TransStat_NO_SUPPORTING_DISEQUALITIES : 6 TransStat_NO_DISJUNCTIONS : 100 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.008525 RENAME_VARIABLES(MILLISECONDS) : 0.221479 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.000332 PROJECTAWAY(MILLISECONDS) : 0.074667 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.040890 DISJOIN(MILLISECONDS) : 0.562366 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.235567 ADD_EQUALITY(MILLISECONDS) : 0.004506 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.002383 #CONJOIN_DISJUNCTIVE : 1096 #RENAME_VARIABLES : 2401 #UNFREEZE : 0 #CONJOIN : 1530 #PROJECTAWAY : 1430 #ADD_WEAK_EQUALITY : 14 #DISJOIN : 377 #RENAME_VARIABLES_DISJUNCTIVE : 2445 #ADD_EQUALITY : 167 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 3 * Results from de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: - StatisticsResult: HeapSeparatorStatistics #COUNT_NEW_ARRAY_VARS_[#memory_int] : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_0 : 5 COUNT_BLOCKS_for_[#memory_int]_at_dim_0 : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_1 : 5 COUNT_BLOCKS_for_[#memory_int]_at_dim_1 : 1 COUNT_ARRAY_READS for [#memory_int] : 10 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 39]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 78 locations, 1 error locations. UNSAFE Result, 9.0s OverallTime, 15 OverallIterations, 11 TraceHistogramMax, 3.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1032 SDtfs, 540 SDslu, 9534 SDs, 0 SdLazy, 1251 SolverSat, 143 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1791 GetRequests, 1436 SyntacticMatches, 0 SemanticMatches, 355 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2297 ImplicationChecksByTransitivity, 4.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=211occurred in iteration=14, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 14 MinimizatonAttempts, 85 StatesRemovedByMinimization, 11 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 1.2s SatisfiabilityAnalysisTime, 3.5s InterpolantComputationTime, 3208 NumberOfCodeBlocks, 3143 NumberOfCodeBlocksAsserted, 61 NumberOfCheckSat, 2992 ConstructedInterpolants, 0 QuantifiedInterpolants, 697166 SizeOfPredicates, 134 NumberOfNonLiveVariables, 2064 ConjunctsInSsa, 148 ConjunctsInUnsatCore, 26 InterpolantComputations, 3 PerfectInterpolantSequences, 3524/6508 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sum10_true-unreach-call_true-termination.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-Benchmark-0-2018-01-31_10-30-57-023.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sum10_true-unreach-call_true-termination.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-VPDomainBenchmark-0-2018-01-31_10-30-57-023.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sum10_true-unreach-call_true-termination.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-0-2018-01-31_10-30-57-023.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sum10_true-unreach-call_true-termination.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-HeapSeparatorBenchmark-0-2018-01-31_10-30-57-023.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sum10_true-unreach-call_true-termination.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-31_10-30-57-023.csv Received shutdown request...