java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/array-memsafety/diff-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-8168ed2-m [2018-04-12 01:06:02,051 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-12 01:06:02,053 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-12 01:06:02,072 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2018-04-12 01:06:02,106 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf [2018-04-12 01:06:02,134 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-12 01:06:02,134 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-12 01:06:02,135 INFO L131 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2018-04-12 01:06:02,135 INFO L133 SettingsManager]: * ultimate.logging.details=de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation=DEBUG; [2018-04-12 01:06:02,135 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-04-12 01:06:02,136 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-04-12 01:06:02,136 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-04-12 01:06:02,136 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-04-12 01:06:02,136 INFO L133 SettingsManager]: * Parallel states before merging=1 [2018-04-12 01:06:02,136 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-04-12 01:06:02,137 INFO L131 SettingsManager]: Preferences of LTL2Aut differ from their defaults: [2018-04-12 01:06:02,137 INFO L133 SettingsManager]: * Property to check=[] a a: x > 42 [2018-04-12 01:06:02,137 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-12 01:06:02,137 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-12 01:06:02,138 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-12 01:06:02,138 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-12 01:06:02,138 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-12 01:06:02,138 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-12 01:06:02,138 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-12 01:06:02,138 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-04-12 01:06:02,140 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-12 01:06:02,140 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-12 01:06:02,140 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-12 01:06:02,140 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-04-12 01:06:02,141 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-04-12 01:06:02,141 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-12 01:06:02,141 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-12 01:06:02,141 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-12 01:06:02,141 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-04-12 01:06:02,142 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-04-12 01:06:02,142 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-04-12 01:06:02,142 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-04-12 01:06:02,142 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:06:02,142 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-04-12 01:06:02,143 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-04-12 01:06:02,143 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-04-12 01:06:02,143 INFO L131 SettingsManager]: Preferences of Boogie Printer differ from their defaults: [2018-04-12 01:06:02,144 INFO L133 SettingsManager]: * Dump path:=C:\Users\alex\AppData\Local\Temp\ [2018-04-12 01:06:02,194 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-12 01:06:02,209 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-12 01:06:02,215 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-12 01:06:02,216 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-12 01:06:02,218 INFO L276 PluginConnector]: CDTParser initialized [2018-04-12 01:06:02,219 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,575 INFO L225 CDTParser]: Created temporary CDT project at /storage/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGe64c228be [2018-04-12 01:06:02,757 INFO L287 CDTParser]: IsIndexed: true [2018-04-12 01:06:02,757 INFO L288 CDTParser]: Found 1 translation units. [2018-04-12 01:06:02,758 INFO L168 CDTParser]: Scanning diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,768 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-12 01:06:02,768 INFO L215 ultiparseSymbolTable]: [2018-04-12 01:06:02,768 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-12 01:06:02,768 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,768 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_32 ('__bswap_32') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,768 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_64 ('__bswap_64') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,768 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff ('diff') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,769 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-12 01:06:02,769 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsfilcnt64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,769 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ino_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,769 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,769 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,769 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,769 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____ssize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,770 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____mode_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,770 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____socklen_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,770 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____nlink_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,770 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,770 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____timer_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,770 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__size_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,770 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__off_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,770 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____intptr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,770 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__key_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,771 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsword_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,771 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_short in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,771 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,771 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__caddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,771 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__timer_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,771 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__mode_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,771 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____sig_atomic_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,771 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_short in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,772 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__nlink_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,772 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__gid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,772 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fsfilcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,772 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____blkcnt64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,772 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,772 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ssize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,772 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__loff_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,772 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__id_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,773 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__uint in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,773 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_rwlock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,773 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_condattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,773 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_int in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,773 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____useconds_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,773 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fd_set in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,773 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____qaddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,773 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____dev_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,773 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____rlim64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,774 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsblkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,774 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____blksize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,774 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__time_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,774 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_key_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,774 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fsid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,774 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__dev_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,774 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____blkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,775 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____clock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,775 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_mutex_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,775 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,775 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____WAIT_STATUS in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,775 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____syscall_slong_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,775 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__register_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,775 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____daddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,775 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsfilcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,775 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_barrierattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,775 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,775 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____time_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,775 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ushort in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____key_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ldiv_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__clock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__daddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_char in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_long in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____gid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__blkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____loff_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,776 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__suseconds_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____sigset_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fd_mask in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__sigset_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____ino_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_long in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____ino64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____caddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____off_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ulong in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_rwlockattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__wchar_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,777 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__lldiv_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,778 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__uid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,778 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,778 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____clockid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,778 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__div_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,778 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__blksize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,778 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_spinlock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,778 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__clockid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,778 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fsblkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,778 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,778 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,778 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fd_mask in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,778 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____id_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,778 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,779 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____syscall_ulong_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,779 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_cond_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,779 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_once_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,779 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,779 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____rlim_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,779 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsblkcnt64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,779 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____pid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,779 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,779 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____pthread_list_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,779 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_mutexattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,780 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_char in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,780 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_barrier_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,780 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_attr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,780 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____off64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,780 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____suseconds_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,780 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,780 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-12 01:06:02,801 INFO L330 CDTParser]: Deleted temporary CDT project at /storage/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGe64c228be [2018-04-12 01:06:02,805 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-12 01:06:02,807 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-04-12 01:06:02,808 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-12 01:06:02,809 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-12 01:06:02,815 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-12 01:06:02,815 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.04 01:06:02" (1/1) ... [2018-04-12 01:06:02,817 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@77ab0c3f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 01:06:02, skipping insertion in model container [2018-04-12 01:06:02,818 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.04 01:06:02" (1/1) ... [2018-04-12 01:06:02,831 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-12 01:06:02,867 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-12 01:06:03,038 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-12 01:06:03,086 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-12 01:06:03,094 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-12 01:06:03,140 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 01:06:03 WrapperNode [2018-04-12 01:06:03,140 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-12 01:06:03,141 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-12 01:06:03,141 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-12 01:06:03,141 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-12 01:06:03,156 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 01:06:03" (1/1) ... [2018-04-12 01:06:03,156 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 01:06:03" (1/1) ... [2018-04-12 01:06:03,175 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 01:06:03" (1/1) ... [2018-04-12 01:06:03,175 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 01:06:03" (1/1) ... [2018-04-12 01:06:03,187 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 01:06:03" (1/1) ... [2018-04-12 01:06:03,194 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 01:06:03" (1/1) ... [2018-04-12 01:06:03,197 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 01:06:03" (1/1) ... [2018-04-12 01:06:03,202 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-12 01:06:03,203 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-12 01:06:03,203 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-12 01:06:03,203 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-12 01:06:03,204 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 01:06:03" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-12 01:06:03,328 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-12 01:06:03,328 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-12 01:06:03,328 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-12 01:06:03,328 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-12 01:06:03,328 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff [2018-04-12 01:06:03,328 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-12 01:06:03,328 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-12 01:06:03,328 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-12 01:06:03,329 INFO L128 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-04-12 01:06:03,329 INFO L128 BoogieDeclarations]: Found specification of procedure atof [2018-04-12 01:06:03,329 INFO L128 BoogieDeclarations]: Found specification of procedure atoi [2018-04-12 01:06:03,329 INFO L128 BoogieDeclarations]: Found specification of procedure atol [2018-04-12 01:06:03,329 INFO L128 BoogieDeclarations]: Found specification of procedure atoll [2018-04-12 01:06:03,329 INFO L128 BoogieDeclarations]: Found specification of procedure strtod [2018-04-12 01:06:03,330 INFO L128 BoogieDeclarations]: Found specification of procedure strtof [2018-04-12 01:06:03,330 INFO L128 BoogieDeclarations]: Found specification of procedure strtold [2018-04-12 01:06:03,330 INFO L128 BoogieDeclarations]: Found specification of procedure strtol [2018-04-12 01:06:03,330 INFO L128 BoogieDeclarations]: Found specification of procedure strtoul [2018-04-12 01:06:03,330 INFO L128 BoogieDeclarations]: Found specification of procedure strtoq [2018-04-12 01:06:03,330 INFO L128 BoogieDeclarations]: Found specification of procedure strtouq [2018-04-12 01:06:03,331 INFO L128 BoogieDeclarations]: Found specification of procedure strtoll [2018-04-12 01:06:03,331 INFO L128 BoogieDeclarations]: Found specification of procedure strtoull [2018-04-12 01:06:03,331 INFO L128 BoogieDeclarations]: Found specification of procedure l64a [2018-04-12 01:06:03,331 INFO L128 BoogieDeclarations]: Found specification of procedure a64l [2018-04-12 01:06:03,331 INFO L128 BoogieDeclarations]: Found specification of procedure select [2018-04-12 01:06:03,331 INFO L128 BoogieDeclarations]: Found specification of procedure pselect [2018-04-12 01:06:03,331 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-04-12 01:06:03,331 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-04-12 01:06:03,332 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-04-12 01:06:03,332 INFO L128 BoogieDeclarations]: Found specification of procedure random [2018-04-12 01:06:03,332 INFO L128 BoogieDeclarations]: Found specification of procedure srandom [2018-04-12 01:06:03,332 INFO L128 BoogieDeclarations]: Found specification of procedure initstate [2018-04-12 01:06:03,332 INFO L128 BoogieDeclarations]: Found specification of procedure setstate [2018-04-12 01:06:03,332 INFO L128 BoogieDeclarations]: Found specification of procedure random_r [2018-04-12 01:06:03,332 INFO L128 BoogieDeclarations]: Found specification of procedure srandom_r [2018-04-12 01:06:03,332 INFO L128 BoogieDeclarations]: Found specification of procedure initstate_r [2018-04-12 01:06:03,332 INFO L128 BoogieDeclarations]: Found specification of procedure setstate_r [2018-04-12 01:06:03,332 INFO L128 BoogieDeclarations]: Found specification of procedure rand [2018-04-12 01:06:03,332 INFO L128 BoogieDeclarations]: Found specification of procedure srand [2018-04-12 01:06:03,332 INFO L128 BoogieDeclarations]: Found specification of procedure rand_r [2018-04-12 01:06:03,333 INFO L128 BoogieDeclarations]: Found specification of procedure drand48 [2018-04-12 01:06:03,333 INFO L128 BoogieDeclarations]: Found specification of procedure erand48 [2018-04-12 01:06:03,333 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48 [2018-04-12 01:06:03,333 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48 [2018-04-12 01:06:03,333 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48 [2018-04-12 01:06:03,333 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48 [2018-04-12 01:06:03,333 INFO L128 BoogieDeclarations]: Found specification of procedure srand48 [2018-04-12 01:06:03,333 INFO L128 BoogieDeclarations]: Found specification of procedure seed48 [2018-04-12 01:06:03,333 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48 [2018-04-12 01:06:03,333 INFO L128 BoogieDeclarations]: Found specification of procedure drand48_r [2018-04-12 01:06:03,334 INFO L128 BoogieDeclarations]: Found specification of procedure erand48_r [2018-04-12 01:06:03,334 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-04-12 01:06:03,334 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-04-12 01:06:03,334 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-04-12 01:06:03,334 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-04-12 01:06:03,334 INFO L128 BoogieDeclarations]: Found specification of procedure srand48_r [2018-04-12 01:06:03,334 INFO L128 BoogieDeclarations]: Found specification of procedure seed48_r [2018-04-12 01:06:03,334 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-04-12 01:06:03,334 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-04-12 01:06:03,334 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-04-12 01:06:03,335 INFO L128 BoogieDeclarations]: Found specification of procedure realloc [2018-04-12 01:06:03,335 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-04-12 01:06:03,335 INFO L128 BoogieDeclarations]: Found specification of procedure cfree [2018-04-12 01:06:03,335 INFO L128 BoogieDeclarations]: Found specification of procedure alloca [2018-04-12 01:06:03,335 INFO L128 BoogieDeclarations]: Found specification of procedure valloc [2018-04-12 01:06:03,335 INFO L128 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-04-12 01:06:03,335 INFO L128 BoogieDeclarations]: Found specification of procedure abort [2018-04-12 01:06:03,335 INFO L128 BoogieDeclarations]: Found specification of procedure atexit [2018-04-12 01:06:03,335 INFO L128 BoogieDeclarations]: Found specification of procedure on_exit [2018-04-12 01:06:03,335 INFO L128 BoogieDeclarations]: Found specification of procedure exit [2018-04-12 01:06:03,335 INFO L128 BoogieDeclarations]: Found specification of procedure _Exit [2018-04-12 01:06:03,335 INFO L128 BoogieDeclarations]: Found specification of procedure getenv [2018-04-12 01:06:03,335 INFO L128 BoogieDeclarations]: Found specification of procedure putenv [2018-04-12 01:06:03,336 INFO L128 BoogieDeclarations]: Found specification of procedure setenv [2018-04-12 01:06:03,336 INFO L128 BoogieDeclarations]: Found specification of procedure unsetenv [2018-04-12 01:06:03,336 INFO L128 BoogieDeclarations]: Found specification of procedure clearenv [2018-04-12 01:06:03,336 INFO L128 BoogieDeclarations]: Found specification of procedure mktemp [2018-04-12 01:06:03,336 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemp [2018-04-12 01:06:03,336 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemps [2018-04-12 01:06:03,336 INFO L128 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-04-12 01:06:03,336 INFO L128 BoogieDeclarations]: Found specification of procedure system [2018-04-12 01:06:03,336 INFO L128 BoogieDeclarations]: Found specification of procedure realpath [2018-04-12 01:06:03,336 INFO L128 BoogieDeclarations]: Found specification of procedure bsearch [2018-04-12 01:06:03,336 INFO L128 BoogieDeclarations]: Found specification of procedure qsort [2018-04-12 01:06:03,336 INFO L128 BoogieDeclarations]: Found specification of procedure abs [2018-04-12 01:06:03,337 INFO L128 BoogieDeclarations]: Found specification of procedure labs [2018-04-12 01:06:03,337 INFO L128 BoogieDeclarations]: Found specification of procedure llabs [2018-04-12 01:06:03,337 INFO L128 BoogieDeclarations]: Found specification of procedure div [2018-04-12 01:06:03,337 INFO L128 BoogieDeclarations]: Found specification of procedure ldiv [2018-04-12 01:06:03,337 INFO L128 BoogieDeclarations]: Found specification of procedure lldiv [2018-04-12 01:06:03,337 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt [2018-04-12 01:06:03,337 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt [2018-04-12 01:06:03,337 INFO L128 BoogieDeclarations]: Found specification of procedure gcvt [2018-04-12 01:06:03,338 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt [2018-04-12 01:06:03,338 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt [2018-04-12 01:06:03,338 INFO L128 BoogieDeclarations]: Found specification of procedure qgcvt [2018-04-12 01:06:03,338 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-04-12 01:06:03,338 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-04-12 01:06:03,338 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-04-12 01:06:03,338 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-04-12 01:06:03,338 INFO L128 BoogieDeclarations]: Found specification of procedure mblen [2018-04-12 01:06:03,339 INFO L128 BoogieDeclarations]: Found specification of procedure mbtowc [2018-04-12 01:06:03,339 INFO L128 BoogieDeclarations]: Found specification of procedure wctomb [2018-04-12 01:06:03,339 INFO L128 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-04-12 01:06:03,339 INFO L128 BoogieDeclarations]: Found specification of procedure wcstombs [2018-04-12 01:06:03,339 INFO L128 BoogieDeclarations]: Found specification of procedure rpmatch [2018-04-12 01:06:03,339 INFO L128 BoogieDeclarations]: Found specification of procedure getsubopt [2018-04-12 01:06:03,339 INFO L128 BoogieDeclarations]: Found specification of procedure getloadavg [2018-04-12 01:06:03,339 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-04-12 01:06:03,340 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff [2018-04-12 01:06:03,340 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-12 01:06:03,340 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-12 01:06:03,340 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-12 01:06:03,340 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-12 01:06:03,340 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-12 01:06:03,340 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-12 01:06:03,341 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-12 01:06:03,341 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-12 01:06:03,741 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-12 01:06:03,742 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.04 01:06:03 BoogieIcfgContainer [2018-04-12 01:06:03,742 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-12 01:06:03,742 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2018-04-12 01:06:03,742 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2018-04-12 01:06:03,743 INFO L276 PluginConnector]: IcfgTransformer initialized [2018-04-12 01:06:03,747 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.04 01:06:03" (1/1) ... [2018-04-12 01:06:03,756 INFO L139 apSepIcfgTransformer]: HeapSepIcfgTransformer: Starting heap partitioning [2018-04-12 01:06:03,756 INFO L140 apSepIcfgTransformer]: To be partitioned heap arrays found [#memory_int] [2018-04-12 01:06:03,775 INFO L299 apSepIcfgTransformer]: Heap separator: starting memloc-array-style preprocessing [2018-04-12 01:06:03,797 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-12 01:06:03,813 INFO L332 apSepIcfgTransformer]: finished MemlocArrayUpdater, created 2 location literals (each corresponds to one heap write) [2018-04-12 01:06:03,824 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-12 01:06:03,841 INFO L412 apSepIcfgTransformer]: finished preprocessing for the equality analysis [2018-04-12 01:06:03,842 DEBUG L416 apSepIcfgTransformer]: storeIndexInfoToLocLiteral: Map: (Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) : |mll_L558'_0| (Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2)) : |mll_L558'_1| [2018-04-12 01:06:03,844 DEBUG L418 apSepIcfgTransformer]: edgeToIndexToStoreIndexInfo: NestedMap2: (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') : v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 : (Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') : (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2) : (Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2)) [2018-04-12 01:06:03,907 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=1) [2018-04-12 01:06:37,383 INFO L314 AbstractInterpreter]: Visited 90 different actions 765 times. Merged at 58 different actions 438 times. Widened at 1 different actions 3 times. Found 64 fixpoints after 14 different actions. Largest state had 46 variables. [2018-04-12 01:06:37,385 INFO L424 apSepIcfgTransformer]: finished equality analysis [2018-04-12 01:06:37,393 INFO L195 HeapSepPreAnalysis]: Number of read from array group [#memory_int] : 4 [2018-04-12 01:06:37,393 INFO L434 apSepIcfgTransformer]: Finished pre analysis before partitioning [2018-04-12 01:06:37,394 INFO L435 apSepIcfgTransformer]: array groups: Set: [#memory_int] [2018-04-12 01:06:37,394 INFO L437 apSepIcfgTransformer]: select infos: Set: ((select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))), at (SUMMARY for call #t~mem5 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L558)) ((select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))), at (SUMMARY for call #t~mem3 := read~int(~B.base, ~B.offset + ~j~0 * 4, 4); srcloc: L551')) ((select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))), at (SUMMARY for call #t~mem2 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L551)) ((select |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2), at (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558')) [2018-04-12 01:06:37,416 DEBUG L373 HeapPartitionManager]: creating LocationBlock locs_32 [2018-04-12 01:06:37,417 DEBUG L374 HeapPartitionManager]: with contents [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-12 01:06:37,417 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-12 01:06:37,417 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))), at (SUMMARY for call #t~mem5 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L558)) [2018-04-12 01:06:37,417 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-12 01:06:37,418 DEBUG L373 HeapPartitionManager]: creating LocationBlock locs_31 [2018-04-12 01:06:37,418 DEBUG L374 HeapPartitionManager]: with contents [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-12 01:06:37,418 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_31 [2018-04-12 01:06:37,418 DEBUG L324 HeapPartitionManager]: at dimension 1 for ((select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))), at (SUMMARY for call #t~mem5 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L558)) [2018-04-12 01:06:37,418 DEBUG L325 HeapPartitionManager]: write locations: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-12 01:06:37,418 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-12 01:06:37,419 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))), at (SUMMARY for call #t~mem3 := read~int(~B.base, ~B.offset + ~j~0 * 4, 4); srcloc: L551')) [2018-04-12 01:06:37,419 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-12 01:06:37,419 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_31 [2018-04-12 01:06:37,419 DEBUG L324 HeapPartitionManager]: at dimension 1 for ((select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))), at (SUMMARY for call #t~mem3 := read~int(~B.base, ~B.offset + ~j~0 * 4, 4); srcloc: L551')) [2018-04-12 01:06:37,419 DEBUG L325 HeapPartitionManager]: write locations: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-12 01:06:37,420 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-12 01:06:37,420 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))), at (SUMMARY for call #t~mem2 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L551)) [2018-04-12 01:06:37,420 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-12 01:06:37,420 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_31 [2018-04-12 01:06:37,420 DEBUG L324 HeapPartitionManager]: at dimension 1 for ((select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))), at (SUMMARY for call #t~mem2 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L551)) [2018-04-12 01:06:37,420 DEBUG L325 HeapPartitionManager]: write locations: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-12 01:06:37,420 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-12 01:06:37,421 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2), at (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558')) [2018-04-12 01:06:37,421 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-12 01:06:37,421 INFO L330 HeapPartitionManager]: partitioning result: [2018-04-12 01:06:37,421 INFO L335 HeapPartitionManager]: location blocks for array group [#memory_int] [2018-04-12 01:06:37,421 INFO L344 HeapPartitionManager]: at dimension 0 [2018-04-12 01:06:37,422 INFO L345 HeapPartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 1 [2018-04-12 01:06:37,422 INFO L346 HeapPartitionManager]: # location blocks :1 [2018-04-12 01:06:37,422 DEBUG L353 HeapPartitionManager]: location block contents: [2018-04-12 01:06:37,422 DEBUG L356 HeapPartitionManager]: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-12 01:06:37,422 INFO L344 HeapPartitionManager]: at dimension 1 [2018-04-12 01:06:37,422 INFO L345 HeapPartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 1 [2018-04-12 01:06:37,423 INFO L346 HeapPartitionManager]: # location blocks :1 [2018-04-12 01:06:37,423 DEBUG L353 HeapPartitionManager]: location block contents: [2018-04-12 01:06:37,423 DEBUG L356 HeapPartitionManager]: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-12 01:06:37,424 INFO L134 ransitionTransformer]: executing heap partitioning transformation [2018-04-12 01:06:37,427 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,427 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,427 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,427 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,427 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,428 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,428 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,428 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,428 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,428 DEBUG L331 ransitionTransformer]: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] [2018-04-12 01:06:37,428 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,428 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,429 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,429 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,429 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,429 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,429 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,429 DEBUG L331 ransitionTransformer]: Formula: (and (<= 0 (+ |v_main_#t~nondet8_1| 2147483648)) (<= |v_main_#t~nondet8_1| 2147483647)) InVars {main_#t~nondet8=|v_main_#t~nondet8_1|} OutVars{main_#t~nondet8=|v_main_#t~nondet8_1|} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,429 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,429 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,429 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,430 DEBUG L331 ransitionTransformer]: Formula: (= |v_#valid_9| (store |v_#valid_10| 0 0)) InVars {#valid=|v_#valid_10|} OutVars{#valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid] [2018-04-12 01:06:37,430 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,430 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,430 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,430 DEBUG L331 ransitionTransformer]: Formula: (= v_main_~Alen~0_1 |v_main_#t~nondet8_2|) InVars {main_#t~nondet8=|v_main_#t~nondet8_2|} OutVars{main_#t~nondet8=|v_main_#t~nondet8_2|, main_~Alen~0=v_main_~Alen~0_1} AuxVars[] AssignedVars[main_~Alen~0] [2018-04-12 01:06:37,430 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,430 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,430 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,430 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,430 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,431 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,431 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,431 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,431 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,431 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,431 DEBUG L356 ransitionTransformer]: {main_#t~nondet8=|v_main_#t~nondet8_3|} [2018-04-12 01:06:37,431 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,431 DEBUG L358 ransitionTransformer]: {} [2018-04-12 01:06:37,431 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,431 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,432 DEBUG L331 ransitionTransformer]: Formula: (and (<= |v_main_#t~nondet9_1| 2147483647) (<= 0 (+ |v_main_#t~nondet9_1| 2147483648))) InVars {main_#t~nondet9=|v_main_#t~nondet9_1|} OutVars{main_#t~nondet9=|v_main_#t~nondet9_1|} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,432 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,432 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,432 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,432 DEBUG L331 ransitionTransformer]: Formula: (= v_main_~Blen~0_1 |v_main_#t~nondet9_2|) InVars {main_#t~nondet9=|v_main_#t~nondet9_2|} OutVars{main_~Blen~0=v_main_~Blen~0_1, main_#t~nondet9=|v_main_#t~nondet9_2|} AuxVars[] AssignedVars[main_~Blen~0] [2018-04-12 01:06:37,432 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,432 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,432 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,432 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,432 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,432 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,433 DEBUG L356 ransitionTransformer]: {main_#t~nondet9=|v_main_#t~nondet9_3|} [2018-04-12 01:06:37,433 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,433 DEBUG L358 ransitionTransformer]: {} [2018-04-12 01:06:37,433 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,433 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,433 DEBUG L331 ransitionTransformer]: Formula: (or (<= 536870911 v_main_~Alen~0_2) (< v_main_~Alen~0_2 1)) InVars {main_~Alen~0=v_main_~Alen~0_2} OutVars{main_~Alen~0=v_main_~Alen~0_2} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,433 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,433 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,433 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,434 DEBUG L331 ransitionTransformer]: Formula: (and (not (<= 536870911 v_main_~Alen~0_4)) (not (< v_main_~Alen~0_4 1))) InVars {main_~Alen~0=v_main_~Alen~0_4} OutVars{main_~Alen~0=v_main_~Alen~0_4} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,434 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,434 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,434 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,434 DEBUG L331 ransitionTransformer]: Formula: (= v_main_~Alen~0_3 1) InVars {} OutVars{main_~Alen~0=v_main_~Alen~0_3} AuxVars[] AssignedVars[main_~Alen~0] [2018-04-12 01:06:37,434 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,434 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,434 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,434 DEBUG L331 ransitionTransformer]: Formula: (or (<= 536870911 v_main_~Blen~0_2) (< v_main_~Blen~0_2 1)) InVars {main_~Blen~0=v_main_~Blen~0_2} OutVars{main_~Blen~0=v_main_~Blen~0_2} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,435 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,435 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,435 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,435 DEBUG L331 ransitionTransformer]: Formula: (and (not (<= 536870911 v_main_~Blen~0_4)) (not (< v_main_~Blen~0_4 1))) InVars {main_~Blen~0=v_main_~Blen~0_4} OutVars{main_~Blen~0=v_main_~Blen~0_4} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,435 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,435 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,435 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,435 DEBUG L331 ransitionTransformer]: Formula: (= v_main_~Blen~0_3 1) InVars {} OutVars{main_~Blen~0=v_main_~Blen~0_3} AuxVars[] AssignedVars[main_~Blen~0] [2018-04-12 01:06:37,435 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,436 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,436 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,436 DEBUG L331 ransitionTransformer]: Formula: (and (not (= 0 |v_main_#t~malloc10.base_1|)) (= (store |v_#valid_12| |v_main_#t~malloc10.base_1| 1) |v_#valid_11|) (= |v_main_#t~malloc10.offset_1| 0) (= 0 (select |v_#valid_12| |v_main_#t~malloc10.base_1|)) (= |v_#length_9| (store |v_#length_10| |v_main_#t~malloc10.base_1| (* 4 v_main_~Alen~0_5)))) InVars {#length=|v_#length_10|, main_~Alen~0=v_main_~Alen~0_5, #valid=|v_#valid_12|} OutVars{#length=|v_#length_9|, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_1|, main_~Alen~0=v_main_~Alen~0_5, main_#t~malloc10.base=|v_main_#t~malloc10.base_1|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid, #length, main_#t~malloc10.offset, main_#t~malloc10.base] [2018-04-12 01:06:37,436 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,436 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,437 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,437 DEBUG L331 ransitionTransformer]: Formula: (and (= v_main_~A~0.offset_1 |v_main_#t~malloc10.offset_2|) (= v_main_~A~0.base_1 |v_main_#t~malloc10.base_2|)) InVars {main_#t~malloc10.base=|v_main_#t~malloc10.base_2|, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_2|} OutVars{main_~A~0.offset=v_main_~A~0.offset_1, main_~A~0.base=v_main_~A~0.base_1, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_2|, main_#t~malloc10.base=|v_main_#t~malloc10.base_2|} AuxVars[] AssignedVars[main_~A~0.offset, main_~A~0.base] [2018-04-12 01:06:37,437 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,437 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,437 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,438 DEBUG L331 ransitionTransformer]: Formula: (and (= |v_main_#t~malloc11.offset_1| 0) (not (= |v_main_#t~malloc11.base_1| 0)) (= (store |v_#valid_14| |v_main_#t~malloc11.base_1| 1) |v_#valid_13|) (= |v_#length_11| (store |v_#length_12| |v_main_#t~malloc11.base_1| (* 4 v_main_~Blen~0_5))) (= 0 (select |v_#valid_14| |v_main_#t~malloc11.base_1|))) InVars {#length=|v_#length_12|, main_~Blen~0=v_main_~Blen~0_5, #valid=|v_#valid_14|} OutVars{#length=|v_#length_11|, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_1|, main_~Blen~0=v_main_~Blen~0_5, main_#t~malloc11.base=|v_main_#t~malloc11.base_1|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[#valid, #length, main_#t~malloc11.offset, main_#t~malloc11.base] [2018-04-12 01:06:37,438 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,438 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,438 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,438 DEBUG L331 ransitionTransformer]: Formula: (and (= v_main_~B~0.offset_1 |v_main_#t~malloc11.offset_2|) (= v_main_~B~0.base_1 |v_main_#t~malloc11.base_2|)) InVars {main_#t~malloc11.base=|v_main_#t~malloc11.base_2|, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_2|} OutVars{main_~B~0.offset=v_main_~B~0.offset_1, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_2|, main_~B~0.base=v_main_~B~0.base_1, main_#t~malloc11.base=|v_main_#t~malloc11.base_2|} AuxVars[] AssignedVars[main_~B~0.offset, main_~B~0.base] [2018-04-12 01:06:37,439 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,439 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,439 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,439 DEBUG L331 ransitionTransformer]: Formula: (and (not (= 0 |v_main_#t~malloc12.base_1|)) (= |v_#valid_15| (store |v_#valid_16| |v_main_#t~malloc12.base_1| 1)) (= 0 |v_main_#t~malloc12.offset_1|) (= 0 (select |v_#valid_16| |v_main_#t~malloc12.base_1|)) (= |v_#length_13| (store |v_#length_14| |v_main_#t~malloc12.base_1| (* 4 v_main_~Alen~0_6)))) InVars {#length=|v_#length_14|, main_~Alen~0=v_main_~Alen~0_6, #valid=|v_#valid_16|} OutVars{main_#t~malloc12.offset=|v_main_#t~malloc12.offset_1|, #length=|v_#length_13|, main_~Alen~0=v_main_~Alen~0_6, main_#t~malloc12.base=|v_main_#t~malloc12.base_1|, #valid=|v_#valid_15|} AuxVars[] AssignedVars[main_#t~malloc12.offset, #valid, #length, main_#t~malloc12.base] [2018-04-12 01:06:37,439 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,440 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,440 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,440 DEBUG L331 ransitionTransformer]: Formula: (and (= v_main_~D~0.base_1 |v_main_#t~malloc12.base_2|) (= v_main_~D~0.offset_1 |v_main_#t~malloc12.offset_2|)) InVars {main_#t~malloc12.offset=|v_main_#t~malloc12.offset_2|, main_#t~malloc12.base=|v_main_#t~malloc12.base_2|} OutVars{main_#t~malloc12.offset=|v_main_#t~malloc12.offset_2|, main_~D~0.base=v_main_~D~0.base_1, main_~D~0.offset=v_main_~D~0.offset_1, main_#t~malloc12.base=|v_main_#t~malloc12.base_2|} AuxVars[] AssignedVars[main_~D~0.base, main_~D~0.offset] [2018-04-12 01:06:37,440 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,440 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,441 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,441 DEBUG L331 ransitionTransformer]: Formula: (and (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offsetInParam_1| v_main_~A~0.offset_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offsetInParam_1| v_main_~B~0.offset_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.baseInParam_1| v_main_~A~0.base_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.baseInParam_1| v_main_~B~0.base_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~BlenInParam_1| v_main_~Blen~0_7) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offsetInParam_1| v_main_~D~0.offset_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~AlenInParam_1| v_main_~Alen~0_8) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.baseInParam_1| v_main_~D~0.base_3)) InVars {main_~B~0.offset=v_main_~B~0.offset_3, main_~A~0.offset=v_main_~A~0.offset_3, main_~Blen~0=v_main_~Blen~0_7, main_~Alen~0=v_main_~Alen~0_8, main_~D~0.base=v_main_~D~0.base_3, main_~A~0.base=v_main_~A~0.base_3, main_~B~0.base=v_main_~B~0.base_3, main_~D~0.offset=v_main_~D~0.offset_3} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.baseInParam_1|, main_~B~0.offset=v_main_~B~0.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offsetInParam_1|, main_~B~0.base=v_main_~B~0.base_3, main_~A~0.offset=v_main_~A~0.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~BlenInParam_1|, main_~Blen~0=v_main_~Blen~0_7, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offsetInParam_1|, main_~Alen~0=v_main_~Alen~0_8, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offsetInParam_1|, main_~D~0.base=v_main_~D~0.base_3, main_~A~0.base=v_main_~A~0.base_3, main_~D~0.offset=v_main_~D~0.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~AlenInParam_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen] [2018-04-12 01:06:37,441 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,441 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,441 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~BlenInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offsetInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offsetInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offsetInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~AlenInParam_1|} [2018-04-12 01:06:37,442 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,442 DEBUG L358 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.baseInParam_1|, main_~B~0.offset=v_main_~B~0.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offsetInParam_1|, main_~B~0.base=v_main_~B~0.base_3, main_~A~0.offset=v_main_~A~0.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~BlenInParam_1|, main_~Blen~0=v_main_~Blen~0_7, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offsetInParam_1|, main_~Alen~0=v_main_~Alen~0_8, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offsetInParam_1|, main_~D~0.base=v_main_~D~0.base_3, main_~A~0.base=v_main_~A~0.base_3, main_~D~0.offset=v_main_~D~0.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~AlenInParam_1|} [2018-04-12 01:06:37,442 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,442 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,442 DEBUG L331 ransitionTransformer]: Formula: (= |v_main_#res_1| 0) InVars {} OutVars{main_#res=|v_main_#res_1|} AuxVars[] AssignedVars[main_#res] [2018-04-12 01:06:37,442 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,443 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,443 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,443 DEBUG L331 ransitionTransformer]: Formula: (and (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base_1|) (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset_1|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base] [2018-04-12 01:06:37,443 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,443 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,444 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,444 DEBUG L331 ransitionTransformer]: Formula: (= |v_#valid_17| (store |v_#valid_18| |v_main_#t~malloc10.base_3| 0)) InVars {main_#t~malloc10.base=|v_main_#t~malloc10.base_3|, #valid=|v_#valid_18|} OutVars{main_#t~malloc10.base=|v_main_#t~malloc10.base_3|, #valid=|v_#valid_17|} AuxVars[] AssignedVars[#valid] [2018-04-12 01:06:37,444 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,444 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,444 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,444 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen_1|) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen] [2018-04-12 01:06:37,445 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,445 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,445 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,445 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,445 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,445 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,445 DEBUG L356 ransitionTransformer]: {main_#t~malloc10.offset=|v_main_#t~malloc10.offset_4|, main_#t~malloc10.base=|v_main_#t~malloc10.base_4|} [2018-04-12 01:06:37,446 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,446 DEBUG L358 ransitionTransformer]: {} [2018-04-12 01:06:37,446 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,446 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,446 DEBUG L331 ransitionTransformer]: Formula: (and (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base_1|) (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset_1|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset] [2018-04-12 01:06:37,446 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,447 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,447 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,447 DEBUG L331 ransitionTransformer]: Formula: (= |v_#valid_19| (store |v_#valid_20| |v_main_#t~malloc11.base_3| 0)) InVars {main_#t~malloc11.base=|v_main_#t~malloc11.base_3|, #valid=|v_#valid_20|} OutVars{main_#t~malloc11.base=|v_main_#t~malloc11.base_3|, #valid=|v_#valid_19|} AuxVars[] AssignedVars[#valid] [2018-04-12 01:06:37,447 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,447 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,447 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,448 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen_1|) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen] [2018-04-12 01:06:37,448 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,448 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,448 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,448 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,448 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,449 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,449 DEBUG L356 ransitionTransformer]: {main_#t~malloc11.offset=|v_main_#t~malloc11.offset_4|, main_#t~malloc11.base=|v_main_#t~malloc11.base_4|} [2018-04-12 01:06:37,449 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,449 DEBUG L358 ransitionTransformer]: {} [2018-04-12 01:06:37,449 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,449 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,450 DEBUG L331 ransitionTransformer]: Formula: (and (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset_1|) (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base_1|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset] [2018-04-12 01:06:37,450 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,450 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,450 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,450 DEBUG L331 ransitionTransformer]: Formula: (= (store |v_#valid_22| |v_main_#t~malloc12.base_3| 0) |v_#valid_21|) InVars {main_#t~malloc12.base=|v_main_#t~malloc12.base_3|, #valid=|v_#valid_22|} OutVars{main_#t~malloc12.base=|v_main_#t~malloc12.base_3|, #valid=|v_#valid_21|} AuxVars[] AssignedVars[#valid] [2018-04-12 01:06:37,450 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,451 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,451 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,451 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_1 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0] [2018-04-12 01:06:37,451 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,451 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,451 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,452 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,452 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,452 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,452 DEBUG L356 ransitionTransformer]: {main_#t~malloc12.offset=|v_main_#t~malloc12.offset_4|, main_#t~malloc12.base=|v_main_#t~malloc12.base_4|} [2018-04-12 01:06:37,452 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,452 DEBUG L358 ransitionTransformer]: {} [2018-04-12 01:06:37,452 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,453 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,453 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_1 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0] [2018-04-12 01:06:37,453 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,453 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,453 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,453 DEBUG L331 ransitionTransformer]: Formula: (= |v_#valid_23| |old(#valid)|) InVars {#valid=|v_#valid_23|, old(#valid)=|old(#valid)|} OutVars{#valid=|v_#valid_23|, old(#valid)=|old(#valid)|} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,454 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,454 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,454 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,454 DEBUG L331 ransitionTransformer]: Formula: (not (= |v_#valid_24| |old(#valid)|)) InVars {#valid=|v_#valid_24|, old(#valid)=|old(#valid)|} OutVars{#valid=|v_#valid_24|, old(#valid)=|old(#valid)|} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,454 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,454 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,455 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,455 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_1 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_2) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_2} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0] [2018-04-12 01:06:37,455 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,455 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,456 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,456 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_1 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_2) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0] [2018-04-12 01:06:37,456 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,456 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,456 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,456 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,457 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,457 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,457 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_1} [2018-04-12 01:06:37,457 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,457 DEBUG L358 ransitionTransformer]: {} [2018-04-12 01:06:37,457 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,457 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,458 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,458 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,458 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,458 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,458 DEBUG L331 ransitionTransformer]: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,458 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,458 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,459 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,459 DEBUG L331 ransitionTransformer]: Formula: (not (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_2 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_2)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_2} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,459 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,459 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,459 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,459 DEBUG L331 ransitionTransformer]: Formula: (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_3 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_3) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_3} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_3} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,460 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,466 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,466 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,467 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,467 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,467 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,467 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,467 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_1 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0] [2018-04-12 01:06:37,468 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,468 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,468 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,468 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_2 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_2} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0] [2018-04-12 01:06:37,468 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,468 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,469 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,469 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,469 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,469 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,469 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,469 DEBUG L331 ransitionTransformer]: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,469 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,470 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,470 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,470 DEBUG L331 ransitionTransformer]: Formula: (or (not (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_3)) (not (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_2 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_2))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_2} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,470 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,470 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,471 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,471 DEBUG L331 ransitionTransformer]: Formula: (and (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_3 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_3) (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_4)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_3} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_3} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,471 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,471 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,471 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,471 DEBUG L331 ransitionTransformer]: Formula: (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_6) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_6} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_6} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,471 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,472 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,472 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,472 DEBUG L331 ransitionTransformer]: Formula: (not (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_7)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_7} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_7} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,472 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,472 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,475 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,476 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0 4) (select |v_#length_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (<= 0 .cse1) (= 1 (select |v_#valid_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (= (select (select |v_#memory_int_part_locs_32_locs_31_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2] [2018-04-12 01:06:37,476 DEBUG L338 ransitionTransformer]: formula has changed [2018-04-12 01:06:37,476 DEBUG L339 ransitionTransformer]: old formula: [2018-04-12 01:06:37,476 DEBUG L340 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0 4) (select |v_#length_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (<= 0 .cse1) (= 1 (select |v_#valid_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (= (select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|)))) [2018-04-12 01:06:37,477 DEBUG L341 ransitionTransformer]: new formula: [2018-04-12 01:06:37,477 DEBUG L342 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0 4) (select |v_#length_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (<= 0 .cse1) (= 1 (select |v_#valid_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (= (select (select |v_#memory_int_part_locs_32_locs_31_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|)))) [2018-04-12 01:06:37,477 DEBUG L346 ransitionTransformer]: invars have changed [2018-04-12 01:06:37,477 DEBUG L347 ransitionTransformer]: old invars: [2018-04-12 01:06:37,477 DEBUG L348 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #length=|v_#length_1|} [2018-04-12 01:06:37,478 DEBUG L349 ransitionTransformer]: new invars: [2018-04-12 01:06:37,478 DEBUG L350 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|} [2018-04-12 01:06:37,478 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,478 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,478 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #length=|v_#length_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|} [2018-04-12 01:06:37,478 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,478 DEBUG L358 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|} [2018-04-12 01:06:37,479 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,479 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,479 DEBUG L331 ransitionTransformer]: Formula: (not (= 1 (select |v_#valid_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_3))) InVars {#valid=|v_#valid_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_3} OutVars{#valid=|v_#valid_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_3} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,479 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,480 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,480 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,480 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_5))) (or (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3 .cse0))) (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3 .cse0 4) (select |v_#length_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_4))))) InVars {#length=|v_#length_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_4} OutVars{#length=|v_#length_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_4} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,480 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,481 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,482 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,482 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0 4) (select |v_#length_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (= (select (select |v_#memory_int_part_locs_32_locs_31_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|) (= 1 (select |v_#valid_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (<= 0 .cse1)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5] [2018-04-12 01:06:37,482 DEBUG L338 ransitionTransformer]: formula has changed [2018-04-12 01:06:37,482 DEBUG L339 ransitionTransformer]: old formula: [2018-04-12 01:06:37,483 DEBUG L340 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0 4) (select |v_#length_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (= (select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|) (= 1 (select |v_#valid_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (<= 0 .cse1)))) [2018-04-12 01:06:37,483 DEBUG L341 ransitionTransformer]: new formula: [2018-04-12 01:06:37,483 DEBUG L342 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0 4) (select |v_#length_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (= (select (select |v_#memory_int_part_locs_32_locs_31_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|) (= 1 (select |v_#valid_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (<= 0 .cse1)))) [2018-04-12 01:06:37,483 DEBUG L346 ransitionTransformer]: invars have changed [2018-04-12 01:06:37,483 DEBUG L347 ransitionTransformer]: old invars: [2018-04-12 01:06:37,483 DEBUG L348 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_3|, #length=|v_#length_5|} [2018-04-12 01:06:37,484 DEBUG L349 ransitionTransformer]: new invars: [2018-04-12 01:06:37,484 DEBUG L350 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|} [2018-04-12 01:06:37,484 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,484 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,484 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_3|, #length=|v_#length_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|} [2018-04-12 01:06:37,484 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,484 DEBUG L358 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|} [2018-04-12 01:06:37,485 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,485 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,485 DEBUG L331 ransitionTransformer]: Formula: (not (= (select |v_#valid_6| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_6) 1)) InVars {#valid=|v_#valid_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_6} OutVars{#valid=|v_#valid_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_6} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,485 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,485 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,486 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,486 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_7))) (or (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5 .cse0))) (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5 .cse0 4) (select |v_#length_6| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_7))))) InVars {#length=|v_#length_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_7, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_7} OutVars{#length=|v_#length_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_7, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_7} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,486 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,486 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,486 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,487 DEBUG L331 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_8) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_8} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_8} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7] [2018-04-12 01:06:37,487 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,487 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,487 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,488 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0 4) (select |v_#length_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (= 1 (select |v_#valid_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (<= 0 .cse1) (= (select (select |v_#memory_int_part_locs_32_locs_31_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3] [2018-04-12 01:06:37,488 DEBUG L338 ransitionTransformer]: formula has changed [2018-04-12 01:06:37,488 DEBUG L339 ransitionTransformer]: old formula: [2018-04-12 01:06:37,488 DEBUG L340 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0 4) (select |v_#length_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (= 1 (select |v_#valid_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (<= 0 .cse1) (= (select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|)))) [2018-04-12 01:06:37,488 DEBUG L341 ransitionTransformer]: new formula: [2018-04-12 01:06:37,488 DEBUG L342 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0 4) (select |v_#length_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (= 1 (select |v_#valid_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (<= 0 .cse1) (= (select (select |v_#memory_int_part_locs_32_locs_31_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|)))) [2018-04-12 01:06:37,489 DEBUG L346 ransitionTransformer]: invars have changed [2018-04-12 01:06:37,489 DEBUG L347 ransitionTransformer]: old invars: [2018-04-12 01:06:37,489 DEBUG L348 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int=|v_#memory_int_2|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2} [2018-04-12 01:06:37,489 DEBUG L349 ransitionTransformer]: new invars: [2018-04-12 01:06:37,489 DEBUG L350 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2} [2018-04-12 01:06:37,489 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,489 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,490 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int=|v_#memory_int_2|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|} [2018-04-12 01:06:37,490 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,490 DEBUG L358 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|} [2018-04-12 01:06:37,490 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,490 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,490 DEBUG L331 ransitionTransformer]: Formula: (not (= 1 (select |v_#valid_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_3))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_3, #valid=|v_#valid_4|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_3, #valid=|v_#valid_4|} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,491 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,491 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,491 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,491 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_5))) (or (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3 .cse0 4) (select |v_#length_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_4))) (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3 .cse0))))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_4, #length=|v_#length_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_5} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_4, #length=|v_#length_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_5} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,491 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,492 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,494 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,494 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2))) (let ((.cse1 (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))) (and (<= (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2 4) (select |v_#length_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)) (= (store |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 (store (select |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) .cse1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|)) |v_#memory_int_part_locs_32_locs_31_5|) (= (select |v_#valid_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) 1) (<= 0 .cse1)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} AuxVars[] AssignedVars[#memory_int_part_locs_32_locs_31] [2018-04-12 01:06:37,494 DEBUG L338 ransitionTransformer]: formula has changed [2018-04-12 01:06:37,494 DEBUG L339 ransitionTransformer]: old formula: [2018-04-12 01:06:37,494 DEBUG L340 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2))) (let ((.cse1 (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))) (and (<= (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2 4) (select |v_#length_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)) (= (store |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 (store (select |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) .cse1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|)) |v_#memory_int_4|) (= (select |v_#valid_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) 1) (<= 0 .cse1)))) [2018-04-12 01:06:37,495 DEBUG L341 ransitionTransformer]: new formula: [2018-04-12 01:06:37,495 DEBUG L342 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2))) (let ((.cse1 (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))) (and (<= (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2 4) (select |v_#length_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)) (= (store |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 (store (select |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) .cse1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|)) |v_#memory_int_part_locs_32_locs_31_5|) (= (select |v_#valid_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) 1) (<= 0 .cse1)))) [2018-04-12 01:06:37,495 DEBUG L346 ransitionTransformer]: invars have changed [2018-04-12 01:06:37,495 DEBUG L347 ransitionTransformer]: old invars: [2018-04-12 01:06:37,495 DEBUG L348 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int=|v_#memory_int_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-12 01:06:37,495 DEBUG L349 ransitionTransformer]: new invars: [2018-04-12 01:06:37,496 DEBUG L350 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-12 01:06:37,496 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,496 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,496 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int=|v_#memory_int_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-12 01:06:37,496 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,496 DEBUG L358 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-12 01:06:37,497 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,497 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,497 DEBUG L331 ransitionTransformer]: Formula: (not (= (select |v_#valid_8| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_3) 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_3, #valid=|v_#valid_8|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_3, #valid=|v_#valid_8|} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,497 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,497 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,498 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,498 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_3))) (or (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3 .cse0))) (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3 .cse0 4) (select |v_#length_8| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_4))))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_3, #length=|v_#length_8|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_4} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_3, #length=|v_#length_8|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_4} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,498 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,498 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,498 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,498 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_9 (+ |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_2| 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_9, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_2|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0] [2018-04-12 01:06:37,499 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,499 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,499 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,499 DEBUG L331 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_2| |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_2|) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_2|} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,499 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,499 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,500 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,500 DEBUG L331 ransitionTransformer]: Formula: (not (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_4| |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_4|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_4|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_4|} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,500 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,500 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,500 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,500 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,501 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,501 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,501 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_3|} [2018-04-12 01:06:37,501 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,501 DEBUG L358 ransitionTransformer]: {} [2018-04-12 01:06:37,501 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,501 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,502 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,502 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,502 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,502 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_3|} [2018-04-12 01:06:37,502 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,502 DEBUG L358 ransitionTransformer]: {} [2018-04-12 01:06:37,502 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,503 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,503 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,503 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,503 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,503 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_3|} [2018-04-12 01:06:37,503 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,503 DEBUG L358 ransitionTransformer]: {} [2018-04-12 01:06:37,504 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,504 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,504 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,504 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,504 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,504 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_5|} [2018-04-12 01:06:37,504 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,505 DEBUG L358 ransitionTransformer]: {} [2018-04-12 01:06:37,505 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,505 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,505 DEBUG L331 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_4) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_4} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_4} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6] [2018-04-12 01:06:37,505 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,505 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,506 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,506 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,506 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,506 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,506 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_3|} [2018-04-12 01:06:37,506 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,506 DEBUG L358 ransitionTransformer]: {} [2018-04-12 01:06:37,507 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,507 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,507 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,507 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,507 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,507 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_5|} [2018-04-12 01:06:37,507 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,508 DEBUG L358 ransitionTransformer]: {} [2018-04-12 01:06:37,508 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,508 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,508 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_5 (+ |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_2| 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_5} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0] [2018-04-12 01:06:37,508 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,508 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,508 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,509 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_5 1) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_5} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0] [2018-04-12 01:06:37,509 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,509 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,509 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,509 DEBUG L331 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_6) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_6} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_6} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4] [2018-04-12 01:06:37,509 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,509 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,510 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,510 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,510 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,510 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,510 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_3|} [2018-04-12 01:06:37,510 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,510 DEBUG L358 ransitionTransformer]: {} [2018-04-12 01:06:37,511 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,511 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,511 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_7 (+ |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_2| 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_7} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0] [2018-04-12 01:06:37,511 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,511 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,512 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,512 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,512 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,512 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,512 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_3|} [2018-04-12 01:06:37,512 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,512 DEBUG L358 ransitionTransformer]: {} [2018-04-12 01:06:37,513 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,513 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,513 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,513 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,513 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,513 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,513 DEBUG L331 ransitionTransformer]: Formula: (= |v_ULTIMATE.start_#t~ret13_2| |v_main_#resOutParam_1|) InVars {main_#res=|v_main_#resOutParam_1|} OutVars{ULTIMATE.start_#t~ret13=|v_ULTIMATE.start_#t~ret13_2|, main_#res=|v_main_#resOutParam_1|} AuxVars[] AssignedVars[ULTIMATE.start_#t~ret13] [2018-04-12 01:06:37,513 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-12 01:06:37,513 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-12 01:06:37,513 DEBUG L356 ransitionTransformer]: {ULTIMATE.start_#t~ret13=|v_ULTIMATE.start_#t~ret13_2|} [2018-04-12 01:06:37,514 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-12 01:06:37,514 DEBUG L358 ransitionTransformer]: {ULTIMATE.start_#t~ret13=|v_ULTIMATE.start_#t~ret13_2|, main_#res=|v_main_#resOutParam_1|} [2018-04-12 01:06:37,514 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,514 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-12 01:06:37,514 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-12 01:06:37,514 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-12 01:06:37,514 DEBUG L360 ransitionTransformer]: [2018-04-12 01:06:37,515 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-12 01:06:37,533 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 12.04 01:06:37 BasicIcfg [2018-04-12 01:06:37,533 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2018-04-12 01:06:37,534 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-12 01:06:37,535 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-12 01:06:37,538 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-12 01:06:37,538 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 12.04 01:06:02" (1/4) ... [2018-04-12 01:06:37,539 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@20a46d7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.04 01:06:37, skipping insertion in model container [2018-04-12 01:06:37,539 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 01:06:03" (2/4) ... [2018-04-12 01:06:37,539 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@20a46d7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.04 01:06:37, skipping insertion in model container [2018-04-12 01:06:37,539 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.04 01:06:03" (3/4) ... [2018-04-12 01:06:37,540 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@20a46d7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 12.04 01:06:37, skipping insertion in model container [2018-04-12 01:06:37,540 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 12.04 01:06:37" (4/4) ... [2018-04-12 01:06:37,541 INFO L107 eAbstractionObserver]: Analyzing ICFG memPartitionedIcfg [2018-04-12 01:06:37,551 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-04-12 01:06:37,560 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 9 error locations. [2018-04-12 01:06:37,599 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-12 01:06:37,600 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-12 01:06:37,600 INFO L370 AbstractCegarLoop]: Hoare is true [2018-04-12 01:06:37,600 INFO L371 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-04-12 01:06:37,600 INFO L372 AbstractCegarLoop]: Backedges is TWOTRACK [2018-04-12 01:06:37,600 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-12 01:06:37,600 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-12 01:06:37,600 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-12 01:06:37,600 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-12 01:06:37,601 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-12 01:06:37,610 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states. [2018-04-12 01:06:37,615 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-12 01:06:37,615 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:06:37,616 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:06:37,616 INFO L408 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:06:37,621 INFO L82 PathProgramCache]: Analyzing trace with hash 2139476875, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:06:37,634 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:06:37,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:06:37,693 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:06:37,732 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 01:06:37,733 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:37,740 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:06:37,740 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-12 01:06:37,767 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:37,768 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:37,770 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-12 01:06:37,770 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:37,784 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-12 01:06:37,784 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-04-12 01:06:37,818 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 20 [2018-04-12 01:06:37,819 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:37,842 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-12 01:06:37,842 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:21, output treesize:20 [2018-04-12 01:06:37,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:37,944 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:06:38,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:38,072 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-12 01:06:38,072 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6, 6] imperfect sequences [] total 10 [2018-04-12 01:06:38,074 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-12 01:06:38,082 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-12 01:06:38,083 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-04-12 01:06:38,084 INFO L87 Difference]: Start difference. First operand 82 states. Second operand 11 states. [2018-04-12 01:06:38,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:06:38,355 INFO L93 Difference]: Finished difference Result 129 states and 143 transitions. [2018-04-12 01:06:38,359 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-12 01:06:38,360 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2018-04-12 01:06:38,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:06:38,372 INFO L225 Difference]: With dead ends: 129 [2018-04-12 01:06:38,372 INFO L226 Difference]: Without dead ends: 77 [2018-04-12 01:06:38,376 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 64 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2018-04-12 01:06:38,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2018-04-12 01:06:38,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 77. [2018-04-12 01:06:38,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-04-12 01:06:38,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 82 transitions. [2018-04-12 01:06:38,418 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 82 transitions. Word has length 38 [2018-04-12 01:06:38,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:06:38,419 INFO L459 AbstractCegarLoop]: Abstraction has 77 states and 82 transitions. [2018-04-12 01:06:38,419 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-12 01:06:38,419 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 82 transitions. [2018-04-12 01:06:38,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-12 01:06:38,421 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:06:38,421 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:06:38,421 INFO L408 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:06:38,421 INFO L82 PathProgramCache]: Analyzing trace with hash 2139476876, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:06:38,432 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:06:38,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:06:38,463 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:06:38,472 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 01:06:38,472 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:38,482 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 01:06:38,482 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:38,489 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:06:38,489 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-04-12 01:06:38,525 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:38,527 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-12 01:06:38,528 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:38,548 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:38,549 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:38,549 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-12 01:06:38,550 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:38,564 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-12 01:06:38,564 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:35 [2018-04-12 01:06:38,586 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:38,587 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:38,589 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 34 [2018-04-12 01:06:38,590 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:38,609 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:38,610 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:38,610 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:38,611 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-04-12 01:06:38,611 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:38,623 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-1 vars, End of recursive call: 4 dim-0 vars, and 1 xjuncts. [2018-04-12 01:06:38,623 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 6 variables, input treesize:48, output treesize:40 [2018-04-12 01:06:38,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:38,811 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:06:43,199 WARN L148 SmtUtils]: Spent 4079ms on a formula simplification that was a NOOP. DAG size: 41 [2018-04-12 01:06:43,227 INFO L682 Elim1Store]: detected equality via solver [2018-04-12 01:06:43,228 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 30 [2018-04-12 01:06:43,276 INFO L682 Elim1Store]: detected equality via solver [2018-04-12 01:06:43,277 INFO L682 Elim1Store]: detected equality via solver [2018-04-12 01:06:43,277 INFO L682 Elim1Store]: detected equality via solver [2018-04-12 01:06:43,277 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 10 [2018-04-12 01:06:43,278 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:43,282 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:06:43,295 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 24 [2018-04-12 01:06:43,298 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 30 [2018-04-12 01:06:43,316 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 9 [2018-04-12 01:06:43,316 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:43,319 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:06:43,320 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:06:43,325 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:06:43,325 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 6 variables, input treesize:42, output treesize:5 [2018-04-12 01:06:43,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:43,365 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-12 01:06:43,365 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 9] imperfect sequences [] total 16 [2018-04-12 01:06:43,366 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-12 01:06:43,367 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-12 01:06:43,367 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2018-04-12 01:06:43,367 INFO L87 Difference]: Start difference. First operand 77 states and 82 transitions. Second operand 17 states. [2018-04-12 01:06:43,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:06:43,982 INFO L93 Difference]: Finished difference Result 118 states and 131 transitions. [2018-04-12 01:06:43,982 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-12 01:06:43,982 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 38 [2018-04-12 01:06:43,982 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:06:43,986 INFO L225 Difference]: With dead ends: 118 [2018-04-12 01:06:43,986 INFO L226 Difference]: Without dead ends: 116 [2018-04-12 01:06:43,987 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 59 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 96 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=112, Invalid=440, Unknown=0, NotChecked=0, Total=552 [2018-04-12 01:06:43,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-04-12 01:06:43,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 86. [2018-04-12 01:06:43,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-04-12 01:06:43,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 94 transitions. [2018-04-12 01:06:43,997 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 94 transitions. Word has length 38 [2018-04-12 01:06:43,997 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:06:43,997 INFO L459 AbstractCegarLoop]: Abstraction has 86 states and 94 transitions. [2018-04-12 01:06:43,997 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-12 01:06:43,997 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 94 transitions. [2018-04-12 01:06:43,998 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-04-12 01:06:43,998 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:06:43,998 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:06:43,998 INFO L408 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:06:43,998 INFO L82 PathProgramCache]: Analyzing trace with hash 1899273898, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:06:44,004 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:06:44,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:06:44,023 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:06:44,028 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 01:06:44,028 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:44,030 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:06:44,030 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-12 01:06:44,036 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:44,037 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:44,037 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-12 01:06:44,038 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:44,042 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-12 01:06:44,042 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-04-12 01:06:44,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:44,086 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:06:44,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:44,153 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-12 01:06:44,154 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6, 6] imperfect sequences [] total 10 [2018-04-12 01:06:44,154 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-12 01:06:44,154 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-12 01:06:44,154 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-04-12 01:06:44,154 INFO L87 Difference]: Start difference. First operand 86 states and 94 transitions. Second operand 11 states. [2018-04-12 01:06:44,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:06:44,239 INFO L93 Difference]: Finished difference Result 86 states and 94 transitions. [2018-04-12 01:06:44,239 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-12 01:06:44,239 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 39 [2018-04-12 01:06:44,240 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:06:44,241 INFO L225 Difference]: With dead ends: 86 [2018-04-12 01:06:44,241 INFO L226 Difference]: Without dead ends: 85 [2018-04-12 01:06:44,241 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 68 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2018-04-12 01:06:44,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-04-12 01:06:44,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-04-12 01:06:44,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-04-12 01:06:44,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 93 transitions. [2018-04-12 01:06:44,252 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 93 transitions. Word has length 39 [2018-04-12 01:06:44,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:06:44,253 INFO L459 AbstractCegarLoop]: Abstraction has 85 states and 93 transitions. [2018-04-12 01:06:44,253 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-12 01:06:44,253 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 93 transitions. [2018-04-12 01:06:44,254 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-04-12 01:06:44,254 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:06:44,254 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:06:44,254 INFO L408 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:06:44,254 INFO L82 PathProgramCache]: Analyzing trace with hash 1899273899, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:06:44,263 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:06:44,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:06:44,287 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:06:44,296 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 01:06:44,296 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:44,303 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 01:06:44,304 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:44,309 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-12 01:06:44,309 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:21, output treesize:19 [2018-04-12 01:06:44,328 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:44,328 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:44,329 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-12 01:06:44,329 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:44,339 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-12 01:06:44,339 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:44,346 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-12 01:06:44,347 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 5 variables, input treesize:32, output treesize:25 [2018-04-12 01:06:44,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:44,439 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:06:46,551 WARN L148 SmtUtils]: Spent 2038ms on a formula simplification that was a NOOP. DAG size: 26 [2018-04-12 01:06:50,636 WARN L148 SmtUtils]: Spent 4060ms on a formula simplification that was a NOOP. DAG size: 26 [2018-04-12 01:06:50,645 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-04-12 01:06:50,645 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:50,649 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-04-12 01:06:50,661 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 5 [2018-04-12 01:06:50,661 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:50,662 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-04-12 01:06:50,662 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:50,665 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:06:50,668 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:06:50,668 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:25, output treesize:5 [2018-04-12 01:06:50,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:50,695 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-12 01:06:50,695 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8, 8] imperfect sequences [] total 14 [2018-04-12 01:06:50,695 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-04-12 01:06:50,695 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-04-12 01:06:50,695 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=174, Unknown=0, NotChecked=0, Total=210 [2018-04-12 01:06:50,695 INFO L87 Difference]: Start difference. First operand 85 states and 93 transitions. Second operand 15 states. [2018-04-12 01:06:51,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:06:51,081 INFO L93 Difference]: Finished difference Result 136 states and 152 transitions. [2018-04-12 01:06:51,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-12 01:06:51,081 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 39 [2018-04-12 01:06:51,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:06:51,083 INFO L225 Difference]: With dead ends: 136 [2018-04-12 01:06:51,083 INFO L226 Difference]: Without dead ends: 135 [2018-04-12 01:06:51,083 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 63 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 6.4s TimeCoverageRelationStatistics Valid=91, Invalid=371, Unknown=0, NotChecked=0, Total=462 [2018-04-12 01:06:51,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-04-12 01:06:51,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 89. [2018-04-12 01:06:51,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-04-12 01:06:51,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 98 transitions. [2018-04-12 01:06:51,092 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 98 transitions. Word has length 39 [2018-04-12 01:06:51,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:06:51,092 INFO L459 AbstractCegarLoop]: Abstraction has 89 states and 98 transitions. [2018-04-12 01:06:51,093 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-04-12 01:06:51,093 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 98 transitions. [2018-04-12 01:06:51,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-04-12 01:06:51,093 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:06:51,093 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:06:51,093 INFO L408 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:06:51,094 INFO L82 PathProgramCache]: Analyzing trace with hash -1252082927, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:06:51,099 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:06:51,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:06:51,119 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:06:51,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:51,148 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:06:51,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:51,194 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-12 01:06:51,194 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8, 8] imperfect sequences [] total 10 [2018-04-12 01:06:51,194 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-12 01:06:51,194 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-12 01:06:51,194 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-04-12 01:06:51,195 INFO L87 Difference]: Start difference. First operand 89 states and 98 transitions. Second operand 10 states. [2018-04-12 01:06:51,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:06:51,329 INFO L93 Difference]: Finished difference Result 203 states and 226 transitions. [2018-04-12 01:06:51,329 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-12 01:06:51,329 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 40 [2018-04-12 01:06:51,329 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:06:51,330 INFO L225 Difference]: With dead ends: 203 [2018-04-12 01:06:51,330 INFO L226 Difference]: Without dead ends: 151 [2018-04-12 01:06:51,331 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 67 SyntacticMatches, 4 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=76, Invalid=164, Unknown=0, NotChecked=0, Total=240 [2018-04-12 01:06:51,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-04-12 01:06:51,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 88. [2018-04-12 01:06:51,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-04-12 01:06:51,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 95 transitions. [2018-04-12 01:06:51,340 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 95 transitions. Word has length 40 [2018-04-12 01:06:51,340 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:06:51,340 INFO L459 AbstractCegarLoop]: Abstraction has 88 states and 95 transitions. [2018-04-12 01:06:51,341 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-12 01:06:51,341 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 95 transitions. [2018-04-12 01:06:51,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-04-12 01:06:51,341 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:06:51,341 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:06:51,341 INFO L408 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:06:51,341 INFO L82 PathProgramCache]: Analyzing trace with hash -1717465618, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:06:51,347 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:06:51,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:06:51,369 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:06:51,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:51,393 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:06:51,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:51,467 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-12 01:06:51,467 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7, 7] imperfect sequences [] total 10 [2018-04-12 01:06:51,467 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-12 01:06:51,468 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-12 01:06:51,468 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2018-04-12 01:06:51,468 INFO L87 Difference]: Start difference. First operand 88 states and 95 transitions. Second operand 10 states. [2018-04-12 01:06:51,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:06:51,602 INFO L93 Difference]: Finished difference Result 128 states and 138 transitions. [2018-04-12 01:06:51,602 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-12 01:06:51,603 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 43 [2018-04-12 01:06:51,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:06:51,604 INFO L225 Difference]: With dead ends: 128 [2018-04-12 01:06:51,604 INFO L226 Difference]: Without dead ends: 117 [2018-04-12 01:06:51,605 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 74 SyntacticMatches, 3 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=50, Invalid=106, Unknown=0, NotChecked=0, Total=156 [2018-04-12 01:06:51,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-04-12 01:06:51,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 88. [2018-04-12 01:06:51,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-04-12 01:06:51,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 94 transitions. [2018-04-12 01:06:51,618 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 94 transitions. Word has length 43 [2018-04-12 01:06:51,619 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:06:51,619 INFO L459 AbstractCegarLoop]: Abstraction has 88 states and 94 transitions. [2018-04-12 01:06:51,619 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-12 01:06:51,619 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 94 transitions. [2018-04-12 01:06:51,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-04-12 01:06:51,620 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:06:51,620 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:06:51,620 INFO L408 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:06:51,621 INFO L82 PathProgramCache]: Analyzing trace with hash 29055424, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:06:51,634 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:06:51,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:06:51,663 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:06:51,672 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:51,672 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:06:51,691 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:51,712 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-12 01:06:51,712 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 3] imperfect sequences [] total 3 [2018-04-12 01:06:51,712 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-12 01:06:51,712 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-12 01:06:51,713 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-12 01:06:51,713 INFO L87 Difference]: Start difference. First operand 88 states and 94 transitions. Second operand 3 states. [2018-04-12 01:06:51,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:06:51,735 INFO L93 Difference]: Finished difference Result 147 states and 159 transitions. [2018-04-12 01:06:51,736 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-12 01:06:51,736 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2018-04-12 01:06:51,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:06:51,737 INFO L225 Difference]: With dead ends: 147 [2018-04-12 01:06:51,737 INFO L226 Difference]: Without dead ends: 98 [2018-04-12 01:06:51,737 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 93 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-12 01:06:51,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-04-12 01:06:51,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 89. [2018-04-12 01:06:51,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-04-12 01:06:51,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 94 transitions. [2018-04-12 01:06:51,745 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 94 transitions. Word has length 48 [2018-04-12 01:06:51,745 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:06:51,745 INFO L459 AbstractCegarLoop]: Abstraction has 89 states and 94 transitions. [2018-04-12 01:06:51,746 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-12 01:06:51,746 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 94 transitions. [2018-04-12 01:06:51,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-04-12 01:06:51,747 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:06:51,747 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:06:51,747 INFO L408 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:06:51,747 INFO L82 PathProgramCache]: Analyzing trace with hash -1793713475, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:06:51,755 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:06:51,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:06:51,782 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:06:51,786 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 01:06:51,786 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:51,803 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 01:06:51,803 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:51,807 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:06:51,807 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-12 01:06:51,820 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:51,821 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:51,821 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-12 01:06:51,821 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:51,829 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-12 01:06:51,829 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:51,835 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-12 01:06:51,836 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:29, output treesize:22 [2018-04-12 01:06:52,118 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:52,118 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:06:54,553 WARN L148 SmtUtils]: Spent 2017ms on a formula simplification that was a NOOP. DAG size: 41 [2018-04-12 01:06:54,624 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 01:06:54,643 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 01:06:54,643 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 23 [2018-04-12 01:06:54,644 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-04-12 01:06:54,644 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-04-12 01:06:54,644 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=484, Unknown=0, NotChecked=0, Total=552 [2018-04-12 01:06:54,644 INFO L87 Difference]: Start difference. First operand 89 states and 94 transitions. Second operand 24 states. [2018-04-12 01:06:56,836 WARN L151 SmtUtils]: Spent 2106ms on a formula simplification. DAG size of input: 57 DAG size of output 56 [2018-04-12 01:06:58,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:06:58,082 INFO L93 Difference]: Finished difference Result 147 states and 157 transitions. [2018-04-12 01:06:58,082 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-04-12 01:06:58,083 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 49 [2018-04-12 01:06:58,083 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:06:58,083 INFO L225 Difference]: With dead ends: 147 [2018-04-12 01:06:58,083 INFO L226 Difference]: Without dead ends: 146 [2018-04-12 01:06:58,084 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 155 ImplicationChecksByTransitivity, 5.5s TimeCoverageRelationStatistics Valid=249, Invalid=1083, Unknown=0, NotChecked=0, Total=1332 [2018-04-12 01:06:58,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-04-12 01:06:58,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 86. [2018-04-12 01:06:58,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-04-12 01:06:58,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 91 transitions. [2018-04-12 01:06:58,098 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 91 transitions. Word has length 49 [2018-04-12 01:06:58,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:06:58,098 INFO L459 AbstractCegarLoop]: Abstraction has 86 states and 91 transitions. [2018-04-12 01:06:58,098 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-04-12 01:06:58,098 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 91 transitions. [2018-04-12 01:06:58,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-04-12 01:06:58,099 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:06:58,099 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:06:58,099 INFO L408 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:06:58,099 INFO L82 PathProgramCache]: Analyzing trace with hash 229425471, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:06:58,109 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:06:58,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:06:58,132 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:06:58,135 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 01:06:58,135 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:58,136 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:06:58,136 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-12 01:06:58,152 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 01:06:58,152 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:06:58,159 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 01:06:58,179 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-12 01:06:58,179 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5, 5] imperfect sequences [] total 5 [2018-04-12 01:06:58,179 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-12 01:06:58,179 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-12 01:06:58,179 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-04-12 01:06:58,179 INFO L87 Difference]: Start difference. First operand 86 states and 91 transitions. Second operand 6 states. [2018-04-12 01:06:58,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:06:58,234 INFO L93 Difference]: Finished difference Result 86 states and 91 transitions. [2018-04-12 01:06:58,234 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-12 01:06:58,234 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 50 [2018-04-12 01:06:58,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:06:58,235 INFO L225 Difference]: With dead ends: 86 [2018-04-12 01:06:58,235 INFO L226 Difference]: Without dead ends: 85 [2018-04-12 01:06:58,236 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 101 GetRequests, 95 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-04-12 01:06:58,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-04-12 01:06:58,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-04-12 01:06:58,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-04-12 01:06:58,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 90 transitions. [2018-04-12 01:06:58,250 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 90 transitions. Word has length 50 [2018-04-12 01:06:58,250 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:06:58,250 INFO L459 AbstractCegarLoop]: Abstraction has 85 states and 90 transitions. [2018-04-12 01:06:58,250 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-12 01:06:58,250 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 90 transitions. [2018-04-12 01:06:58,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-04-12 01:06:58,251 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:06:58,251 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:06:58,251 INFO L408 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:06:58,252 INFO L82 PathProgramCache]: Analyzing trace with hash 229425472, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:06:58,260 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:06:58,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:06:58,282 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:06:58,319 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 01:06:58,319 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:58,378 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-12 01:06:58,378 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:15, output treesize:14 [2018-04-12 01:06:58,460 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 01:06:58,461 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:06:58,540 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 01:06:58,565 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-12 01:06:58,565 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7, 7] imperfect sequences [] total 12 [2018-04-12 01:06:58,566 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-04-12 01:06:58,566 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-04-12 01:06:58,566 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2018-04-12 01:06:58,566 INFO L87 Difference]: Start difference. First operand 85 states and 90 transitions. Second operand 13 states. [2018-04-12 01:06:58,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:06:58,725 INFO L93 Difference]: Finished difference Result 121 states and 130 transitions. [2018-04-12 01:06:58,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-12 01:06:58,726 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 50 [2018-04-12 01:06:58,726 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:06:58,726 INFO L225 Difference]: With dead ends: 121 [2018-04-12 01:06:58,726 INFO L226 Difference]: Without dead ends: 120 [2018-04-12 01:06:58,727 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 87 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=67, Invalid=239, Unknown=0, NotChecked=0, Total=306 [2018-04-12 01:06:58,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-04-12 01:06:58,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 114. [2018-04-12 01:06:58,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-04-12 01:06:58,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 124 transitions. [2018-04-12 01:06:58,740 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 124 transitions. Word has length 50 [2018-04-12 01:06:58,740 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:06:58,740 INFO L459 AbstractCegarLoop]: Abstraction has 114 states and 124 transitions. [2018-04-12 01:06:58,740 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-04-12 01:06:58,740 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 124 transitions. [2018-04-12 01:06:58,740 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-04-12 01:06:58,740 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:06:58,741 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:06:58,741 INFO L408 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:06:58,741 INFO L82 PathProgramCache]: Analyzing trace with hash -72993622, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:06:58,747 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:06:58,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:06:58,765 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:06:58,768 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 01:06:58,768 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:58,773 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 01:06:58,773 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:58,777 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:06:58,777 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-12 01:06:58,790 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:58,791 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:06:58,791 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-12 01:06:58,791 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:58,799 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-12 01:06:58,799 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 01:06:58,804 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-12 01:06:58,804 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:29, output treesize:22 [2018-04-12 01:06:58,831 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 23 treesize of output 30 [2018-04-12 01:06:58,832 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 2 xjuncts. [2018-04-12 01:06:58,850 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-04-12 01:06:58,850 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 4 variables, input treesize:30, output treesize:52 [2018-04-12 01:06:59,057 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 01:06:59,057 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:06:59,630 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 01:06:59,650 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 01:06:59,650 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13] total 24 [2018-04-12 01:06:59,650 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-04-12 01:06:59,650 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-04-12 01:06:59,650 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=531, Unknown=0, NotChecked=0, Total=600 [2018-04-12 01:06:59,651 INFO L87 Difference]: Start difference. First operand 114 states and 124 transitions. Second operand 25 states. [2018-04-12 01:06:59,835 WARN L151 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 61 DAG size of output 60 [2018-04-12 01:07:00,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:07:00,857 INFO L93 Difference]: Finished difference Result 145 states and 159 transitions. [2018-04-12 01:07:00,857 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-12 01:07:00,858 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 56 [2018-04-12 01:07:00,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:07:00,858 INFO L225 Difference]: With dead ends: 145 [2018-04-12 01:07:00,858 INFO L226 Difference]: Without dead ends: 144 [2018-04-12 01:07:00,859 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 124 GetRequests, 88 SyntacticMatches, 1 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 153 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=232, Invalid=1100, Unknown=0, NotChecked=0, Total=1332 [2018-04-12 01:07:00,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-04-12 01:07:00,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 107. [2018-04-12 01:07:00,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-04-12 01:07:00,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 116 transitions. [2018-04-12 01:07:00,873 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 116 transitions. Word has length 56 [2018-04-12 01:07:00,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:07:00,874 INFO L459 AbstractCegarLoop]: Abstraction has 107 states and 116 transitions. [2018-04-12 01:07:00,874 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-04-12 01:07:00,874 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 116 transitions. [2018-04-12 01:07:00,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-04-12 01:07:00,874 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:07:00,875 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:07:00,875 INFO L408 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:07:00,875 INFO L82 PathProgramCache]: Analyzing trace with hash 1791438736, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:07:00,881 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:07:00,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:07:00,898 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:07:00,935 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:07:00,936 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 32 [2018-04-12 01:07:00,954 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:07:00,955 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:07:00,956 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 42 [2018-04-12 01:07:00,958 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 34 [2018-04-12 01:07:00,959 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 01:07:00,967 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:07:00,973 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:07:00,981 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-12 01:07:00,981 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-12 01:07:01,046 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-12 01:07:01,051 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-12 01:07:01,064 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-12 01:07:01,065 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:07:01,122 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_20| Int)) (or (= (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_20| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_20| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_20|))))) is different from false [2018-04-12 01:07:01,126 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_20| Int) (|v_main_#t~malloc11.base_19| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_19| 1))) (or (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_19|))) (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_20| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_19| 0) |v_main_#t~malloc12.base_20| 0) |c_old(#valid)|) (not (= 0 (select .cse0 |v_main_#t~malloc12.base_20|)))))) is different from false [2018-04-12 01:07:01,129 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_20| Int) (|v_main_#t~malloc10.base_17| Int) (|v_main_#t~malloc11.base_19| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_17| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_19| 1))) (or (not (= (select |c_#valid| |v_main_#t~malloc10.base_17|) 0)) (not (= (select .cse0 |v_main_#t~malloc11.base_19|) 0)) (= (store (store (store (store .cse1 |v_main_#t~malloc12.base_20| 1) |v_main_#t~malloc10.base_17| 0) |v_main_#t~malloc11.base_19| 0) |v_main_#t~malloc12.base_20| 0) |c_old(#valid)|) (not (= (select .cse1 |v_main_#t~malloc12.base_20|) 0)))))) is different from false [2018-04-12 01:07:01,144 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-12 01:07:01,164 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-12 01:07:01,165 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-12 01:07:01,165 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-12 01:07:01,165 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-12 01:07:01,165 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-12 01:07:01,165 INFO L87 Difference]: Start difference. First operand 107 states and 116 transitions. Second operand 16 states. [2018-04-12 01:07:01,185 WARN L1011 $PredicateComparison]: unable to prove that (and (= |c_#valid| |c_old(#valid)|) (forall ((|v_main_#t~malloc12.base_20| Int) (|v_main_#t~malloc10.base_17| Int) (|v_main_#t~malloc11.base_19| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_17| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_19| 1))) (or (not (= (select |c_#valid| |v_main_#t~malloc10.base_17|) 0)) (not (= (select .cse0 |v_main_#t~malloc11.base_19|) 0)) (= (store (store (store (store .cse1 |v_main_#t~malloc12.base_20| 1) |v_main_#t~malloc10.base_17| 0) |v_main_#t~malloc11.base_19| 0) |v_main_#t~malloc12.base_20| 0) |c_old(#valid)|) (not (= (select .cse1 |v_main_#t~malloc12.base_20|) 0))))))) is different from false [2018-04-12 01:07:01,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:07:01,703 INFO L93 Difference]: Finished difference Result 199 states and 216 transitions. [2018-04-12 01:07:01,703 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-12 01:07:01,703 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 61 [2018-04-12 01:07:01,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:07:01,705 INFO L225 Difference]: With dead ends: 199 [2018-04-12 01:07:01,705 INFO L226 Difference]: Without dead ends: 188 [2018-04-12 01:07:01,705 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 129 GetRequests, 107 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=54, Invalid=169, Unknown=11, NotChecked=186, Total=420 [2018-04-12 01:07:01,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-04-12 01:07:01,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 185. [2018-04-12 01:07:01,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2018-04-12 01:07:01,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 202 transitions. [2018-04-12 01:07:01,735 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 202 transitions. Word has length 61 [2018-04-12 01:07:01,735 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:07:01,736 INFO L459 AbstractCegarLoop]: Abstraction has 185 states and 202 transitions. [2018-04-12 01:07:01,736 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-12 01:07:01,736 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 202 transitions. [2018-04-12 01:07:01,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-04-12 01:07:01,737 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:07:01,737 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:07:01,737 INFO L408 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:07:01,737 INFO L82 PathProgramCache]: Analyzing trace with hash -1032331687, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:07:01,746 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:07:01,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:07:01,765 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:07:01,803 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:07:01,804 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 38 [2018-04-12 01:07:01,822 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:07:01,823 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:07:01,824 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 40 [2018-04-12 01:07:01,829 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 34 [2018-04-12 01:07:01,830 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 01:07:01,841 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:07:01,879 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:07:01,887 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-12 01:07:01,887 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-12 01:07:02,013 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-12 01:07:02,020 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-12 01:07:02,041 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-12 01:07:02,041 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:07:02,097 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_21| Int)) (or (= (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_21| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_21| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_21|))))) is different from false [2018-04-12 01:07:02,106 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_20| Int) (|v_main_#t~malloc12.base_21| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_20| 1))) (or (not (= (select .cse0 |v_main_#t~malloc12.base_21|) 0)) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_21| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_20| 0) |v_main_#t~malloc12.base_21| 0)) (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_20|)))))) is different from false [2018-04-12 01:07:02,112 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_20| Int) (|v_main_#t~malloc10.base_18| Int) (|v_main_#t~malloc12.base_21| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_18| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_20| 1))) (or (not (= (select .cse0 |v_main_#t~malloc11.base_20|) 0)) (not (= 0 (select |c_#valid| |v_main_#t~malloc10.base_18|))) (= (store (store (store (store .cse1 |v_main_#t~malloc12.base_21| 1) |v_main_#t~malloc10.base_18| 0) |v_main_#t~malloc11.base_20| 0) |v_main_#t~malloc12.base_21| 0) |c_old(#valid)|) (not (= 0 (select .cse1 |v_main_#t~malloc12.base_21|))))))) is different from false [2018-04-12 01:07:02,135 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-12 01:07:02,168 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-12 01:07:02,168 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-12 01:07:02,168 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-12 01:07:02,168 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-12 01:07:02,169 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-12 01:07:02,169 INFO L87 Difference]: Start difference. First operand 185 states and 202 transitions. Second operand 16 states. [2018-04-12 01:07:02,208 WARN L1011 $PredicateComparison]: unable to prove that (and (forall ((|v_main_#t~malloc11.base_20| Int) (|v_main_#t~malloc10.base_18| Int) (|v_main_#t~malloc12.base_21| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_18| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_20| 1))) (or (not (= (select .cse0 |v_main_#t~malloc11.base_20|) 0)) (not (= 0 (select |c_#valid| |v_main_#t~malloc10.base_18|))) (= (store (store (store (store .cse1 |v_main_#t~malloc12.base_21| 1) |v_main_#t~malloc10.base_18| 0) |v_main_#t~malloc11.base_20| 0) |v_main_#t~malloc12.base_21| 0) |c_old(#valid)|) (not (= 0 (select .cse1 |v_main_#t~malloc12.base_21|))))))) (= |c_#valid| |c_old(#valid)|)) is different from false [2018-04-12 01:07:02,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:07:02,929 INFO L93 Difference]: Finished difference Result 277 states and 301 transitions. [2018-04-12 01:07:02,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-12 01:07:02,929 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 62 [2018-04-12 01:07:02,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:07:02,930 INFO L225 Difference]: With dead ends: 277 [2018-04-12 01:07:02,930 INFO L226 Difference]: Without dead ends: 266 [2018-04-12 01:07:02,931 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 109 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=54, Invalid=171, Unknown=9, NotChecked=186, Total=420 [2018-04-12 01:07:02,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 266 states. [2018-04-12 01:07:02,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 266 to 186. [2018-04-12 01:07:02,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-04-12 01:07:02,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 203 transitions. [2018-04-12 01:07:02,960 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 203 transitions. Word has length 62 [2018-04-12 01:07:02,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:07:02,960 INFO L459 AbstractCegarLoop]: Abstraction has 186 states and 203 transitions. [2018-04-12 01:07:02,960 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-12 01:07:02,960 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 203 transitions. [2018-04-12 01:07:02,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-04-12 01:07:02,961 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:07:02,961 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:07:02,961 INFO L408 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:07:02,961 INFO L82 PathProgramCache]: Analyzing trace with hash -1753613222, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:07:02,967 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:07:02,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:07:02,985 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:07:03,019 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:07:03,020 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 32 [2018-04-12 01:07:03,034 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:07:03,035 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:07:03,036 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 40 [2018-04-12 01:07:03,038 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 34 [2018-04-12 01:07:03,038 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 01:07:03,046 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:07:03,051 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:07:03,057 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-12 01:07:03,057 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-12 01:07:03,103 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-12 01:07:03,106 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-12 01:07:03,119 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-12 01:07:03,120 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:07:03,154 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_22| Int)) (or (= (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_22| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_22| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_22|))))) is different from false [2018-04-12 01:07:03,157 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_21| Int) (|v_main_#t~malloc12.base_22| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_21| 1))) (or (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_21|))) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_22| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_21| 0) |v_main_#t~malloc12.base_22| 0)) (not (= (select .cse0 |v_main_#t~malloc12.base_22|) 0))))) is different from false [2018-04-12 01:07:03,160 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_21| Int) (|v_main_#t~malloc10.base_19| Int) (|v_main_#t~malloc12.base_22| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_19| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_21| 1))) (or (not (= 0 (select .cse0 |v_main_#t~malloc11.base_21|))) (= (store (store (store (store .cse1 |v_main_#t~malloc12.base_22| 1) |v_main_#t~malloc10.base_19| 0) |v_main_#t~malloc11.base_21| 0) |v_main_#t~malloc12.base_22| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc10.base_19|))) (not (= 0 (select .cse1 |v_main_#t~malloc12.base_22|))))))) is different from false [2018-04-12 01:07:03,176 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-12 01:07:03,195 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-12 01:07:03,195 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-12 01:07:03,196 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-12 01:07:03,196 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-12 01:07:03,196 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-12 01:07:03,196 INFO L87 Difference]: Start difference. First operand 186 states and 203 transitions. Second operand 16 states. [2018-04-12 01:07:03,211 WARN L1011 $PredicateComparison]: unable to prove that (and (= |c_#valid| |c_old(#valid)|) (forall ((|v_main_#t~malloc11.base_21| Int) (|v_main_#t~malloc10.base_19| Int) (|v_main_#t~malloc12.base_22| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_19| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_21| 1))) (or (not (= 0 (select .cse0 |v_main_#t~malloc11.base_21|))) (= (store (store (store (store .cse1 |v_main_#t~malloc12.base_22| 1) |v_main_#t~malloc10.base_19| 0) |v_main_#t~malloc11.base_21| 0) |v_main_#t~malloc12.base_22| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc10.base_19|))) (not (= 0 (select .cse1 |v_main_#t~malloc12.base_22|)))))))) is different from false [2018-04-12 01:07:05,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:07:05,082 INFO L93 Difference]: Finished difference Result 277 states and 301 transitions. [2018-04-12 01:07:05,082 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-12 01:07:05,082 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 62 [2018-04-12 01:07:05,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:07:05,083 INFO L225 Difference]: With dead ends: 277 [2018-04-12 01:07:05,083 INFO L226 Difference]: Without dead ends: 266 [2018-04-12 01:07:05,084 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 109 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=171, Unknown=9, NotChecked=186, Total=420 [2018-04-12 01:07:05,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 266 states. [2018-04-12 01:07:05,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 266 to 186. [2018-04-12 01:07:05,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-04-12 01:07:05,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 203 transitions. [2018-04-12 01:07:05,113 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 203 transitions. Word has length 62 [2018-04-12 01:07:05,113 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:07:05,113 INFO L459 AbstractCegarLoop]: Abstraction has 186 states and 203 transitions. [2018-04-12 01:07:05,113 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-12 01:07:05,113 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 203 transitions. [2018-04-12 01:07:05,114 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-04-12 01:07:05,114 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:07:05,114 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:07:05,114 INFO L408 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:07:05,114 INFO L82 PathProgramCache]: Analyzing trace with hash 740207311, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:07:05,129 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:07:05,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:07:05,149 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:07:05,181 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:07:05,182 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 38 [2018-04-12 01:07:05,197 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:07:05,198 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 01:07:05,198 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 40 [2018-04-12 01:07:05,200 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 34 [2018-04-12 01:07:05,200 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 01:07:05,207 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:07:05,212 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:07:05,219 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-12 01:07:05,219 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-12 01:07:05,285 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-12 01:07:05,289 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-12 01:07:05,302 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-12 01:07:05,303 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:07:05,347 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_23| Int)) (or (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_23|))) (= |c_old(#valid)| (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_23| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_23| 0)))) is different from false [2018-04-12 01:07:05,351 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_23| Int) (|v_main_#t~malloc11.base_22| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_22| 1))) (or (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_23| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_22| 0) |v_main_#t~malloc12.base_23| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_22|))) (not (= (select .cse0 |v_main_#t~malloc12.base_23|) 0))))) is different from false [2018-04-12 01:07:05,355 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_23| Int) (|v_main_#t~malloc10.base_20| Int) (|v_main_#t~malloc11.base_22| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_20| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_22| 1))) (or (not (= 0 (select .cse0 |v_main_#t~malloc12.base_23|))) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_23| 1) |v_main_#t~malloc10.base_20| 0) |v_main_#t~malloc11.base_22| 0) |v_main_#t~malloc12.base_23| 0)) (not (= 0 (select .cse1 |v_main_#t~malloc11.base_22|))) (not (= (select |c_#valid| |v_main_#t~malloc10.base_20|) 0)))))) is different from false [2018-04-12 01:07:05,371 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-12 01:07:05,391 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-12 01:07:05,391 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-12 01:07:05,391 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-12 01:07:05,391 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-12 01:07:05,392 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-12 01:07:05,392 INFO L87 Difference]: Start difference. First operand 186 states and 203 transitions. Second operand 16 states. [2018-04-12 01:07:05,408 WARN L1011 $PredicateComparison]: unable to prove that (and (forall ((|v_main_#t~malloc12.base_23| Int) (|v_main_#t~malloc10.base_20| Int) (|v_main_#t~malloc11.base_22| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_20| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_22| 1))) (or (not (= 0 (select .cse0 |v_main_#t~malloc12.base_23|))) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_23| 1) |v_main_#t~malloc10.base_20| 0) |v_main_#t~malloc11.base_22| 0) |v_main_#t~malloc12.base_23| 0)) (not (= 0 (select .cse1 |v_main_#t~malloc11.base_22|))) (not (= (select |c_#valid| |v_main_#t~malloc10.base_20|) 0)))))) (= |c_#valid| |c_old(#valid)|)) is different from false [2018-04-12 01:07:08,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:07:08,002 INFO L93 Difference]: Finished difference Result 187 states and 203 transitions. [2018-04-12 01:07:08,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-12 01:07:08,003 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 63 [2018-04-12 01:07:08,003 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:07:08,003 INFO L225 Difference]: With dead ends: 187 [2018-04-12 01:07:08,003 INFO L226 Difference]: Without dead ends: 176 [2018-04-12 01:07:08,004 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 135 GetRequests, 111 SyntacticMatches, 5 SemanticMatches, 19 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=54, Invalid=170, Unknown=10, NotChecked=186, Total=420 [2018-04-12 01:07:08,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-04-12 01:07:08,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 94. [2018-04-12 01:07:08,020 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-04-12 01:07:08,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 102 transitions. [2018-04-12 01:07:08,020 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 102 transitions. Word has length 63 [2018-04-12 01:07:08,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:07:08,021 INFO L459 AbstractCegarLoop]: Abstraction has 94 states and 102 transitions. [2018-04-12 01:07:08,021 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-12 01:07:08,021 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 102 transitions. [2018-04-12 01:07:08,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-04-12 01:07:08,022 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:07:08,022 INFO L355 BasicCegarLoop]: trace histogram [4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:07:08,022 INFO L408 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:07:08,022 INFO L82 PathProgramCache]: Analyzing trace with hash -452021334, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:07:08,029 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:07:08,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:07:08,055 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:07:08,058 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 01:07:08,059 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:07:08,065 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:07:08,066 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-12 01:07:08,321 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-12 01:07:08,322 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:07:08,634 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-12 01:07:08,654 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 01:07:08,654 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 27 [2018-04-12 01:07:08,654 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-04-12 01:07:08,654 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-04-12 01:07:08,654 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=671, Unknown=0, NotChecked=0, Total=756 [2018-04-12 01:07:08,655 INFO L87 Difference]: Start difference. First operand 94 states and 102 transitions. Second operand 28 states. [2018-04-12 01:07:09,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:07:09,815 INFO L93 Difference]: Finished difference Result 202 states and 221 transitions. [2018-04-12 01:07:09,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-12 01:07:09,816 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 76 [2018-04-12 01:07:09,816 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:07:09,817 INFO L225 Difference]: With dead ends: 202 [2018-04-12 01:07:09,817 INFO L226 Difference]: Without dead ends: 201 [2018-04-12 01:07:09,818 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 171 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 284 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=402, Invalid=1760, Unknown=0, NotChecked=0, Total=2162 [2018-04-12 01:07:09,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2018-04-12 01:07:09,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 149. [2018-04-12 01:07:09,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-04-12 01:07:09,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 163 transitions. [2018-04-12 01:07:09,865 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 163 transitions. Word has length 76 [2018-04-12 01:07:09,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:07:09,866 INFO L459 AbstractCegarLoop]: Abstraction has 149 states and 163 transitions. [2018-04-12 01:07:09,866 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-04-12 01:07:09,866 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 163 transitions. [2018-04-12 01:07:09,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-04-12 01:07:09,867 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:07:09,867 INFO L355 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:07:09,867 INFO L408 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:07:09,868 INFO L82 PathProgramCache]: Analyzing trace with hash 888884808, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:07:09,874 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:07:09,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:07:09,899 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:07:09,901 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 01:07:09,901 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:07:09,904 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:07:09,904 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-12 01:07:10,172 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 16 proven. 42 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-04-12 01:07:10,173 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:07:10,576 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 16 proven. 42 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-04-12 01:07:10,596 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 01:07:10,596 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 31 [2018-04-12 01:07:10,596 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-12 01:07:10,596 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-12 01:07:10,597 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=112, Invalid=880, Unknown=0, NotChecked=0, Total=992 [2018-04-12 01:07:10,597 INFO L87 Difference]: Start difference. First operand 149 states and 163 transitions. Second operand 32 states. [2018-04-12 01:07:12,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:07:12,178 INFO L93 Difference]: Finished difference Result 268 states and 293 transitions. [2018-04-12 01:07:12,179 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-04-12 01:07:12,179 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 94 [2018-04-12 01:07:12,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:07:12,180 INFO L225 Difference]: With dead ends: 268 [2018-04-12 01:07:12,180 INFO L226 Difference]: Without dead ends: 267 [2018-04-12 01:07:12,181 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 209 GetRequests, 158 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 360 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=532, Invalid=2224, Unknown=0, NotChecked=0, Total=2756 [2018-04-12 01:07:12,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states. [2018-04-12 01:07:12,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 158. [2018-04-12 01:07:12,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-04-12 01:07:12,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 172 transitions. [2018-04-12 01:07:12,217 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 172 transitions. Word has length 94 [2018-04-12 01:07:12,217 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:07:12,218 INFO L459 AbstractCegarLoop]: Abstraction has 158 states and 172 transitions. [2018-04-12 01:07:12,218 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-12 01:07:12,218 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 172 transitions. [2018-04-12 01:07:12,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-04-12 01:07:12,218 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:07:12,219 INFO L355 BasicCegarLoop]: trace histogram [8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:07:12,219 INFO L408 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:07:12,219 INFO L82 PathProgramCache]: Analyzing trace with hash 1100056318, now seen corresponding path program 2 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:07:12,226 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:07:12,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:07:12,261 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:07:12,264 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 01:07:12,264 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:07:12,280 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:07:12,280 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-12 01:07:12,795 INFO L134 CoverageAnalysis]: Checked inductivity of 167 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-12 01:07:12,795 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:07:13,586 INFO L134 CoverageAnalysis]: Checked inductivity of 167 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-12 01:07:13,606 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 01:07:13,606 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 43 [2018-04-12 01:07:13,607 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-04-12 01:07:13,607 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-04-12 01:07:13,608 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=1725, Unknown=0, NotChecked=0, Total=1892 [2018-04-12 01:07:13,608 INFO L87 Difference]: Start difference. First operand 158 states and 172 transitions. Second operand 44 states. [2018-04-12 01:07:15,009 WARN L151 SmtUtils]: Spent 153ms on a formula simplification. DAG size of input: 73 DAG size of output 69 [2018-04-12 01:07:15,808 WARN L151 SmtUtils]: Spent 728ms on a formula simplification. DAG size of input: 62 DAG size of output 58 [2018-04-12 01:07:16,066 WARN L151 SmtUtils]: Spent 194ms on a formula simplification. DAG size of input: 69 DAG size of output 67 [2018-04-12 01:07:16,457 WARN L148 SmtUtils]: Spent 325ms on a formula simplification that was a NOOP. DAG size: 54 [2018-04-12 01:07:18,794 WARN L151 SmtUtils]: Spent 688ms on a formula simplification. DAG size of input: 75 DAG size of output 67 [2018-04-12 01:07:19,019 WARN L151 SmtUtils]: Spent 158ms on a formula simplification. DAG size of input: 85 DAG size of output 81 [2018-04-12 01:07:19,683 WARN L148 SmtUtils]: Spent 607ms on a formula simplification that was a NOOP. DAG size: 65 [2018-04-12 01:07:20,302 WARN L148 SmtUtils]: Spent 566ms on a formula simplification that was a NOOP. DAG size: 59 [2018-04-12 01:07:21,619 WARN L151 SmtUtils]: Spent 1227ms on a formula simplification. DAG size of input: 72 DAG size of output 70 [2018-04-12 01:07:21,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:07:21,642 INFO L93 Difference]: Finished difference Result 421 states and 460 transitions. [2018-04-12 01:07:21,642 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-04-12 01:07:21,642 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 128 [2018-04-12 01:07:21,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:07:21,644 INFO L225 Difference]: With dead ends: 421 [2018-04-12 01:07:21,644 INFO L226 Difference]: Without dead ends: 420 [2018-04-12 01:07:21,645 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 297 GetRequests, 214 SyntacticMatches, 0 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1207 ImplicationChecksByTransitivity, 8.1s TimeCoverageRelationStatistics Valid=1221, Invalid=5919, Unknown=0, NotChecked=0, Total=7140 [2018-04-12 01:07:21,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 420 states. [2018-04-12 01:07:21,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 420 to 277. [2018-04-12 01:07:21,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 277 states. [2018-04-12 01:07:21,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277 states to 277 states and 303 transitions. [2018-04-12 01:07:21,715 INFO L78 Accepts]: Start accepts. Automaton has 277 states and 303 transitions. Word has length 128 [2018-04-12 01:07:21,715 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:07:21,716 INFO L459 AbstractCegarLoop]: Abstraction has 277 states and 303 transitions. [2018-04-12 01:07:21,716 INFO L460 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-04-12 01:07:21,716 INFO L276 IsEmpty]: Start isEmpty. Operand 277 states and 303 transitions. [2018-04-12 01:07:21,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-04-12 01:07:21,717 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:07:21,717 INFO L355 BasicCegarLoop]: trace histogram [10, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:07:21,717 INFO L408 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:07:21,718 INFO L82 PathProgramCache]: Analyzing trace with hash 746499740, now seen corresponding path program 2 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:07:21,731 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:07:21,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:07:21,768 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:07:21,771 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 01:07:21,771 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:07:21,774 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:07:21,774 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-12 01:07:22,358 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 16 proven. 216 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-04-12 01:07:22,359 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:07:23,326 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 16 proven. 216 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-04-12 01:07:23,346 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 01:07:23,346 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 47 [2018-04-12 01:07:23,346 INFO L442 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-04-12 01:07:23,346 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-04-12 01:07:23,347 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=2042, Unknown=0, NotChecked=0, Total=2256 [2018-04-12 01:07:23,347 INFO L87 Difference]: Start difference. First operand 277 states and 303 transitions. Second operand 48 states. [2018-04-12 01:07:24,677 WARN L151 SmtUtils]: Spent 370ms on a formula simplification. DAG size of input: 75 DAG size of output 67 [2018-04-12 01:07:26,035 WARN L151 SmtUtils]: Spent 1295ms on a formula simplification. DAG size of input: 85 DAG size of output 81 [2018-04-12 01:07:26,610 WARN L151 SmtUtils]: Spent 136ms on a formula simplification. DAG size of input: 79 DAG size of output 65 [2018-04-12 01:07:27,085 WARN L151 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 72 DAG size of output 70 [2018-04-12 01:07:27,817 WARN L148 SmtUtils]: Spent 273ms on a formula simplification that was a NOOP. DAG size: 48 [2018-04-12 01:07:28,139 WARN L151 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 77 DAG size of output 65 [2018-04-12 01:07:29,043 WARN L148 SmtUtils]: Spent 555ms on a formula simplification that was a NOOP. DAG size: 56 [2018-04-12 01:07:29,678 WARN L151 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 76 DAG size of output 64 [2018-04-12 01:07:30,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:07:30,261 INFO L93 Difference]: Finished difference Result 554 states and 605 transitions. [2018-04-12 01:07:30,261 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-04-12 01:07:30,261 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 146 [2018-04-12 01:07:30,262 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:07:30,263 INFO L225 Difference]: With dead ends: 554 [2018-04-12 01:07:30,263 INFO L226 Difference]: Without dead ends: 553 [2018-04-12 01:07:30,265 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 333 GetRequests, 246 SyntacticMatches, 0 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1353 ImplicationChecksByTransitivity, 7.1s TimeCoverageRelationStatistics Valid=1402, Invalid=6430, Unknown=0, NotChecked=0, Total=7832 [2018-04-12 01:07:30,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2018-04-12 01:07:30,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 286. [2018-04-12 01:07:30,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 286 states. [2018-04-12 01:07:30,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 286 states to 286 states and 312 transitions. [2018-04-12 01:07:30,346 INFO L78 Accepts]: Start accepts. Automaton has 286 states and 312 transitions. Word has length 146 [2018-04-12 01:07:30,347 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:07:30,347 INFO L459 AbstractCegarLoop]: Abstraction has 286 states and 312 transitions. [2018-04-12 01:07:30,347 INFO L460 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-04-12 01:07:30,347 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 312 transitions. [2018-04-12 01:07:30,348 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 233 [2018-04-12 01:07:30,348 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:07:30,348 INFO L355 BasicCegarLoop]: trace histogram [16, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:07:30,348 INFO L408 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:07:30,348 INFO L82 PathProgramCache]: Analyzing trace with hash -1895798874, now seen corresponding path program 3 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:07:30,354 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:07:30,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:07:30,405 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:07:30,407 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 01:07:30,408 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:07:30,410 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:07:30,411 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-12 01:07:31,749 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 0 proven. 791 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-04-12 01:07:31,749 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:07:34,135 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 0 proven. 791 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-04-12 01:07:34,155 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 01:07:34,155 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 75 [2018-04-12 01:07:34,155 INFO L442 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-04-12 01:07:34,156 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-04-12 01:07:34,157 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=451, Invalid=5249, Unknown=0, NotChecked=0, Total=5700 [2018-04-12 01:07:34,157 INFO L87 Difference]: Start difference. First operand 286 states and 312 transitions. Second operand 76 states. [2018-04-12 01:07:35,454 WARN L151 SmtUtils]: Spent 171ms on a formula simplification. DAG size of input: 107 DAG size of output 101 [2018-04-12 01:07:36,502 WARN L151 SmtUtils]: Spent 267ms on a formula simplification. DAG size of input: 140 DAG size of output 124 [2018-04-12 01:07:37,394 WARN L151 SmtUtils]: Spent 749ms on a formula simplification. DAG size of input: 117 DAG size of output 97 [2018-04-12 01:07:38,620 WARN L151 SmtUtils]: Spent 1111ms on a formula simplification. DAG size of input: 136 DAG size of output 126 [2018-04-12 01:07:40,903 WARN L151 SmtUtils]: Spent 1109ms on a formula simplification. DAG size of input: 123 DAG size of output 115 [2018-04-12 01:07:41,755 WARN L151 SmtUtils]: Spent 735ms on a formula simplification. DAG size of input: 103 DAG size of output 87 [2018-04-12 01:07:43,290 WARN L151 SmtUtils]: Spent 1422ms on a formula simplification. DAG size of input: 119 DAG size of output 111 [2018-04-12 01:07:45,367 WARN L151 SmtUtils]: Spent 930ms on a formula simplification. DAG size of input: 106 DAG size of output 100 [2018-04-12 01:07:46,745 WARN L151 SmtUtils]: Spent 1257ms on a formula simplification. DAG size of input: 89 DAG size of output 77 [2018-04-12 01:07:47,074 WARN L151 SmtUtils]: Spent 196ms on a formula simplification. DAG size of input: 102 DAG size of output 96 [2018-04-12 01:07:48,776 WARN L151 SmtUtils]: Spent 584ms on a formula simplification. DAG size of input: 89 DAG size of output 85 [2018-04-12 01:07:49,612 WARN L151 SmtUtils]: Spent 728ms on a formula simplification. DAG size of input: 75 DAG size of output 67 [2018-04-12 01:07:50,434 WARN L151 SmtUtils]: Spent 707ms on a formula simplification. DAG size of input: 85 DAG size of output 81 [2018-04-12 01:07:51,755 WARN L151 SmtUtils]: Spent 254ms on a formula simplification. DAG size of input: 72 DAG size of output 70 [2018-04-12 01:07:52,159 WARN L151 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 69 DAG size of output 67 [2018-04-12 01:07:53,263 WARN L148 SmtUtils]: Spent 115ms on a formula simplification that was a NOOP. DAG size: 56 [2018-04-12 01:07:54,652 WARN L151 SmtUtils]: Spent 134ms on a formula simplification. DAG size of input: 111 DAG size of output 91 [2018-04-12 01:07:55,705 WARN L151 SmtUtils]: Spent 858ms on a formula simplification. DAG size of input: 130 DAG size of output 106 [2018-04-12 01:07:57,299 WARN L151 SmtUtils]: Spent 1431ms on a formula simplification. DAG size of input: 152 DAG size of output 140 [2018-04-12 01:07:57,526 WARN L148 SmtUtils]: Spent 101ms on a formula simplification that was a NOOP. DAG size: 112 [2018-04-12 01:07:58,190 WARN L151 SmtUtils]: Spent 272ms on a formula simplification. DAG size of input: 139 DAG size of output 127 [2018-04-12 01:07:58,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:07:58,266 INFO L93 Difference]: Finished difference Result 865 states and 944 transitions. [2018-04-12 01:07:58,267 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2018-04-12 01:07:58,267 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 232 [2018-04-12 01:07:58,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:07:58,270 INFO L225 Difference]: With dead ends: 865 [2018-04-12 01:07:58,270 INFO L226 Difference]: Without dead ends: 864 [2018-04-12 01:07:58,274 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 545 GetRequests, 390 SyntacticMatches, 0 SemanticMatches, 155 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4999 ImplicationChecksByTransitivity, 24.5s TimeCoverageRelationStatistics Valid=3993, Invalid=20499, Unknown=0, NotChecked=0, Total=24492 [2018-04-12 01:07:58,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 864 states. [2018-04-12 01:07:58,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 864 to 533. [2018-04-12 01:07:58,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 533 states. [2018-04-12 01:07:58,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 533 states and 583 transitions. [2018-04-12 01:07:58,448 INFO L78 Accepts]: Start accepts. Automaton has 533 states and 583 transitions. Word has length 232 [2018-04-12 01:07:58,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:07:58,448 INFO L459 AbstractCegarLoop]: Abstraction has 533 states and 583 transitions. [2018-04-12 01:07:58,448 INFO L460 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-04-12 01:07:58,448 INFO L276 IsEmpty]: Start isEmpty. Operand 533 states and 583 transitions. [2018-04-12 01:07:58,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 251 [2018-04-12 01:07:58,449 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:07:58,450 INFO L355 BasicCegarLoop]: trace histogram [18, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:07:58,450 INFO L408 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:07:58,450 INFO L82 PathProgramCache]: Analyzing trace with hash 947464516, now seen corresponding path program 3 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:07:58,456 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:07:58,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:07:58,527 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:07:58,542 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 01:07:58,543 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:07:58,561 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:07:58,561 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-12 01:07:59,937 INFO L134 CoverageAnalysis]: Checked inductivity of 958 backedges. 16 proven. 924 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-12 01:07:59,937 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:08:02,482 INFO L134 CoverageAnalysis]: Checked inductivity of 958 backedges. 16 proven. 924 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-12 01:08:02,502 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 01:08:02,503 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 79 [2018-04-12 01:08:02,503 INFO L442 AbstractCegarLoop]: Interpolant automaton has 80 states [2018-04-12 01:08:02,503 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2018-04-12 01:08:02,504 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=566, Invalid=5754, Unknown=0, NotChecked=0, Total=6320 [2018-04-12 01:08:02,504 INFO L87 Difference]: Start difference. First operand 533 states and 583 transitions. Second operand 80 states. [2018-04-12 01:08:03,759 WARN L151 SmtUtils]: Spent 113ms on a formula simplification. DAG size of input: 103 DAG size of output 89 [2018-04-12 01:08:04,115 WARN L151 SmtUtils]: Spent 214ms on a formula simplification. DAG size of input: 130 DAG size of output 106 [2018-04-12 01:08:04,621 WARN L151 SmtUtils]: Spent 368ms on a formula simplification. DAG size of input: 152 DAG size of output 140 [2018-04-12 01:08:04,850 WARN L148 SmtUtils]: Spent 106ms on a formula simplification that was a NOOP. DAG size: 112 [2018-04-12 01:08:05,528 WARN L151 SmtUtils]: Spent 189ms on a formula simplification. DAG size of input: 114 DAG size of output 92 [2018-04-12 01:08:06,347 WARN L151 SmtUtils]: Spent 284ms on a formula simplification. DAG size of input: 139 DAG size of output 127 [2018-04-12 01:08:07,290 WARN L151 SmtUtils]: Spent 797ms on a formula simplification. DAG size of input: 117 DAG size of output 97 [2018-04-12 01:08:08,349 WARN L151 SmtUtils]: Spent 930ms on a formula simplification. DAG size of input: 136 DAG size of output 126 [2018-04-12 01:08:09,214 WARN L151 SmtUtils]: Spent 136ms on a formula simplification. DAG size of input: 112 DAG size of output 92 [2018-04-12 01:08:11,166 WARN L151 SmtUtils]: Spent 1432ms on a formula simplification. DAG size of input: 123 DAG size of output 115 [2018-04-12 01:08:12,215 WARN L151 SmtUtils]: Spent 892ms on a formula simplification. DAG size of input: 103 DAG size of output 87 [2018-04-12 01:08:13,490 WARN L151 SmtUtils]: Spent 1159ms on a formula simplification. DAG size of input: 119 DAG size of output 111 [2018-04-12 01:08:14,383 WARN L148 SmtUtils]: Spent 536ms on a formula simplification that was a NOOP. DAG size: 83 [2018-04-12 01:08:14,925 WARN L151 SmtUtils]: Spent 181ms on a formula simplification. DAG size of input: 111 DAG size of output 91 [2018-04-12 01:08:15,593 WARN L151 SmtUtils]: Spent 184ms on a formula simplification. DAG size of input: 106 DAG size of output 100 [2018-04-12 01:08:16,389 WARN L151 SmtUtils]: Spent 674ms on a formula simplification. DAG size of input: 89 DAG size of output 77 [2018-04-12 01:08:16,704 WARN L151 SmtUtils]: Spent 199ms on a formula simplification. DAG size of input: 102 DAG size of output 96 [2018-04-12 01:08:17,469 WARN L151 SmtUtils]: Spent 124ms on a formula simplification. DAG size of input: 111 DAG size of output 91 [2018-04-12 01:08:18,562 WARN L151 SmtUtils]: Spent 619ms on a formula simplification. DAG size of input: 89 DAG size of output 85 [2018-04-12 01:08:19,349 WARN L151 SmtUtils]: Spent 669ms on a formula simplification. DAG size of input: 75 DAG size of output 67 [2018-04-12 01:08:20,150 WARN L151 SmtUtils]: Spent 689ms on a formula simplification. DAG size of input: 85 DAG size of output 81 [2018-04-12 01:08:20,988 WARN L151 SmtUtils]: Spent 178ms on a formula simplification. DAG size of input: 111 DAG size of output 91 [2018-04-12 01:08:22,152 WARN L151 SmtUtils]: Spent 699ms on a formula simplification. DAG size of input: 72 DAG size of output 70 [2018-04-12 01:08:22,568 WARN L151 SmtUtils]: Spent 305ms on a formula simplification. DAG size of input: 62 DAG size of output 58 [2018-04-12 01:08:22,779 WARN L151 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 69 DAG size of output 67 [2018-04-12 01:08:23,466 WARN L148 SmtUtils]: Spent 578ms on a formula simplification that was a NOOP. DAG size: 54 [2018-04-12 01:08:24,029 WARN L151 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 111 DAG size of output 91 [2018-04-12 01:08:25,484 WARN L151 SmtUtils]: Spent 181ms on a formula simplification. DAG size of input: 111 DAG size of output 91 [2018-04-12 01:08:26,182 WARN L151 SmtUtils]: Spent 119ms on a formula simplification. DAG size of input: 113 DAG size of output 92 [2018-04-12 01:08:26,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:08:26,381 INFO L93 Difference]: Finished difference Result 1126 states and 1229 transitions. [2018-04-12 01:08:26,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2018-04-12 01:08:26,382 INFO L78 Accepts]: Start accepts. Automaton has 80 states. Word has length 250 [2018-04-12 01:08:26,382 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:08:26,385 INFO L225 Difference]: With dead ends: 1126 [2018-04-12 01:08:26,385 INFO L226 Difference]: Without dead ends: 1125 [2018-04-12 01:08:26,387 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 581 GetRequests, 422 SyntacticMatches, 0 SemanticMatches, 159 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5391 ImplicationChecksByTransitivity, 24.2s TimeCoverageRelationStatistics Valid=4538, Invalid=21222, Unknown=0, NotChecked=0, Total=25760 [2018-04-12 01:08:26,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1125 states. [2018-04-12 01:08:26,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1125 to 542. [2018-04-12 01:08:26,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 542 states. [2018-04-12 01:08:26,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 542 states to 542 states and 592 transitions. [2018-04-12 01:08:26,600 INFO L78 Accepts]: Start accepts. Automaton has 542 states and 592 transitions. Word has length 250 [2018-04-12 01:08:26,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 01:08:26,601 INFO L459 AbstractCegarLoop]: Abstraction has 542 states and 592 transitions. [2018-04-12 01:08:26,601 INFO L460 AbstractCegarLoop]: Interpolant automaton has 80 states. [2018-04-12 01:08:26,601 INFO L276 IsEmpty]: Start isEmpty. Operand 542 states and 592 transitions. [2018-04-12 01:08:26,604 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 441 [2018-04-12 01:08:26,604 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 01:08:26,604 INFO L355 BasicCegarLoop]: trace histogram [32, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 01:08:26,604 INFO L408 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-12 01:08:26,605 INFO L82 PathProgramCache]: Analyzing trace with hash -760278794, now seen corresponding path program 4 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-12 01:08:26,614 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 01:08:26,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 01:08:26,728 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 01:08:26,741 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 01:08:26,741 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 01:08:26,752 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 01:08:26,752 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-12 01:08:30,921 INFO L134 CoverageAnalysis]: Checked inductivity of 3527 backedges. 0 proven. 3495 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-04-12 01:08:30,922 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-12 01:08:39,151 INFO L134 CoverageAnalysis]: Checked inductivity of 3527 backedges. 0 proven. 3495 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-04-12 01:08:39,171 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 01:08:39,172 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 70] total 139 [2018-04-12 01:08:39,172 INFO L442 AbstractCegarLoop]: Interpolant automaton has 140 states [2018-04-12 01:08:39,173 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 140 interpolants. [2018-04-12 01:08:39,174 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1499, Invalid=17961, Unknown=0, NotChecked=0, Total=19460 [2018-04-12 01:08:39,174 INFO L87 Difference]: Start difference. First operand 542 states and 592 transitions. Second operand 140 states. [2018-04-12 01:08:40,994 WARN L151 SmtUtils]: Spent 197ms on a formula simplification. DAG size of input: 162 DAG size of output 132 [2018-04-12 01:08:42,707 WARN L151 SmtUtils]: Spent 1399ms on a formula simplification. DAG size of input: 201 DAG size of output 185 [2018-04-12 01:08:46,223 WARN L151 SmtUtils]: Spent 2106ms on a formula simplification. DAG size of input: 274 DAG size of output 246 [2018-04-12 01:08:47,042 WARN L151 SmtUtils]: Spent 441ms on a formula simplification. DAG size of input: 227 DAG size of output 175 [2018-04-12 01:08:48,175 WARN L151 SmtUtils]: Spent 821ms on a formula simplification. DAG size of input: 270 DAG size of output 244 [2018-04-12 01:08:48,687 WARN L148 SmtUtils]: Spent 238ms on a formula simplification that was a NOOP. DAG size: 195 [2018-04-12 01:08:49,418 WARN L151 SmtUtils]: Spent 431ms on a formula simplification. DAG size of input: 189 DAG size of output 181 [2018-04-12 01:08:52,642 WARN L151 SmtUtils]: Spent 2055ms on a formula simplification. DAG size of input: 257 DAG size of output 225 [2018-04-12 01:08:53,335 WARN L151 SmtUtils]: Spent 380ms on a formula simplification. DAG size of input: 213 DAG size of output 165 [2018-04-12 01:08:54,382 WARN L151 SmtUtils]: Spent 746ms on a formula simplification. DAG size of input: 253 DAG size of output 229 [2018-04-12 01:08:54,861 WARN L148 SmtUtils]: Spent 212ms on a formula simplification that was a NOOP. DAG size: 183 [2018-04-12 01:08:56,183 WARN L151 SmtUtils]: Spent 1013ms on a formula simplification. DAG size of input: 177 DAG size of output 169 [2018-04-12 01:08:58,596 WARN L151 SmtUtils]: Spent 1240ms on a formula simplification. DAG size of input: 240 DAG size of output 210 [2018-04-12 01:08:59,275 WARN L151 SmtUtils]: Spent 356ms on a formula simplification. DAG size of input: 199 DAG size of output 155 [2018-04-12 01:09:01,096 WARN L151 SmtUtils]: Spent 1464ms on a formula simplification. DAG size of input: 236 DAG size of output 214 [2018-04-12 01:09:01,560 WARN L148 SmtUtils]: Spent 192ms on a formula simplification that was a NOOP. DAG size: 171 [2018-04-12 01:09:02,214 WARN L151 SmtUtils]: Spent 352ms on a formula simplification. DAG size of input: 165 DAG size of output 159 [2018-04-12 01:09:05,240 WARN L151 SmtUtils]: Spent 1865ms on a formula simplification. DAG size of input: 223 DAG size of output 197 [2018-04-12 01:09:05,851 WARN L151 SmtUtils]: Spent 310ms on a formula simplification. DAG size of input: 185 DAG size of output 145 [2018-04-12 01:09:06,891 WARN L151 SmtUtils]: Spent 729ms on a formula simplification. DAG size of input: 219 DAG size of output 199 [2018-04-12 01:09:07,330 WARN L148 SmtUtils]: Spent 174ms on a formula simplification that was a NOOP. DAG size: 159 [2018-04-12 01:09:08,603 WARN L151 SmtUtils]: Spent 977ms on a formula simplification. DAG size of input: 153 DAG size of output 149 [2018-04-12 01:09:11,406 WARN L151 SmtUtils]: Spent 1608ms on a formula simplification. DAG size of input: 206 DAG size of output 184 [2018-04-12 01:09:12,036 WARN L151 SmtUtils]: Spent 298ms on a formula simplification. DAG size of input: 172 DAG size of output 136 [2018-04-12 01:09:13,342 WARN L151 SmtUtils]: Spent 960ms on a formula simplification. DAG size of input: 203 DAG size of output 185 [2018-04-12 01:09:13,751 WARN L148 SmtUtils]: Spent 152ms on a formula simplification that was a NOOP. DAG size: 148 [2018-04-12 01:09:15,514 WARN L151 SmtUtils]: Spent 1466ms on a formula simplification. DAG size of input: 142 DAG size of output 138 [2018-04-12 01:09:17,823 WARN L151 SmtUtils]: Spent 1155ms on a formula simplification. DAG size of input: 190 DAG size of output 170 [2018-04-12 01:09:18,440 WARN L151 SmtUtils]: Spent 277ms on a formula simplification. DAG size of input: 158 DAG size of output 126 [2018-04-12 01:09:19,498 WARN L151 SmtUtils]: Spent 727ms on a formula simplification. DAG size of input: 186 DAG size of output 170 [2018-04-12 01:09:19,957 WARN L148 SmtUtils]: Spent 147ms on a formula simplification that was a NOOP. DAG size: 136 [2018-04-12 01:09:21,006 WARN L148 SmtUtils]: Spent 749ms on a formula simplification that was a NOOP. DAG size: 130 [2018-04-12 01:09:23,203 WARN L151 SmtUtils]: Spent 1048ms on a formula simplification. DAG size of input: 173 DAG size of output 155 [2018-04-12 01:09:23,711 WARN L151 SmtUtils]: Spent 220ms on a formula simplification. DAG size of input: 144 DAG size of output 116 [2018-04-12 01:09:24,397 WARN L151 SmtUtils]: Spent 390ms on a formula simplification. DAG size of input: 169 DAG size of output 155 [2018-04-12 01:09:24,777 WARN L148 SmtUtils]: Spent 131ms on a formula simplification that was a NOOP. DAG size: 124 [2018-04-12 01:09:25,176 WARN L148 SmtUtils]: Spent 112ms on a formula simplification that was a NOOP. DAG size: 118 [2018-04-12 01:09:27,425 WARN L151 SmtUtils]: Spent 1086ms on a formula simplification. DAG size of input: 156 DAG size of output 140 [2018-04-12 01:09:27,947 WARN L151 SmtUtils]: Spent 211ms on a formula simplification. DAG size of input: 130 DAG size of output 106 [2018-04-12 01:09:29,234 WARN L151 SmtUtils]: Spent 1001ms on a formula simplification. DAG size of input: 152 DAG size of output 140 [2018-04-12 01:09:29,583 WARN L148 SmtUtils]: Spent 103ms on a formula simplification that was a NOOP. DAG size: 112 [2018-04-12 01:09:30,578 WARN L148 SmtUtils]: Spent 685ms on a formula simplification that was a NOOP. DAG size: 106 [2018-04-12 01:09:32,108 WARN L151 SmtUtils]: Spent 375ms on a formula simplification. DAG size of input: 139 DAG size of output 127 [2018-04-12 01:09:32,547 WARN L151 SmtUtils]: Spent 166ms on a formula simplification. DAG size of input: 117 DAG size of output 97 [2018-04-12 01:09:33,122 WARN L151 SmtUtils]: Spent 292ms on a formula simplification. DAG size of input: 136 DAG size of output 126 [2018-04-12 01:09:34,418 WARN L148 SmtUtils]: Spent 678ms on a formula simplification that was a NOOP. DAG size: 95 [2018-04-12 01:09:36,549 WARN L151 SmtUtils]: Spent 918ms on a formula simplification. DAG size of input: 123 DAG size of output 115 [2018-04-12 01:09:36,990 WARN L151 SmtUtils]: Spent 144ms on a formula simplification. DAG size of input: 103 DAG size of output 87 [2018-04-12 01:09:37,495 WARN L151 SmtUtils]: Spent 232ms on a formula simplification. DAG size of input: 119 DAG size of output 111 [2018-04-12 01:09:38,488 WARN L148 SmtUtils]: Spent 400ms on a formula simplification that was a NOOP. DAG size: 83 [2018-04-12 01:09:40,211 WARN L151 SmtUtils]: Spent 586ms on a formula simplification. DAG size of input: 106 DAG size of output 100 [2018-04-12 01:09:40,588 WARN L151 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 89 DAG size of output 77 [2018-04-12 01:09:41,073 WARN L151 SmtUtils]: Spent 200ms on a formula simplification. DAG size of input: 102 DAG size of output 96 [2018-04-12 01:09:43,323 WARN L151 SmtUtils]: Spent 302ms on a formula simplification. DAG size of input: 89 DAG size of output 85 [2018-04-12 01:09:43,731 WARN L151 SmtUtils]: Spent 120ms on a formula simplification. DAG size of input: 75 DAG size of output 67 [2018-04-12 01:09:44,174 WARN L151 SmtUtils]: Spent 149ms on a formula simplification. DAG size of input: 85 DAG size of output 81 [2018-04-12 01:09:46,558 WARN L151 SmtUtils]: Spent 744ms on a formula simplification. DAG size of input: 72 DAG size of output 70 [2018-04-12 01:09:49,134 WARN L148 SmtUtils]: Spent 315ms on a formula simplification that was a NOOP. DAG size: 56 [2018-04-12 01:09:52,194 WARN L151 SmtUtils]: Spent 276ms on a formula simplification. DAG size of input: 181 DAG size of output 145 [2018-04-12 01:09:53,376 WARN L151 SmtUtils]: Spent 625ms on a formula simplification. DAG size of input: 240 DAG size of output 184 [2018-04-12 01:09:55,039 WARN L151 SmtUtils]: Spent 1075ms on a formula simplification. DAG size of input: 286 DAG size of output 258 [2018-04-12 01:09:55,761 WARN L148 SmtUtils]: Spent 297ms on a formula simplification that was a NOOP. DAG size: 206 [2018-04-12 01:09:56,703 WARN L151 SmtUtils]: Spent 544ms on a formula simplification. DAG size of input: 200 DAG size of output 192 [2018-04-12 01:09:58,130 WARN L151 SmtUtils]: Spent 903ms on a formula simplification. DAG size of input: 273 DAG size of output 247 [2018-04-12 01:09:58,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 01:09:58,302 INFO L93 Difference]: Finished difference Result 1753 states and 1912 transitions. [2018-04-12 01:09:58,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 165 states. [2018-04-12 01:09:58,303 INFO L78 Accepts]: Start accepts. Automaton has 140 states. Word has length 440 [2018-04-12 01:09:58,304 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 01:09:58,310 INFO L225 Difference]: With dead ends: 1753 [2018-04-12 01:09:58,310 INFO L226 Difference]: Without dead ends: 1752 [2018-04-12 01:09:58,315 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1041 GetRequests, 742 SyntacticMatches, 0 SemanticMatches, 299 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20551 ImplicationChecksByTransitivity, 81.0s TimeCoverageRelationStatistics Valid=14433, Invalid=75867, Unknown=0, NotChecked=0, Total=90300 [2018-04-12 01:09:58,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1752 states. Received shutdown request... [2018-04-12 01:09:58,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1752 to 1045. [2018-04-12 01:09:58,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1045 states. [2018-04-12 01:09:58,747 WARN L519 AbstractCegarLoop]: Verification canceled [2018-04-12 01:09:58,753 WARN L197 ceAbstractionStarter]: Timeout [2018-04-12 01:09:58,754 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 12.04 01:09:58 BasicIcfg [2018-04-12 01:09:58,754 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-04-12 01:09:58,755 INFO L168 Benchmark]: Toolchain (without parser) took 235949.06 ms. Allocated memory was 306.7 MB in the beginning and 563.1 MB in the end (delta: 256.4 MB). Free memory was 244.1 MB in the beginning and 302.4 MB in the end (delta: -58.3 MB). Peak memory consumption was 231.4 MB. Max. memory is 5.3 GB. [2018-04-12 01:09:58,755 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 306.7 MB. Free memory is still 268.7 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-12 01:09:58,755 INFO L168 Benchmark]: CACSL2BoogieTranslator took 331.90 ms. Allocated memory is still 306.7 MB. Free memory was 243.1 MB in the beginning and 220.0 MB in the end (delta: 23.2 MB). Peak memory consumption was 23.2 MB. Max. memory is 5.3 GB. [2018-04-12 01:09:58,756 INFO L168 Benchmark]: Boogie Preprocessor took 61.69 ms. Allocated memory is still 306.7 MB. Free memory was 220.0 MB in the beginning and 217.0 MB in the end (delta: 3.0 MB). Peak memory consumption was 3.0 MB. Max. memory is 5.3 GB. [2018-04-12 01:09:58,756 INFO L168 Benchmark]: RCFGBuilder took 538.96 ms. Allocated memory was 306.7 MB in the beginning and 469.2 MB in the end (delta: 162.5 MB). Free memory was 217.0 MB in the beginning and 402.7 MB in the end (delta: -185.7 MB). Peak memory consumption was 21.4 MB. Max. memory is 5.3 GB. [2018-04-12 01:09:58,756 INFO L168 Benchmark]: IcfgTransformer took 33791.25 ms. Allocated memory was 469.2 MB in the beginning and 1.2 GB in the end (delta: 717.2 MB). Free memory was 402.7 MB in the beginning and 593.7 MB in the end (delta: -191.0 MB). Peak memory consumption was 526.2 MB. Max. memory is 5.3 GB. [2018-04-12 01:09:58,757 INFO L168 Benchmark]: TraceAbstraction took 201219.32 ms. Allocated memory was 1.2 GB in the beginning and 563.1 MB in the end (delta: -623.4 MB). Free memory was 593.7 MB in the beginning and 302.4 MB in the end (delta: 291.3 MB). There was no memory consumed. Max. memory is 5.3 GB. [2018-04-12 01:09:58,759 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 306.7 MB. Free memory is still 268.7 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 331.90 ms. Allocated memory is still 306.7 MB. Free memory was 243.1 MB in the beginning and 220.0 MB in the end (delta: 23.2 MB). Peak memory consumption was 23.2 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 61.69 ms. Allocated memory is still 306.7 MB. Free memory was 220.0 MB in the beginning and 217.0 MB in the end (delta: 3.0 MB). Peak memory consumption was 3.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 538.96 ms. Allocated memory was 306.7 MB in the beginning and 469.2 MB in the end (delta: 162.5 MB). Free memory was 217.0 MB in the beginning and 402.7 MB in the end (delta: -185.7 MB). Peak memory consumption was 21.4 MB. Max. memory is 5.3 GB. * IcfgTransformer took 33791.25 ms. Allocated memory was 469.2 MB in the beginning and 1.2 GB in the end (delta: 717.2 MB). Free memory was 402.7 MB in the beginning and 593.7 MB in the end (delta: -191.0 MB). Peak memory consumption was 526.2 MB. Max. memory is 5.3 GB. * TraceAbstraction took 201219.32 ms. Allocated memory was 1.2 GB in the beginning and 563.1 MB in the end (delta: -623.4 MB). Free memory was 593.7 MB in the beginning and 302.4 MB in the end (delta: 291.3 MB). There was no memory consumed. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 78 LocStat_MAX_WEQGRAPH_SIZE : 2 LocStat_MAX_SIZEOF_WEQEDGELABEL : 3 LocStat_NO_SUPPORTING_EQUALITIES : 1610 LocStat_NO_SUPPORTING_DISEQUALITIES : 431 LocStat_NO_DISJUNCTIONS : -156 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 96 TransStat_MAX_WEQGRAPH_SIZE : 4 TransStat_MAX_SIZEOF_WEQEDGELABEL : 1 TransStat_NO_SUPPORTING_EQUALITIES : 111 TransStat_NO_SUPPORTING_DISEQUALITIES : 14 TransStat_NO_DISJUNCTIONS : 99 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 6954.11 RENAME_VARIABLES(MILLISECONDS) : 446.38 UNFREEZE(MILLISECONDS) : 0.00 CONJOIN(MILLISECONDS) : 6965.74 PROJECTAWAY(MILLISECONDS) : 14139.60 ADD_WEAK_EQUALITY(MILLISECONDS) : 6.82 DISJOIN(MILLISECONDS) : 363.94 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 477.88 ADD_EQUALITY(MILLISECONDS) : 11.15 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.00 ADD_DISEQUALITY(MILLISECONDS) : 0.73 #CONJOIN_DISJUNCTIVE : 792 #RENAME_VARIABLES : 1636 #UNFREEZE : 0 #CONJOIN : 952 #PROJECTAWAY : 916 #ADD_WEAK_EQUALITY : 14 #DISJOIN : 400 #RENAME_VARIABLES_DISJUNCTIVE : 1594 #ADD_EQUALITY : 112 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 11 - StatisticsResult: WeqCcManagerStatistics FREEZE(MILLISECONDS) : 17733.25 ADDNODE(MILLISECONDS) : 0.00 MEET(MILLISECONDS) : 6951.48 FILTERREDUNDANT(MILLISECONDS) : 0.00 REPORTWEQ(MILLISECONDS) : 6.65 JOIN(MILLISECONDS) : 341.56 RENAMEVARS(MILLISECONDS) : 431.71 FLATTENLABELS(MILLISECONDS) : 0.00 COPY(MILLISECONDS) : 0.00 ISSTRONGERTHAN(MILLISECONDS) : 10084.25 ISLABELSTRONGERTHAN(MILLISECONDS) : 1936.67 ISWEQGRAPHSTRONGERTHAN(MILLISECONDS) : 88.22 UNFREEZE(MILLISECONDS) : 162.61 REPORTCONTAINS(MILLISECONDS) : 2.52 PROJECTAWAY(MILLISECONDS) : 13965.02 MEETEDGELABELS(MILLISECONDS) : 972.39 REPORTEQUALITY(MILLISECONDS) : 1810.35 ADDALLNODES(MILLISECONDS) : 582.54 REPORTDISEQUALITY(MILLISECONDS) : 8.64 WEQGRAPHJOIN(MILLISECONDS) : 114.51 #FREEZE : 6718 #ADDNODE : 0 #MEET : 709 #FILTERREDUNDANT : 0 #REPORTWEQ : 14 #JOIN : 400 #RENAMEVARS : 1636 #FLATTENLABELS : 0 #COPY : 0 #ISSTRONGERTHAN : 1879 #ISLABELSTRONGERTHAN : 187713 #ISWEQGRAPHSTRONGERTHAN : 851 #UNFREEZE : 4189 #REPORTCONTAINS : 99 #PROJECTAWAY : 1844 #MEETEDGELABELS : 8542 #REPORTEQUALITY : 16918 #ADDALLNODES : 709 #REPORTDISEQUALITY : 3839 #WEQGRAPHJOIN : 400 - StatisticsResult: CcManagerStatistics ADDNODE(MILLISECONDS) : 0.00 MEET(MILLISECONDS) : 10801.90 REPORT_EQUALITY(MILLISECONDS) : 4432.57 FILTERREDUNDANT(MILLISECONDS) : 8443.40 ADD_ALL_ELEMENTS(MILLISECONDS) : 1965.02 JOIN(MILLISECONDS) : 168.53 ALIGN_ELEMENTS(MILLISECONDS) : 2507.49 COPY(MILLISECONDS) : 0.00 REPORT_DISEQUALITY(MILLISECONDS) : 539.88 UNFREEZE(MILLISECONDS) : 0.00 OVERALL(MILLISECONDS) : 15576.85 REPORTCONTAINS(MILLISECONDS) : 22.98 IS_STRONGER_THAN_NO_CACHING(MILLISECONDS) : 4043.10 REMOVE(MILLISECONDS) : 0.00 IS_STRONGER_THAN_W_CACHING(MILLISECONDS) : 0.00 PROJECT_TO_ELEMENTS(MILLISECONDS) : 1836.51 #ADDNODE : 0 #MEET : 27803 #REPORT_EQUALITY : 533106 #FILTERREDUNDANT : 423820 #ADD_ALL_ELEMENTS : 94402 #JOIN : 400 #ALIGN_ELEMENTS : 32346 #COPY : 0 #REPORT_DISEQUALITY : 132418 #UNFREEZE : 0 #OVERALL : 1643453 #REPORTCONTAINS : 1563 #IS_STRONGER_THAN_NO_CACHING : 371764 #REMOVE : 0 #IS_STRONGER_THAN_W_CACHING : 0 #PROJECT_TO_ELEMENTS : 25831 * Results from de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: - StatisticsResult: HeapSeparatorStatistics #COUNT_NEW_ARRAY_VARS_[#memory_int] : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_0 : 1 COUNT_BLOCKS_for_[#memory_int]_at_dim_0 : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_1 : 1 COUNT_BLOCKS_for_[#memory_int]_at_dim_1 : 1 COUNT_ARRAY_READS for [#memory_int] : 4 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 564]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 564). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 82 locations, 9 error locations. TIMEOUT Result, 201.1s OverallTime, 22 OverallIterations, 32 TraceHistogramMax, 157.1s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 2526 SDtfs, 32819 SDslu, 46933 SDs, 0 SdLazy, 26133 SolverSat, 3211 SolverUnsat, 33 SolverUnknown, 0 SolverNotchecked, 19.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 4735 GetRequests, 3568 SyntacticMatches, 28 SemanticMatches, 1139 ConstructedPredicates, 24 IntricatePredicates, 0 DeprecatedPredicates, 34717 ImplicationChecksByTransitivity, 167.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=542occurred in iteration=21, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 1.2s AutomataMinimizationTime, 22 MinimizatonAttempts, 2010 StatesRemovedByMinimization, 18 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 41.2s InterpolantComputationTime, 2104 NumberOfCodeBlocks, 2104 NumberOfCodeBlocksAsserted, 22 NumberOfCheckSat, 4164 ConstructedInterpolants, 1681 QuantifiedInterpolants, 16385623 SizeOfPredicates, 320 NumberOfNonLiveVariables, 5624 ConjunctsInSsa, 616 ConjunctsInUnsatCore, 44 InterpolantComputations, 26 PerfectInterpolantSequences, 336/11658 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-Benchmark-0-2018-04-12_01-09-58-770.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-VPDomainBenchmark-0-2018-04-12_01-09-58-770.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-0-2018-04-12_01-09-58-770.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-1-2018-04-12_01-09-58-770.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-2-2018-04-12_01-09-58-770.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-HeapSeparatorBenchmark-0-2018-04-12_01-09-58-770.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-TraceAbstractionBenchmarks-0-2018-04-12_01-09-58-770.csv Completed graceful shutdown