./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 551b0097 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe --- Real Ultimate output --- This is Ultimate 0.3.0-?-551b009-m [2025-01-10 07:05:45,175 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-01-10 07:05:45,235 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf [2025-01-10 07:05:45,239 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-01-10 07:05:45,239 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-01-10 07:05:45,267 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-01-10 07:05:45,268 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-01-10 07:05:45,268 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-01-10 07:05:45,269 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-01-10 07:05:45,269 INFO L153 SettingsManager]: * Use memory slicer=true [2025-01-10 07:05:45,269 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-01-10 07:05:45,269 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-01-10 07:05:45,269 INFO L153 SettingsManager]: * Use SBE=true [2025-01-10 07:05:45,269 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-01-10 07:05:45,269 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-01-10 07:05:45,271 INFO L153 SettingsManager]: * Use old map elimination=false [2025-01-10 07:05:45,271 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-01-10 07:05:45,271 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-01-10 07:05:45,271 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-01-10 07:05:45,271 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-01-10 07:05:45,271 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-01-10 07:05:45,271 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-01-10 07:05:45,271 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-01-10 07:05:45,271 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-01-10 07:05:45,271 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-01-10 07:05:45,271 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-01-10 07:05:45,272 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-01-10 07:05:45,272 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-01-10 07:05:45,272 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-01-10 07:05:45,272 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-01-10 07:05:45,272 INFO L153 SettingsManager]: * Use constant arrays=true [2025-01-10 07:05:45,272 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2025-01-10 07:05:45,272 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-01-10 07:05:45,272 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-01-10 07:05:45,272 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-01-10 07:05:45,272 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-01-10 07:05:45,272 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe [2025-01-10 07:05:45,574 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-01-10 07:05:45,579 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-01-10 07:05:45,580 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-01-10 07:05:45,581 INFO L270 PluginConnector]: Initializing CDTParser... [2025-01-10 07:05:45,581 INFO L274 PluginConnector]: CDTParser initialized [2025-01-10 07:05:45,582 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i [2025-01-10 07:05:46,943 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/9751388c5/e300d4a83d2c438f81d3afa9a66dbcf9/FLAG74b3b4bb1 [2025-01-10 07:05:47,216 INFO L384 CDTParser]: Found 1 translation units. [2025-01-10 07:05:47,217 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i [2025-01-10 07:05:47,225 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/9751388c5/e300d4a83d2c438f81d3afa9a66dbcf9/FLAG74b3b4bb1 [2025-01-10 07:05:47,239 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/9751388c5/e300d4a83d2c438f81d3afa9a66dbcf9 [2025-01-10 07:05:47,242 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-01-10 07:05:47,243 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-01-10 07:05:47,244 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-01-10 07:05:47,244 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-01-10 07:05:47,247 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-01-10 07:05:47,247 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,249 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4ceaecac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47, skipping insertion in model container [2025-01-10 07:05:47,250 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,278 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-01-10 07:05:47,484 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:05:47,491 INFO L200 MainTranslator]: Completed pre-run [2025-01-10 07:05:47,520 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:05:47,540 INFO L204 MainTranslator]: Completed translation [2025-01-10 07:05:47,541 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47 WrapperNode [2025-01-10 07:05:47,541 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-01-10 07:05:47,542 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-01-10 07:05:47,542 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-01-10 07:05:47,542 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-01-10 07:05:47,556 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,566 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,575 INFO L138 Inliner]: procedures = 109, calls = 13, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 31 [2025-01-10 07:05:47,579 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-01-10 07:05:47,579 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-01-10 07:05:47,579 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-01-10 07:05:47,579 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-01-10 07:05:47,586 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,586 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,589 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,600 INFO L175 MemorySlicer]: Split 7 memory accesses to 2 slices as follows [3, 4]. 57 percent of accesses are in the largest equivalence class. The 0 initializations are split as follows [0, 0]. The 3 writes are split as follows [1, 2]. [2025-01-10 07:05:47,601 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,601 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,604 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,609 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,613 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,618 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,618 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,619 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-01-10 07:05:47,620 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2025-01-10 07:05:47,620 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2025-01-10 07:05:47,620 INFO L274 PluginConnector]: RCFGBuilder initialized [2025-01-10 07:05:47,621 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47" (1/1) ... [2025-01-10 07:05:47,629 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:05:47,648 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:05:47,663 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:05:47,666 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-01-10 07:05:47,688 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-01-10 07:05:47,688 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-01-10 07:05:47,688 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-01-10 07:05:47,688 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-01-10 07:05:47,688 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-01-10 07:05:47,688 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-01-10 07:05:47,688 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-01-10 07:05:47,689 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-01-10 07:05:47,752 INFO L234 CfgBuilder]: Building ICFG [2025-01-10 07:05:47,753 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2025-01-10 07:05:47,807 INFO L? ?]: Removed 4 outVars from TransFormulas that were not future-live. [2025-01-10 07:05:47,807 INFO L283 CfgBuilder]: Performing block encoding [2025-01-10 07:05:47,816 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-01-10 07:05:47,817 INFO L312 CfgBuilder]: Removed 2 assume(true) statements. [2025-01-10 07:05:47,817 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:05:47 BoogieIcfgContainer [2025-01-10 07:05:47,818 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2025-01-10 07:05:47,818 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-01-10 07:05:47,820 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-01-10 07:05:47,824 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-01-10 07:05:47,824 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:05:47,824 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.01 07:05:47" (1/3) ... [2025-01-10 07:05:47,825 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2a51590 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:05:47, skipping insertion in model container [2025-01-10 07:05:47,825 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:05:47,825 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:05:47" (2/3) ... [2025-01-10 07:05:47,825 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2a51590 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:05:47, skipping insertion in model container [2025-01-10 07:05:47,825 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:05:47,825 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:05:47" (3/3) ... [2025-01-10 07:05:47,826 INFO L363 chiAutomizerObserver]: Analyzing ICFG Urban-2013WST-Fig2-modified1000-alloca.i [2025-01-10 07:05:47,872 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-01-10 07:05:47,872 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-01-10 07:05:47,872 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-01-10 07:05:47,872 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-01-10 07:05:47,873 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-01-10 07:05:47,873 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-01-10 07:05:47,873 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-01-10 07:05:47,873 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-01-10 07:05:47,877 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 13 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 12 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:05:47,889 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2025-01-10 07:05:47,890 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:05:47,890 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:05:47,893 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-01-10 07:05:47,893 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-01-10 07:05:47,893 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-01-10 07:05:47,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 13 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 12 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:05:47,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2025-01-10 07:05:47,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:05:47,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:05:47,894 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-01-10 07:05:47,894 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-01-10 07:05:47,899 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-01-10 07:05:47,899 INFO L754 eck$LassoCheckResult]: Loop: "call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;" "call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !true;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-01-10 07:05:47,903 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:05:47,903 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2025-01-10 07:05:47,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:05:47,909 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022422870] [2025-01-10 07:05:47,909 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:05:47,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:05:47,961 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:05:47,970 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:05:47,970 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:05:47,970 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:05:47,971 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:05:47,973 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:05:47,976 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:05:47,976 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:05:47,976 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:05:47,986 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:05:47,988 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:05:47,989 INFO L85 PathProgramCache]: Analyzing trace with hash 34451723, now seen corresponding path program 1 times [2025-01-10 07:05:47,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:05:47,989 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1259113249] [2025-01-10 07:05:47,989 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:05:47,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:05:47,996 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-01-10 07:05:47,998 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-01-10 07:05:47,998 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:05:47,998 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:05:48,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:05:48,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:05:48,023 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1259113249] [2025-01-10 07:05:48,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1259113249] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:05:48,023 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:05:48,023 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:05:48,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396389437] [2025-01-10 07:05:48,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:05:48,026 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:05:48,027 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:05:48,043 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-01-10 07:05:48,043 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-01-10 07:05:48,044 INFO L87 Difference]: Start difference. First operand has 13 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 12 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 2.5) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:05:48,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:05:48,048 INFO L93 Difference]: Finished difference Result 13 states and 14 transitions. [2025-01-10 07:05:48,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 14 transitions. [2025-01-10 07:05:48,049 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2025-01-10 07:05:48,052 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 9 states and 10 transitions. [2025-01-10 07:05:48,053 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2025-01-10 07:05:48,053 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2025-01-10 07:05:48,053 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 10 transitions. [2025-01-10 07:05:48,054 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:05:48,054 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2025-01-10 07:05:48,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 10 transitions. [2025-01-10 07:05:48,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2025-01-10 07:05:48,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 8 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:05:48,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 10 transitions. [2025-01-10 07:05:48,069 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2025-01-10 07:05:48,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-01-10 07:05:48,071 INFO L432 stractBuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2025-01-10 07:05:48,072 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-01-10 07:05:48,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 10 transitions. [2025-01-10 07:05:48,072 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2025-01-10 07:05:48,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:05:48,072 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:05:48,072 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-01-10 07:05:48,072 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-01-10 07:05:48,073 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-01-10 07:05:48,073 INFO L754 eck$LassoCheckResult]: Loop: "call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;" "call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-01-10 07:05:48,073 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:05:48,074 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times [2025-01-10 07:05:48,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:05:48,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022517448] [2025-01-10 07:05:48,074 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:05:48,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:05:48,080 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:05:48,085 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:05:48,085 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:05:48,085 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:05:48,085 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:05:48,087 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:05:48,090 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:05:48,090 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:05:48,090 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:05:48,092 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:05:48,092 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:05:48,092 INFO L85 PathProgramCache]: Analyzing trace with hash 1067994606, now seen corresponding path program 1 times [2025-01-10 07:05:48,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:05:48,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [527029577] [2025-01-10 07:05:48,092 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:05:48,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:05:48,097 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-01-10 07:05:48,102 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-01-10 07:05:48,102 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:05:48,102 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:05:48,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:05:48,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:05:48,178 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [527029577] [2025-01-10 07:05:48,178 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [527029577] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:05:48,178 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:05:48,178 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:05:48,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [968684497] [2025-01-10 07:05:48,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:05:48,178 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:05:48,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:05:48,179 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:05:48,179 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:05:48,179 INFO L87 Difference]: Start difference. First operand 9 states and 10 transitions. cyclomatic complexity: 2 Second operand has 4 states, 4 states have (on average 1.5) internal successors, (6), 4 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:05:48,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:05:48,214 INFO L93 Difference]: Finished difference Result 12 states and 13 transitions. [2025-01-10 07:05:48,214 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12 states and 13 transitions. [2025-01-10 07:05:48,214 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 10 [2025-01-10 07:05:48,215 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12 states to 12 states and 13 transitions. [2025-01-10 07:05:48,215 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2025-01-10 07:05:48,215 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2025-01-10 07:05:48,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 13 transitions. [2025-01-10 07:05:48,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:05:48,215 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12 states and 13 transitions. [2025-01-10 07:05:48,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 13 transitions. [2025-01-10 07:05:48,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 11. [2025-01-10 07:05:48,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 10 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:05:48,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 12 transitions. [2025-01-10 07:05:48,216 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11 states and 12 transitions. [2025-01-10 07:05:48,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:05:48,221 INFO L432 stractBuchiCegarLoop]: Abstraction has 11 states and 12 transitions. [2025-01-10 07:05:48,222 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-01-10 07:05:48,222 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 12 transitions. [2025-01-10 07:05:48,222 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 9 [2025-01-10 07:05:48,222 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:05:48,222 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:05:48,223 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-01-10 07:05:48,223 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:05:48,223 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-01-10 07:05:48,223 INFO L754 eck$LassoCheckResult]: Loop: "call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;" "call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-01-10 07:05:48,223 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:05:48,223 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 3 times [2025-01-10 07:05:48,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:05:48,223 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2108832836] [2025-01-10 07:05:48,223 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:05:48,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:05:48,236 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:05:48,242 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:05:48,242 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:05:48,242 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:05:48,242 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:05:48,243 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:05:48,250 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:05:48,254 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:05:48,254 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:05:48,256 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:05:48,257 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:05:48,259 INFO L85 PathProgramCache]: Analyzing trace with hash -492370581, now seen corresponding path program 1 times [2025-01-10 07:05:48,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:05:48,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119990509] [2025-01-10 07:05:48,259 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:05:48,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:05:48,267 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-01-10 07:05:48,273 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-01-10 07:05:48,276 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:05:48,276 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:05:48,442 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:05:48,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:05:48,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2119990509] [2025-01-10 07:05:48,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2119990509] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:05:48,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [623018920] [2025-01-10 07:05:48,443 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:05:48,443 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:05:48,443 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:05:48,448 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:05:48,450 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2025-01-10 07:05:48,483 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-01-10 07:05:48,491 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-01-10 07:05:48,491 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:05:48,491 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:05:48,492 INFO L256 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 7 conjuncts are in the unsatisfiable core [2025-01-10 07:05:48,494 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:05:48,518 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-01-10 07:05:48,540 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2025-01-10 07:05:48,546 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2025-01-10 07:05:48,551 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:05:48,551 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:05:48,590 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:05:48,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [623018920] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:05:48,591 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:05:48,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5, 5] total 10 [2025-01-10 07:05:48,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [962092435] [2025-01-10 07:05:48,591 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:05:48,591 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:05:48,591 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:05:48,592 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-01-10 07:05:48,592 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=55, Unknown=0, NotChecked=0, Total=90 [2025-01-10 07:05:48,592 INFO L87 Difference]: Start difference. First operand 11 states and 12 transitions. cyclomatic complexity: 2 Second operand has 10 states, 10 states have (on average 1.8) internal successors, (18), 10 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:05:48,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:05:48,645 INFO L93 Difference]: Finished difference Result 21 states and 22 transitions. [2025-01-10 07:05:48,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21 states and 22 transitions. [2025-01-10 07:05:48,646 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 19 [2025-01-10 07:05:48,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21 states to 21 states and 22 transitions. [2025-01-10 07:05:48,646 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2025-01-10 07:05:48,646 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2025-01-10 07:05:48,646 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 22 transitions. [2025-01-10 07:05:48,647 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:05:48,647 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21 states and 22 transitions. [2025-01-10 07:05:48,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 22 transitions. [2025-01-10 07:05:48,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 20. [2025-01-10 07:05:48,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.05) internal successors, (21), 19 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:05:48,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 21 transitions. [2025-01-10 07:05:48,655 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20 states and 21 transitions. [2025-01-10 07:05:48,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-01-10 07:05:48,657 INFO L432 stractBuchiCegarLoop]: Abstraction has 20 states and 21 transitions. [2025-01-10 07:05:48,657 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-01-10 07:05:48,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 21 transitions. [2025-01-10 07:05:48,657 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 18 [2025-01-10 07:05:48,658 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:05:48,659 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:05:48,659 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-01-10 07:05:48,660 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [5, 4, 4, 1, 1, 1, 1, 1] [2025-01-10 07:05:48,660 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-01-10 07:05:48,660 INFO L754 eck$LassoCheckResult]: Loop: "call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;" "call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-01-10 07:05:48,660 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:05:48,661 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 4 times [2025-01-10 07:05:48,661 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:05:48,661 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308225816] [2025-01-10 07:05:48,662 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:05:48,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:05:48,668 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-01-10 07:05:48,674 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:05:48,674 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:05:48,674 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:05:48,674 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:05:48,675 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:05:48,677 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:05:48,677 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:05:48,677 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:05:48,678 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:05:48,679 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:05:48,679 INFO L85 PathProgramCache]: Analyzing trace with hash -1039037522, now seen corresponding path program 2 times [2025-01-10 07:05:48,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:05:48,679 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703082434] [2025-01-10 07:05:48,679 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:05:48,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:05:48,685 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 18 statements into 2 equivalence classes. [2025-01-10 07:05:48,692 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 18 of 18 statements. [2025-01-10 07:05:48,692 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-01-10 07:05:48,692 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:05:49,053 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:05:49,054 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:05:49,054 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1703082434] [2025-01-10 07:05:49,054 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1703082434] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:05:49,054 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1068667967] [2025-01-10 07:05:49,054 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:05:49,054 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:05:49,054 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:05:49,056 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:05:49,058 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2025-01-10 07:05:49,090 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 18 statements into 2 equivalence classes. [2025-01-10 07:05:49,102 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 18 of 18 statements. [2025-01-10 07:05:49,102 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-01-10 07:05:49,102 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:05:49,103 INFO L256 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 16 conjuncts are in the unsatisfiable core [2025-01-10 07:05:49,105 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:05:49,108 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-01-10 07:05:49,120 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2025-01-10 07:05:49,128 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:49,138 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:49,148 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:49,153 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2025-01-10 07:05:49,155 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:05:49,155 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:05:49,242 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:05:49,243 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1068667967] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:05:49,243 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:05:49,243 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8] total 18 [2025-01-10 07:05:49,243 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [759984800] [2025-01-10 07:05:49,243 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:05:49,243 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:05:49,244 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:05:49,244 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2025-01-10 07:05:49,244 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=125, Invalid=181, Unknown=0, NotChecked=0, Total=306 [2025-01-10 07:05:49,244 INFO L87 Difference]: Start difference. First operand 20 states and 21 transitions. cyclomatic complexity: 2 Second operand has 18 states, 18 states have (on average 2.2222222222222223) internal successors, (40), 18 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:05:49,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:05:49,366 INFO L93 Difference]: Finished difference Result 39 states and 40 transitions. [2025-01-10 07:05:49,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39 states and 40 transitions. [2025-01-10 07:05:49,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 37 [2025-01-10 07:05:49,368 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39 states to 39 states and 40 transitions. [2025-01-10 07:05:49,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2025-01-10 07:05:49,368 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2025-01-10 07:05:49,368 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 40 transitions. [2025-01-10 07:05:49,368 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:05:49,368 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 40 transitions. [2025-01-10 07:05:49,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 40 transitions. [2025-01-10 07:05:49,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 38. [2025-01-10 07:05:49,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.0263157894736843) internal successors, (39), 37 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:05:49,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 39 transitions. [2025-01-10 07:05:49,370 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38 states and 39 transitions. [2025-01-10 07:05:49,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2025-01-10 07:05:49,371 INFO L432 stractBuchiCegarLoop]: Abstraction has 38 states and 39 transitions. [2025-01-10 07:05:49,371 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-01-10 07:05:49,371 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 39 transitions. [2025-01-10 07:05:49,371 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 36 [2025-01-10 07:05:49,371 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:05:49,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:05:49,372 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-01-10 07:05:49,372 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [11, 10, 10, 1, 1, 1, 1, 1] [2025-01-10 07:05:49,372 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-01-10 07:05:49,372 INFO L754 eck$LassoCheckResult]: Loop: "call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;" "call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-01-10 07:05:49,372 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:05:49,372 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 5 times [2025-01-10 07:05:49,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:05:49,373 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116660314] [2025-01-10 07:05:49,373 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:05:49,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:05:49,376 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:05:49,378 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:05:49,378 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:05:49,378 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:05:49,378 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:05:49,379 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:05:49,380 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:05:49,380 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:05:49,380 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:05:49,381 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:05:49,381 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:05:49,382 INFO L85 PathProgramCache]: Analyzing trace with hash -1778189234, now seen corresponding path program 3 times [2025-01-10 07:05:49,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:05:49,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1844697724] [2025-01-10 07:05:49,382 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:05:49,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:05:49,390 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 36 statements into 11 equivalence classes. [2025-01-10 07:05:49,427 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) and asserted 36 of 36 statements. [2025-01-10 07:05:49,427 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2025-01-10 07:05:49,427 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:05:50,092 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:05:50,093 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:05:50,093 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1844697724] [2025-01-10 07:05:50,093 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1844697724] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:05:50,093 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1356748648] [2025-01-10 07:05:50,093 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:05:50,093 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:05:50,093 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:05:50,097 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:05:50,098 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2025-01-10 07:05:50,142 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 36 statements into 11 equivalence classes. [2025-01-10 07:05:50,186 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) and asserted 36 of 36 statements. [2025-01-10 07:05:50,186 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2025-01-10 07:05:50,186 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:05:50,187 INFO L256 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 34 conjuncts are in the unsatisfiable core [2025-01-10 07:05:50,191 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:05:50,194 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-01-10 07:05:50,206 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2025-01-10 07:05:50,215 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:50,225 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:50,235 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:50,245 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:50,263 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:50,285 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:50,303 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:50,324 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:50,341 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:50,354 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2025-01-10 07:05:50,358 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:05:50,360 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:05:50,712 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:05:50,712 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1356748648] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:05:50,713 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:05:50,713 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14, 14] total 27 [2025-01-10 07:05:50,713 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125620747] [2025-01-10 07:05:50,713 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:05:50,713 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:05:50,713 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:05:50,714 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2025-01-10 07:05:50,716 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=304, Invalid=398, Unknown=0, NotChecked=0, Total=702 [2025-01-10 07:05:50,716 INFO L87 Difference]: Start difference. First operand 38 states and 39 transitions. cyclomatic complexity: 2 Second operand has 27 states, 27 states have (on average 2.6296296296296298) internal successors, (71), 27 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:05:51,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:05:51,071 INFO L93 Difference]: Finished difference Result 75 states and 76 transitions. [2025-01-10 07:05:51,071 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 76 transitions. [2025-01-10 07:05:51,072 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 73 [2025-01-10 07:05:51,073 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 75 states and 76 transitions. [2025-01-10 07:05:51,073 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75 [2025-01-10 07:05:51,073 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75 [2025-01-10 07:05:51,073 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 76 transitions. [2025-01-10 07:05:51,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:05:51,074 INFO L218 hiAutomatonCegarLoop]: Abstraction has 75 states and 76 transitions. [2025-01-10 07:05:51,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 76 transitions. [2025-01-10 07:05:51,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 74. [2025-01-10 07:05:51,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.0135135135135136) internal successors, (75), 73 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:05:51,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 75 transitions. [2025-01-10 07:05:51,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74 states and 75 transitions. [2025-01-10 07:05:51,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2025-01-10 07:05:51,078 INFO L432 stractBuchiCegarLoop]: Abstraction has 74 states and 75 transitions. [2025-01-10 07:05:51,078 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-01-10 07:05:51,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 75 transitions. [2025-01-10 07:05:51,078 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2025-01-10 07:05:51,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:05:51,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:05:51,079 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-01-10 07:05:51,079 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [23, 22, 22, 1, 1, 1, 1, 1] [2025-01-10 07:05:51,079 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-01-10 07:05:51,079 INFO L754 eck$LassoCheckResult]: Loop: "call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;" "call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-01-10 07:05:51,080 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:05:51,080 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 6 times [2025-01-10 07:05:51,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:05:51,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877883033] [2025-01-10 07:05:51,080 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:05:51,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:05:51,084 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:05:51,087 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:05:51,087 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-01-10 07:05:51,087 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:05:51,087 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:05:51,088 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:05:51,089 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:05:51,089 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:05:51,089 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:05:51,090 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:05:51,090 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:05:51,090 INFO L85 PathProgramCache]: Analyzing trace with hash -372038258, now seen corresponding path program 4 times [2025-01-10 07:05:51,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:05:51,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665961856] [2025-01-10 07:05:51,091 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:05:51,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:05:51,105 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 72 statements into 2 equivalence classes. [2025-01-10 07:05:51,129 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 72 of 72 statements. [2025-01-10 07:05:51,129 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:05:51,129 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:05:53,576 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:05:53,577 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:05:53,577 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [665961856] [2025-01-10 07:05:53,577 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [665961856] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:05:53,577 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1384078326] [2025-01-10 07:05:53,577 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:05:53,577 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:05:53,577 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:05:53,579 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:05:53,581 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2025-01-10 07:05:53,634 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 72 statements into 2 equivalence classes. [2025-01-10 07:05:53,822 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 72 of 72 statements. [2025-01-10 07:05:53,822 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:05:53,822 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:05:53,826 INFO L256 TraceCheckSpWp]: Trace formula consists of 362 conjuncts, 70 conjuncts are in the unsatisfiable core [2025-01-10 07:05:53,832 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:05:53,834 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-01-10 07:05:53,843 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2025-01-10 07:05:53,849 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,857 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,864 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,871 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,878 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,885 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,893 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,899 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,906 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,914 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,921 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,928 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,935 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,942 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,949 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,957 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,964 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,971 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,978 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,985 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,993 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:05:53,997 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2025-01-10 07:05:53,999 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:05:53,999 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:05:54,760 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:05:54,760 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1384078326] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:05:54,760 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:05:54,760 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 26, 26] total 71 [2025-01-10 07:05:54,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256178169] [2025-01-10 07:05:54,760 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:05:54,760 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:05:54,760 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:05:54,762 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2025-01-10 07:05:54,763 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=2151, Invalid=2819, Unknown=0, NotChecked=0, Total=4970 [2025-01-10 07:05:54,763 INFO L87 Difference]: Start difference. First operand 74 states and 75 transitions. cyclomatic complexity: 2 Second operand has 71 states, 71 states have (on average 2.563380281690141) internal successors, (182), 71 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:05:55,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:05:55,647 INFO L93 Difference]: Finished difference Result 147 states and 148 transitions. [2025-01-10 07:05:55,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 147 states and 148 transitions. [2025-01-10 07:05:55,648 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2025-01-10 07:05:55,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 147 states to 147 states and 148 transitions. [2025-01-10 07:05:55,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147 [2025-01-10 07:05:55,649 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147 [2025-01-10 07:05:55,649 INFO L73 IsDeterministic]: Start isDeterministic. Operand 147 states and 148 transitions. [2025-01-10 07:05:55,650 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:05:55,650 INFO L218 hiAutomatonCegarLoop]: Abstraction has 147 states and 148 transitions. [2025-01-10 07:05:55,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states and 148 transitions. [2025-01-10 07:05:55,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 146. [2025-01-10 07:05:55,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146 states, 146 states have (on average 1.0068493150684932) internal successors, (147), 145 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:05:55,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 147 transitions. [2025-01-10 07:05:55,654 INFO L240 hiAutomatonCegarLoop]: Abstraction has 146 states and 147 transitions. [2025-01-10 07:05:55,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2025-01-10 07:05:55,655 INFO L432 stractBuchiCegarLoop]: Abstraction has 146 states and 147 transitions. [2025-01-10 07:05:55,655 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-01-10 07:05:55,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146 states and 147 transitions. [2025-01-10 07:05:55,656 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 144 [2025-01-10 07:05:55,656 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:05:55,656 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:05:55,657 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-01-10 07:05:55,657 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [47, 46, 46, 1, 1, 1, 1, 1] [2025-01-10 07:05:55,657 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-01-10 07:05:55,657 INFO L754 eck$LassoCheckResult]: Loop: "call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;" "call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-01-10 07:05:55,657 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:05:55,658 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 7 times [2025-01-10 07:05:55,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:05:55,658 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658291135] [2025-01-10 07:05:55,658 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:05:55,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:05:55,661 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:05:55,662 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:05:55,662 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:05:55,662 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:05:55,662 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:05:55,663 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:05:55,663 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:05:55,663 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:05:55,663 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:05:55,664 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:05:55,665 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:05:55,665 INFO L85 PathProgramCache]: Analyzing trace with hash 255891470, now seen corresponding path program 5 times [2025-01-10 07:05:55,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:05:55,665 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1868273013] [2025-01-10 07:05:55,665 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:05:55,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:05:55,680 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 144 statements into 47 equivalence classes. [2025-01-10 07:05:55,743 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) and asserted 144 of 144 statements. [2025-01-10 07:05:55,743 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2025-01-10 07:05:55,743 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:06:00,834 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:06:00,834 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:06:00,834 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1868273013] [2025-01-10 07:06:00,834 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1868273013] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:06:00,834 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [446325108] [2025-01-10 07:06:00,834 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:06:00,834 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:06:00,834 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:06:00,841 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:06:00,847 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2025-01-10 07:06:00,932 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 144 statements into 47 equivalence classes. [2025-01-10 07:06:26,067 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) and asserted 144 of 144 statements. [2025-01-10 07:06:26,067 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2025-01-10 07:06:26,067 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:06:26,087 INFO L256 TraceCheckSpWp]: Trace formula consists of 722 conjuncts, 142 conjuncts are in the unsatisfiable core [2025-01-10 07:06:26,116 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:06:26,125 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-01-10 07:06:26,139 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2025-01-10 07:06:26,145 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,156 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,169 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,175 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,186 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,197 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,206 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,214 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,221 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,228 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,237 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,245 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,255 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,262 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,272 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,279 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,286 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,298 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,306 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,315 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,326 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,334 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,347 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,356 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,371 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,380 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,389 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,400 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,412 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,422 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,432 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,441 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,452 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,461 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,470 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,478 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,484 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,493 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,503 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,521 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,528 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,539 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,556 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,572 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,585 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2025-01-10 07:06:26,590 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2025-01-10 07:06:26,594 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:06:26,594 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:06:29,160 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:06:29,161 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [446325108] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:06:29,161 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:06:29,161 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 50, 50] total 99 [2025-01-10 07:06:29,161 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2056396449] [2025-01-10 07:06:29,161 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:06:29,161 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:06:29,161 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:06:29,163 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 99 interpolants. [2025-01-10 07:06:29,166 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=4648, Invalid=5054, Unknown=0, NotChecked=0, Total=9702 [2025-01-10 07:06:29,166 INFO L87 Difference]: Start difference. First operand 146 states and 147 transitions. cyclomatic complexity: 2 Second operand has 99 states, 99 states have (on average 2.898989898989899) internal successors, (287), 99 states have internal predecessors, (287), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:06:31,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:06:31,991 INFO L93 Difference]: Finished difference Result 291 states and 292 transitions. [2025-01-10 07:06:31,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 291 states and 292 transitions. [2025-01-10 07:06:31,995 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 289 [2025-01-10 07:06:32,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 291 states to 291 states and 292 transitions. [2025-01-10 07:06:32,002 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 291 [2025-01-10 07:06:32,002 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291 [2025-01-10 07:06:32,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 291 states and 292 transitions. [2025-01-10 07:06:32,003 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:06:32,003 INFO L218 hiAutomatonCegarLoop]: Abstraction has 291 states and 292 transitions. [2025-01-10 07:06:32,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states and 292 transitions. [2025-01-10 07:06:32,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 290. [2025-01-10 07:06:32,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 290 states, 290 states have (on average 1.0034482758620689) internal successors, (291), 289 states have internal predecessors, (291), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:06:32,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 290 states to 290 states and 291 transitions. [2025-01-10 07:06:32,028 INFO L240 hiAutomatonCegarLoop]: Abstraction has 290 states and 291 transitions. [2025-01-10 07:06:32,032 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 190 states. [2025-01-10 07:06:32,032 INFO L432 stractBuchiCegarLoop]: Abstraction has 290 states and 291 transitions. [2025-01-10 07:06:32,033 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-01-10 07:06:32,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 290 states and 291 transitions. [2025-01-10 07:06:32,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 288 [2025-01-10 07:06:32,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:06:32,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:06:32,037 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-01-10 07:06:32,037 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [95, 94, 94, 1, 1, 1, 1, 1] [2025-01-10 07:06:32,038 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-01-10 07:06:32,038 INFO L754 eck$LassoCheckResult]: Loop: "call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;" "call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-01-10 07:06:32,039 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:06:32,040 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 8 times [2025-01-10 07:06:32,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:06:32,040 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [860508486] [2025-01-10 07:06:32,040 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:06:32,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:06:32,044 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:06:32,045 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:06:32,045 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:06:32,046 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:06:32,046 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:06:32,047 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:06:32,047 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:06:32,047 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:06:32,047 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:06:32,049 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:06:32,049 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:06:32,049 INFO L85 PathProgramCache]: Analyzing trace with hash 1846541582, now seen corresponding path program 6 times [2025-01-10 07:06:32,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:06:32,050 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2066479274] [2025-01-10 07:06:32,050 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:06:32,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:06:32,124 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 288 statements into 95 equivalence classes. [2025-01-10 07:06:32,323 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) and asserted 288 of 288 statements. [2025-01-10 07:06:32,323 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2025-01-10 07:06:32,323 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:06:47,639 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 0 proven. 13301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:06:47,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:06:47,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2066479274] [2025-01-10 07:06:47,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2066479274] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:06:47,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [570771828] [2025-01-10 07:06:47,640 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:06:47,640 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:06:47,640 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:06:47,644 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:06:47,662 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2025-01-10 07:06:47,795 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 288 statements into 95 equivalence classes.