./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/kundu2.cil.c --full-output --architecture 32bit


--------------------------------------------------------------------------------


Checking for termination
Using default analysis
Version 551b0097
Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/kundu2.cil.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) )

 --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf
--- Real Ultimate output ---
This is Ultimate 0.3.0-?-551b009-m
[2025-01-10 07:51:13,346 INFO  L188        SettingsManager]: Resetting all preferences to default values...
[2025-01-10 07:51:13,393 INFO  L114        SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf
[2025-01-10 07:51:13,397 WARN  L101        SettingsManager]: Preference file contains the following unknown settings:
[2025-01-10 07:51:13,397 WARN  L103        SettingsManager]:   * de.uni_freiburg.informatik.ultimate.core.Log level for class
[2025-01-10 07:51:13,424 INFO  L130        SettingsManager]: Preferences different from defaults after loading the file:
[2025-01-10 07:51:13,424 INFO  L151        SettingsManager]: Preferences of UltimateCore differ from their defaults:
[2025-01-10 07:51:13,424 INFO  L153        SettingsManager]:  * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR;
[2025-01-10 07:51:13,425 INFO  L151        SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults:
[2025-01-10 07:51:13,425 INFO  L153        SettingsManager]:  * Use memory slicer=true
[2025-01-10 07:51:13,425 INFO  L151        SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults:
[2025-01-10 07:51:13,425 INFO  L153        SettingsManager]:  * Create parallel compositions if possible=false
[2025-01-10 07:51:13,425 INFO  L153        SettingsManager]:  * Use SBE=true
[2025-01-10 07:51:13,426 INFO  L151        SettingsManager]: Preferences of BuchiAutomizer differ from their defaults:
[2025-01-10 07:51:13,426 INFO  L153        SettingsManager]:  * NCSB implementation=INTSET_LAZY3
[2025-01-10 07:51:13,426 INFO  L153        SettingsManager]:  * Use old map elimination=false
[2025-01-10 07:51:13,426 INFO  L153        SettingsManager]:  * Use external solver (rank synthesis)=false
[2025-01-10 07:51:13,426 INFO  L153        SettingsManager]:  * Use only trivial implications for array writes=true
[2025-01-10 07:51:13,426 INFO  L153        SettingsManager]:  * Rank analysis=LINEAR_WITH_GUESSES
[2025-01-10 07:51:13,426 INFO  L151        SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults:
[2025-01-10 07:51:13,427 INFO  L153        SettingsManager]:  * Pointer base address is valid at dereference=ASSUME
[2025-01-10 07:51:13,427 INFO  L153        SettingsManager]:  * sizeof long=4
[2025-01-10 07:51:13,427 INFO  L153        SettingsManager]:  * Overapproximate operations on floating types=true
[2025-01-10 07:51:13,427 INFO  L153        SettingsManager]:  * sizeof POINTER=4
[2025-01-10 07:51:13,427 INFO  L153        SettingsManager]:  * Check division by zero=IGNORE
[2025-01-10 07:51:13,427 INFO  L153        SettingsManager]:  * Pointer to allocated memory at dereference=ASSUME
[2025-01-10 07:51:13,427 INFO  L153        SettingsManager]:  * If two pointers are subtracted or compared they have the same base address=ASSUME
[2025-01-10 07:51:13,427 INFO  L153        SettingsManager]:  * Check array bounds for arrays that are off heap=ASSUME
[2025-01-10 07:51:13,427 INFO  L153        SettingsManager]:  * Check unreachability of reach_error function=false
[2025-01-10 07:51:13,428 INFO  L153        SettingsManager]:  * sizeof long double=12
[2025-01-10 07:51:13,428 INFO  L153        SettingsManager]:  * Check if freed pointer was valid=false
[2025-01-10 07:51:13,428 INFO  L153        SettingsManager]:  * Assume nondeterminstic values are in range=false
[2025-01-10 07:51:13,428 INFO  L153        SettingsManager]:  * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR
[2025-01-10 07:51:13,428 INFO  L153        SettingsManager]:  * Use constant arrays=true
[2025-01-10 07:51:13,428 INFO  L151        SettingsManager]: Preferences of RCFGBuilder differ from their defaults:
[2025-01-10 07:51:13,428 INFO  L153        SettingsManager]:  * Size of a code block=SequenceOfStatements
[2025-01-10 07:51:13,429 INFO  L151        SettingsManager]: Preferences of TraceAbstraction differ from their defaults:
[2025-01-10 07:51:13,429 INFO  L153        SettingsManager]:  * Trace refinement strategy=CAMEL
[2025-01-10 07:51:13,429 INFO  L151        SettingsManager]: Preferences of IcfgTransformer differ from their defaults:
[2025-01-10 07:51:13,429 INFO  L153        SettingsManager]:  * TransformationType=MODULO_NEIGHBOR
Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) )


Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf
[2025-01-10 07:51:13,687 INFO  L75    nceAwareModelManager]: Repository-Root is: /tmp
[2025-01-10 07:51:13,698 INFO  L261   ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized
[2025-01-10 07:51:13,701 INFO  L217   ainManager$Toolchain]: [Toolchain 1]: Toolchain selected.
[2025-01-10 07:51:13,702 INFO  L270        PluginConnector]: Initializing CDTParser...
[2025-01-10 07:51:13,703 INFO  L274        PluginConnector]: CDTParser initialized
[2025-01-10 07:51:13,704 INFO  L431   ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/kundu2.cil.c
[2025-01-10 07:51:14,961 INFO  L533              CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/df1759c12/c5d9c34053a5467e91d81ffbcc49aa2a/FLAG97f4c23e9
[2025-01-10 07:51:15,245 INFO  L384              CDTParser]: Found 1 translation units.
[2025-01-10 07:51:15,246 INFO  L180              CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/kundu2.cil.c
[2025-01-10 07:51:15,253 INFO  L427              CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/df1759c12/c5d9c34053a5467e91d81ffbcc49aa2a/FLAG97f4c23e9
[2025-01-10 07:51:15,265 INFO  L435              CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/df1759c12/c5d9c34053a5467e91d81ffbcc49aa2a
[2025-01-10 07:51:15,269 INFO  L299   ainManager$Toolchain]: ####################### [Toolchain 1] #######################
[2025-01-10 07:51:15,276 INFO  L133        ToolchainWalker]: Walking toolchain with 6 elements.
[2025-01-10 07:51:15,277 INFO  L112        PluginConnector]: ------------------------CACSL2BoogieTranslator----------------------------
[2025-01-10 07:51:15,278 INFO  L270        PluginConnector]: Initializing CACSL2BoogieTranslator...
[2025-01-10 07:51:15,287 INFO  L274        PluginConnector]: CACSL2BoogieTranslator initialized
[2025-01-10 07:51:15,291 INFO  L184        PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,294 INFO  L204        PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@73653f7a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15, skipping insertion in model container
[2025-01-10 07:51:15,294 INFO  L184        PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,353 INFO  L175         MainTranslator]: Built tables and reachable declarations
[2025-01-10 07:51:15,626 INFO  L210          PostProcessor]: Analyzing one entry point: main
[2025-01-10 07:51:15,643 INFO  L200         MainTranslator]: Completed pre-run
[2025-01-10 07:51:15,679 INFO  L210          PostProcessor]: Analyzing one entry point: main
[2025-01-10 07:51:15,693 INFO  L204         MainTranslator]: Completed translation
[2025-01-10 07:51:15,694 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15 WrapperNode
[2025-01-10 07:51:15,695 INFO  L131        PluginConnector]: ------------------------ END CACSL2BoogieTranslator----------------------------
[2025-01-10 07:51:15,695 INFO  L112        PluginConnector]: ------------------------Boogie Procedure Inliner----------------------------
[2025-01-10 07:51:15,695 INFO  L270        PluginConnector]: Initializing Boogie Procedure Inliner...
[2025-01-10 07:51:15,695 INFO  L274        PluginConnector]: Boogie Procedure Inliner initialized
[2025-01-10 07:51:15,699 INFO  L184        PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,704 INFO  L184        PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,721 INFO  L138                Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 49, statements flattened = 520
[2025-01-10 07:51:15,721 INFO  L131        PluginConnector]: ------------------------ END Boogie Procedure Inliner----------------------------
[2025-01-10 07:51:15,721 INFO  L112        PluginConnector]: ------------------------Boogie Preprocessor----------------------------
[2025-01-10 07:51:15,722 INFO  L270        PluginConnector]: Initializing Boogie Preprocessor...
[2025-01-10 07:51:15,722 INFO  L274        PluginConnector]: Boogie Preprocessor initialized
[2025-01-10 07:51:15,727 INFO  L184        PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,728 INFO  L184        PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,729 INFO  L184        PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,737 INFO  L175           MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0].
[2025-01-10 07:51:15,737 INFO  L184        PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,737 INFO  L184        PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,741 INFO  L184        PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,742 INFO  L184        PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,745 INFO  L184        PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,746 INFO  L184        PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,747 INFO  L184        PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,748 INFO  L131        PluginConnector]: ------------------------ END Boogie Preprocessor----------------------------
[2025-01-10 07:51:15,749 INFO  L112        PluginConnector]: ------------------------RCFGBuilder----------------------------
[2025-01-10 07:51:15,749 INFO  L270        PluginConnector]: Initializing RCFGBuilder...
[2025-01-10 07:51:15,749 INFO  L274        PluginConnector]: RCFGBuilder initialized
[2025-01-10 07:51:15,750 INFO  L184        PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15" (1/1) ...
[2025-01-10 07:51:15,753 INFO  L173          SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000
[2025-01-10 07:51:15,762 INFO  L189       MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3
[2025-01-10 07:51:15,777 INFO  L229       MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null)
[2025-01-10 07:51:15,780 INFO  L327       MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process
[2025-01-10 07:51:15,799 INFO  L130     BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit
[2025-01-10 07:51:15,800 INFO  L130     BoogieDeclarations]: Found specification of procedure write~init~int#0
[2025-01-10 07:51:15,800 INFO  L130     BoogieDeclarations]: Found specification of procedure ULTIMATE.start
[2025-01-10 07:51:15,800 INFO  L138     BoogieDeclarations]: Found implementation of procedure ULTIMATE.start
[2025-01-10 07:51:15,862 INFO  L234             CfgBuilder]: Building ICFG
[2025-01-10 07:51:15,863 INFO  L260             CfgBuilder]: Building CFG for each procedure with an implementation
[2025-01-10 07:51:16,252 INFO  L?                        ?]: Removed 101 outVars from TransFormulas that were not future-live.
[2025-01-10 07:51:16,252 INFO  L283             CfgBuilder]: Performing block encoding
[2025-01-10 07:51:16,267 INFO  L307             CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start)
[2025-01-10 07:51:16,267 INFO  L312             CfgBuilder]: Removed 2 assume(true) statements.
[2025-01-10 07:51:16,268 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:51:16 BoogieIcfgContainer
[2025-01-10 07:51:16,268 INFO  L131        PluginConnector]: ------------------------ END RCFGBuilder----------------------------
[2025-01-10 07:51:16,271 INFO  L112        PluginConnector]: ------------------------BuchiAutomizer----------------------------
[2025-01-10 07:51:16,271 INFO  L270        PluginConnector]: Initializing BuchiAutomizer...
[2025-01-10 07:51:16,275 INFO  L274        PluginConnector]: BuchiAutomizer initialized
[2025-01-10 07:51:16,275 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-01-10 07:51:16,275 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.01 07:51:15" (1/3) ...
[2025-01-10 07:51:16,276 INFO  L204        PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@21bc3fc3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:51:16, skipping insertion in model container
[2025-01-10 07:51:16,277 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-01-10 07:51:16,277 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:15" (2/3) ...
[2025-01-10 07:51:16,278 INFO  L204        PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@21bc3fc3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:51:16, skipping insertion in model container
[2025-01-10 07:51:16,278 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-01-10 07:51:16,278 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:51:16" (3/3) ...
[2025-01-10 07:51:16,279 INFO  L363   chiAutomizerObserver]: Analyzing ICFG kundu2.cil.c
[2025-01-10 07:51:16,321 INFO  L306   stractBuchiCegarLoop]: Interprodecural is true
[2025-01-10 07:51:16,321 INFO  L307   stractBuchiCegarLoop]: Hoare is None
[2025-01-10 07:51:16,321 INFO  L308   stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates
[2025-01-10 07:51:16,321 INFO  L309   stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE
[2025-01-10 07:51:16,321 INFO  L310   stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION
[2025-01-10 07:51:16,322 INFO  L311   stractBuchiCegarLoop]: Difference is false
[2025-01-10 07:51:16,322 INFO  L312   stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA
[2025-01-10 07:51:16,322 INFO  L316   stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ========
[2025-01-10 07:51:16,327 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand  has 192 states, 191 states have (on average 1.4712041884816753) internal successors, (281), 191 states have internal predecessors, (281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:16,342 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 155
[2025-01-10 07:51:16,342 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-01-10 07:51:16,342 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-01-10 07:51:16,348 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:16,348 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:16,348 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 1 ============
[2025-01-10 07:51:16,349 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand  has 192 states, 191 states have (on average 1.4712041884816753) internal successors, (281), 191 states have internal predecessors, (281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:16,353 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 155
[2025-01-10 07:51:16,354 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-01-10 07:51:16,354 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-01-10 07:51:16,354 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:16,355 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:16,359 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~P_1_i~0);~P_1_st~0 := 2;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume !(1 == ~C_1_i~0);~C_1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-01-10 07:51:16,360 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume !true;" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-01-10 07:51:16,364 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:16,364 INFO  L85        PathProgramCache]: Analyzing trace with hash 1332213672, now seen corresponding path program 1 times
[2025-01-10 07:51:16,368 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:16,369 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414508296]
[2025-01-10 07:51:16,369 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:16,369 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:16,422 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes.
[2025-01-10 07:51:16,437 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements.
[2025-01-10 07:51:16,437 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:16,438 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:16,509 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:16,509 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:16,509 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414508296]
[2025-01-10 07:51:16,510 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [414508296] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:16,510 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:16,510 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-01-10 07:51:16,511 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1845932174]
[2025-01-10 07:51:16,513 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:16,515 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-01-10 07:51:16,516 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:16,516 INFO  L85        PathProgramCache]: Analyzing trace with hash 1738231933, now seen corresponding path program 1 times
[2025-01-10 07:51:16,516 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:16,516 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1976830215]
[2025-01-10 07:51:16,516 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:16,516 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:16,522 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes.
[2025-01-10 07:51:16,523 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements.
[2025-01-10 07:51:16,523 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:16,523 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:16,541 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:16,541 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:16,541 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1976830215]
[2025-01-10 07:51:16,541 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1976830215] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:16,541 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:16,541 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-01-10 07:51:16,541 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56030643]
[2025-01-10 07:51:16,541 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:16,542 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-01-10 07:51:16,542 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-01-10 07:51:16,562 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-01-10 07:51:16,563 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-01-10 07:51:16,564 INFO  L87              Difference]: Start difference. First operand  has 192 states, 191 states have (on average 1.4712041884816753) internal successors, (281), 191 states have internal predecessors, (281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand  has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:16,583 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-01-10 07:51:16,583 INFO  L93              Difference]: Finished difference Result 184 states and 266 transitions.
[2025-01-10 07:51:16,584 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 184 states and 266 transitions.
[2025-01-10 07:51:16,587 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 143
[2025-01-10 07:51:16,592 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 184 states to 176 states and 258 transitions.
[2025-01-10 07:51:16,592 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 176
[2025-01-10 07:51:16,593 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 176
[2025-01-10 07:51:16,595 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 176 states and 258 transitions.
[2025-01-10 07:51:16,596 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-01-10 07:51:16,596 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 176 states and 258 transitions.
[2025-01-10 07:51:16,606 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 176 states and 258 transitions.
[2025-01-10 07:51:16,616 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 176.
[2025-01-10 07:51:16,617 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 176 states, 176 states have (on average 1.4659090909090908) internal successors, (258), 175 states have internal predecessors, (258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:16,618 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 258 transitions.
[2025-01-10 07:51:16,619 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 176 states and 258 transitions.
[2025-01-10 07:51:16,620 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-01-10 07:51:16,622 INFO  L432   stractBuchiCegarLoop]: Abstraction has 176 states and 258 transitions.
[2025-01-10 07:51:16,622 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 2 ============
[2025-01-10 07:51:16,622 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 176 states and 258 transitions.
[2025-01-10 07:51:16,624 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 143
[2025-01-10 07:51:16,626 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-01-10 07:51:16,626 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-01-10 07:51:16,627 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:16,627 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:16,627 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume !(1 == ~C_1_i~0);~C_1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-01-10 07:51:16,628 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-01-10 07:51:16,628 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:16,628 INFO  L85        PathProgramCache]: Analyzing trace with hash 1466227178, now seen corresponding path program 1 times
[2025-01-10 07:51:16,628 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:16,628 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002926032]
[2025-01-10 07:51:16,628 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:16,628 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:16,639 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes.
[2025-01-10 07:51:16,646 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements.
[2025-01-10 07:51:16,648 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:16,648 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:16,693 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:16,694 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:16,694 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1002926032]
[2025-01-10 07:51:16,694 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1002926032] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:16,694 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:16,694 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-01-10 07:51:16,694 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1502872465]
[2025-01-10 07:51:16,694 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:16,696 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-01-10 07:51:16,697 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:16,697 INFO  L85        PathProgramCache]: Analyzing trace with hash -909564326, now seen corresponding path program 1 times
[2025-01-10 07:51:16,697 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:16,697 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008907696]
[2025-01-10 07:51:16,697 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:16,697 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:16,706 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes.
[2025-01-10 07:51:16,721 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements.
[2025-01-10 07:51:16,723 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:16,724 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:16,804 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:16,805 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:16,805 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008907696]
[2025-01-10 07:51:16,805 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008907696] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:16,805 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:16,805 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-01-10 07:51:16,805 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527259585]
[2025-01-10 07:51:16,805 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:16,805 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-01-10 07:51:16,805 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-01-10 07:51:16,806 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-01-10 07:51:16,806 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-01-10 07:51:16,806 INFO  L87              Difference]: Start difference. First operand 176 states and 258 transitions. cyclomatic complexity: 83 Second operand  has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:16,817 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-01-10 07:51:16,818 INFO  L93              Difference]: Finished difference Result 176 states and 257 transitions.
[2025-01-10 07:51:16,818 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 176 states and 257 transitions.
[2025-01-10 07:51:16,819 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 143
[2025-01-10 07:51:16,820 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 176 states to 176 states and 257 transitions.
[2025-01-10 07:51:16,820 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 176
[2025-01-10 07:51:16,821 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 176
[2025-01-10 07:51:16,821 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 176 states and 257 transitions.
[2025-01-10 07:51:16,821 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-01-10 07:51:16,821 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 176 states and 257 transitions.
[2025-01-10 07:51:16,822 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 176 states and 257 transitions.
[2025-01-10 07:51:16,825 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 176.
[2025-01-10 07:51:16,825 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 176 states, 176 states have (on average 1.4602272727272727) internal successors, (257), 175 states have internal predecessors, (257), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:16,826 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 257 transitions.
[2025-01-10 07:51:16,826 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 176 states and 257 transitions.
[2025-01-10 07:51:16,826 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-01-10 07:51:16,826 INFO  L432   stractBuchiCegarLoop]: Abstraction has 176 states and 257 transitions.
[2025-01-10 07:51:16,827 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 3 ============
[2025-01-10 07:51:16,827 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 176 states and 257 transitions.
[2025-01-10 07:51:16,828 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 143
[2025-01-10 07:51:16,828 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-01-10 07:51:16,828 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-01-10 07:51:16,828 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:16,829 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:16,829 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-01-10 07:51:16,829 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-01-10 07:51:16,829 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:16,829 INFO  L85        PathProgramCache]: Analyzing trace with hash 1247372460, now seen corresponding path program 1 times
[2025-01-10 07:51:16,830 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:16,830 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837304198]
[2025-01-10 07:51:16,830 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:16,830 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:16,834 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes.
[2025-01-10 07:51:16,838 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements.
[2025-01-10 07:51:16,838 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:16,838 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:16,877 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:16,878 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:16,878 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [837304198]
[2025-01-10 07:51:16,878 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [837304198] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:16,878 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:16,878 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-01-10 07:51:16,878 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [839655244]
[2025-01-10 07:51:16,878 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:16,878 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-01-10 07:51:16,879 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:16,879 INFO  L85        PathProgramCache]: Analyzing trace with hash -909564326, now seen corresponding path program 2 times
[2025-01-10 07:51:16,879 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:16,879 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702571652]
[2025-01-10 07:51:16,879 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-01-10 07:51:16,879 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:16,884 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 40 statements into 1 equivalence classes.
[2025-01-10 07:51:16,888 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 40 of 40 statements.
[2025-01-10 07:51:16,888 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-01-10 07:51:16,888 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:16,923 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:16,923 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:16,923 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702571652]
[2025-01-10 07:51:16,923 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [702571652] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:16,923 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:16,923 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-01-10 07:51:16,924 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [719933575]
[2025-01-10 07:51:16,924 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:16,924 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-01-10 07:51:16,924 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-01-10 07:51:16,924 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2025-01-10 07:51:16,924 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2025-01-10 07:51:16,925 INFO  L87              Difference]: Start difference. First operand 176 states and 257 transitions. cyclomatic complexity: 82 Second operand  has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:17,002 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-01-10 07:51:17,002 INFO  L93              Difference]: Finished difference Result 188 states and 269 transitions.
[2025-01-10 07:51:17,002 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 188 states and 269 transitions.
[2025-01-10 07:51:17,004 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 152
[2025-01-10 07:51:17,005 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 188 states to 188 states and 269 transitions.
[2025-01-10 07:51:17,005 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 188
[2025-01-10 07:51:17,005 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 188
[2025-01-10 07:51:17,005 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 188 states and 269 transitions.
[2025-01-10 07:51:17,006 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-01-10 07:51:17,006 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 188 states and 269 transitions.
[2025-01-10 07:51:17,006 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 188 states and 269 transitions.
[2025-01-10 07:51:17,009 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 188.
[2025-01-10 07:51:17,010 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 188 states, 188 states have (on average 1.4308510638297873) internal successors, (269), 187 states have internal predecessors, (269), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:17,010 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 269 transitions.
[2025-01-10 07:51:17,010 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 188 states and 269 transitions.
[2025-01-10 07:51:17,011 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 
[2025-01-10 07:51:17,011 INFO  L432   stractBuchiCegarLoop]: Abstraction has 188 states and 269 transitions.
[2025-01-10 07:51:17,012 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 4 ============
[2025-01-10 07:51:17,012 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 188 states and 269 transitions.
[2025-01-10 07:51:17,013 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 152
[2025-01-10 07:51:17,013 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-01-10 07:51:17,013 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-01-10 07:51:17,013 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:17,013 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:17,014 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-01-10 07:51:17,014 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-01-10 07:51:17,014 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:17,014 INFO  L85        PathProgramCache]: Analyzing trace with hash -32491218, now seen corresponding path program 1 times
[2025-01-10 07:51:17,014 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:17,014 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1579003581]
[2025-01-10 07:51:17,014 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:17,015 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:17,018 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes.
[2025-01-10 07:51:17,021 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements.
[2025-01-10 07:51:17,021 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:17,021 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:17,066 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:17,066 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:17,066 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1579003581]
[2025-01-10 07:51:17,066 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1579003581] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:17,066 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:17,066 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-01-10 07:51:17,067 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [504578487]
[2025-01-10 07:51:17,067 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:17,067 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-01-10 07:51:17,067 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:17,067 INFO  L85        PathProgramCache]: Analyzing trace with hash -909564326, now seen corresponding path program 3 times
[2025-01-10 07:51:17,067 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:17,067 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748111583]
[2025-01-10 07:51:17,067 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2
[2025-01-10 07:51:17,067 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:17,073 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 40 statements into 1 equivalence classes.
[2025-01-10 07:51:17,077 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 40 of 40 statements.
[2025-01-10 07:51:17,081 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s)
[2025-01-10 07:51:17,081 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:17,121 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:17,121 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:17,122 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1748111583]
[2025-01-10 07:51:17,122 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1748111583] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:17,122 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:17,122 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-01-10 07:51:17,122 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2089502701]
[2025-01-10 07:51:17,122 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:17,122 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-01-10 07:51:17,124 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-01-10 07:51:17,124 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-01-10 07:51:17,124 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-01-10 07:51:17,124 INFO  L87              Difference]: Start difference. First operand 188 states and 269 transitions. cyclomatic complexity: 82 Second operand  has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:17,201 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-01-10 07:51:17,202 INFO  L93              Difference]: Finished difference Result 469 states and 659 transitions.
[2025-01-10 07:51:17,202 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 469 states and 659 transitions.
[2025-01-10 07:51:17,206 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 406
[2025-01-10 07:51:17,208 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 469 states to 469 states and 659 transitions.
[2025-01-10 07:51:17,210 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 469
[2025-01-10 07:51:17,210 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 469
[2025-01-10 07:51:17,210 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 469 states and 659 transitions.
[2025-01-10 07:51:17,212 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-01-10 07:51:17,215 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 469 states and 659 transitions.
[2025-01-10 07:51:17,215 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 469 states and 659 transitions.
[2025-01-10 07:51:17,230 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 427.
[2025-01-10 07:51:17,230 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 427 states, 427 states have (on average 1.414519906323185) internal successors, (604), 426 states have internal predecessors, (604), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:17,233 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 427 states to 427 states and 604 transitions.
[2025-01-10 07:51:17,233 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 427 states and 604 transitions.
[2025-01-10 07:51:17,234 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-01-10 07:51:17,234 INFO  L432   stractBuchiCegarLoop]: Abstraction has 427 states and 604 transitions.
[2025-01-10 07:51:17,234 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 5 ============
[2025-01-10 07:51:17,234 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 427 states and 604 transitions.
[2025-01-10 07:51:17,236 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 390
[2025-01-10 07:51:17,236 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-01-10 07:51:17,236 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-01-10 07:51:17,237 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:17,237 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:17,237 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-01-10 07:51:17,237 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-01-10 07:51:17,242 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:17,242 INFO  L85        PathProgramCache]: Analyzing trace with hash -1311815953, now seen corresponding path program 1 times
[2025-01-10 07:51:17,242 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:17,242 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [16923898]
[2025-01-10 07:51:17,242 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:17,242 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:17,247 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes.
[2025-01-10 07:51:17,252 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements.
[2025-01-10 07:51:17,252 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:17,252 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:17,292 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:17,292 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:17,292 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [16923898]
[2025-01-10 07:51:17,292 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [16923898] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:17,292 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:17,292 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-01-10 07:51:17,292 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2005576854]
[2025-01-10 07:51:17,292 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:17,293 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-01-10 07:51:17,293 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:17,293 INFO  L85        PathProgramCache]: Analyzing trace with hash 1479555998, now seen corresponding path program 1 times
[2025-01-10 07:51:17,293 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:17,293 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [566730881]
[2025-01-10 07:51:17,293 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:17,293 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:17,299 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes.
[2025-01-10 07:51:17,303 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements.
[2025-01-10 07:51:17,303 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:17,304 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:17,335 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:17,336 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:17,336 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [566730881]
[2025-01-10 07:51:17,336 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [566730881] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:17,336 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:17,336 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-01-10 07:51:17,336 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100657196]
[2025-01-10 07:51:17,336 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:17,337 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-01-10 07:51:17,337 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-01-10 07:51:17,337 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-01-10 07:51:17,337 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-01-10 07:51:17,337 INFO  L87              Difference]: Start difference. First operand 427 states and 604 transitions. cyclomatic complexity: 179 Second operand  has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:17,449 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-01-10 07:51:17,449 INFO  L93              Difference]: Finished difference Result 1161 states and 1606 transitions.
[2025-01-10 07:51:17,449 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 1161 states and 1606 transitions.
[2025-01-10 07:51:17,455 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 1081
[2025-01-10 07:51:17,459 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 1161 states to 1161 states and 1606 transitions.
[2025-01-10 07:51:17,460 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 1161
[2025-01-10 07:51:17,461 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 1161
[2025-01-10 07:51:17,461 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 1161 states and 1606 transitions.
[2025-01-10 07:51:17,462 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-01-10 07:51:17,462 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 1161 states and 1606 transitions.
[2025-01-10 07:51:17,463 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 1161 states and 1606 transitions.
[2025-01-10 07:51:17,507 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 1161 to 1102.
[2025-01-10 07:51:17,509 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 1102 states, 1102 states have (on average 1.3920145190562614) internal successors, (1534), 1101 states have internal predecessors, (1534), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:17,513 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 1102 states to 1102 states and 1534 transitions.
[2025-01-10 07:51:17,513 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 1102 states and 1534 transitions.
[2025-01-10 07:51:17,513 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-01-10 07:51:17,514 INFO  L432   stractBuchiCegarLoop]: Abstraction has 1102 states and 1534 transitions.
[2025-01-10 07:51:17,516 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 6 ============
[2025-01-10 07:51:17,516 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 1102 states and 1534 transitions.
[2025-01-10 07:51:17,521 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 1060
[2025-01-10 07:51:17,521 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-01-10 07:51:17,521 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-01-10 07:51:17,522 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:17,523 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:17,523 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume 2 == ~C_1_pc~0;" "assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-01-10 07:51:17,523 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume 2 == ~C_1_pc~0;" "assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-01-10 07:51:17,523 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:17,524 INFO  L85        PathProgramCache]: Analyzing trace with hash -122788309, now seen corresponding path program 1 times
[2025-01-10 07:51:17,525 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:17,525 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304570712]
[2025-01-10 07:51:17,525 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:17,525 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:17,529 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes.
[2025-01-10 07:51:17,537 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements.
[2025-01-10 07:51:17,537 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:17,537 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:17,563 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:17,563 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:17,563 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [304570712]
[2025-01-10 07:51:17,563 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [304570712] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:17,563 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:17,564 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-01-10 07:51:17,564 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984252101]
[2025-01-10 07:51:17,564 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:17,564 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-01-10 07:51:17,564 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:17,564 INFO  L85        PathProgramCache]: Analyzing trace with hash -931126980, now seen corresponding path program 1 times
[2025-01-10 07:51:17,564 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:17,566 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399785183]
[2025-01-10 07:51:17,566 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:17,566 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:17,571 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes.
[2025-01-10 07:51:17,575 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements.
[2025-01-10 07:51:17,575 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:17,575 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:17,609 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:17,610 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:17,610 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1399785183]
[2025-01-10 07:51:17,612 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1399785183] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:17,612 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:17,612 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-01-10 07:51:17,612 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1595337259]
[2025-01-10 07:51:17,612 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:17,612 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-01-10 07:51:17,612 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-01-10 07:51:17,613 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-01-10 07:51:17,613 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-01-10 07:51:17,613 INFO  L87              Difference]: Start difference. First operand 1102 states and 1534 transitions. cyclomatic complexity: 436 Second operand  has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:17,650 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-01-10 07:51:17,651 INFO  L93              Difference]: Finished difference Result 1464 states and 2007 transitions.
[2025-01-10 07:51:17,651 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 1464 states and 2007 transitions.
[2025-01-10 07:51:17,657 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 1417
[2025-01-10 07:51:17,662 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 1464 states to 1464 states and 2007 transitions.
[2025-01-10 07:51:17,663 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 1464
[2025-01-10 07:51:17,665 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 1464
[2025-01-10 07:51:17,665 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 1464 states and 2007 transitions.
[2025-01-10 07:51:17,666 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-01-10 07:51:17,666 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 1464 states and 2007 transitions.
[2025-01-10 07:51:17,667 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 1464 states and 2007 transitions.
[2025-01-10 07:51:17,679 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 1464 to 1440.
[2025-01-10 07:51:17,680 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 1440 states, 1440 states have (on average 1.3729166666666666) internal successors, (1977), 1439 states have internal predecessors, (1977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:17,684 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 1440 states to 1440 states and 1977 transitions.
[2025-01-10 07:51:17,684 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 1440 states and 1977 transitions.
[2025-01-10 07:51:17,684 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-01-10 07:51:17,685 INFO  L432   stractBuchiCegarLoop]: Abstraction has 1440 states and 1977 transitions.
[2025-01-10 07:51:17,685 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 7 ============
[2025-01-10 07:51:17,685 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 1440 states and 1977 transitions.
[2025-01-10 07:51:17,690 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 1393
[2025-01-10 07:51:17,691 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-01-10 07:51:17,691 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-01-10 07:51:17,692 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:17,692 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:17,692 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-01-10 07:51:17,693 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-01-10 07:51:17,693 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:17,693 INFO  L85        PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 1 times
[2025-01-10 07:51:17,693 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:17,693 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915972325]
[2025-01-10 07:51:17,694 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:17,694 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:17,698 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes.
[2025-01-10 07:51:17,700 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements.
[2025-01-10 07:51:17,702 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:17,702 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:17,702 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-01-10 07:51:17,703 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes.
[2025-01-10 07:51:17,706 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements.
[2025-01-10 07:51:17,709 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:17,709 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:17,729 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-01-10 07:51:17,730 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:17,730 INFO  L85        PathProgramCache]: Analyzing trace with hash 60037693, now seen corresponding path program 1 times
[2025-01-10 07:51:17,730 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:17,730 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319767728]
[2025-01-10 07:51:17,731 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:17,731 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:17,734 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes.
[2025-01-10 07:51:17,737 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements.
[2025-01-10 07:51:17,737 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:17,737 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:17,778 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:17,778 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:17,778 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319767728]
[2025-01-10 07:51:17,778 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [319767728] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:17,778 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:17,778 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-01-10 07:51:17,779 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1902933552]
[2025-01-10 07:51:17,779 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:17,779 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-01-10 07:51:17,779 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-01-10 07:51:17,779 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2025-01-10 07:51:17,779 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2025-01-10 07:51:17,779 INFO  L87              Difference]: Start difference. First operand 1440 states and 1977 transitions. cyclomatic complexity: 541 Second operand  has 5 states, 5 states have (on average 8.2) internal successors, (41), 5 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:17,817 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-01-10 07:51:17,818 INFO  L93              Difference]: Finished difference Result 1524 states and 2061 transitions.
[2025-01-10 07:51:17,818 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 1524 states and 2061 transitions.
[2025-01-10 07:51:17,824 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 1477
[2025-01-10 07:51:17,828 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 1524 states to 1524 states and 2061 transitions.
[2025-01-10 07:51:17,828 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 1524
[2025-01-10 07:51:17,829 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 1524
[2025-01-10 07:51:17,829 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 1524 states and 2061 transitions.
[2025-01-10 07:51:17,831 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-01-10 07:51:17,831 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 1524 states and 2061 transitions.
[2025-01-10 07:51:17,831 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 1524 states and 2061 transitions.
[2025-01-10 07:51:17,841 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 1524 to 1476.
[2025-01-10 07:51:17,843 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 1476 states, 1476 states have (on average 1.363821138211382) internal successors, (2013), 1475 states have internal predecessors, (2013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:17,846 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2013 transitions.
[2025-01-10 07:51:17,846 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 1476 states and 2013 transitions.
[2025-01-10 07:51:17,846 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 
[2025-01-10 07:51:17,847 INFO  L432   stractBuchiCegarLoop]: Abstraction has 1476 states and 2013 transitions.
[2025-01-10 07:51:17,847 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 8 ============
[2025-01-10 07:51:17,847 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2013 transitions.
[2025-01-10 07:51:17,851 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 1429
[2025-01-10 07:51:17,851 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-01-10 07:51:17,851 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-01-10 07:51:17,852 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:17,852 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:17,852 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-01-10 07:51:17,852 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume !(0 == ~P_1_st~0);" "assume !(0 == ~P_2_st~0);" "assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-01-10 07:51:17,852 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:17,853 INFO  L85        PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 2 times
[2025-01-10 07:51:17,853 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:17,853 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [593963679]
[2025-01-10 07:51:17,853 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-01-10 07:51:17,853 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:17,856 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 29 statements into 1 equivalence classes.
[2025-01-10 07:51:17,858 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 29 of 29 statements.
[2025-01-10 07:51:17,858 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-01-10 07:51:17,858 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:17,858 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-01-10 07:51:17,859 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes.
[2025-01-10 07:51:17,860 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements.
[2025-01-10 07:51:17,860 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:17,860 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:17,863 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-01-10 07:51:17,864 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:17,864 INFO  L85        PathProgramCache]: Analyzing trace with hash 1896892260, now seen corresponding path program 1 times
[2025-01-10 07:51:17,864 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:17,864 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1790231102]
[2025-01-10 07:51:17,864 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:17,864 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:17,867 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes.
[2025-01-10 07:51:17,868 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements.
[2025-01-10 07:51:17,869 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:17,869 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:17,880 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:17,881 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:17,881 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1790231102]
[2025-01-10 07:51:17,881 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1790231102] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:17,881 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:17,881 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-01-10 07:51:17,881 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1398901343]
[2025-01-10 07:51:17,881 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:17,881 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-01-10 07:51:17,881 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-01-10 07:51:17,881 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-01-10 07:51:17,882 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-01-10 07:51:17,882 INFO  L87              Difference]: Start difference. First operand 1476 states and 2013 transitions. cyclomatic complexity: 541 Second operand  has 3 states, 3 states have (on average 14.333333333333334) internal successors, (43), 3 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:17,953 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-01-10 07:51:17,954 INFO  L93              Difference]: Finished difference Result 2282 states and 3075 transitions.
[2025-01-10 07:51:17,954 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 2282 states and 3075 transitions.
[2025-01-10 07:51:17,962 INFO  L131   ngComponentsAnalysis]: Automaton has 7 accepting balls. 2186
[2025-01-10 07:51:17,969 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 2282 states to 2282 states and 3075 transitions.
[2025-01-10 07:51:17,969 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 2282
[2025-01-10 07:51:17,971 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 2282
[2025-01-10 07:51:17,971 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 2282 states and 3075 transitions.
[2025-01-10 07:51:17,973 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-01-10 07:51:17,973 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 2282 states and 3075 transitions.
[2025-01-10 07:51:17,974 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 2282 states and 3075 transitions.
[2025-01-10 07:51:17,988 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 2282 to 2282.
[2025-01-10 07:51:17,991 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 2282 states, 2282 states have (on average 1.3475021910604732) internal successors, (3075), 2281 states have internal predecessors, (3075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:17,996 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 2282 states to 2282 states and 3075 transitions.
[2025-01-10 07:51:17,996 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 2282 states and 3075 transitions.
[2025-01-10 07:51:17,996 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-01-10 07:51:17,998 INFO  L432   stractBuchiCegarLoop]: Abstraction has 2282 states and 3075 transitions.
[2025-01-10 07:51:17,998 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 9 ============
[2025-01-10 07:51:17,998 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 2282 states and 3075 transitions.
[2025-01-10 07:51:18,004 INFO  L131   ngComponentsAnalysis]: Automaton has 7 accepting balls. 2186
[2025-01-10 07:51:18,005 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-01-10 07:51:18,005 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-01-10 07:51:18,006 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:18,006 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:18,006 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" 
[2025-01-10 07:51:18,006 INFO  L754   eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume !(0 == ~P_2_st~0);" "assume !(0 == ~C_1_st~0);" 
[2025-01-10 07:51:18,007 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:18,007 INFO  L85        PathProgramCache]: Analyzing trace with hash 833355080, now seen corresponding path program 1 times
[2025-01-10 07:51:18,008 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:18,008 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563543989]
[2025-01-10 07:51:18,008 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:18,008 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:18,012 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes.
[2025-01-10 07:51:18,013 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements.
[2025-01-10 07:51:18,013 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:18,013 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:18,013 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-01-10 07:51:18,014 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes.
[2025-01-10 07:51:18,018 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements.
[2025-01-10 07:51:18,018 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:18,018 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:18,024 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-01-10 07:51:18,024 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:18,024 INFO  L85        PathProgramCache]: Analyzing trace with hash -723781654, now seen corresponding path program 1 times
[2025-01-10 07:51:18,024 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:18,025 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562004065]
[2025-01-10 07:51:18,025 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:18,025 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:18,026 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes.
[2025-01-10 07:51:18,027 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements.
[2025-01-10 07:51:18,027 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:18,027 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:18,027 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-01-10 07:51:18,028 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes.
[2025-01-10 07:51:18,028 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements.
[2025-01-10 07:51:18,029 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:18,029 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:18,030 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-01-10 07:51:18,031 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:18,031 INFO  L85        PathProgramCache]: Analyzing trace with hash -1464141181, now seen corresponding path program 1 times
[2025-01-10 07:51:18,031 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:18,031 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752098387]
[2025-01-10 07:51:18,031 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:18,031 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:18,035 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes.
[2025-01-10 07:51:18,038 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements.
[2025-01-10 07:51:18,039 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:18,039 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:18,067 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:18,067 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:18,067 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1752098387]
[2025-01-10 07:51:18,067 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1752098387] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:18,067 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:18,067 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-01-10 07:51:18,067 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [530406860]
[2025-01-10 07:51:18,067 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:18,130 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-01-10 07:51:18,130 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-01-10 07:51:18,130 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-01-10 07:51:18,130 INFO  L87              Difference]: Start difference. First operand 2282 states and 3075 transitions. cyclomatic complexity: 800 Second operand  has 3 states, 3 states have (on average 13.0) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:18,188 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-01-10 07:51:18,188 INFO  L93              Difference]: Finished difference Result 3791 states and 5034 transitions.
[2025-01-10 07:51:18,188 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 3791 states and 5034 transitions.
[2025-01-10 07:51:18,206 INFO  L131   ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641
[2025-01-10 07:51:18,221 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 3791 states to 3791 states and 5034 transitions.
[2025-01-10 07:51:18,222 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 3791
[2025-01-10 07:51:18,224 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 3791
[2025-01-10 07:51:18,224 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 3791 states and 5034 transitions.
[2025-01-10 07:51:18,229 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-01-10 07:51:18,229 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 3791 states and 5034 transitions.
[2025-01-10 07:51:18,232 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 3791 states and 5034 transitions.
[2025-01-10 07:51:18,264 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 3791 to 3707.
[2025-01-10 07:51:18,269 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 3707 states, 3707 states have (on average 1.3304558942541138) internal successors, (4932), 3706 states have internal predecessors, (4932), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:18,277 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 3707 states to 3707 states and 4932 transitions.
[2025-01-10 07:51:18,278 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 3707 states and 4932 transitions.
[2025-01-10 07:51:18,278 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-01-10 07:51:18,280 INFO  L432   stractBuchiCegarLoop]: Abstraction has 3707 states and 4932 transitions.
[2025-01-10 07:51:18,280 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 10 ============
[2025-01-10 07:51:18,280 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 3707 states and 4932 transitions.
[2025-01-10 07:51:18,291 INFO  L131   ngComponentsAnalysis]: Automaton has 7 accepting balls. 3557
[2025-01-10 07:51:18,291 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-01-10 07:51:18,291 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-01-10 07:51:18,292 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:18,292 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:18,293 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume !(1 == ~P_2_i~0);~P_2_st~0 := 2;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" 
[2025-01-10 07:51:18,293 INFO  L754   eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume !(0 == ~C_1_st~0);" 
[2025-01-10 07:51:18,293 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:18,294 INFO  L85        PathProgramCache]: Analyzing trace with hash 272839112, now seen corresponding path program 1 times
[2025-01-10 07:51:18,294 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:18,294 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056962335]
[2025-01-10 07:51:18,294 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:18,294 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:18,299 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes.
[2025-01-10 07:51:18,301 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements.
[2025-01-10 07:51:18,301 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:18,301 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:18,318 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:18,318 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:18,319 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1056962335]
[2025-01-10 07:51:18,319 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1056962335] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:18,319 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:18,319 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-01-10 07:51:18,319 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1291755164]
[2025-01-10 07:51:18,319 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:18,319 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-01-10 07:51:18,319 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:18,319 INFO  L85        PathProgramCache]: Analyzing trace with hash -962532473, now seen corresponding path program 1 times
[2025-01-10 07:51:18,319 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:18,320 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2009728795]
[2025-01-10 07:51:18,320 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:18,320 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:18,321 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes.
[2025-01-10 07:51:18,322 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements.
[2025-01-10 07:51:18,322 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:18,322 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:18,322 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-01-10 07:51:18,327 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes.
[2025-01-10 07:51:18,328 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements.
[2025-01-10 07:51:18,328 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:18,328 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:18,329 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-01-10 07:51:18,415 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-01-10 07:51:18,415 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-01-10 07:51:18,415 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-01-10 07:51:18,416 INFO  L87              Difference]: Start difference. First operand 3707 states and 4932 transitions. cyclomatic complexity: 1232 Second operand  has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:18,443 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-01-10 07:51:18,447 INFO  L93              Difference]: Finished difference Result 3683 states and 4905 transitions.
[2025-01-10 07:51:18,448 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 3683 states and 4905 transitions.
[2025-01-10 07:51:18,468 INFO  L131   ngComponentsAnalysis]: Automaton has 7 accepting balls. 3557
[2025-01-10 07:51:18,498 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 3683 states to 3683 states and 4905 transitions.
[2025-01-10 07:51:18,498 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 3683
[2025-01-10 07:51:18,500 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 3683
[2025-01-10 07:51:18,504 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 3683 states and 4905 transitions.
[2025-01-10 07:51:18,510 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-01-10 07:51:18,513 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 3683 states and 4905 transitions.
[2025-01-10 07:51:18,516 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 3683 states and 4905 transitions.
[2025-01-10 07:51:18,598 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 3683 to 3683.
[2025-01-10 07:51:18,607 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 3683 states, 3683 states have (on average 1.3317947325549824) internal successors, (4905), 3682 states have internal predecessors, (4905), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:18,634 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 3683 states to 3683 states and 4905 transitions.
[2025-01-10 07:51:18,634 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 3683 states and 4905 transitions.
[2025-01-10 07:51:18,634 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-01-10 07:51:18,635 INFO  L432   stractBuchiCegarLoop]: Abstraction has 3683 states and 4905 transitions.
[2025-01-10 07:51:18,635 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 11 ============
[2025-01-10 07:51:18,635 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 3683 states and 4905 transitions.
[2025-01-10 07:51:18,666 INFO  L131   ngComponentsAnalysis]: Automaton has 7 accepting balls. 3557
[2025-01-10 07:51:18,669 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-01-10 07:51:18,670 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-01-10 07:51:18,670 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:18,670 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:18,670 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" 
[2025-01-10 07:51:18,671 INFO  L754   eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume !(0 == ~C_1_st~0);" 
[2025-01-10 07:51:18,675 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:18,675 INFO  L85        PathProgramCache]: Analyzing trace with hash 833355080, now seen corresponding path program 2 times
[2025-01-10 07:51:18,675 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:18,675 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74712939]
[2025-01-10 07:51:18,675 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-01-10 07:51:18,675 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:18,683 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 30 statements into 1 equivalence classes.
[2025-01-10 07:51:18,687 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 30 of 30 statements.
[2025-01-10 07:51:18,688 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-01-10 07:51:18,688 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:18,688 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-01-10 07:51:18,690 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes.
[2025-01-10 07:51:18,696 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements.
[2025-01-10 07:51:18,699 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:18,699 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:18,704 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-01-10 07:51:18,708 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:18,708 INFO  L85        PathProgramCache]: Analyzing trace with hash -962532473, now seen corresponding path program 2 times
[2025-01-10 07:51:18,708 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:18,708 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [462641483]
[2025-01-10 07:51:18,708 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-01-10 07:51:18,708 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:18,711 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 10 statements into 1 equivalence classes.
[2025-01-10 07:51:18,716 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 10 of 10 statements.
[2025-01-10 07:51:18,716 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-01-10 07:51:18,716 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:18,716 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-01-10 07:51:18,717 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes.
[2025-01-10 07:51:18,721 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements.
[2025-01-10 07:51:18,721 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:18,722 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:18,723 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-01-10 07:51:18,723 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:18,727 INFO  L85        PathProgramCache]: Analyzing trace with hash 1856125966, now seen corresponding path program 1 times
[2025-01-10 07:51:18,728 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:18,728 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892161713]
[2025-01-10 07:51:18,728 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:18,728 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:18,736 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes.
[2025-01-10 07:51:18,739 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements.
[2025-01-10 07:51:18,742 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:18,743 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-01-10 07:51:18,778 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-01-10 07:51:18,779 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-01-10 07:51:18,779 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1892161713]
[2025-01-10 07:51:18,779 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1892161713] provided 1 perfect and 0 imperfect interpolant sequences
[2025-01-10 07:51:18,779 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-01-10 07:51:18,779 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-01-10 07:51:18,779 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [892525679]
[2025-01-10 07:51:18,779 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-01-10 07:51:18,819 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-01-10 07:51:18,820 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-01-10 07:51:18,820 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-01-10 07:51:18,820 INFO  L87              Difference]: Start difference. First operand 3683 states and 4905 transitions. cyclomatic complexity: 1229 Second operand  has 3 states, 2 states have (on average 20.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:18,871 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-01-10 07:51:18,871 INFO  L93              Difference]: Finished difference Result 6409 states and 8463 transitions.
[2025-01-10 07:51:18,871 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 6409 states and 8463 transitions.
[2025-01-10 07:51:18,898 INFO  L131   ngComponentsAnalysis]: Automaton has 7 accepting balls. 6187
[2025-01-10 07:51:18,923 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 6409 states to 6409 states and 8463 transitions.
[2025-01-10 07:51:18,923 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 6409
[2025-01-10 07:51:18,927 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 6409
[2025-01-10 07:51:18,928 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 6409 states and 8463 transitions.
[2025-01-10 07:51:18,935 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-01-10 07:51:18,935 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 6409 states and 8463 transitions.
[2025-01-10 07:51:18,939 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 6409 states and 8463 transitions.
[2025-01-10 07:51:18,997 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 6409 to 6409.
[2025-01-10 07:51:19,004 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 6409 states, 6409 states have (on average 1.3204868154158216) internal successors, (8463), 6408 states have internal predecessors, (8463), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-01-10 07:51:19,019 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 6409 states to 6409 states and 8463 transitions.
[2025-01-10 07:51:19,020 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 6409 states and 8463 transitions.
[2025-01-10 07:51:19,020 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-01-10 07:51:19,020 INFO  L432   stractBuchiCegarLoop]: Abstraction has 6409 states and 8463 transitions.
[2025-01-10 07:51:19,020 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 12 ============
[2025-01-10 07:51:19,020 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 6409 states and 8463 transitions.
[2025-01-10 07:51:19,034 INFO  L131   ngComponentsAnalysis]: Automaton has 7 accepting balls. 6187
[2025-01-10 07:51:19,034 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-01-10 07:51:19,035 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-01-10 07:51:19,035 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:19,035 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-01-10 07:51:19,035 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" 
[2025-01-10 07:51:19,035 INFO  L754   eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume 0 == ~C_1_st~0;havoc eval_#t~nondet8#1;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp___1~0#1);" 
[2025-01-10 07:51:19,036 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:19,036 INFO  L85        PathProgramCache]: Analyzing trace with hash 833355080, now seen corresponding path program 3 times
[2025-01-10 07:51:19,036 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:19,036 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1092982056]
[2025-01-10 07:51:19,036 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2
[2025-01-10 07:51:19,036 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:19,040 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 30 statements into 1 equivalence classes.
[2025-01-10 07:51:19,042 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 30 of 30 statements.
[2025-01-10 07:51:19,042 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s)
[2025-01-10 07:51:19,042 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:19,042 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-01-10 07:51:19,043 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes.
[2025-01-10 07:51:19,045 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements.
[2025-01-10 07:51:19,045 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:19,045 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:19,047 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-01-10 07:51:19,048 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:19,048 INFO  L85        PathProgramCache]: Analyzing trace with hash 226262445, now seen corresponding path program 1 times
[2025-01-10 07:51:19,048 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:19,048 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497008712]
[2025-01-10 07:51:19,048 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:19,048 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:19,050 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes.
[2025-01-10 07:51:19,051 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements.
[2025-01-10 07:51:19,051 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:19,051 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:19,051 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-01-10 07:51:19,052 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes.
[2025-01-10 07:51:19,052 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements.
[2025-01-10 07:51:19,052 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:19,052 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:19,053 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-01-10 07:51:19,054 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-01-10 07:51:19,054 INFO  L85        PathProgramCache]: Analyzing trace with hash 1705328134, now seen corresponding path program 1 times
[2025-01-10 07:51:19,054 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-01-10 07:51:19,054 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1401743360]
[2025-01-10 07:51:19,054 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-01-10 07:51:19,054 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-01-10 07:51:19,058 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes.
[2025-01-10 07:51:19,060 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements.
[2025-01-10 07:51:19,060 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:19,060 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:19,060 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-01-10 07:51:19,062 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes.
[2025-01-10 07:51:19,063 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements.
[2025-01-10 07:51:19,064 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:19,064 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:19,067 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-01-10 07:51:19,789 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes.
[2025-01-10 07:51:19,792 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements.
[2025-01-10 07:51:19,792 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:19,792 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:19,792 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-01-10 07:51:19,800 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes.
[2025-01-10 07:51:19,803 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements.
[2025-01-10 07:51:19,803 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-01-10 07:51:19,803 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-01-10 07:51:19,891 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 10.01 07:51:19 BoogieIcfgContainer
[2025-01-10 07:51:19,894 INFO  L131        PluginConnector]: ------------------------ END BuchiAutomizer----------------------------
[2025-01-10 07:51:19,895 INFO  L112        PluginConnector]: ------------------------Witness Printer----------------------------
[2025-01-10 07:51:19,895 INFO  L270        PluginConnector]: Initializing Witness Printer...
[2025-01-10 07:51:19,895 INFO  L274        PluginConnector]: Witness Printer initialized
[2025-01-10 07:51:19,900 INFO  L184        PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:51:16" (3/4) ...
[2025-01-10 07:51:19,901 INFO  L143         WitnessPrinter]: Generating witness for non-termination counterexample
[2025-01-10 07:51:19,956 INFO  L149         WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml
[2025-01-10 07:51:19,956 INFO  L131        PluginConnector]: ------------------------ END Witness Printer----------------------------
[2025-01-10 07:51:19,958 INFO  L158              Benchmark]: Toolchain (without parser) took 4686.09ms. Allocated memory was 167.8MB in the beginning and 352.3MB in the end (delta: 184.5MB). Free memory was 129.2MB in the beginning and 243.2MB in the end (delta: -114.0MB). Peak memory consumption was 69.1MB. Max. memory is 16.1GB.
[2025-01-10 07:51:19,958 INFO  L158              Benchmark]: CDTParser took 0.30ms. Allocated memory is still 226.5MB. Free memory is still 146.5MB. There was no memory consumed. Max. memory is 16.1GB.
[2025-01-10 07:51:19,958 INFO  L158              Benchmark]: CACSL2BoogieTranslator took 417.39ms. Allocated memory is still 167.8MB. Free memory was 129.2MB in the beginning and 115.0MB in the end (delta: 14.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
[2025-01-10 07:51:19,958 INFO  L158              Benchmark]: Boogie Procedure Inliner took 25.81ms. Allocated memory is still 167.8MB. Free memory was 115.0MB in the beginning and 112.9MB in the end (delta: 2.1MB). There was no memory consumed. Max. memory is 16.1GB.
[2025-01-10 07:51:19,959 INFO  L158              Benchmark]: Boogie Preprocessor took 27.02ms. Allocated memory is still 167.8MB. Free memory was 112.9MB in the beginning and 109.9MB in the end (delta: 3.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
[2025-01-10 07:51:19,959 INFO  L158              Benchmark]: RCFGBuilder took 518.94ms. Allocated memory is still 167.8MB. Free memory was 109.9MB in the beginning and 80.5MB in the end (delta: 29.4MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB.
[2025-01-10 07:51:19,959 INFO  L158              Benchmark]: BuchiAutomizer took 3623.51ms. Allocated memory was 167.8MB in the beginning and 352.3MB in the end (delta: 184.5MB). Free memory was 79.4MB in the beginning and 248.3MB in the end (delta: -168.8MB). Peak memory consumption was 18.8MB. Max. memory is 16.1GB.
[2025-01-10 07:51:19,960 INFO  L158              Benchmark]: Witness Printer took 61.10ms. Allocated memory is still 352.3MB. Free memory was 248.3MB in the beginning and 243.2MB in the end (delta: 5.1MB). There was no memory consumed. Max. memory is 16.1GB.
[2025-01-10 07:51:19,961 INFO  L338   ainManager$Toolchain]: #######################  End [Toolchain 1] #######################
 --- Results ---
 * Results from de.uni_freiburg.informatik.ultimate.core:
  - StatisticsResult: Toolchain Benchmarks
    Benchmark results are:
 * CDTParser took 0.30ms. Allocated memory is still 226.5MB. Free memory is still 146.5MB. There was no memory consumed. Max. memory is 16.1GB.
 * CACSL2BoogieTranslator took 417.39ms. Allocated memory is still 167.8MB. Free memory was 129.2MB in the beginning and 115.0MB in the end (delta: 14.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
 * Boogie Procedure Inliner took 25.81ms. Allocated memory is still 167.8MB. Free memory was 115.0MB in the beginning and 112.9MB in the end (delta: 2.1MB). There was no memory consumed. Max. memory is 16.1GB.
 * Boogie Preprocessor took 27.02ms. Allocated memory is still 167.8MB. Free memory was 112.9MB in the beginning and 109.9MB in the end (delta: 3.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
 * RCFGBuilder took 518.94ms. Allocated memory is still 167.8MB. Free memory was 109.9MB in the beginning and 80.5MB in the end (delta: 29.4MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB.
 * BuchiAutomizer took 3623.51ms. Allocated memory was 167.8MB in the beginning and 352.3MB in the end (delta: 184.5MB). Free memory was 79.4MB in the beginning and 248.3MB in the end (delta: -168.8MB). Peak memory consumption was 18.8MB. Max. memory is 16.1GB.
 * Witness Printer took 61.10ms. Allocated memory is still 352.3MB. Free memory was 248.3MB in the beginning and 243.2MB in the end (delta: 5.1MB). There was no memory consumed. Max. memory is 16.1GB.
 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction:
  - StatisticsResult: Constructed decomposition of program
    Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 6409 locations.
  - StatisticsResult: Timing statistics
    BüchiAutomizer plugin needed 3.5s and 12 iterations.  TraceHistogramMax:1. Analysis of lassos took 2.0s. Construction of modules took 0.3s. Büchi inclusion checks took 0.9s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.4s AutomataMinimizationTime, 11 MinimizatonAttempts, 257 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1.	Nontrivial modules had stage [0, 0, 0, 0, 0].	InterpolantCoveringCapabilityFinite: 0/0	InterpolantCoveringCapabilityBuchi: 0/0	HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2654 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2654 mSDsluCounter, 5833 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3067 mSDsCounter, 111 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 310 IncrementalHoareTripleChecker+Invalid, 421 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 111 mSolverCounterUnsat, 2766 mSDtfsCounter, 310 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown	LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0	LassoNonterminationAnalysisSatUnbounded: 0	LassoNonterminationAnalysisUnsat: 0	LassoNonterminationAnalysisUnknown: 0	LassoNonterminationAnalysisTime: 0.0s	InitialAbstractionConstructionTime: 0.0s
  - TerminationAnalysisResult: Nontermination possible
    Buchi Automizer proved that your program is nonterminating for some inputs
  - LassoShapedNonTerminationArgument [Line: 1]: Nontermination argument in form of an infinite program execution.
    Nontermination argument in form of an infinite program execution.
Stem:
[L25]               int max_loop ;
[L26]               int num ;
[L27]               int i  ;
[L28]               int e  ;
[L29]               int timer ;
[L30]               char data_0  ;
[L31]               char data_1  ;
[L74]               int P_1_pc;
[L75]               int P_1_st  ;
[L76]               int P_1_i  ;
[L77]               int P_1_ev  ;
[L132]              int P_2_pc  ;
[L133]              int P_2_st  ;
[L134]              int P_2_i  ;
[L135]              int P_2_ev  ;
[L200]              int C_1_pc  ;
[L201]              int C_1_st  ;
[L202]              int C_1_i  ;
[L203]              int C_1_ev  ;
[L204]              int C_1_pr  ;
        VAL         [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0]
[L603]              int count ;
[L604]              int __retres2 ;
[L608]              num  =    0
[L609]              i  =    0
[L610]              max_loop = 2
[L612]              timer  =    0
[L613]              P_1_pc  =    0
[L614]              P_2_pc  =    0
[L615]              C_1_pc  =    0
[L617]              count = 0
[L618]  CALL        init_model()
[L595]              P_1_i = 1
[L596]              P_2_i = 1
[L597]              C_1_i = 1
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L618]  RET         init_model()
[L619]  CALL        start_simulation()
[L533]              int kernel_st ;
[L534]              int tmp ;
[L535]              int tmp___0 ;
[L539]              kernel_st = 0
[L540]  FCALL       update_channels()
[L541]  CALL        init_threads()
[L304]  COND TRUE   (int )P_1_i == 1
[L305]              P_1_st = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L309]  COND TRUE   (int )P_2_i == 1
[L310]              P_2_st = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L314]  COND TRUE   (int )C_1_i == 1
[L315]              C_1_st = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L541]  RET         init_threads()
[L542]  FCALL       fire_delta_events()
[L543]  CALL        activate_threads()
[L469]              int tmp ;
[L470]              int tmp___0 ;
[L471]              int tmp___1 ;
[L475]  CALL, EXPR  is_P_1_triggered()
[L114]              int __retres1 ;
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L117]  COND FALSE  !((int )P_1_pc == 1)
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L127]              __retres1 = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L129]              return (__retres1);
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L475]  RET, EXPR   is_P_1_triggered()
[L475]              tmp = is_P_1_triggered()
[L477]  COND FALSE  !(\read(tmp))
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L483]  CALL, EXPR  is_P_2_triggered()
[L182]              int __retres1 ;
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L185]  COND FALSE  !((int )P_2_pc == 1)
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L195]              __retres1 = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L197]              return (__retres1);
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L483]  RET, EXPR   is_P_2_triggered()
[L483]              tmp___0 = is_P_2_triggered()
[L485]  COND FALSE  !(\read(tmp___0))
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L491]  CALL, EXPR  is_C_1_triggered()
[L264]              int __retres1 ;
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L267]  COND FALSE  !((int )C_1_pc == 1)
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L277]  COND FALSE  !((int )C_1_pc == 2)
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L287]              __retres1 = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L289]              return (__retres1);
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L491]  RET, EXPR   is_C_1_triggered()
[L491]              tmp___1 = is_C_1_triggered()
[L493]  COND FALSE  !(\read(tmp___1))
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L543]  RET         activate_threads()
[L544]  FCALL       reset_delta_events()
[L550]              kernel_st = 1
[L551]  CALL        eval()
[L349]              int tmp ;
[L350]              int tmp___0 ;
[L351]              int tmp___1 ;
[L352]              int tmp___2 ;
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
Loop:
[L359]  CALL, EXPR  exists_runnable_thread()
[L324]              int __retres1 ;
[L327]  COND TRUE   (int )P_1_st == 0
[L328]              __retres1 = 1
[L345]              return (__retres1);
[L359]  RET, EXPR   exists_runnable_thread()
[L359]              tmp___2 = exists_runnable_thread()
[L361]  COND TRUE   \read(tmp___2)
[L366]  COND TRUE   (int )P_1_st == 0
[L368]              tmp = __VERIFIER_nondet_int()
[L370]  COND FALSE  !(\read(tmp))
[L381]  COND TRUE   (int )P_2_st == 0
[L383]              tmp___0 = __VERIFIER_nondet_int()
[L385]  COND FALSE  !(\read(tmp___0))
[L396]  COND TRUE   (int )C_1_st == 0
[L398]              tmp___1 = __VERIFIER_nondet_int()
[L400]  COND FALSE  !(\read(tmp___1))
End of lasso representation.
  - StatisticsResult: NonterminationArgumentStatistics
    Fixpoint
  - NonterminatingLassoResult [Line: 1]: Nonterminating execution
    Found a nonterminating execution for the following lasso shaped sequence of statements.
Stem:
[L25]               int max_loop ;
[L26]               int num ;
[L27]               int i  ;
[L28]               int e  ;
[L29]               int timer ;
[L30]               char data_0  ;
[L31]               char data_1  ;
[L74]               int P_1_pc;
[L75]               int P_1_st  ;
[L76]               int P_1_i  ;
[L77]               int P_1_ev  ;
[L132]              int P_2_pc  ;
[L133]              int P_2_st  ;
[L134]              int P_2_i  ;
[L135]              int P_2_ev  ;
[L200]              int C_1_pc  ;
[L201]              int C_1_st  ;
[L202]              int C_1_i  ;
[L203]              int C_1_ev  ;
[L204]              int C_1_pr  ;
        VAL         [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0]
[L603]              int count ;
[L604]              int __retres2 ;
[L608]              num  =    0
[L609]              i  =    0
[L610]              max_loop = 2
[L612]              timer  =    0
[L613]              P_1_pc  =    0
[L614]              P_2_pc  =    0
[L615]              C_1_pc  =    0
[L617]              count = 0
[L618]  CALL        init_model()
[L595]              P_1_i = 1
[L596]              P_2_i = 1
[L597]              C_1_i = 1
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L618]  RET         init_model()
[L619]  CALL        start_simulation()
[L533]              int kernel_st ;
[L534]              int tmp ;
[L535]              int tmp___0 ;
[L539]              kernel_st = 0
[L540]  FCALL       update_channels()
[L541]  CALL        init_threads()
[L304]  COND TRUE   (int )P_1_i == 1
[L305]              P_1_st = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L309]  COND TRUE   (int )P_2_i == 1
[L310]              P_2_st = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L314]  COND TRUE   (int )C_1_i == 1
[L315]              C_1_st = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L541]  RET         init_threads()
[L542]  FCALL       fire_delta_events()
[L543]  CALL        activate_threads()
[L469]              int tmp ;
[L470]              int tmp___0 ;
[L471]              int tmp___1 ;
[L475]  CALL, EXPR  is_P_1_triggered()
[L114]              int __retres1 ;
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L117]  COND FALSE  !((int )P_1_pc == 1)
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L127]              __retres1 = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L129]              return (__retres1);
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L475]  RET, EXPR   is_P_1_triggered()
[L475]              tmp = is_P_1_triggered()
[L477]  COND FALSE  !(\read(tmp))
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L483]  CALL, EXPR  is_P_2_triggered()
[L182]              int __retres1 ;
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L185]  COND FALSE  !((int )P_2_pc == 1)
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L195]              __retres1 = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L197]              return (__retres1);
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L483]  RET, EXPR   is_P_2_triggered()
[L483]              tmp___0 = is_P_2_triggered()
[L485]  COND FALSE  !(\read(tmp___0))
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L491]  CALL, EXPR  is_C_1_triggered()
[L264]              int __retres1 ;
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L267]  COND FALSE  !((int )C_1_pc == 1)
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L277]  COND FALSE  !((int )C_1_pc == 2)
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L287]              __retres1 = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L289]              return (__retres1);
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L491]  RET, EXPR   is_C_1_triggered()
[L491]              tmp___1 = is_C_1_triggered()
[L493]  COND FALSE  !(\read(tmp___1))
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L543]  RET         activate_threads()
[L544]  FCALL       reset_delta_events()
[L550]              kernel_st = 1
[L551]  CALL        eval()
[L349]              int tmp ;
[L350]              int tmp___0 ;
[L351]              int tmp___1 ;
[L352]              int tmp___2 ;
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
Loop:
[L359]  CALL, EXPR  exists_runnable_thread()
[L324]              int __retres1 ;
[L327]  COND TRUE   (int )P_1_st == 0
[L328]              __retres1 = 1
[L345]              return (__retres1);
[L359]  RET, EXPR   exists_runnable_thread()
[L359]              tmp___2 = exists_runnable_thread()
[L361]  COND TRUE   \read(tmp___2)
[L366]  COND TRUE   (int )P_1_st == 0
[L368]              tmp = __VERIFIER_nondet_int()
[L370]  COND FALSE  !(\read(tmp))
[L381]  COND TRUE   (int )P_2_st == 0
[L383]              tmp___0 = __VERIFIER_nondet_int()
[L385]  COND FALSE  !(\read(tmp___0))
[L396]  COND TRUE   (int )C_1_st == 0
[L398]              tmp___1 = __VERIFIER_nondet_int()
[L400]  COND FALSE  !(\read(tmp___1))
End of lasso representation.
RESULT: Ultimate proved your program to be incorrect!
[2025-01-10 07:51:19,978 INFO  L540       MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0
Received shutdown request...
--- End real Ultimate output ---

Execution finished normally
Writing output log to file Ultimate.log
Writing human readable error path to file UltimateCounterExample.errorpath
Result:
FALSE(TERM)