./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 551b0097 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f --- Real Ultimate output --- This is Ultimate 0.3.0-?-551b009-m [2025-01-10 07:51:26,653 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-01-10 07:51:26,722 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-01-10 07:51:26,728 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-01-10 07:51:26,728 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-01-10 07:51:26,744 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-01-10 07:51:26,745 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-01-10 07:51:26,745 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-01-10 07:51:26,745 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-01-10 07:51:26,745 INFO L153 SettingsManager]: * Use memory slicer=true [2025-01-10 07:51:26,746 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-01-10 07:51:26,746 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-01-10 07:51:26,746 INFO L153 SettingsManager]: * Use SBE=true [2025-01-10 07:51:26,746 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-01-10 07:51:26,746 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-01-10 07:51:26,746 INFO L153 SettingsManager]: * Use old map elimination=false [2025-01-10 07:51:26,746 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-01-10 07:51:26,746 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-01-10 07:51:26,746 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-01-10 07:51:26,746 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-01-10 07:51:26,746 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-01-10 07:51:26,747 INFO L153 SettingsManager]: * sizeof long=4 [2025-01-10 07:51:26,747 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-01-10 07:51:26,747 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-01-10 07:51:26,747 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-01-10 07:51:26,747 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-01-10 07:51:26,747 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-01-10 07:51:26,747 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-01-10 07:51:26,747 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-01-10 07:51:26,747 INFO L153 SettingsManager]: * sizeof long double=12 [2025-01-10 07:51:26,747 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-01-10 07:51:26,747 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-01-10 07:51:26,748 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-01-10 07:51:26,748 INFO L153 SettingsManager]: * Use constant arrays=true [2025-01-10 07:51:26,748 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2025-01-10 07:51:26,748 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-01-10 07:51:26,748 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-01-10 07:51:26,748 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-01-10 07:51:26,748 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-01-10 07:51:26,748 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f [2025-01-10 07:51:27,074 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-01-10 07:51:27,080 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-01-10 07:51:27,081 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-01-10 07:51:27,082 INFO L270 PluginConnector]: Initializing CDTParser... [2025-01-10 07:51:27,082 INFO L274 PluginConnector]: CDTParser initialized [2025-01-10 07:51:27,083 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2025-01-10 07:51:28,340 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/c61bf476e/e51497f58d6f44ddbb617da2b7099e99/FLAG0ad72e3e5 [2025-01-10 07:51:28,605 INFO L384 CDTParser]: Found 1 translation units. [2025-01-10 07:51:28,609 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2025-01-10 07:51:28,619 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/c61bf476e/e51497f58d6f44ddbb617da2b7099e99/FLAG0ad72e3e5 [2025-01-10 07:51:28,928 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/c61bf476e/e51497f58d6f44ddbb617da2b7099e99 [2025-01-10 07:51:28,930 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-01-10 07:51:28,932 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-01-10 07:51:28,933 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-01-10 07:51:28,933 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-01-10 07:51:28,936 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-01-10 07:51:28,937 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:51:28" (1/1) ... [2025-01-10 07:51:28,937 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2aa32fba and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:28, skipping insertion in model container [2025-01-10 07:51:28,938 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:51:28" (1/1) ... [2025-01-10 07:51:28,969 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-01-10 07:51:29,117 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:51:29,125 INFO L200 MainTranslator]: Completed pre-run [2025-01-10 07:51:29,145 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:51:29,157 INFO L204 MainTranslator]: Completed translation [2025-01-10 07:51:29,157 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29 WrapperNode [2025-01-10 07:51:29,158 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-01-10 07:51:29,158 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-01-10 07:51:29,158 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-01-10 07:51:29,159 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-01-10 07:51:29,163 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29" (1/1) ... [2025-01-10 07:51:29,168 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29" (1/1) ... [2025-01-10 07:51:29,187 INFO L138 Inliner]: procedures = 29, calls = 32, calls flagged for inlining = 27, calls inlined = 29, statements flattened = 295 [2025-01-10 07:51:29,187 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-01-10 07:51:29,188 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-01-10 07:51:29,188 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-01-10 07:51:29,188 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-01-10 07:51:29,193 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29" (1/1) ... [2025-01-10 07:51:29,194 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29" (1/1) ... [2025-01-10 07:51:29,195 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29" (1/1) ... [2025-01-10 07:51:29,203 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-01-10 07:51:29,204 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29" (1/1) ... [2025-01-10 07:51:29,204 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29" (1/1) ... [2025-01-10 07:51:29,207 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29" (1/1) ... [2025-01-10 07:51:29,208 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29" (1/1) ... [2025-01-10 07:51:29,211 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29" (1/1) ... [2025-01-10 07:51:29,212 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29" (1/1) ... [2025-01-10 07:51:29,213 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29" (1/1) ... [2025-01-10 07:51:29,214 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-01-10 07:51:29,215 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2025-01-10 07:51:29,215 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2025-01-10 07:51:29,215 INFO L274 PluginConnector]: RCFGBuilder initialized [2025-01-10 07:51:29,216 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29" (1/1) ... [2025-01-10 07:51:29,219 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:51:29,233 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:51:29,247 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:51:29,251 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-01-10 07:51:29,269 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-01-10 07:51:29,269 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-01-10 07:51:29,269 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-01-10 07:51:29,269 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-01-10 07:51:29,329 INFO L234 CfgBuilder]: Building ICFG [2025-01-10 07:51:29,330 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2025-01-10 07:51:29,540 INFO L? ?]: Removed 41 outVars from TransFormulas that were not future-live. [2025-01-10 07:51:29,540 INFO L283 CfgBuilder]: Performing block encoding [2025-01-10 07:51:29,547 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-01-10 07:51:29,548 INFO L312 CfgBuilder]: Removed 4 assume(true) statements. [2025-01-10 07:51:29,548 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:51:29 BoogieIcfgContainer [2025-01-10 07:51:29,548 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2025-01-10 07:51:29,549 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-01-10 07:51:29,549 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-01-10 07:51:29,553 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-01-10 07:51:29,553 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:51:29,554 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.01 07:51:28" (1/3) ... [2025-01-10 07:51:29,554 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@423b4eb9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:51:29, skipping insertion in model container [2025-01-10 07:51:29,554 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:51:29,555 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:29" (2/3) ... [2025-01-10 07:51:29,555 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@423b4eb9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:51:29, skipping insertion in model container [2025-01-10 07:51:29,555 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:51:29,555 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:51:29" (3/3) ... [2025-01-10 07:51:29,556 INFO L363 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-1.c [2025-01-10 07:51:29,588 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-01-10 07:51:29,588 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-01-10 07:51:29,588 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-01-10 07:51:29,588 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-01-10 07:51:29,588 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-01-10 07:51:29,589 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-01-10 07:51:29,589 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-01-10 07:51:29,589 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-01-10 07:51:29,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 101 states, 100 states have (on average 1.51) internal successors, (151), 100 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:29,605 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 65 [2025-01-10 07:51:29,606 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:29,606 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:29,613 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:29,614 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:29,614 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-01-10 07:51:29,614 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 101 states, 100 states have (on average 1.51) internal successors, (151), 100 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:29,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 65 [2025-01-10 07:51:29,617 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:29,617 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:29,618 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:29,618 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:29,624 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:29,624 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume !true;" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-01-10 07:51:29,628 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:29,631 INFO L85 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2025-01-10 07:51:29,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:29,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1918303277] [2025-01-10 07:51:29,637 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:29,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:29,702 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-01-10 07:51:29,716 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-01-10 07:51:29,717 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:29,717 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:29,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:29,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:29,775 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1918303277] [2025-01-10 07:51:29,775 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1918303277] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:29,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:29,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:29,777 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [349186896] [2025-01-10 07:51:29,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:29,779 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:29,780 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:29,780 INFO L85 PathProgramCache]: Analyzing trace with hash 1811575011, now seen corresponding path program 1 times [2025-01-10 07:51:29,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:29,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1833863568] [2025-01-10 07:51:29,780 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:29,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:29,786 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-01-10 07:51:29,786 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-01-10 07:51:29,787 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:29,787 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:29,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:29,795 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:29,795 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1833863568] [2025-01-10 07:51:29,795 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1833863568] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:29,795 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:29,795 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:29,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1462052639] [2025-01-10 07:51:29,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:29,796 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:29,797 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:29,814 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:29,814 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:29,816 INFO L87 Difference]: Start difference. First operand has 101 states, 100 states have (on average 1.51) internal successors, (151), 100 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:29,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:29,830 INFO L93 Difference]: Finished difference Result 97 states and 140 transitions. [2025-01-10 07:51:29,831 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 140 transitions. [2025-01-10 07:51:29,833 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-01-10 07:51:29,844 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 91 states and 134 transitions. [2025-01-10 07:51:29,845 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91 [2025-01-10 07:51:29,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91 [2025-01-10 07:51:29,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91 states and 134 transitions. [2025-01-10 07:51:29,847 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:29,847 INFO L218 hiAutomatonCegarLoop]: Abstraction has 91 states and 134 transitions. [2025-01-10 07:51:29,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states and 134 transitions. [2025-01-10 07:51:29,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 91. [2025-01-10 07:51:29,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 91 states have (on average 1.4725274725274726) internal successors, (134), 90 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:29,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 134 transitions. [2025-01-10 07:51:29,877 INFO L240 hiAutomatonCegarLoop]: Abstraction has 91 states and 134 transitions. [2025-01-10 07:51:29,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:29,880 INFO L432 stractBuchiCegarLoop]: Abstraction has 91 states and 134 transitions. [2025-01-10 07:51:29,880 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-01-10 07:51:29,880 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91 states and 134 transitions. [2025-01-10 07:51:29,881 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-01-10 07:51:29,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:29,881 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:29,882 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:29,882 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:29,883 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:29,883 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-01-10 07:51:29,883 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:29,883 INFO L85 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2025-01-10 07:51:29,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:29,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [316524223] [2025-01-10 07:51:29,884 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:29,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:29,890 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-01-10 07:51:29,904 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-01-10 07:51:29,904 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:29,904 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:29,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:29,973 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:29,973 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [316524223] [2025-01-10 07:51:29,973 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [316524223] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:29,973 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:29,973 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:29,973 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1593412587] [2025-01-10 07:51:29,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:29,973 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:29,974 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:29,974 INFO L85 PathProgramCache]: Analyzing trace with hash -1232562028, now seen corresponding path program 1 times [2025-01-10 07:51:29,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:29,974 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1100225989] [2025-01-10 07:51:29,974 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:29,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:29,980 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-01-10 07:51:29,985 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-01-10 07:51:29,986 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:29,986 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:30,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:30,037 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:30,037 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1100225989] [2025-01-10 07:51:30,037 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1100225989] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:30,037 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:30,037 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:30,038 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [537072242] [2025-01-10 07:51:30,038 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:30,038 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:30,038 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:30,038 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:30,038 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:30,039 INFO L87 Difference]: Start difference. First operand 91 states and 134 transitions. cyclomatic complexity: 44 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:30,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:30,120 INFO L93 Difference]: Finished difference Result 199 states and 287 transitions. [2025-01-10 07:51:30,120 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 199 states and 287 transitions. [2025-01-10 07:51:30,122 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 165 [2025-01-10 07:51:30,124 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 199 states to 199 states and 287 transitions. [2025-01-10 07:51:30,124 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 199 [2025-01-10 07:51:30,124 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 199 [2025-01-10 07:51:30,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 199 states and 287 transitions. [2025-01-10 07:51:30,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:30,125 INFO L218 hiAutomatonCegarLoop]: Abstraction has 199 states and 287 transitions. [2025-01-10 07:51:30,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states and 287 transitions. [2025-01-10 07:51:30,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 187. [2025-01-10 07:51:30,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 187 states, 187 states have (on average 1.4491978609625669) internal successors, (271), 186 states have internal predecessors, (271), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:30,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 271 transitions. [2025-01-10 07:51:30,140 INFO L240 hiAutomatonCegarLoop]: Abstraction has 187 states and 271 transitions. [2025-01-10 07:51:30,140 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:51:30,141 INFO L432 stractBuchiCegarLoop]: Abstraction has 187 states and 271 transitions. [2025-01-10 07:51:30,141 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-01-10 07:51:30,141 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 187 states and 271 transitions. [2025-01-10 07:51:30,143 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 155 [2025-01-10 07:51:30,143 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:30,143 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:30,143 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:30,143 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:30,143 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:30,144 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-01-10 07:51:30,144 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:30,144 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2025-01-10 07:51:30,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:30,144 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779299322] [2025-01-10 07:51:30,144 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:30,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:30,162 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-01-10 07:51:30,170 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-01-10 07:51:30,170 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:30,170 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:30,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:30,252 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:30,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779299322] [2025-01-10 07:51:30,252 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [779299322] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:30,252 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:30,252 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:30,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1525877253] [2025-01-10 07:51:30,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:30,253 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:30,253 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:30,253 INFO L85 PathProgramCache]: Analyzing trace with hash -1345948685, now seen corresponding path program 1 times [2025-01-10 07:51:30,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:30,253 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332568860] [2025-01-10 07:51:30,253 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:30,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:30,267 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-01-10 07:51:30,270 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-01-10 07:51:30,270 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:30,270 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:30,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:30,372 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:30,372 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1332568860] [2025-01-10 07:51:30,372 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1332568860] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:30,372 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:30,372 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:30,372 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473942669] [2025-01-10 07:51:30,372 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:30,373 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:30,373 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:30,373 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:30,373 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:30,373 INFO L87 Difference]: Start difference. First operand 187 states and 271 transitions. cyclomatic complexity: 86 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:30,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:30,461 INFO L93 Difference]: Finished difference Result 431 states and 603 transitions. [2025-01-10 07:51:30,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 431 states and 603 transitions. [2025-01-10 07:51:30,464 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 357 [2025-01-10 07:51:30,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 431 states to 431 states and 603 transitions. [2025-01-10 07:51:30,466 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 431 [2025-01-10 07:51:30,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 431 [2025-01-10 07:51:30,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 431 states and 603 transitions. [2025-01-10 07:51:30,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:30,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 431 states and 603 transitions. [2025-01-10 07:51:30,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431 states and 603 transitions. [2025-01-10 07:51:30,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431 to 431. [2025-01-10 07:51:30,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 431 states, 431 states have (on average 1.3990719257540603) internal successors, (603), 430 states have internal predecessors, (603), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:30,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 431 states to 431 states and 603 transitions. [2025-01-10 07:51:30,481 INFO L240 hiAutomatonCegarLoop]: Abstraction has 431 states and 603 transitions. [2025-01-10 07:51:30,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:51:30,482 INFO L432 stractBuchiCegarLoop]: Abstraction has 431 states and 603 transitions. [2025-01-10 07:51:30,482 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-01-10 07:51:30,482 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 431 states and 603 transitions. [2025-01-10 07:51:30,484 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 357 [2025-01-10 07:51:30,484 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:30,484 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:30,484 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:30,484 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:30,485 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:30,485 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-01-10 07:51:30,487 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:30,487 INFO L85 PathProgramCache]: Analyzing trace with hash 1964845233, now seen corresponding path program 1 times [2025-01-10 07:51:30,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:30,487 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1118099461] [2025-01-10 07:51:30,487 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:30,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:30,492 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-01-10 07:51:30,493 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-01-10 07:51:30,493 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:30,493 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:30,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:30,513 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:30,513 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1118099461] [2025-01-10 07:51:30,513 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1118099461] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:30,514 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:30,514 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:30,514 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [925390262] [2025-01-10 07:51:30,514 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:30,514 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:30,514 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:30,514 INFO L85 PathProgramCache]: Analyzing trace with hash -665890315, now seen corresponding path program 1 times [2025-01-10 07:51:30,514 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:30,514 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239924746] [2025-01-10 07:51:30,514 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:30,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:30,518 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-01-10 07:51:30,520 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-01-10 07:51:30,520 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:30,520 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:30,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:30,559 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:30,559 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239924746] [2025-01-10 07:51:30,559 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1239924746] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:30,559 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:30,559 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:30,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [664241051] [2025-01-10 07:51:30,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:30,559 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:30,560 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:30,560 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:30,560 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:30,560 INFO L87 Difference]: Start difference. First operand 431 states and 603 transitions. cyclomatic complexity: 176 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:30,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:30,602 INFO L93 Difference]: Finished difference Result 674 states and 924 transitions. [2025-01-10 07:51:30,603 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 674 states and 924 transitions. [2025-01-10 07:51:30,611 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 559 [2025-01-10 07:51:30,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 674 states to 674 states and 924 transitions. [2025-01-10 07:51:30,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 674 [2025-01-10 07:51:30,623 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 674 [2025-01-10 07:51:30,623 INFO L73 IsDeterministic]: Start isDeterministic. Operand 674 states and 924 transitions. [2025-01-10 07:51:30,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:30,625 INFO L218 hiAutomatonCegarLoop]: Abstraction has 674 states and 924 transitions. [2025-01-10 07:51:30,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 674 states and 924 transitions. [2025-01-10 07:51:30,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 674 to 492. [2025-01-10 07:51:30,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 492 states, 492 states have (on average 1.3719512195121952) internal successors, (675), 491 states have internal predecessors, (675), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:30,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 492 states to 492 states and 675 transitions. [2025-01-10 07:51:30,652 INFO L240 hiAutomatonCegarLoop]: Abstraction has 492 states and 675 transitions. [2025-01-10 07:51:30,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:30,653 INFO L432 stractBuchiCegarLoop]: Abstraction has 492 states and 675 transitions. [2025-01-10 07:51:30,653 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-01-10 07:51:30,653 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 492 states and 675 transitions. [2025-01-10 07:51:30,655 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 404 [2025-01-10 07:51:30,655 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:30,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:30,660 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:30,660 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:30,660 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:30,660 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-01-10 07:51:30,661 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:30,661 INFO L85 PathProgramCache]: Analyzing trace with hash -29299473, now seen corresponding path program 1 times [2025-01-10 07:51:30,661 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:30,661 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1171627713] [2025-01-10 07:51:30,661 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:30,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:30,666 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-01-10 07:51:30,673 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-01-10 07:51:30,673 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:30,673 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:30,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:30,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:30,711 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1171627713] [2025-01-10 07:51:30,711 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1171627713] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:30,711 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:30,711 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:30,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1069008602] [2025-01-10 07:51:30,711 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:30,711 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:30,711 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:30,711 INFO L85 PathProgramCache]: Analyzing trace with hash -1464413579, now seen corresponding path program 1 times [2025-01-10 07:51:30,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:30,711 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819754433] [2025-01-10 07:51:30,711 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:30,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:30,720 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-01-10 07:51:30,726 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-01-10 07:51:30,726 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:30,726 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:30,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:30,770 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:30,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1819754433] [2025-01-10 07:51:30,770 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1819754433] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:30,770 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:30,770 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:30,770 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1458110457] [2025-01-10 07:51:30,770 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:30,771 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:30,771 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:30,771 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:30,771 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:30,771 INFO L87 Difference]: Start difference. First operand 492 states and 675 transitions. cyclomatic complexity: 185 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:30,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:30,875 INFO L93 Difference]: Finished difference Result 718 states and 975 transitions. [2025-01-10 07:51:30,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 718 states and 975 transitions. [2025-01-10 07:51:30,883 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 595 [2025-01-10 07:51:30,891 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 718 states to 718 states and 975 transitions. [2025-01-10 07:51:30,891 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 718 [2025-01-10 07:51:30,891 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 718 [2025-01-10 07:51:30,892 INFO L73 IsDeterministic]: Start isDeterministic. Operand 718 states and 975 transitions. [2025-01-10 07:51:30,892 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:30,892 INFO L218 hiAutomatonCegarLoop]: Abstraction has 718 states and 975 transitions. [2025-01-10 07:51:30,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 718 states and 975 transitions. [2025-01-10 07:51:30,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 718 to 545. [2025-01-10 07:51:30,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 545 states, 545 states have (on average 1.3596330275229358) internal successors, (741), 544 states have internal predecessors, (741), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:30,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 545 states to 545 states and 741 transitions. [2025-01-10 07:51:30,918 INFO L240 hiAutomatonCegarLoop]: Abstraction has 545 states and 741 transitions. [2025-01-10 07:51:30,918 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:51:30,919 INFO L432 stractBuchiCegarLoop]: Abstraction has 545 states and 741 transitions. [2025-01-10 07:51:30,919 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-01-10 07:51:30,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 545 states and 741 transitions. [2025-01-10 07:51:30,921 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 440 [2025-01-10 07:51:30,921 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:30,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:30,921 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:30,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:30,926 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:30,927 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-01-10 07:51:30,927 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:30,927 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2025-01-10 07:51:30,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:30,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714412206] [2025-01-10 07:51:30,927 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:30,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:30,939 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-01-10 07:51:30,945 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-01-10 07:51:30,945 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:30,946 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:30,946 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:30,952 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-01-10 07:51:30,954 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-01-10 07:51:30,954 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:30,954 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:30,988 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:30,989 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:30,989 INFO L85 PathProgramCache]: Analyzing trace with hash -918368715, now seen corresponding path program 1 times [2025-01-10 07:51:30,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:30,989 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893856835] [2025-01-10 07:51:30,989 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:30,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:30,998 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-01-10 07:51:31,000 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-01-10 07:51:31,000 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,000 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:31,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:31,071 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:31,071 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1893856835] [2025-01-10 07:51:31,071 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1893856835] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:31,072 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:31,072 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:31,072 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162507430] [2025-01-10 07:51:31,072 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:31,072 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:31,072 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:31,072 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-10 07:51:31,072 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-10 07:51:31,072 INFO L87 Difference]: Start difference. First operand 545 states and 741 transitions. cyclomatic complexity: 198 Second operand has 5 states, 5 states have (on average 6.8) internal successors, (34), 5 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:31,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:31,161 INFO L93 Difference]: Finished difference Result 575 states and 771 transitions. [2025-01-10 07:51:31,161 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 575 states and 771 transitions. [2025-01-10 07:51:31,163 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 470 [2025-01-10 07:51:31,171 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 575 states to 575 states and 771 transitions. [2025-01-10 07:51:31,171 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 575 [2025-01-10 07:51:31,172 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 575 [2025-01-10 07:51:31,172 INFO L73 IsDeterministic]: Start isDeterministic. Operand 575 states and 771 transitions. [2025-01-10 07:51:31,178 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:31,178 INFO L218 hiAutomatonCegarLoop]: Abstraction has 575 states and 771 transitions. [2025-01-10 07:51:31,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 575 states and 771 transitions. [2025-01-10 07:51:31,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 575 to 563. [2025-01-10 07:51:31,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 563 states, 563 states have (on average 1.3481349911190053) internal successors, (759), 562 states have internal predecessors, (759), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:31,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 563 states and 759 transitions. [2025-01-10 07:51:31,223 INFO L240 hiAutomatonCegarLoop]: Abstraction has 563 states and 759 transitions. [2025-01-10 07:51:31,227 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:51:31,227 INFO L432 stractBuchiCegarLoop]: Abstraction has 563 states and 759 transitions. [2025-01-10 07:51:31,227 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-01-10 07:51:31,227 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 563 states and 759 transitions. [2025-01-10 07:51:31,229 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 458 [2025-01-10 07:51:31,229 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:31,229 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:31,230 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:31,230 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:31,230 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:31,230 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~p_dw_st~0);" "assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-01-10 07:51:31,230 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:31,233 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2025-01-10 07:51:31,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:31,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902804017] [2025-01-10 07:51:31,233 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:31,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:31,241 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 26 statements into 1 equivalence classes. [2025-01-10 07:51:31,248 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-01-10 07:51:31,248 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:31,249 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:31,249 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:31,250 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-01-10 07:51:31,256 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-01-10 07:51:31,256 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,256 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:31,266 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:31,267 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:31,267 INFO L85 PathProgramCache]: Analyzing trace with hash -750573371, now seen corresponding path program 1 times [2025-01-10 07:51:31,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:31,267 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483981741] [2025-01-10 07:51:31,267 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:31,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:31,276 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 35 statements into 1 equivalence classes. [2025-01-10 07:51:31,285 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 35 of 35 statements. [2025-01-10 07:51:31,285 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,285 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:31,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:31,392 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:31,392 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1483981741] [2025-01-10 07:51:31,392 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1483981741] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:31,392 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:31,392 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:31,392 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1852021968] [2025-01-10 07:51:31,392 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:31,392 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:31,392 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:31,393 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-10 07:51:31,393 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-10 07:51:31,393 INFO L87 Difference]: Start difference. First operand 563 states and 759 transitions. cyclomatic complexity: 198 Second operand has 5 states, 5 states have (on average 7.0) internal successors, (35), 5 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:31,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:31,477 INFO L93 Difference]: Finished difference Result 575 states and 759 transitions. [2025-01-10 07:51:31,477 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 575 states and 759 transitions. [2025-01-10 07:51:31,483 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 470 [2025-01-10 07:51:31,485 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 575 states to 575 states and 759 transitions. [2025-01-10 07:51:31,489 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 575 [2025-01-10 07:51:31,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 575 [2025-01-10 07:51:31,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 575 states and 759 transitions. [2025-01-10 07:51:31,491 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:31,491 INFO L218 hiAutomatonCegarLoop]: Abstraction has 575 states and 759 transitions. [2025-01-10 07:51:31,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 575 states and 759 transitions. [2025-01-10 07:51:31,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 575 to 575. [2025-01-10 07:51:31,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 575 states, 575 states have (on average 1.32) internal successors, (759), 574 states have internal predecessors, (759), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:31,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 575 states to 575 states and 759 transitions. [2025-01-10 07:51:31,515 INFO L240 hiAutomatonCegarLoop]: Abstraction has 575 states and 759 transitions. [2025-01-10 07:51:31,522 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:51:31,522 INFO L432 stractBuchiCegarLoop]: Abstraction has 575 states and 759 transitions. [2025-01-10 07:51:31,522 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-01-10 07:51:31,522 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 575 states and 759 transitions. [2025-01-10 07:51:31,524 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 470 [2025-01-10 07:51:31,524 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:31,524 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:31,525 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:31,525 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:31,525 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:31,525 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~p_dw_st~0);" "assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-01-10 07:51:31,525 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:31,525 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2025-01-10 07:51:31,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:31,527 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114916028] [2025-01-10 07:51:31,527 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:51:31,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:31,531 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 26 statements into 1 equivalence classes. [2025-01-10 07:51:31,533 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-01-10 07:51:31,535 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:51:31,535 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:31,535 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:31,536 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-01-10 07:51:31,537 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-01-10 07:51:31,537 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,537 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:31,542 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:31,542 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:31,542 INFO L85 PathProgramCache]: Analyzing trace with hash 1550249219, now seen corresponding path program 1 times [2025-01-10 07:51:31,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:31,542 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295735839] [2025-01-10 07:51:31,542 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:31,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:31,545 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 35 statements into 1 equivalence classes. [2025-01-10 07:51:31,546 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 35 of 35 statements. [2025-01-10 07:51:31,546 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,546 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:31,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:31,557 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:31,557 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295735839] [2025-01-10 07:51:31,558 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [295735839] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:31,558 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:31,558 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:31,558 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1331892688] [2025-01-10 07:51:31,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:31,558 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:31,558 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:31,558 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:31,558 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:31,558 INFO L87 Difference]: Start difference. First operand 575 states and 759 transitions. cyclomatic complexity: 186 Second operand has 3 states, 3 states have (on average 11.666666666666666) internal successors, (35), 3 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:31,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:31,581 INFO L93 Difference]: Finished difference Result 800 states and 1033 transitions. [2025-01-10 07:51:31,581 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 800 states and 1033 transitions. [2025-01-10 07:51:31,591 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 615 [2025-01-10 07:51:31,594 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 800 states to 800 states and 1033 transitions. [2025-01-10 07:51:31,594 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 800 [2025-01-10 07:51:31,595 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 800 [2025-01-10 07:51:31,595 INFO L73 IsDeterministic]: Start isDeterministic. Operand 800 states and 1033 transitions. [2025-01-10 07:51:31,596 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:31,596 INFO L218 hiAutomatonCegarLoop]: Abstraction has 800 states and 1033 transitions. [2025-01-10 07:51:31,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 800 states and 1033 transitions. [2025-01-10 07:51:31,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 800 to 800. [2025-01-10 07:51:31,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 800 states, 800 states have (on average 1.29125) internal successors, (1033), 799 states have internal predecessors, (1033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:31,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 800 states to 800 states and 1033 transitions. [2025-01-10 07:51:31,608 INFO L240 hiAutomatonCegarLoop]: Abstraction has 800 states and 1033 transitions. [2025-01-10 07:51:31,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:31,610 INFO L432 stractBuchiCegarLoop]: Abstraction has 800 states and 1033 transitions. [2025-01-10 07:51:31,611 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-01-10 07:51:31,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 800 states and 1033 transitions. [2025-01-10 07:51:31,613 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 615 [2025-01-10 07:51:31,613 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:31,613 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:31,614 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:31,614 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:31,614 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:31,614 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~p_dw_st~0);" "assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~p_dw_st~0);" "assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-01-10 07:51:31,614 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:31,614 INFO L85 PathProgramCache]: Analyzing trace with hash -1194945487, now seen corresponding path program 1 times [2025-01-10 07:51:31,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:31,614 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [394303694] [2025-01-10 07:51:31,614 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:31,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:31,617 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-01-10 07:51:31,618 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-01-10 07:51:31,619 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,619 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:31,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:31,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:31,632 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [394303694] [2025-01-10 07:51:31,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [394303694] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:31,632 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:31,632 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:31,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708325186] [2025-01-10 07:51:31,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:31,632 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:31,632 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:31,632 INFO L85 PathProgramCache]: Analyzing trace with hash 688541753, now seen corresponding path program 1 times [2025-01-10 07:51:31,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:31,632 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189504308] [2025-01-10 07:51:31,632 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:31,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:31,635 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-01-10 07:51:31,637 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-01-10 07:51:31,637 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,637 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:31,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:31,663 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:31,663 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189504308] [2025-01-10 07:51:31,663 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1189504308] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:31,663 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:31,663 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:31,663 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1656470379] [2025-01-10 07:51:31,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:31,663 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:31,663 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:31,663 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:31,663 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:31,663 INFO L87 Difference]: Start difference. First operand 800 states and 1033 transitions. cyclomatic complexity: 237 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:31,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:31,669 INFO L93 Difference]: Finished difference Result 722 states and 939 transitions. [2025-01-10 07:51:31,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 722 states and 939 transitions. [2025-01-10 07:51:31,672 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 615 [2025-01-10 07:51:31,674 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 722 states to 722 states and 939 transitions. [2025-01-10 07:51:31,674 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 722 [2025-01-10 07:51:31,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 722 [2025-01-10 07:51:31,675 INFO L73 IsDeterministic]: Start isDeterministic. Operand 722 states and 939 transitions. [2025-01-10 07:51:31,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:31,675 INFO L218 hiAutomatonCegarLoop]: Abstraction has 722 states and 939 transitions. [2025-01-10 07:51:31,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 722 states and 939 transitions. [2025-01-10 07:51:31,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 722 to 722. [2025-01-10 07:51:31,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 722 states, 722 states have (on average 1.3005540166204985) internal successors, (939), 721 states have internal predecessors, (939), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:31,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 722 states and 939 transitions. [2025-01-10 07:51:31,683 INFO L240 hiAutomatonCegarLoop]: Abstraction has 722 states and 939 transitions. [2025-01-10 07:51:31,683 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:31,684 INFO L432 stractBuchiCegarLoop]: Abstraction has 722 states and 939 transitions. [2025-01-10 07:51:31,684 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-01-10 07:51:31,684 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 722 states and 939 transitions. [2025-01-10 07:51:31,686 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 615 [2025-01-10 07:51:31,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:31,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:31,686 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:31,686 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:31,686 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" [2025-01-10 07:51:31,686 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume 0 != eval_~tmp___1~0#1;" "assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp~2#1);" "assume !(0 == ~c_dr_st~0);" [2025-01-10 07:51:31,687 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:31,687 INFO L85 PathProgramCache]: Analyzing trace with hash 1392540970, now seen corresponding path program 1 times [2025-01-10 07:51:31,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:31,687 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188792660] [2025-01-10 07:51:31,687 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:31,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:31,690 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:51:31,691 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:51:31,691 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,691 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:31,691 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:31,692 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:51:31,693 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:51:31,693 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,693 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:31,696 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:31,696 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:31,696 INFO L85 PathProgramCache]: Analyzing trace with hash 1351698447, now seen corresponding path program 1 times [2025-01-10 07:51:31,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:31,696 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1033749238] [2025-01-10 07:51:31,696 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:31,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:31,698 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-01-10 07:51:31,698 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-01-10 07:51:31,698 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,698 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:31,698 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:31,699 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-01-10 07:51:31,699 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-01-10 07:51:31,699 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,699 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:31,700 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:31,700 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:31,700 INFO L85 PathProgramCache]: Analyzing trace with hash -860189640, now seen corresponding path program 1 times [2025-01-10 07:51:31,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:31,700 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415887096] [2025-01-10 07:51:31,700 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:31,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:31,703 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 35 statements into 1 equivalence classes. [2025-01-10 07:51:31,704 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 35 of 35 statements. [2025-01-10 07:51:31,704 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,704 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:31,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:31,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:31,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [415887096] [2025-01-10 07:51:31,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [415887096] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:31,716 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:31,716 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:31,717 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408870709] [2025-01-10 07:51:31,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:31,749 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:31,750 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:31,750 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:31,750 INFO L87 Difference]: Start difference. First operand 722 states and 939 transitions. cyclomatic complexity: 221 Second operand has 3 states, 2 states have (on average 17.5) internal successors, (35), 3 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:31,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:31,775 INFO L93 Difference]: Finished difference Result 794 states and 1031 transitions. [2025-01-10 07:51:31,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 794 states and 1031 transitions. [2025-01-10 07:51:31,779 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 687 [2025-01-10 07:51:31,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 794 states to 794 states and 1031 transitions. [2025-01-10 07:51:31,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 794 [2025-01-10 07:51:31,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 794 [2025-01-10 07:51:31,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 794 states and 1031 transitions. [2025-01-10 07:51:31,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:31,783 INFO L218 hiAutomatonCegarLoop]: Abstraction has 794 states and 1031 transitions. [2025-01-10 07:51:31,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 794 states and 1031 transitions. [2025-01-10 07:51:31,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 794 to 776. [2025-01-10 07:51:31,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.3028350515463918) internal successors, (1011), 775 states have internal predecessors, (1011), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:31,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1011 transitions. [2025-01-10 07:51:31,821 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1011 transitions. [2025-01-10 07:51:31,821 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:31,822 INFO L432 stractBuchiCegarLoop]: Abstraction has 776 states and 1011 transitions. [2025-01-10 07:51:31,822 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-01-10 07:51:31,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1011 transitions. [2025-01-10 07:51:31,824 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 669 [2025-01-10 07:51:31,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:31,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:31,825 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:31,825 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:31,826 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" [2025-01-10 07:51:31,826 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume 0 != eval_~tmp___1~0#1;" "assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp~2#1);" "assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1;" "assume !(0 != eval_~tmp___0~2#1);" [2025-01-10 07:51:31,826 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:31,826 INFO L85 PathProgramCache]: Analyzing trace with hash 1392540970, now seen corresponding path program 2 times [2025-01-10 07:51:31,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:31,826 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [341622803] [2025-01-10 07:51:31,826 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:31,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:31,830 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:51:31,832 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:51:31,832 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:31,832 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:31,832 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:31,835 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:51:31,836 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:51:31,836 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,836 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:31,841 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:31,842 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:31,842 INFO L85 PathProgramCache]: Analyzing trace with hash -1047022718, now seen corresponding path program 1 times [2025-01-10 07:51:31,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:31,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999370605] [2025-01-10 07:51:31,842 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:31,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:31,846 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-01-10 07:51:31,847 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-01-10 07:51:31,847 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,847 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:31,847 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:31,848 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-01-10 07:51:31,849 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-01-10 07:51:31,849 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,849 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:31,850 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:31,850 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:31,850 INFO L85 PathProgramCache]: Analyzing trace with hash -896076679, now seen corresponding path program 1 times [2025-01-10 07:51:31,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:31,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159487967] [2025-01-10 07:51:31,850 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:31,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:31,856 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-01-10 07:51:31,857 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-01-10 07:51:31,857 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,857 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:31,857 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:31,859 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-01-10 07:51:31,860 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-01-10 07:51:31,861 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:31,861 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:31,864 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:32,356 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:51:32,359 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:51:32,359 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:32,359 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:32,359 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:32,364 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:51:32,367 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:51:32,367 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:32,367 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:32,422 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 10.01 07:51:32 BoogieIcfgContainer [2025-01-10 07:51:32,423 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-01-10 07:51:32,423 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-01-10 07:51:32,423 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-01-10 07:51:32,423 INFO L274 PluginConnector]: Witness Printer initialized [2025-01-10 07:51:32,424 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:51:29" (3/4) ... [2025-01-10 07:51:32,425 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-01-10 07:51:32,485 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-01-10 07:51:32,486 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-01-10 07:51:32,486 INFO L158 Benchmark]: Toolchain (without parser) took 3554.51ms. Allocated memory is still 167.8MB. Free memory was 132.4MB in the beginning and 117.6MB in the end (delta: 14.9MB). Peak memory consumption was 11.3MB. Max. memory is 16.1GB. [2025-01-10 07:51:32,486 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 201.3MB. Free memory is still 127.3MB. There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:51:32,486 INFO L158 Benchmark]: CACSL2BoogieTranslator took 225.25ms. Allocated memory is still 167.8MB. Free memory was 132.4MB in the beginning and 119.3MB in the end (delta: 13.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-01-10 07:51:32,486 INFO L158 Benchmark]: Boogie Procedure Inliner took 28.93ms. Allocated memory is still 167.8MB. Free memory was 119.3MB in the beginning and 117.6MB in the end (delta: 1.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-01-10 07:51:32,487 INFO L158 Benchmark]: Boogie Preprocessor took 26.51ms. Allocated memory is still 167.8MB. Free memory was 117.6MB in the beginning and 115.9MB in the end (delta: 1.7MB). There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:51:32,487 INFO L158 Benchmark]: RCFGBuilder took 333.27ms. Allocated memory is still 167.8MB. Free memory was 115.5MB in the beginning and 96.3MB in the end (delta: 19.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-01-10 07:51:32,487 INFO L158 Benchmark]: BuchiAutomizer took 2873.93ms. Allocated memory is still 167.8MB. Free memory was 96.3MB in the beginning and 121.9MB in the end (delta: -25.5MB). There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:51:32,491 INFO L158 Benchmark]: Witness Printer took 62.39ms. Allocated memory is still 167.8MB. Free memory was 121.9MB in the beginning and 117.6MB in the end (delta: 4.3MB). There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:51:32,492 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 201.3MB. Free memory is still 127.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 225.25ms. Allocated memory is still 167.8MB. Free memory was 132.4MB in the beginning and 119.3MB in the end (delta: 13.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 28.93ms. Allocated memory is still 167.8MB. Free memory was 119.3MB in the beginning and 117.6MB in the end (delta: 1.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 26.51ms. Allocated memory is still 167.8MB. Free memory was 117.6MB in the beginning and 115.9MB in the end (delta: 1.7MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 333.27ms. Allocated memory is still 167.8MB. Free memory was 115.5MB in the beginning and 96.3MB in the end (delta: 19.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 2873.93ms. Allocated memory is still 167.8MB. Free memory was 96.3MB in the beginning and 121.9MB in the end (delta: -25.5MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 62.39ms. Allocated memory is still 167.8MB. Free memory was 121.9MB in the beginning and 117.6MB in the end (delta: 4.3MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 10 terminating modules (10 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.10 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 776 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.8s and 11 iterations. TraceHistogramMax:1. Analysis of lassos took 1.7s. Construction of modules took 0.3s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 0. Minimization of det autom 10. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 10 MinimizatonAttempts, 397 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1330 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1330 mSDsluCounter, 2772 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1405 mSDsCounter, 67 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 230 IncrementalHoareTripleChecker+Invalid, 297 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 67 mSolverCounterUnsat, 1367 mSDtfsCounter, 230 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 1]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 1]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-01-10 07:51:32,506 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)