./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pipeline.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 551b0097 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pipeline.cil-1.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 79bbe68806c3ba3852cd8c209d4ce80dca551636a131cc65daaf97524d927c63 --- Real Ultimate output --- This is Ultimate 0.3.0-?-551b009-m [2025-01-10 07:51:36,196 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-01-10 07:51:36,257 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-01-10 07:51:36,263 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-01-10 07:51:36,263 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-01-10 07:51:36,286 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-01-10 07:51:36,287 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-01-10 07:51:36,287 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-01-10 07:51:36,287 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-01-10 07:51:36,287 INFO L153 SettingsManager]: * Use memory slicer=true [2025-01-10 07:51:36,288 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-01-10 07:51:36,288 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-01-10 07:51:36,288 INFO L153 SettingsManager]: * Use SBE=true [2025-01-10 07:51:36,288 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-01-10 07:51:36,288 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-01-10 07:51:36,288 INFO L153 SettingsManager]: * Use old map elimination=false [2025-01-10 07:51:36,288 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-01-10 07:51:36,289 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-01-10 07:51:36,289 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-01-10 07:51:36,289 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-01-10 07:51:36,289 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-01-10 07:51:36,289 INFO L153 SettingsManager]: * sizeof long=4 [2025-01-10 07:51:36,289 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-01-10 07:51:36,289 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-01-10 07:51:36,289 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-01-10 07:51:36,290 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-01-10 07:51:36,290 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-01-10 07:51:36,290 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-01-10 07:51:36,290 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-01-10 07:51:36,290 INFO L153 SettingsManager]: * sizeof long double=12 [2025-01-10 07:51:36,290 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-01-10 07:51:36,290 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-01-10 07:51:36,290 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-01-10 07:51:36,290 INFO L153 SettingsManager]: * Use constant arrays=true [2025-01-10 07:51:36,291 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2025-01-10 07:51:36,291 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-01-10 07:51:36,291 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-01-10 07:51:36,291 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-01-10 07:51:36,291 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-01-10 07:51:36,291 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 79bbe68806c3ba3852cd8c209d4ce80dca551636a131cc65daaf97524d927c63 [2025-01-10 07:51:36,567 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-01-10 07:51:36,578 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-01-10 07:51:36,581 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-01-10 07:51:36,583 INFO L270 PluginConnector]: Initializing CDTParser... [2025-01-10 07:51:36,584 INFO L274 PluginConnector]: CDTParser initialized [2025-01-10 07:51:36,586 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pipeline.cil-1.c [2025-01-10 07:51:37,868 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/88005787f/e9c3cdded876449b9464ff22da42052b/FLAG2304e0324 [2025-01-10 07:51:38,158 INFO L384 CDTParser]: Found 1 translation units. [2025-01-10 07:51:38,162 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/pipeline.cil-1.c [2025-01-10 07:51:38,178 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/88005787f/e9c3cdded876449b9464ff22da42052b/FLAG2304e0324 [2025-01-10 07:51:38,195 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/88005787f/e9c3cdded876449b9464ff22da42052b [2025-01-10 07:51:38,198 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-01-10 07:51:38,199 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-01-10 07:51:38,201 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-01-10 07:51:38,202 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-01-10 07:51:38,206 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-01-10 07:51:38,206 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,207 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@526bdd33 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38, skipping insertion in model container [2025-01-10 07:51:38,207 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,238 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-01-10 07:51:38,458 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:51:38,473 INFO L200 MainTranslator]: Completed pre-run [2025-01-10 07:51:38,534 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:51:38,553 INFO L204 MainTranslator]: Completed translation [2025-01-10 07:51:38,555 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38 WrapperNode [2025-01-10 07:51:38,556 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-01-10 07:51:38,557 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-01-10 07:51:38,557 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-01-10 07:51:38,557 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-01-10 07:51:38,562 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,575 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,628 INFO L138 Inliner]: procedures = 20, calls = 18, calls flagged for inlining = 13, calls inlined = 25, statements flattened = 1031 [2025-01-10 07:51:38,628 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-01-10 07:51:38,629 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-01-10 07:51:38,629 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-01-10 07:51:38,629 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-01-10 07:51:38,643 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,643 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,648 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,682 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-01-10 07:51:38,683 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,683 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,702 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,707 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,737 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,740 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,743 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,748 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-01-10 07:51:38,749 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2025-01-10 07:51:38,749 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2025-01-10 07:51:38,749 INFO L274 PluginConnector]: RCFGBuilder initialized [2025-01-10 07:51:38,750 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,759 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:51:38,772 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:51:38,785 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:51:38,787 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-01-10 07:51:38,810 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-01-10 07:51:38,810 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-01-10 07:51:38,810 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-01-10 07:51:38,810 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-01-10 07:51:38,906 INFO L234 CfgBuilder]: Building ICFG [2025-01-10 07:51:38,908 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2025-01-10 07:51:40,033 INFO L? ?]: Removed 76 outVars from TransFormulas that were not future-live. [2025-01-10 07:51:40,034 INFO L283 CfgBuilder]: Performing block encoding [2025-01-10 07:51:40,056 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-01-10 07:51:40,056 INFO L312 CfgBuilder]: Removed 7 assume(true) statements. [2025-01-10 07:51:40,056 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:51:40 BoogieIcfgContainer [2025-01-10 07:51:40,057 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2025-01-10 07:51:40,057 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-01-10 07:51:40,058 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-01-10 07:51:40,062 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-01-10 07:51:40,063 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:51:40,063 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.01 07:51:38" (1/3) ... [2025-01-10 07:51:40,064 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@392d668e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:51:40, skipping insertion in model container [2025-01-10 07:51:40,064 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:51:40,064 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (2/3) ... [2025-01-10 07:51:40,064 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@392d668e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:51:40, skipping insertion in model container [2025-01-10 07:51:40,065 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:51:40,065 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:51:40" (3/3) ... [2025-01-10 07:51:40,068 INFO L363 chiAutomizerObserver]: Analyzing ICFG pipeline.cil-1.c [2025-01-10 07:51:40,119 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-01-10 07:51:40,120 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-01-10 07:51:40,120 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-01-10 07:51:40,120 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-01-10 07:51:40,120 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-01-10 07:51:40,121 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-01-10 07:51:40,121 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-01-10 07:51:40,121 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-01-10 07:51:40,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 416 states, 415 states have (on average 1.8096385542168674) internal successors, (751), 415 states have internal predecessors, (751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:40,163 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 354 [2025-01-10 07:51:40,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:40,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:40,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:40,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:40,174 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-01-10 07:51:40,177 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 416 states, 415 states have (on average 1.8096385542168674) internal successors, (751), 415 states have internal predecessors, (751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:40,187 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 354 [2025-01-10 07:51:40,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:40,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:40,188 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:40,188 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:40,195 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume 1 == ~S2_presdbl_i~0;~S2_presdbl_st~0 := 0;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:40,196 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !true;" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1;" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2;" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-01-10 07:51:40,201 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:40,201 INFO L85 PathProgramCache]: Analyzing trace with hash 1291793407, now seen corresponding path program 1 times [2025-01-10 07:51:40,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:40,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677328861] [2025-01-10 07:51:40,208 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:40,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:40,278 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:40,314 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:40,314 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:40,314 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:40,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:40,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:40,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1677328861] [2025-01-10 07:51:40,562 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1677328861] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:40,563 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:40,563 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:40,564 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1675848336] [2025-01-10 07:51:40,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:40,568 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:40,571 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:40,571 INFO L85 PathProgramCache]: Analyzing trace with hash 1416441316, now seen corresponding path program 1 times [2025-01-10 07:51:40,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:40,571 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332081736] [2025-01-10 07:51:40,571 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:40,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:40,585 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-01-10 07:51:40,586 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-01-10 07:51:40,586 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:40,586 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:40,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:40,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:40,607 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [332081736] [2025-01-10 07:51:40,607 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [332081736] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:40,607 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:40,607 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:40,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1820322046] [2025-01-10 07:51:40,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:40,608 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:40,615 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:40,640 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-01-10 07:51:40,641 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-01-10 07:51:40,643 INFO L87 Difference]: Start difference. First operand has 416 states, 415 states have (on average 1.8096385542168674) internal successors, (751), 415 states have internal predecessors, (751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 19.0) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:40,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:40,673 INFO L93 Difference]: Finished difference Result 410 states and 738 transitions. [2025-01-10 07:51:40,674 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 410 states and 738 transitions. [2025-01-10 07:51:40,678 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 351 [2025-01-10 07:51:40,690 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 410 states to 409 states and 737 transitions. [2025-01-10 07:51:40,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 409 [2025-01-10 07:51:40,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 409 [2025-01-10 07:51:40,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 409 states and 737 transitions. [2025-01-10 07:51:40,698 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:40,698 INFO L218 hiAutomatonCegarLoop]: Abstraction has 409 states and 737 transitions. [2025-01-10 07:51:40,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 409 states and 737 transitions. [2025-01-10 07:51:40,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 409 to 409. [2025-01-10 07:51:40,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 409 states, 409 states have (on average 1.8019559902200488) internal successors, (737), 408 states have internal predecessors, (737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:40,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 409 states and 737 transitions. [2025-01-10 07:51:40,743 INFO L240 hiAutomatonCegarLoop]: Abstraction has 409 states and 737 transitions. [2025-01-10 07:51:40,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-01-10 07:51:40,748 INFO L432 stractBuchiCegarLoop]: Abstraction has 409 states and 737 transitions. [2025-01-10 07:51:40,748 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-01-10 07:51:40,748 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 409 states and 737 transitions. [2025-01-10 07:51:40,751 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 351 [2025-01-10 07:51:40,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:40,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:40,752 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:40,752 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:40,753 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume 1 == ~S2_presdbl_i~0;~S2_presdbl_st~0 := 0;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:40,753 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1;" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2;" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-01-10 07:51:40,753 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:40,754 INFO L85 PathProgramCache]: Analyzing trace with hash 1291793407, now seen corresponding path program 2 times [2025-01-10 07:51:40,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:40,754 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862438209] [2025-01-10 07:51:40,754 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:40,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:40,763 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:40,770 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:40,770 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:40,770 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:40,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:40,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:40,866 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1862438209] [2025-01-10 07:51:40,866 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1862438209] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:40,866 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:40,866 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:40,866 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [506452240] [2025-01-10 07:51:40,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:40,867 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:40,867 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:40,867 INFO L85 PathProgramCache]: Analyzing trace with hash -539256943, now seen corresponding path program 1 times [2025-01-10 07:51:40,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:40,867 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1233873978] [2025-01-10 07:51:40,867 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:40,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:40,875 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-01-10 07:51:40,878 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-01-10 07:51:40,878 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:40,878 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:40,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:40,942 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:40,942 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1233873978] [2025-01-10 07:51:40,942 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1233873978] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:40,942 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:40,942 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:40,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [68481097] [2025-01-10 07:51:40,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:40,943 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:40,943 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:40,943 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:40,943 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:40,944 INFO L87 Difference]: Start difference. First operand 409 states and 737 transitions. cyclomatic complexity: 330 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:41,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:41,088 INFO L93 Difference]: Finished difference Result 746 states and 1338 transitions. [2025-01-10 07:51:41,088 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 746 states and 1338 transitions. [2025-01-10 07:51:41,094 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 689 [2025-01-10 07:51:41,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 746 states to 746 states and 1338 transitions. [2025-01-10 07:51:41,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2025-01-10 07:51:41,106 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2025-01-10 07:51:41,106 INFO L73 IsDeterministic]: Start isDeterministic. Operand 746 states and 1338 transitions. [2025-01-10 07:51:41,113 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:41,113 INFO L218 hiAutomatonCegarLoop]: Abstraction has 746 states and 1338 transitions. [2025-01-10 07:51:41,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 746 states and 1338 transitions. [2025-01-10 07:51:41,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 746 to 746. [2025-01-10 07:51:41,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 746 states, 746 states have (on average 1.7935656836461127) internal successors, (1338), 745 states have internal predecessors, (1338), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:41,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 746 states to 746 states and 1338 transitions. [2025-01-10 07:51:41,152 INFO L240 hiAutomatonCegarLoop]: Abstraction has 746 states and 1338 transitions. [2025-01-10 07:51:41,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:51:41,155 INFO L432 stractBuchiCegarLoop]: Abstraction has 746 states and 1338 transitions. [2025-01-10 07:51:41,155 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-01-10 07:51:41,155 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 746 states and 1338 transitions. [2025-01-10 07:51:41,159 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 689 [2025-01-10 07:51:41,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:41,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:41,161 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:41,163 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:41,163 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:41,164 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1;" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2;" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-01-10 07:51:41,164 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:41,164 INFO L85 PathProgramCache]: Analyzing trace with hash 782320317, now seen corresponding path program 1 times [2025-01-10 07:51:41,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:41,165 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185119131] [2025-01-10 07:51:41,165 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:41,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:41,173 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:41,181 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:41,181 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,181 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:41,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:41,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:41,253 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [185119131] [2025-01-10 07:51:41,253 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [185119131] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:41,253 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:41,254 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:41,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1785107265] [2025-01-10 07:51:41,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:41,254 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:41,254 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:41,254 INFO L85 PathProgramCache]: Analyzing trace with hash -539256943, now seen corresponding path program 2 times [2025-01-10 07:51:41,255 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:41,255 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [632067861] [2025-01-10 07:51:41,255 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:41,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:41,264 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 42 statements into 1 equivalence classes. [2025-01-10 07:51:41,266 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-01-10 07:51:41,267 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:41,267 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:41,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:41,292 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:41,292 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [632067861] [2025-01-10 07:51:41,292 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [632067861] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:41,293 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:41,293 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:41,293 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [143458483] [2025-01-10 07:51:41,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:41,293 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:41,293 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:41,294 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:41,294 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:41,294 INFO L87 Difference]: Start difference. First operand 746 states and 1338 transitions. cyclomatic complexity: 596 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:41,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:41,528 INFO L93 Difference]: Finished difference Result 1641 states and 2909 transitions. [2025-01-10 07:51:41,529 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1641 states and 2909 transitions. [2025-01-10 07:51:41,543 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1544 [2025-01-10 07:51:41,555 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1641 states to 1641 states and 2909 transitions. [2025-01-10 07:51:41,555 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1641 [2025-01-10 07:51:41,557 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1641 [2025-01-10 07:51:41,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1641 states and 2909 transitions. [2025-01-10 07:51:41,560 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:41,560 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1641 states and 2909 transitions. [2025-01-10 07:51:41,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1641 states and 2909 transitions. [2025-01-10 07:51:41,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1641 to 1641. [2025-01-10 07:51:41,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1641 states, 1641 states have (on average 1.7726995734308348) internal successors, (2909), 1640 states have internal predecessors, (2909), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:41,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1641 states to 1641 states and 2909 transitions. [2025-01-10 07:51:41,603 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1641 states and 2909 transitions. [2025-01-10 07:51:41,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:51:41,604 INFO L432 stractBuchiCegarLoop]: Abstraction has 1641 states and 2909 transitions. [2025-01-10 07:51:41,604 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-01-10 07:51:41,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1641 states and 2909 transitions. [2025-01-10 07:51:41,615 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1544 [2025-01-10 07:51:41,615 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:41,615 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:41,619 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:41,619 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:41,619 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2;" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:41,619 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1;" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2;" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-01-10 07:51:41,620 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:41,620 INFO L85 PathProgramCache]: Analyzing trace with hash 357698877, now seen corresponding path program 1 times [2025-01-10 07:51:41,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:41,620 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592195320] [2025-01-10 07:51:41,620 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:41,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:41,634 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:41,643 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:41,643 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,643 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:41,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:41,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:41,675 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1592195320] [2025-01-10 07:51:41,675 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1592195320] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:41,675 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:41,675 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:41,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1733556934] [2025-01-10 07:51:41,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:41,676 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:41,676 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:41,676 INFO L85 PathProgramCache]: Analyzing trace with hash -116555117, now seen corresponding path program 1 times [2025-01-10 07:51:41,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:41,676 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255662171] [2025-01-10 07:51:41,676 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:41,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:41,682 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-01-10 07:51:41,684 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-01-10 07:51:41,684 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,684 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:41,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:41,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:41,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1255662171] [2025-01-10 07:51:41,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1255662171] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:41,721 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:41,721 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:41,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1218249753] [2025-01-10 07:51:41,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:41,722 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:41,723 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:41,723 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:41,723 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:41,723 INFO L87 Difference]: Start difference. First operand 1641 states and 2909 transitions. cyclomatic complexity: 1276 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:41,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:41,941 INFO L93 Difference]: Finished difference Result 1971 states and 3437 transitions. [2025-01-10 07:51:41,941 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1971 states and 3437 transitions. [2025-01-10 07:51:41,954 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1844 [2025-01-10 07:51:41,966 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1971 states to 1971 states and 3437 transitions. [2025-01-10 07:51:41,966 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1971 [2025-01-10 07:51:41,968 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1971 [2025-01-10 07:51:41,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1971 states and 3437 transitions. [2025-01-10 07:51:41,971 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:41,972 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1971 states and 3437 transitions. [2025-01-10 07:51:41,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1971 states and 3437 transitions. [2025-01-10 07:51:41,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1971 to 1971. [2025-01-10 07:51:42,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1971 states, 1971 states have (on average 1.7437848807711822) internal successors, (3437), 1970 states have internal predecessors, (3437), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:42,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1971 states to 1971 states and 3437 transitions. [2025-01-10 07:51:42,011 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1971 states and 3437 transitions. [2025-01-10 07:51:42,011 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:42,012 INFO L432 stractBuchiCegarLoop]: Abstraction has 1971 states and 3437 transitions. [2025-01-10 07:51:42,012 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-01-10 07:51:42,012 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1971 states and 3437 transitions. [2025-01-10 07:51:42,022 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1844 [2025-01-10 07:51:42,023 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:42,023 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:42,024 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:42,024 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:42,024 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2;" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:42,024 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1;" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2;" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-01-10 07:51:42,024 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:42,025 INFO L85 PathProgramCache]: Analyzing trace with hash 787031863, now seen corresponding path program 1 times [2025-01-10 07:51:42,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:42,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541585176] [2025-01-10 07:51:42,025 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:42,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:42,030 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:42,034 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:42,034 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:42,034 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:42,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:42,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:42,089 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541585176] [2025-01-10 07:51:42,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1541585176] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:42,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:42,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:42,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [734726283] [2025-01-10 07:51:42,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:42,089 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:42,089 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:42,089 INFO L85 PathProgramCache]: Analyzing trace with hash -1715106345, now seen corresponding path program 1 times [2025-01-10 07:51:42,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:42,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [82532489] [2025-01-10 07:51:42,090 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:42,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:42,095 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-01-10 07:51:42,097 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-01-10 07:51:42,097 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:42,097 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:42,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:42,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:42,115 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [82532489] [2025-01-10 07:51:42,115 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [82532489] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:42,115 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:42,115 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:42,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1085822047] [2025-01-10 07:51:42,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:42,115 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:42,116 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:42,116 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:42,116 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:42,116 INFO L87 Difference]: Start difference. First operand 1971 states and 3437 transitions. cyclomatic complexity: 1474 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:42,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:42,429 INFO L93 Difference]: Finished difference Result 3959 states and 6758 transitions. [2025-01-10 07:51:42,429 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3959 states and 6758 transitions. [2025-01-10 07:51:42,474 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3706 [2025-01-10 07:51:42,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3959 states to 3959 states and 6758 transitions. [2025-01-10 07:51:42,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3959 [2025-01-10 07:51:42,502 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3959 [2025-01-10 07:51:42,502 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3959 states and 6758 transitions. [2025-01-10 07:51:42,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:42,510 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3959 states and 6758 transitions. [2025-01-10 07:51:42,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3959 states and 6758 transitions. [2025-01-10 07:51:42,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3959 to 3929. [2025-01-10 07:51:42,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3929 states, 3929 states have (on average 1.7047594807839144) internal successors, (6698), 3928 states have internal predecessors, (6698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:42,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3929 states to 3929 states and 6698 transitions. [2025-01-10 07:51:42,585 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3929 states and 6698 transitions. [2025-01-10 07:51:42,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:51:42,586 INFO L432 stractBuchiCegarLoop]: Abstraction has 3929 states and 6698 transitions. [2025-01-10 07:51:42,586 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-01-10 07:51:42,586 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3929 states and 6698 transitions. [2025-01-10 07:51:42,610 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3706 [2025-01-10 07:51:42,610 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:42,610 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:42,612 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:42,614 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:42,614 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2;" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:42,614 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1;" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2;" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-01-10 07:51:42,615 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:42,615 INFO L85 PathProgramCache]: Analyzing trace with hash 615864315, now seen corresponding path program 1 times [2025-01-10 07:51:42,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:42,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876639902] [2025-01-10 07:51:42,615 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:42,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:42,622 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:42,625 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:42,625 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:42,625 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:42,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:42,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:42,675 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876639902] [2025-01-10 07:51:42,675 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1876639902] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:42,675 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:42,675 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:42,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1319441288] [2025-01-10 07:51:42,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:42,676 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:42,676 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:42,676 INFO L85 PathProgramCache]: Analyzing trace with hash -435352109, now seen corresponding path program 1 times [2025-01-10 07:51:42,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:42,677 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1786874107] [2025-01-10 07:51:42,677 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:42,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:42,684 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-01-10 07:51:42,685 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-01-10 07:51:42,685 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:42,685 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:42,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:42,707 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:42,707 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1786874107] [2025-01-10 07:51:42,707 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1786874107] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:42,707 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:42,707 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:42,707 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [227999390] [2025-01-10 07:51:42,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:42,707 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:42,708 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:42,708 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:42,708 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:42,708 INFO L87 Difference]: Start difference. First operand 3929 states and 6698 transitions. cyclomatic complexity: 2785 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:43,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:43,021 INFO L93 Difference]: Finished difference Result 4389 states and 7466 transitions. [2025-01-10 07:51:43,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4389 states and 7466 transitions. [2025-01-10 07:51:43,043 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4106 [2025-01-10 07:51:43,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4389 states to 4389 states and 7466 transitions. [2025-01-10 07:51:43,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4389 [2025-01-10 07:51:43,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4389 [2025-01-10 07:51:43,070 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4389 states and 7466 transitions. [2025-01-10 07:51:43,077 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:43,078 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4389 states and 7466 transitions. [2025-01-10 07:51:43,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4389 states and 7466 transitions. [2025-01-10 07:51:43,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4389 to 4359. [2025-01-10 07:51:43,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4359 states, 4359 states have (on average 1.6990135352144988) internal successors, (7406), 4358 states have internal predecessors, (7406), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:43,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4359 states to 4359 states and 7406 transitions. [2025-01-10 07:51:43,157 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4359 states and 7406 transitions. [2025-01-10 07:51:43,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:51:43,159 INFO L432 stractBuchiCegarLoop]: Abstraction has 4359 states and 7406 transitions. [2025-01-10 07:51:43,160 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-01-10 07:51:43,160 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4359 states and 7406 transitions. [2025-01-10 07:51:43,176 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4106 [2025-01-10 07:51:43,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:43,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:43,177 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:43,177 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:43,178 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:43,178 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-01-10 07:51:43,179 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:43,179 INFO L85 PathProgramCache]: Analyzing trace with hash 220990263, now seen corresponding path program 1 times [2025-01-10 07:51:43,179 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:43,179 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800375765] [2025-01-10 07:51:43,179 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:43,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:43,187 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:43,190 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:43,191 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:43,191 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:43,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:43,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:43,232 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [800375765] [2025-01-10 07:51:43,232 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [800375765] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:43,232 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:43,232 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:43,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1079245831] [2025-01-10 07:51:43,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:43,232 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:43,233 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:43,233 INFO L85 PathProgramCache]: Analyzing trace with hash 327752083, now seen corresponding path program 1 times [2025-01-10 07:51:43,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:43,234 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716760165] [2025-01-10 07:51:43,234 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:43,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:43,239 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-01-10 07:51:43,242 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-01-10 07:51:43,242 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:43,242 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:43,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:43,262 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:43,263 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [716760165] [2025-01-10 07:51:43,263 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [716760165] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:43,263 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:43,263 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:43,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2118838810] [2025-01-10 07:51:43,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:43,263 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:43,263 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:43,264 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:43,264 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:43,264 INFO L87 Difference]: Start difference. First operand 4359 states and 7406 transitions. cyclomatic complexity: 3063 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:43,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:43,529 INFO L93 Difference]: Finished difference Result 5511 states and 9255 transitions. [2025-01-10 07:51:43,529 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5511 states and 9255 transitions. [2025-01-10 07:51:43,563 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 5177 [2025-01-10 07:51:43,594 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5511 states to 5511 states and 9255 transitions. [2025-01-10 07:51:43,594 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5511 [2025-01-10 07:51:43,599 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5511 [2025-01-10 07:51:43,600 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5511 states and 9255 transitions. [2025-01-10 07:51:43,610 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:43,610 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5511 states and 9255 transitions. [2025-01-10 07:51:43,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5511 states and 9255 transitions. [2025-01-10 07:51:43,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5511 to 5074. [2025-01-10 07:51:43,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5074 states, 5074 states have (on average 1.6828931809223493) internal successors, (8539), 5073 states have internal predecessors, (8539), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:43,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5074 states to 5074 states and 8539 transitions. [2025-01-10 07:51:43,717 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5074 states and 8539 transitions. [2025-01-10 07:51:43,717 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:51:43,719 INFO L432 stractBuchiCegarLoop]: Abstraction has 5074 states and 8539 transitions. [2025-01-10 07:51:43,720 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-01-10 07:51:43,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5074 states and 8539 transitions. [2025-01-10 07:51:43,736 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4756 [2025-01-10 07:51:43,737 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:43,737 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:43,737 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:43,737 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:43,737 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:43,737 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-01-10 07:51:43,738 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:43,739 INFO L85 PathProgramCache]: Analyzing trace with hash 222837305, now seen corresponding path program 1 times [2025-01-10 07:51:43,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:43,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [376539897] [2025-01-10 07:51:43,739 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:43,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:43,746 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:43,749 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:43,750 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:43,750 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:43,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:43,796 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:43,796 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [376539897] [2025-01-10 07:51:43,797 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [376539897] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:43,797 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:43,797 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:43,797 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011964366] [2025-01-10 07:51:43,797 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:43,797 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:43,797 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:43,797 INFO L85 PathProgramCache]: Analyzing trace with hash 385010385, now seen corresponding path program 1 times [2025-01-10 07:51:43,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:43,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078904867] [2025-01-10 07:51:43,797 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:43,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:43,803 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-01-10 07:51:43,805 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-01-10 07:51:43,805 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:43,805 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:43,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:43,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:43,825 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1078904867] [2025-01-10 07:51:43,825 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1078904867] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:43,826 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:43,826 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:43,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [591858246] [2025-01-10 07:51:43,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:43,826 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:43,826 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:43,826 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:43,826 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:43,826 INFO L87 Difference]: Start difference. First operand 5074 states and 8539 transitions. cyclomatic complexity: 3481 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:44,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:44,176 INFO L93 Difference]: Finished difference Result 9355 states and 15412 transitions. [2025-01-10 07:51:44,176 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9355 states and 15412 transitions. [2025-01-10 07:51:44,210 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 8749 [2025-01-10 07:51:44,254 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9355 states to 9355 states and 15412 transitions. [2025-01-10 07:51:44,254 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9355 [2025-01-10 07:51:44,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9355 [2025-01-10 07:51:44,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9355 states and 15412 transitions. [2025-01-10 07:51:44,279 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:44,279 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9355 states and 15412 transitions. [2025-01-10 07:51:44,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9355 states and 15412 transitions. [2025-01-10 07:51:44,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9355 to 6922. [2025-01-10 07:51:44,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6922 states, 6922 states have (on average 1.6579023403640567) internal successors, (11476), 6921 states have internal predecessors, (11476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:44,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6922 states to 6922 states and 11476 transitions. [2025-01-10 07:51:44,402 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6922 states and 11476 transitions. [2025-01-10 07:51:44,403 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:51:44,406 INFO L432 stractBuchiCegarLoop]: Abstraction has 6922 states and 11476 transitions. [2025-01-10 07:51:44,406 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-01-10 07:51:44,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6922 states and 11476 transitions. [2025-01-10 07:51:44,429 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6436 [2025-01-10 07:51:44,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:44,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:44,430 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:44,430 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:44,430 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:44,430 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-01-10 07:51:44,431 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:44,431 INFO L85 PathProgramCache]: Analyzing trace with hash 1911781047, now seen corresponding path program 1 times [2025-01-10 07:51:44,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:44,431 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123814281] [2025-01-10 07:51:44,431 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:44,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:44,437 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:44,440 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:44,440 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:44,440 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:44,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:44,484 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:44,485 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123814281] [2025-01-10 07:51:44,485 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1123814281] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:44,485 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:44,485 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:44,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380617857] [2025-01-10 07:51:44,485 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:44,486 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:44,486 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:44,486 INFO L85 PathProgramCache]: Analyzing trace with hash -430791023, now seen corresponding path program 1 times [2025-01-10 07:51:44,486 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:44,486 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1809496502] [2025-01-10 07:51:44,486 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:44,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:44,491 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-01-10 07:51:44,493 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-01-10 07:51:44,493 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:44,493 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:44,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:44,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:44,509 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1809496502] [2025-01-10 07:51:44,509 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1809496502] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:44,509 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:44,509 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:44,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005692853] [2025-01-10 07:51:44,509 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:44,510 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:44,510 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:44,510 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:44,510 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:44,510 INFO L87 Difference]: Start difference. First operand 6922 states and 11476 transitions. cyclomatic complexity: 4570 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:44,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:44,693 INFO L93 Difference]: Finished difference Result 12727 states and 20931 transitions. [2025-01-10 07:51:44,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12727 states and 20931 transitions. [2025-01-10 07:51:44,745 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 11996 [2025-01-10 07:51:44,790 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12727 states to 12727 states and 20931 transitions. [2025-01-10 07:51:44,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12727 [2025-01-10 07:51:44,800 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12727 [2025-01-10 07:51:44,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12727 states and 20931 transitions. [2025-01-10 07:51:44,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:44,814 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12727 states and 20931 transitions. [2025-01-10 07:51:44,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12727 states and 20931 transitions. [2025-01-10 07:51:45,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12727 to 12727. [2025-01-10 07:51:45,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12727 states, 12727 states have (on average 1.644613813153139) internal successors, (20931), 12726 states have internal predecessors, (20931), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:45,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12727 states to 12727 states and 20931 transitions. [2025-01-10 07:51:45,084 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12727 states and 20931 transitions. [2025-01-10 07:51:45,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:51:45,085 INFO L432 stractBuchiCegarLoop]: Abstraction has 12727 states and 20931 transitions. [2025-01-10 07:51:45,085 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-01-10 07:51:45,086 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12727 states and 20931 transitions. [2025-01-10 07:51:45,122 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 11996 [2025-01-10 07:51:45,123 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:45,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:45,123 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:45,123 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:45,124 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:45,124 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-01-10 07:51:45,127 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:45,127 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 1 times [2025-01-10 07:51:45,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:45,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799190173] [2025-01-10 07:51:45,127 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:45,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:45,133 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:45,137 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:45,137 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:45,137 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:45,137 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:45,141 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:45,145 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:45,147 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:45,147 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:45,176 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:45,177 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:45,178 INFO L85 PathProgramCache]: Analyzing trace with hash -430791023, now seen corresponding path program 2 times [2025-01-10 07:51:45,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:45,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345060996] [2025-01-10 07:51:45,178 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:45,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:45,185 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 42 statements into 1 equivalence classes. [2025-01-10 07:51:45,187 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-01-10 07:51:45,188 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:45,188 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:45,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:45,202 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:45,202 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345060996] [2025-01-10 07:51:45,203 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1345060996] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:45,203 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:45,203 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:45,203 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2071001851] [2025-01-10 07:51:45,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:45,203 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:45,203 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:45,203 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:45,203 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:45,203 INFO L87 Difference]: Start difference. First operand 12727 states and 20931 transitions. cyclomatic complexity: 8236 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:45,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:45,357 INFO L93 Difference]: Finished difference Result 18183 states and 29342 transitions. [2025-01-10 07:51:45,357 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18183 states and 29342 transitions. [2025-01-10 07:51:45,448 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17006 [2025-01-10 07:51:45,509 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18183 states to 18183 states and 29342 transitions. [2025-01-10 07:51:45,510 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18183 [2025-01-10 07:51:45,525 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18183 [2025-01-10 07:51:45,525 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18183 states and 29342 transitions. [2025-01-10 07:51:45,542 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:45,542 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18183 states and 29342 transitions. [2025-01-10 07:51:45,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18183 states and 29342 transitions. [2025-01-10 07:51:45,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18183 to 18183. [2025-01-10 07:51:45,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18183 states, 18183 states have (on average 1.613705109167904) internal successors, (29342), 18182 states have internal predecessors, (29342), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:45,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18183 states to 18183 states and 29342 transitions. [2025-01-10 07:51:45,936 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18183 states and 29342 transitions. [2025-01-10 07:51:45,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:45,937 INFO L432 stractBuchiCegarLoop]: Abstraction has 18183 states and 29342 transitions. [2025-01-10 07:51:45,937 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-01-10 07:51:45,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18183 states and 29342 transitions. [2025-01-10 07:51:45,983 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17006 [2025-01-10 07:51:45,983 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:45,983 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:45,984 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:45,984 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:45,984 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:45,985 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-01-10 07:51:45,985 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:45,985 INFO L85 PathProgramCache]: Analyzing trace with hash -1770965193, now seen corresponding path program 1 times [2025-01-10 07:51:45,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:45,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326447829] [2025-01-10 07:51:45,985 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:45,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:45,991 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:45,995 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:45,995 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:45,995 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:46,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:46,036 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:46,036 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [326447829] [2025-01-10 07:51:46,037 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [326447829] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:46,037 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:46,037 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:46,037 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1456467801] [2025-01-10 07:51:46,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:46,037 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:46,037 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:46,038 INFO L85 PathProgramCache]: Analyzing trace with hash 378555603, now seen corresponding path program 1 times [2025-01-10 07:51:46,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:46,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378779997] [2025-01-10 07:51:46,038 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:46,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:46,042 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-01-10 07:51:46,044 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-01-10 07:51:46,044 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:46,044 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:46,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:46,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:46,060 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1378779997] [2025-01-10 07:51:46,061 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1378779997] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:46,061 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:46,061 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:46,061 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2052176494] [2025-01-10 07:51:46,061 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:46,061 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:46,061 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:46,061 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:46,061 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:46,062 INFO L87 Difference]: Start difference. First operand 18183 states and 29342 transitions. cyclomatic complexity: 11191 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:46,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:46,286 INFO L93 Difference]: Finished difference Result 33375 states and 53648 transitions. [2025-01-10 07:51:46,286 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33375 states and 53648 transitions. [2025-01-10 07:51:46,499 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31564 [2025-01-10 07:51:46,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33375 states to 33375 states and 53648 transitions. [2025-01-10 07:51:46,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33375 [2025-01-10 07:51:46,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33375 [2025-01-10 07:51:46,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33375 states and 53648 transitions. [2025-01-10 07:51:46,648 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:46,648 INFO L218 hiAutomatonCegarLoop]: Abstraction has 33375 states and 53648 transitions. [2025-01-10 07:51:46,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33375 states and 53648 transitions. [2025-01-10 07:51:47,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33375 to 33375. [2025-01-10 07:51:47,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33375 states, 33375 states have (on average 1.607430711610487) internal successors, (53648), 33374 states have internal predecessors, (53648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:47,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33375 states to 33375 states and 53648 transitions. [2025-01-10 07:51:47,354 INFO L240 hiAutomatonCegarLoop]: Abstraction has 33375 states and 53648 transitions. [2025-01-10 07:51:47,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:51:47,355 INFO L432 stractBuchiCegarLoop]: Abstraction has 33375 states and 53648 transitions. [2025-01-10 07:51:47,355 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-01-10 07:51:47,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33375 states and 53648 transitions. [2025-01-10 07:51:47,486 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31564 [2025-01-10 07:51:47,486 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:47,486 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:47,487 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:47,487 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:47,488 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:47,488 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-01-10 07:51:47,488 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:47,489 INFO L85 PathProgramCache]: Analyzing trace with hash -1552110475, now seen corresponding path program 1 times [2025-01-10 07:51:47,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:47,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992368685] [2025-01-10 07:51:47,489 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:47,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:47,497 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:47,503 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:47,503 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:47,503 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:47,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:47,554 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:47,554 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992368685] [2025-01-10 07:51:47,554 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [992368685] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:47,554 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:47,555 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:47,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [639066271] [2025-01-10 07:51:47,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:47,555 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:47,555 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:47,555 INFO L85 PathProgramCache]: Analyzing trace with hash 2058737939, now seen corresponding path program 1 times [2025-01-10 07:51:47,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:47,555 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11028757] [2025-01-10 07:51:47,555 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:47,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:47,560 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-01-10 07:51:47,562 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-01-10 07:51:47,562 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:47,562 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:47,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:47,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:47,581 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [11028757] [2025-01-10 07:51:47,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [11028757] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:47,582 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:47,582 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:47,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1488052746] [2025-01-10 07:51:47,582 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:47,582 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:47,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:47,582 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:47,582 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:47,583 INFO L87 Difference]: Start difference. First operand 33375 states and 53648 transitions. cyclomatic complexity: 20337 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:48,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:48,064 INFO L93 Difference]: Finished difference Result 34566 states and 54933 transitions. [2025-01-10 07:51:48,064 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34566 states and 54933 transitions. [2025-01-10 07:51:48,196 INFO L131 ngComponentsAnalysis]: Automaton has 66 accepting balls. 32644 [2025-01-10 07:51:48,294 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34566 states to 34566 states and 54933 transitions. [2025-01-10 07:51:48,294 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34566 [2025-01-10 07:51:48,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34566 [2025-01-10 07:51:48,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34566 states and 54933 transitions. [2025-01-10 07:51:48,341 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:48,341 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34566 states and 54933 transitions. [2025-01-10 07:51:48,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34566 states and 54933 transitions. [2025-01-10 07:51:48,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34566 to 33375. [2025-01-10 07:51:48,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33375 states, 33375 states have (on average 1.5896329588014981) internal successors, (53054), 33374 states have internal predecessors, (53054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:48,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33375 states to 33375 states and 53054 transitions. [2025-01-10 07:51:48,953 INFO L240 hiAutomatonCegarLoop]: Abstraction has 33375 states and 53054 transitions. [2025-01-10 07:51:48,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:51:48,955 INFO L432 stractBuchiCegarLoop]: Abstraction has 33375 states and 53054 transitions. [2025-01-10 07:51:48,955 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-01-10 07:51:48,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33375 states and 53054 transitions. [2025-01-10 07:51:49,041 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31564 [2025-01-10 07:51:49,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:49,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:49,042 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:49,042 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:49,042 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:49,042 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-01-10 07:51:49,043 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:49,043 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 2 times [2025-01-10 07:51:49,043 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:49,043 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640745123] [2025-01-10 07:51:49,043 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:49,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:49,050 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:49,053 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:49,054 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:49,054 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:49,054 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:49,056 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:49,059 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:49,060 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:49,060 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:49,068 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:49,069 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:49,069 INFO L85 PathProgramCache]: Analyzing trace with hash 2058737939, now seen corresponding path program 2 times [2025-01-10 07:51:49,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:49,070 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1958911180] [2025-01-10 07:51:49,070 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:49,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:49,074 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 42 statements into 1 equivalence classes. [2025-01-10 07:51:49,076 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-01-10 07:51:49,076 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:49,076 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:49,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:49,091 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:49,092 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1958911180] [2025-01-10 07:51:49,092 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1958911180] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:49,092 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:49,092 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:49,092 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [602183697] [2025-01-10 07:51:49,092 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:49,092 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:49,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:49,093 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:49,093 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:49,093 INFO L87 Difference]: Start difference. First operand 33375 states and 53054 transitions. cyclomatic complexity: 19743 Second operand has 3 states, 2 states have (on average 21.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:49,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:49,254 INFO L93 Difference]: Finished difference Result 45801 states and 71945 transitions. [2025-01-10 07:51:49,254 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45801 states and 71945 transitions. [2025-01-10 07:51:49,506 INFO L131 ngComponentsAnalysis]: Automaton has 72 accepting balls. 42630 [2025-01-10 07:51:49,608 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45801 states to 45801 states and 71945 transitions. [2025-01-10 07:51:49,608 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45801 [2025-01-10 07:51:49,644 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45801 [2025-01-10 07:51:49,644 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45801 states and 71945 transitions. [2025-01-10 07:51:49,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:49,675 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45801 states and 71945 transitions. [2025-01-10 07:51:49,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45801 states and 71945 transitions. [2025-01-10 07:51:50,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45801 to 45801. [2025-01-10 07:51:50,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45801 states, 45801 states have (on average 1.5708172310648238) internal successors, (71945), 45800 states have internal predecessors, (71945), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:50,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45801 states to 45801 states and 71945 transitions. [2025-01-10 07:51:50,306 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45801 states and 71945 transitions. [2025-01-10 07:51:50,306 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:50,308 INFO L432 stractBuchiCegarLoop]: Abstraction has 45801 states and 71945 transitions. [2025-01-10 07:51:50,308 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-01-10 07:51:50,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45801 states and 71945 transitions. [2025-01-10 07:51:50,580 INFO L131 ngComponentsAnalysis]: Automaton has 72 accepting balls. 42630 [2025-01-10 07:51:50,581 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:50,581 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:50,581 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:50,581 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:50,582 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:50,582 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume !(0 == ~N_generate_st~0);" "assume 0 == ~S1_addsub_st~0;" [2025-01-10 07:51:50,583 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:50,583 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 3 times [2025-01-10 07:51:50,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:50,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604353660] [2025-01-10 07:51:50,584 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:51:50,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:50,592 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:50,597 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:50,597 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:51:50,597 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:50,597 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:50,599 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:50,602 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:50,602 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:50,602 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:50,613 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:50,613 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:50,614 INFO L85 PathProgramCache]: Analyzing trace with hash -603632599, now seen corresponding path program 1 times [2025-01-10 07:51:50,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:50,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2055584839] [2025-01-10 07:51:50,615 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:50,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:50,619 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-01-10 07:51:50,621 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-01-10 07:51:50,621 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:50,621 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:50,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:50,638 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:50,638 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2055584839] [2025-01-10 07:51:50,638 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2055584839] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:50,638 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:50,639 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:50,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [997974196] [2025-01-10 07:51:50,639 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:50,639 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:50,640 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:50,640 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:50,640 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:50,641 INFO L87 Difference]: Start difference. First operand 45801 states and 71945 transitions. cyclomatic complexity: 26216 Second operand has 3 states, 2 states have (on average 21.5) internal successors, (43), 3 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:50,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:50,863 INFO L93 Difference]: Finished difference Result 68156 states and 106177 transitions. [2025-01-10 07:51:50,863 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68156 states and 106177 transitions. [2025-01-10 07:51:51,274 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 62262 [2025-01-10 07:51:51,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68156 states to 68156 states and 106177 transitions. [2025-01-10 07:51:51,416 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68156 [2025-01-10 07:51:51,464 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68156 [2025-01-10 07:51:51,464 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68156 states and 106177 transitions. [2025-01-10 07:51:51,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:51,507 INFO L218 hiAutomatonCegarLoop]: Abstraction has 68156 states and 106177 transitions. [2025-01-10 07:51:51,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68156 states and 106177 transitions. [2025-01-10 07:51:52,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68156 to 68156. [2025-01-10 07:51:52,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68156 states, 68156 states have (on average 1.557852573507835) internal successors, (106177), 68155 states have internal predecessors, (106177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:52,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68156 states to 68156 states and 106177 transitions. [2025-01-10 07:51:52,420 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68156 states and 106177 transitions. [2025-01-10 07:51:52,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:52,420 INFO L432 stractBuchiCegarLoop]: Abstraction has 68156 states and 106177 transitions. [2025-01-10 07:51:52,420 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-01-10 07:51:52,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68156 states and 106177 transitions. [2025-01-10 07:51:52,799 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 62262 [2025-01-10 07:51:52,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:52,799 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:52,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:52,800 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:52,800 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:52,800 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume 0 == ~S2_presdbl_st~0;" [2025-01-10 07:51:52,801 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:52,801 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 4 times [2025-01-10 07:51:52,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:52,801 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950049322] [2025-01-10 07:51:52,801 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:51:52,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:52,808 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 40 statements into 2 equivalence classes. [2025-01-10 07:51:52,812 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:52,812 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:51:52,812 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:52,813 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:52,815 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:52,818 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:52,819 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:52,819 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:52,826 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:52,827 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:52,827 INFO L85 PathProgramCache]: Analyzing trace with hash -1532740648, now seen corresponding path program 1 times [2025-01-10 07:51:52,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:52,827 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1792988007] [2025-01-10 07:51:52,827 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:52,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:52,832 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-01-10 07:51:52,834 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-01-10 07:51:52,835 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:52,835 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:52,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:52,854 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:52,854 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1792988007] [2025-01-10 07:51:52,854 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1792988007] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:52,854 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:52,854 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:52,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [655093221] [2025-01-10 07:51:52,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:52,854 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:52,854 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:52,854 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:52,855 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:52,855 INFO L87 Difference]: Start difference. First operand 68156 states and 106177 transitions. cyclomatic complexity: 38117 Second operand has 3 states, 2 states have (on average 22.0) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:53,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:53,122 INFO L93 Difference]: Finished difference Result 72945 states and 113076 transitions. [2025-01-10 07:51:53,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72945 states and 113076 transitions. [2025-01-10 07:51:53,414 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 66828 [2025-01-10 07:51:53,817 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72945 states to 72945 states and 113076 transitions. [2025-01-10 07:51:53,817 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72945 [2025-01-10 07:51:53,861 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72945 [2025-01-10 07:51:53,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72945 states and 113076 transitions. [2025-01-10 07:51:53,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:53,894 INFO L218 hiAutomatonCegarLoop]: Abstraction has 72945 states and 113076 transitions. [2025-01-10 07:51:53,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72945 states and 113076 transitions. [2025-01-10 07:51:54,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72945 to 72945. [2025-01-10 07:51:54,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72945 states, 72945 states have (on average 1.5501542257865515) internal successors, (113076), 72944 states have internal predecessors, (113076), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:54,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72945 states to 72945 states and 113076 transitions. [2025-01-10 07:51:54,568 INFO L240 hiAutomatonCegarLoop]: Abstraction has 72945 states and 113076 transitions. [2025-01-10 07:51:54,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:54,569 INFO L432 stractBuchiCegarLoop]: Abstraction has 72945 states and 113076 transitions. [2025-01-10 07:51:54,569 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-01-10 07:51:54,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72945 states and 113076 transitions. [2025-01-10 07:51:54,734 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 66828 [2025-01-10 07:51:54,734 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:54,734 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:54,735 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:54,735 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:54,735 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:54,735 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume 0 == ~S3_zero_st~0;" [2025-01-10 07:51:54,735 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:54,735 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 5 times [2025-01-10 07:51:54,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:54,735 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [656217603] [2025-01-10 07:51:54,735 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:51:54,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:54,742 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:54,745 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:54,745 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:54,745 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:54,745 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:54,747 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:54,749 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:54,749 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:54,749 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:54,759 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:54,759 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:54,759 INFO L85 PathProgramCache]: Analyzing trace with hash -270319090, now seen corresponding path program 1 times [2025-01-10 07:51:54,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:54,759 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1268406311] [2025-01-10 07:51:54,759 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:54,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:54,764 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 45 statements into 1 equivalence classes. [2025-01-10 07:51:54,766 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 45 of 45 statements. [2025-01-10 07:51:54,766 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:54,766 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:54,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:54,788 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:54,789 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1268406311] [2025-01-10 07:51:54,789 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1268406311] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:54,789 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:54,789 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:54,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1631764094] [2025-01-10 07:51:54,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:54,789 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:54,789 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:54,790 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:54,790 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:54,790 INFO L87 Difference]: Start difference. First operand 72945 states and 113076 transitions. cyclomatic complexity: 40227 Second operand has 3 states, 2 states have (on average 22.5) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:55,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:55,403 INFO L93 Difference]: Finished difference Result 115976 states and 179145 transitions. [2025-01-10 07:51:55,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115976 states and 179145 transitions. [2025-01-10 07:51:56,176 INFO L131 ngComponentsAnalysis]: Automaton has 144 accepting balls. 104264 [2025-01-10 07:51:56,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115976 states to 115976 states and 179145 transitions. [2025-01-10 07:51:56,480 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 115976 [2025-01-10 07:51:56,561 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115976 [2025-01-10 07:51:56,561 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115976 states and 179145 transitions. [2025-01-10 07:51:56,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:56,634 INFO L218 hiAutomatonCegarLoop]: Abstraction has 115976 states and 179145 transitions. [2025-01-10 07:51:56,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115976 states and 179145 transitions. [2025-01-10 07:51:57,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115976 to 115976. [2025-01-10 07:51:57,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115976 states, 115976 states have (on average 1.5446730358005105) internal successors, (179145), 115975 states have internal predecessors, (179145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:57,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115976 states to 115976 states and 179145 transitions. [2025-01-10 07:51:57,995 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115976 states and 179145 transitions. [2025-01-10 07:51:57,995 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:57,995 INFO L432 stractBuchiCegarLoop]: Abstraction has 115976 states and 179145 transitions. [2025-01-10 07:51:57,995 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-01-10 07:51:57,996 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115976 states and 179145 transitions. [2025-01-10 07:51:58,679 INFO L131 ngComponentsAnalysis]: Automaton has 144 accepting balls. 104264 [2025-01-10 07:51:58,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:58,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:58,680 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:58,680 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:58,680 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:51:58,680 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume 0 == ~D_print_st~0;" [2025-01-10 07:51:58,680 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:58,680 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 6 times [2025-01-10 07:51:58,681 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:58,681 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1374665447] [2025-01-10 07:51:58,681 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:51:58,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:58,688 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:58,691 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:58,691 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-01-10 07:51:58,691 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:58,691 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:58,694 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:51:58,697 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:51:58,697 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:58,697 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:58,703 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:58,704 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:58,704 INFO L85 PathProgramCache]: Analyzing trace with hash 210043549, now seen corresponding path program 1 times [2025-01-10 07:51:58,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:58,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1909300083] [2025-01-10 07:51:58,705 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:58,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:58,709 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 46 statements into 1 equivalence classes. [2025-01-10 07:51:58,711 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 46 of 46 statements. [2025-01-10 07:51:58,711 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:58,711 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:58,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:58,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:58,725 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1909300083] [2025-01-10 07:51:58,725 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1909300083] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:58,725 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:58,725 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:58,725 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256746909] [2025-01-10 07:51:58,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:58,725 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:58,726 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:58,726 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:58,726 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:58,726 INFO L87 Difference]: Start difference. First operand 115976 states and 179145 transitions. cyclomatic complexity: 63313 Second operand has 3 states, 2 states have (on average 23.0) internal successors, (46), 3 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:59,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:59,158 INFO L93 Difference]: Finished difference Result 195837 states and 300177 transitions. [2025-01-10 07:51:59,158 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195837 states and 300177 transitions. [2025-01-10 07:52:00,305 INFO L131 ngComponentsAnalysis]: Automaton has 224 accepting balls. 169330 [2025-01-10 07:52:00,722 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195837 states to 195837 states and 300177 transitions. [2025-01-10 07:52:00,722 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195837 [2025-01-10 07:52:00,847 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195837 [2025-01-10 07:52:00,847 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195837 states and 300177 transitions. [2025-01-10 07:52:00,975 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:52:00,976 INFO L218 hiAutomatonCegarLoop]: Abstraction has 195837 states and 300177 transitions. [2025-01-10 07:52:01,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195837 states and 300177 transitions. [2025-01-10 07:52:02,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195837 to 195837. [2025-01-10 07:52:03,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195837 states, 195837 states have (on average 1.5327900243569907) internal successors, (300177), 195836 states have internal predecessors, (300177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:03,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195837 states to 195837 states and 300177 transitions. [2025-01-10 07:52:03,359 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195837 states and 300177 transitions. [2025-01-10 07:52:03,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:52:03,360 INFO L432 stractBuchiCegarLoop]: Abstraction has 195837 states and 300177 transitions. [2025-01-10 07:52:03,360 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-01-10 07:52:03,360 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195837 states and 300177 transitions. [2025-01-10 07:52:04,470 INFO L131 ngComponentsAnalysis]: Automaton has 224 accepting balls. 169330 [2025-01-10 07:52:04,470 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:52:04,471 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:52:04,471 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:04,471 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:04,471 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume 1 == ~N_generate_i~0;~N_generate_st~0 := 0;" "assume 1 == ~S1_addsub_i~0;~S1_addsub_st~0 := 0;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0;" "assume 1 == ~D_print_i~0;~D_print_st~0 := 0;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-01-10 07:52:04,471 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 == ~N_generate_st~0;" "assume 0 == ~N_generate_st~0;havoc eval_#t~nondet4#1;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~S1_addsub_st~0;havoc eval_#t~nondet5#1;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume !(0 == ~S2_presdbl_st~0);" "assume 0 == ~S3_zero_st~0;havoc eval_#t~nondet7#1;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___2~0#1);" "assume 0 == ~D_print_st~0;havoc eval_#t~nondet8#1;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp___3~0#1);" [2025-01-10 07:52:04,472 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:04,472 INFO L85 PathProgramCache]: Analyzing trace with hash 476849425, now seen corresponding path program 1 times [2025-01-10 07:52:04,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:04,472 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1207216368] [2025-01-10 07:52:04,472 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:04,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:04,478 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:52:04,481 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:52:04,481 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:04,481 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:52:04,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:52:04,514 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:52:04,514 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1207216368] [2025-01-10 07:52:04,514 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1207216368] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:52:04,514 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:52:04,514 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:52:04,514 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1783024238] [2025-01-10 07:52:04,514 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:52:04,514 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:52:04,515 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:04,515 INFO L85 PathProgramCache]: Analyzing trace with hash -437599327, now seen corresponding path program 1 times [2025-01-10 07:52:04,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:04,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278292131] [2025-01-10 07:52:04,515 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:04,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:04,518 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-01-10 07:52:04,519 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-01-10 07:52:04,519 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:04,519 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:52:04,519 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:52:04,520 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-01-10 07:52:04,520 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-01-10 07:52:04,520 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:04,520 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:52:04,522 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:52:04,580 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:52:04,581 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:52:04,584 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:52:04,585 INFO L87 Difference]: Start difference. First operand 195837 states and 300177 transitions. cyclomatic complexity: 104564 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:04,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:52:04,994 INFO L93 Difference]: Finished difference Result 121543 states and 185115 transitions. [2025-01-10 07:52:04,994 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121543 states and 185115 transitions. [2025-01-10 07:52:05,529 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 104282 [2025-01-10 07:52:06,225 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121543 states to 121543 states and 185115 transitions. [2025-01-10 07:52:06,225 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 121543 [2025-01-10 07:52:06,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 121543 [2025-01-10 07:52:06,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 121543 states and 185115 transitions. [2025-01-10 07:52:06,330 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:52:06,330 INFO L218 hiAutomatonCegarLoop]: Abstraction has 121543 states and 185115 transitions. [2025-01-10 07:52:06,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121543 states and 185115 transitions. [2025-01-10 07:52:07,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121543 to 121543. [2025-01-10 07:52:07,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121543 states, 121543 states have (on average 1.5230412282073011) internal successors, (185115), 121542 states have internal predecessors, (185115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:07,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121543 states to 121543 states and 185115 transitions. [2025-01-10 07:52:07,752 INFO L240 hiAutomatonCegarLoop]: Abstraction has 121543 states and 185115 transitions. [2025-01-10 07:52:07,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:52:07,753 INFO L432 stractBuchiCegarLoop]: Abstraction has 121543 states and 185115 transitions. [2025-01-10 07:52:07,753 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-01-10 07:52:07,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121543 states and 185115 transitions. [2025-01-10 07:52:08,144 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 104282 [2025-01-10 07:52:08,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:52:08,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:52:08,145 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:08,145 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:08,145 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume 1 == ~S1_addsub_i~0;~S1_addsub_st~0 := 0;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0;" "assume 1 == ~D_print_i~0;~D_print_st~0 := 0;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-01-10 07:52:08,145 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == ~N_generate_st~0);" "assume 0 == ~S1_addsub_st~0;" "assume !(0 == ~N_generate_st~0);" "assume 0 == ~S1_addsub_st~0;havoc eval_#t~nondet5#1;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume !(0 == ~S2_presdbl_st~0);" "assume 0 == ~S3_zero_st~0;havoc eval_#t~nondet7#1;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___2~0#1);" "assume 0 == ~D_print_st~0;havoc eval_#t~nondet8#1;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp___3~0#1);" [2025-01-10 07:52:08,146 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:08,146 INFO L85 PathProgramCache]: Analyzing trace with hash 1178449299, now seen corresponding path program 1 times [2025-01-10 07:52:08,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:08,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1062353977] [2025-01-10 07:52:08,146 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:08,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:08,153 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:52:08,159 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:52:08,159 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:08,159 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:52:08,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:52:08,202 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:52:08,202 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1062353977] [2025-01-10 07:52:08,202 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1062353977] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:52:08,202 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:52:08,202 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:52:08,202 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1046218829] [2025-01-10 07:52:08,202 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:52:08,203 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:52:08,204 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:08,204 INFO L85 PathProgramCache]: Analyzing trace with hash -595324569, now seen corresponding path program 1 times [2025-01-10 07:52:08,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:08,205 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1787623713] [2025-01-10 07:52:08,205 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:08,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:08,207 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-01-10 07:52:08,208 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-01-10 07:52:08,208 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:08,208 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:52:08,208 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:52:08,209 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-01-10 07:52:08,210 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-01-10 07:52:08,210 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:08,210 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:52:08,213 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:52:08,253 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:52:08,254 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:52:08,254 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:52:08,254 INFO L87 Difference]: Start difference. First operand 121543 states and 185115 transitions. cyclomatic complexity: 63668 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:08,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:52:08,604 INFO L93 Difference]: Finished difference Result 90663 states and 137347 transitions. [2025-01-10 07:52:08,604 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90663 states and 137347 transitions. [2025-01-10 07:52:09,493 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 78906 [2025-01-10 07:52:09,683 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90663 states to 90663 states and 137347 transitions. [2025-01-10 07:52:09,683 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90663 [2025-01-10 07:52:09,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90663 [2025-01-10 07:52:09,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90663 states and 137347 transitions. [2025-01-10 07:52:09,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:52:09,779 INFO L218 hiAutomatonCegarLoop]: Abstraction has 90663 states and 137347 transitions. [2025-01-10 07:52:09,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90663 states and 137347 transitions. [2025-01-10 07:52:10,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90663 to 90663. [2025-01-10 07:52:10,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90663 states, 90663 states have (on average 1.514917882708492) internal successors, (137347), 90662 states have internal predecessors, (137347), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:11,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90663 states to 90663 states and 137347 transitions. [2025-01-10 07:52:11,043 INFO L240 hiAutomatonCegarLoop]: Abstraction has 90663 states and 137347 transitions. [2025-01-10 07:52:11,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:52:11,043 INFO L432 stractBuchiCegarLoop]: Abstraction has 90663 states and 137347 transitions. [2025-01-10 07:52:11,043 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-01-10 07:52:11,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90663 states and 137347 transitions. [2025-01-10 07:52:11,241 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 78906 [2025-01-10 07:52:11,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:52:11,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:52:11,241 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:11,241 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:11,242 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0;" "assume 1 == ~D_print_i~0;~D_print_st~0 := 0;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-01-10 07:52:11,242 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume 0 == ~S3_zero_st~0;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume 0 == ~S3_zero_st~0;havoc eval_#t~nondet7#1;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___2~0#1);" "assume 0 == ~D_print_st~0;havoc eval_#t~nondet8#1;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp___3~0#1);" [2025-01-10 07:52:11,242 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:11,242 INFO L85 PathProgramCache]: Analyzing trace with hash 1201081553, now seen corresponding path program 1 times [2025-01-10 07:52:11,242 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:11,242 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620455373] [2025-01-10 07:52:11,242 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:11,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:11,248 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:52:11,249 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:52:11,250 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:11,250 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:52:11,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:52:11,279 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:52:11,279 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [620455373] [2025-01-10 07:52:11,279 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [620455373] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:52:11,279 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:52:11,280 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:52:11,280 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [723710976] [2025-01-10 07:52:11,280 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:52:11,280 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:52:11,280 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:11,280 INFO L85 PathProgramCache]: Analyzing trace with hash 858073382, now seen corresponding path program 1 times [2025-01-10 07:52:11,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:11,280 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [900392914] [2025-01-10 07:52:11,280 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:11,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:11,283 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-01-10 07:52:11,284 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-01-10 07:52:11,284 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:11,284 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:52:11,284 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:52:11,285 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-01-10 07:52:11,287 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-01-10 07:52:11,287 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:11,287 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:52:11,288 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:52:11,322 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:52:11,323 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:52:11,323 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:52:11,323 INFO L87 Difference]: Start difference. First operand 90663 states and 137347 transitions. cyclomatic complexity: 46748 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:11,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:52:11,544 INFO L93 Difference]: Finished difference Result 69159 states and 104627 transitions. [2025-01-10 07:52:11,544 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69159 states and 104627 transitions. [2025-01-10 07:52:11,785 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 61384 [2025-01-10 07:52:11,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69159 states to 69159 states and 104627 transitions. [2025-01-10 07:52:11,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69159 [2025-01-10 07:52:11,991 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69159 [2025-01-10 07:52:11,992 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69159 states and 104627 transitions. [2025-01-10 07:52:12,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:52:12,035 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69159 states and 104627 transitions. [2025-01-10 07:52:12,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69159 states and 104627 transitions. [2025-01-10 07:52:12,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69159 to 69159. [2025-01-10 07:52:12,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69159 states, 69159 states have (on average 1.5128472071603118) internal successors, (104627), 69158 states have internal predecessors, (104627), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:13,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69159 states to 69159 states and 104627 transitions. [2025-01-10 07:52:13,060 INFO L240 hiAutomatonCegarLoop]: Abstraction has 69159 states and 104627 transitions. [2025-01-10 07:52:13,061 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:52:13,061 INFO L432 stractBuchiCegarLoop]: Abstraction has 69159 states and 104627 transitions. [2025-01-10 07:52:13,061 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-01-10 07:52:13,061 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69159 states and 104627 transitions. [2025-01-10 07:52:13,229 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 61384 [2025-01-10 07:52:13,229 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:52:13,229 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:52:13,229 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:13,229 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:13,230 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume 1 == ~D_print_i~0;~D_print_st~0 := 0;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-01-10 07:52:13,230 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume 0 == ~D_print_st~0;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume 0 == ~D_print_st~0;havoc eval_#t~nondet8#1;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp___3~0#1);" [2025-01-10 07:52:13,230 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:13,230 INFO L85 PathProgramCache]: Analyzing trace with hash 691608463, now seen corresponding path program 1 times [2025-01-10 07:52:13,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:13,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [391110465] [2025-01-10 07:52:13,230 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:13,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:13,236 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:52:13,238 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:52:13,238 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:13,238 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:52:13,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:52:13,273 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:52:13,273 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [391110465] [2025-01-10 07:52:13,273 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [391110465] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:52:13,273 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:52:13,273 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:52:13,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901604594] [2025-01-10 07:52:13,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:52:13,273 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:52:13,274 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:13,274 INFO L85 PathProgramCache]: Analyzing trace with hash -1680283941, now seen corresponding path program 1 times [2025-01-10 07:52:13,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:13,274 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [13396576] [2025-01-10 07:52:13,274 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:13,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:13,276 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-01-10 07:52:13,278 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-01-10 07:52:13,278 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:13,278 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:52:13,278 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:52:13,279 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-01-10 07:52:13,280 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-01-10 07:52:13,280 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:13,280 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:52:13,281 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:52:13,308 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:52:13,308 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:52:13,310 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:52:13,310 INFO L87 Difference]: Start difference. First operand 69159 states and 104627 transitions. cyclomatic complexity: 35516 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:13,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:52:13,526 INFO L93 Difference]: Finished difference Result 56511 states and 85200 transitions. [2025-01-10 07:52:13,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56511 states and 85200 transitions. [2025-01-10 07:52:13,775 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 51118 [2025-01-10 07:52:13,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56511 states to 56511 states and 85200 transitions. [2025-01-10 07:52:13,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56511 [2025-01-10 07:52:14,433 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56511 [2025-01-10 07:52:14,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56511 states and 85200 transitions. [2025-01-10 07:52:14,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:52:14,444 INFO L218 hiAutomatonCegarLoop]: Abstraction has 56511 states and 85200 transitions. [2025-01-10 07:52:14,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56511 states and 85200 transitions. [2025-01-10 07:52:14,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56511 to 56511. [2025-01-10 07:52:14,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56511 states, 56511 states have (on average 1.5076710728884641) internal successors, (85200), 56510 states have internal predecessors, (85200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:15,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56511 states to 56511 states and 85200 transitions. [2025-01-10 07:52:15,038 INFO L240 hiAutomatonCegarLoop]: Abstraction has 56511 states and 85200 transitions. [2025-01-10 07:52:15,039 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:52:15,039 INFO L432 stractBuchiCegarLoop]: Abstraction has 56511 states and 85200 transitions. [2025-01-10 07:52:15,039 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-01-10 07:52:15,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56511 states and 85200 transitions. [2025-01-10 07:52:15,203 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 51118 [2025-01-10 07:52:15,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:52:15,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:52:15,204 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:15,204 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:15,204 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-01-10 07:52:15,204 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-01-10 07:52:15,205 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:15,205 INFO L85 PathProgramCache]: Analyzing trace with hash 1830128562, now seen corresponding path program 1 times [2025-01-10 07:52:15,205 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:15,205 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2097267256] [2025-01-10 07:52:15,205 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:15,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:15,211 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-01-10 07:52:15,213 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-01-10 07:52:15,213 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:15,213 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:52:15,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:52:15,243 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:52:15,243 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2097267256] [2025-01-10 07:52:15,244 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2097267256] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:52:15,244 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:52:15,244 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:52:15,244 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [909887889] [2025-01-10 07:52:15,244 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:52:15,244 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:52:15,245 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:15,245 INFO L85 PathProgramCache]: Analyzing trace with hash 417540829, now seen corresponding path program 1 times [2025-01-10 07:52:15,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:15,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [383399962] [2025-01-10 07:52:15,245 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:15,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:15,250 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 45 statements into 1 equivalence classes. [2025-01-10 07:52:15,251 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 45 of 45 statements. [2025-01-10 07:52:15,251 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:15,251 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:52:15,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:52:15,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:52:15,271 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [383399962] [2025-01-10 07:52:15,271 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [383399962] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:52:15,271 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:52:15,271 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:52:15,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1441754396] [2025-01-10 07:52:15,271 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:52:15,271 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:52:15,271 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:52:15,271 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:52:15,271 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:52:15,272 INFO L87 Difference]: Start difference. First operand 56511 states and 85200 transitions. cyclomatic complexity: 28729 Second operand has 4 states, 4 states have (on average 10.75) internal successors, (43), 4 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:15,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:52:15,428 INFO L93 Difference]: Finished difference Result 34005 states and 50378 transitions. [2025-01-10 07:52:15,428 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34005 states and 50378 transitions. [2025-01-10 07:52:15,606 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 32468 [2025-01-10 07:52:15,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34005 states to 34005 states and 50378 transitions. [2025-01-10 07:52:15,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34005 [2025-01-10 07:52:15,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34005 [2025-01-10 07:52:15,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34005 states and 50378 transitions. [2025-01-10 07:52:15,825 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:52:15,825 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34005 states and 50378 transitions. [2025-01-10 07:52:15,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34005 states and 50378 transitions. [2025-01-10 07:52:16,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34005 to 33997. [2025-01-10 07:52:16,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33997 states, 33997 states have (on average 1.481601317763332) internal successors, (50370), 33996 states have internal predecessors, (50370), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:16,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33997 states to 33997 states and 50370 transitions. [2025-01-10 07:52:16,604 INFO L240 hiAutomatonCegarLoop]: Abstraction has 33997 states and 50370 transitions. [2025-01-10 07:52:16,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:52:16,605 INFO L432 stractBuchiCegarLoop]: Abstraction has 33997 states and 50370 transitions. [2025-01-10 07:52:16,605 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-01-10 07:52:16,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33997 states and 50370 transitions. [2025-01-10 07:52:16,684 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 32468 [2025-01-10 07:52:16,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:52:16,685 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:52:16,686 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:16,686 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:16,686 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-01-10 07:52:16,687 INFO L754 eck$LassoCheckResult]: Loop: "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-01-10 07:52:16,687 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:16,687 INFO L85 PathProgramCache]: Analyzing trace with hash -1317091332, now seen corresponding path program 1 times [2025-01-10 07:52:16,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:16,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539409385] [2025-01-10 07:52:16,688 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:16,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:16,695 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 87 statements into 1 equivalence classes. [2025-01-10 07:52:16,698 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 87 of 87 statements. [2025-01-10 07:52:16,698 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:16,698 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:52:16,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:52:16,739 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:52:16,739 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [539409385] [2025-01-10 07:52:16,740 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [539409385] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:52:16,740 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:52:16,740 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:52:16,740 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1343777983] [2025-01-10 07:52:16,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:52:16,740 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:52:16,741 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:16,741 INFO L85 PathProgramCache]: Analyzing trace with hash 1951356184, now seen corresponding path program 1 times [2025-01-10 07:52:16,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:16,741 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884052984] [2025-01-10 07:52:16,741 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:16,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:16,750 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 173 statements into 1 equivalence classes. [2025-01-10 07:52:16,751 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 173 of 173 statements. [2025-01-10 07:52:16,751 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:16,751 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:52:16,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:52:16,774 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:52:16,774 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [884052984] [2025-01-10 07:52:16,774 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [884052984] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:52:16,774 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:52:16,775 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:52:16,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [205715430] [2025-01-10 07:52:16,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:52:16,775 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:52:16,775 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:52:16,775 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:52:16,775 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:52:16,776 INFO L87 Difference]: Start difference. First operand 33997 states and 50370 transitions. cyclomatic complexity: 16397 Second operand has 4 states, 4 states have (on average 21.75) internal successors, (87), 4 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:17,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:52:17,072 INFO L93 Difference]: Finished difference Result 72526 states and 106048 transitions. [2025-01-10 07:52:17,072 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72526 states and 106048 transitions. [2025-01-10 07:52:17,394 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 69164 [2025-01-10 07:52:17,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72526 states to 72526 states and 106048 transitions. [2025-01-10 07:52:17,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72526 [2025-01-10 07:52:17,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72526 [2025-01-10 07:52:17,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72526 states and 106048 transitions. [2025-01-10 07:52:17,708 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:52:17,708 INFO L218 hiAutomatonCegarLoop]: Abstraction has 72526 states and 106048 transitions. [2025-01-10 07:52:17,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72526 states and 106048 transitions. [2025-01-10 07:52:18,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72526 to 72526. [2025-01-10 07:52:18,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72526 states, 72526 states have (on average 1.4622066569230345) internal successors, (106048), 72525 states have internal predecessors, (106048), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:18,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72526 states to 72526 states and 106048 transitions. [2025-01-10 07:52:18,725 INFO L240 hiAutomatonCegarLoop]: Abstraction has 72526 states and 106048 transitions. [2025-01-10 07:52:18,726 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:52:18,726 INFO L432 stractBuchiCegarLoop]: Abstraction has 72526 states and 106048 transitions. [2025-01-10 07:52:18,726 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-01-10 07:52:18,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72526 states and 106048 transitions. [2025-01-10 07:52:18,904 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 69164 [2025-01-10 07:52:18,904 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:52:18,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:52:18,906 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:18,906 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:18,906 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-01-10 07:52:18,906 INFO L754 eck$LassoCheckResult]: Loop: "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-01-10 07:52:18,908 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:18,908 INFO L85 PathProgramCache]: Analyzing trace with hash -1317673348, now seen corresponding path program 1 times [2025-01-10 07:52:18,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:18,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415350090] [2025-01-10 07:52:18,908 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:18,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:18,915 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 87 statements into 1 equivalence classes. [2025-01-10 07:52:18,917 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 87 of 87 statements. [2025-01-10 07:52:18,917 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:18,917 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:52:18,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:52:18,953 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:52:18,953 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [415350090] [2025-01-10 07:52:18,953 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [415350090] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:52:18,953 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:52:18,953 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:52:18,954 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1452917198] [2025-01-10 07:52:18,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:52:18,954 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:52:18,955 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:18,955 INFO L85 PathProgramCache]: Analyzing trace with hash -422968298, now seen corresponding path program 1 times [2025-01-10 07:52:18,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:18,955 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [762804759] [2025-01-10 07:52:18,955 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:18,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:18,969 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 173 statements into 1 equivalence classes. [2025-01-10 07:52:18,974 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 173 of 173 statements. [2025-01-10 07:52:18,974 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:18,974 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:52:18,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:52:18,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:52:18,999 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [762804759] [2025-01-10 07:52:18,999 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [762804759] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:52:18,999 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:52:19,000 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:52:19,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1363496092] [2025-01-10 07:52:19,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:52:19,000 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:52:19,000 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:52:19,001 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:52:19,001 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:52:19,001 INFO L87 Difference]: Start difference. First operand 72526 states and 106048 transitions. cyclomatic complexity: 33570 Second operand has 4 states, 4 states have (on average 21.75) internal successors, (87), 4 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:19,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:52:19,411 INFO L93 Difference]: Finished difference Result 83324 states and 120317 transitions. [2025-01-10 07:52:19,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83324 states and 120317 transitions. [2025-01-10 07:52:19,751 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 79156 [2025-01-10 07:52:20,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83324 states to 83324 states and 120317 transitions. [2025-01-10 07:52:20,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83324 [2025-01-10 07:52:20,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83324 [2025-01-10 07:52:20,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83324 states and 120317 transitions. [2025-01-10 07:52:20,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:52:20,494 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83324 states and 120317 transitions. [2025-01-10 07:52:20,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83324 states and 120317 transitions. [2025-01-10 07:52:20,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83324 to 83270. [2025-01-10 07:52:21,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83270 states, 83270 states have (on average 1.4436051399063288) internal successors, (120209), 83269 states have internal predecessors, (120209), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:21,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83270 states to 83270 states and 120209 transitions. [2025-01-10 07:52:21,170 INFO L240 hiAutomatonCegarLoop]: Abstraction has 83270 states and 120209 transitions. [2025-01-10 07:52:21,171 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:52:21,171 INFO L432 stractBuchiCegarLoop]: Abstraction has 83270 states and 120209 transitions. [2025-01-10 07:52:21,171 INFO L338 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-01-10 07:52:21,171 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83270 states and 120209 transitions. [2025-01-10 07:52:21,799 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 79156 [2025-01-10 07:52:21,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:52:21,799 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:52:21,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:21,800 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:52:21,801 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-01-10 07:52:21,801 INFO L754 eck$LassoCheckResult]: Loop: "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-01-10 07:52:21,801 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:21,801 INFO L85 PathProgramCache]: Analyzing trace with hash 69112062, now seen corresponding path program 1 times [2025-01-10 07:52:21,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:21,801 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698009735] [2025-01-10 07:52:21,801 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:21,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:21,809 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 87 statements into 1 equivalence classes. [2025-01-10 07:52:21,812 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 87 of 87 statements. [2025-01-10 07:52:21,813 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:21,813 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:52:21,813 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:52:21,815 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 87 statements into 1 equivalence classes. [2025-01-10 07:52:21,820 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 87 of 87 statements. [2025-01-10 07:52:21,821 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:21,821 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:52:21,834 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:52:21,835 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:52:21,837 INFO L85 PathProgramCache]: Analyzing trace with hash -1354442536, now seen corresponding path program 1 times [2025-01-10 07:52:21,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:52:21,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [874987936] [2025-01-10 07:52:21,837 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:52:21,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:52:21,846 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 173 statements into 1 equivalence classes. [2025-01-10 07:52:21,848 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 173 of 173 statements. [2025-01-10 07:52:21,848 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:52:21,848 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:52:21,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:52:21,888 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:52:21,888 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [874987936] [2025-01-10 07:52:21,888 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [874987936] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:52:21,888 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:52:21,889 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:52:21,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1347513913] [2025-01-10 07:52:21,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:52:21,889 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:52:21,889 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:52:21,892 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:52:21,892 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:52:21,893 INFO L87 Difference]: Start difference. First operand 83270 states and 120209 transitions. cyclomatic complexity: 36987 Second operand has 3 states, 3 states have (on average 57.666666666666664) internal successors, (173), 2 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:52:22,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:52:22,171 INFO L93 Difference]: Finished difference Result 83270 states and 119723 transitions. [2025-01-10 07:52:22,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83270 states and 119723 transitions. [2025-01-10 07:52:22,599 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 79156 [2025-01-10 07:52:22,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83270 states to 83270 states and 119723 transitions. [2025-01-10 07:52:22,845 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83270 [2025-01-10 07:52:22,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83270 [2025-01-10 07:52:22,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83270 states and 119723 transitions. [2025-01-10 07:52:22,962 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:52:22,962 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83270 states and 119723 transitions. [2025-01-10 07:52:23,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83270 states and 119723 transitions.