./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/array-examples/sanfoundry_24-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 551b0097 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/array-examples/sanfoundry_24-1.i -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b --- Real Ultimate output --- This is Ultimate 0.3.0-?-551b009-m [2025-01-10 07:10:27,176 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-01-10 07:10:27,230 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-01-10 07:10:27,233 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-01-10 07:10:27,233 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-01-10 07:10:27,249 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-01-10 07:10:27,250 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-01-10 07:10:27,250 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-01-10 07:10:27,251 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-01-10 07:10:27,251 INFO L153 SettingsManager]: * Use memory slicer=true [2025-01-10 07:10:27,252 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-01-10 07:10:27,252 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-01-10 07:10:27,252 INFO L153 SettingsManager]: * Use SBE=true [2025-01-10 07:10:27,252 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-01-10 07:10:27,252 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-01-10 07:10:27,253 INFO L153 SettingsManager]: * Use old map elimination=false [2025-01-10 07:10:27,253 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-01-10 07:10:27,253 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-01-10 07:10:27,253 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-01-10 07:10:27,253 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-01-10 07:10:27,253 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-01-10 07:10:27,253 INFO L153 SettingsManager]: * sizeof long=4 [2025-01-10 07:10:27,253 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-01-10 07:10:27,253 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-01-10 07:10:27,253 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-01-10 07:10:27,253 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-01-10 07:10:27,253 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-01-10 07:10:27,253 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-01-10 07:10:27,253 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-01-10 07:10:27,254 INFO L153 SettingsManager]: * sizeof long double=12 [2025-01-10 07:10:27,254 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-01-10 07:10:27,254 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-01-10 07:10:27,254 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-01-10 07:10:27,254 INFO L153 SettingsManager]: * Use constant arrays=true [2025-01-10 07:10:27,254 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2025-01-10 07:10:27,255 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-01-10 07:10:27,255 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-01-10 07:10:27,255 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-01-10 07:10:27,255 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-01-10 07:10:27,255 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b [2025-01-10 07:10:27,448 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-01-10 07:10:27,457 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-01-10 07:10:27,459 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-01-10 07:10:27,460 INFO L270 PluginConnector]: Initializing CDTParser... [2025-01-10 07:10:27,461 INFO L274 PluginConnector]: CDTParser initialized [2025-01-10 07:10:27,462 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2025-01-10 07:10:28,575 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/c1e84794c/0052d55c38e24d4ea4fdf3d055966907/FLAG80c5b2cd6 [2025-01-10 07:10:28,830 INFO L384 CDTParser]: Found 1 translation units. [2025-01-10 07:10:28,831 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2025-01-10 07:10:28,836 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/c1e84794c/0052d55c38e24d4ea4fdf3d055966907/FLAG80c5b2cd6 [2025-01-10 07:10:28,850 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/c1e84794c/0052d55c38e24d4ea4fdf3d055966907 [2025-01-10 07:10:28,852 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-01-10 07:10:28,853 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-01-10 07:10:28,854 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-01-10 07:10:28,854 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-01-10 07:10:28,857 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-01-10 07:10:28,858 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:10:28" (1/1) ... [2025-01-10 07:10:28,859 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3f3b9ed3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:28, skipping insertion in model container [2025-01-10 07:10:28,859 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:10:28" (1/1) ... [2025-01-10 07:10:28,868 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-01-10 07:10:28,989 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:10:28,996 INFO L200 MainTranslator]: Completed pre-run [2025-01-10 07:10:29,013 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:10:29,025 INFO L204 MainTranslator]: Completed translation [2025-01-10 07:10:29,026 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29 WrapperNode [2025-01-10 07:10:29,026 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-01-10 07:10:29,027 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-01-10 07:10:29,027 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-01-10 07:10:29,027 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-01-10 07:10:29,032 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29" (1/1) ... [2025-01-10 07:10:29,042 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29" (1/1) ... [2025-01-10 07:10:29,057 INFO L138 Inliner]: procedures = 18, calls = 19, calls flagged for inlining = 7, calls inlined = 8, statements flattened = 69 [2025-01-10 07:10:29,059 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-01-10 07:10:29,059 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-01-10 07:10:29,059 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-01-10 07:10:29,060 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-01-10 07:10:29,067 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29" (1/1) ... [2025-01-10 07:10:29,067 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29" (1/1) ... [2025-01-10 07:10:29,069 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29" (1/1) ... [2025-01-10 07:10:29,082 INFO L175 MemorySlicer]: Split 7 memory accesses to 2 slices as follows [2, 5]. 71 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0]. The 1 writes are split as follows [0, 1]. [2025-01-10 07:10:29,084 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29" (1/1) ... [2025-01-10 07:10:29,085 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29" (1/1) ... [2025-01-10 07:10:29,088 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29" (1/1) ... [2025-01-10 07:10:29,092 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29" (1/1) ... [2025-01-10 07:10:29,096 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29" (1/1) ... [2025-01-10 07:10:29,098 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29" (1/1) ... [2025-01-10 07:10:29,102 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29" (1/1) ... [2025-01-10 07:10:29,103 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-01-10 07:10:29,104 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2025-01-10 07:10:29,104 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2025-01-10 07:10:29,104 INFO L274 PluginConnector]: RCFGBuilder initialized [2025-01-10 07:10:29,105 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29" (1/1) ... [2025-01-10 07:10:29,112 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:29,121 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:29,136 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:29,139 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-01-10 07:10:29,159 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-01-10 07:10:29,159 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-01-10 07:10:29,159 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-01-10 07:10:29,159 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-01-10 07:10:29,159 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-01-10 07:10:29,159 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-01-10 07:10:29,160 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-01-10 07:10:29,160 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-01-10 07:10:29,160 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-01-10 07:10:29,160 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-01-10 07:10:29,160 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-01-10 07:10:29,217 INFO L234 CfgBuilder]: Building ICFG [2025-01-10 07:10:29,219 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2025-01-10 07:10:29,362 INFO L? ?]: Removed 16 outVars from TransFormulas that were not future-live. [2025-01-10 07:10:29,362 INFO L283 CfgBuilder]: Performing block encoding [2025-01-10 07:10:29,369 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-01-10 07:10:29,370 INFO L312 CfgBuilder]: Removed 0 assume(true) statements. [2025-01-10 07:10:29,370 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:10:29 BoogieIcfgContainer [2025-01-10 07:10:29,371 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2025-01-10 07:10:29,371 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-01-10 07:10:29,372 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-01-10 07:10:29,376 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-01-10 07:10:29,376 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:10:29,377 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.01 07:10:28" (1/3) ... [2025-01-10 07:10:29,378 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c1604f8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:10:29, skipping insertion in model container [2025-01-10 07:10:29,378 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:10:29,379 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:10:29" (2/3) ... [2025-01-10 07:10:29,379 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c1604f8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:10:29, skipping insertion in model container [2025-01-10 07:10:29,379 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:10:29,379 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:10:29" (3/3) ... [2025-01-10 07:10:29,380 INFO L363 chiAutomizerObserver]: Analyzing ICFG sanfoundry_24-1.i [2025-01-10 07:10:29,427 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-01-10 07:10:29,427 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-01-10 07:10:29,427 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-01-10 07:10:29,427 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-01-10 07:10:29,427 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-01-10 07:10:29,427 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-01-10 07:10:29,427 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-01-10 07:10:29,428 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-01-10 07:10:29,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:29,441 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19 [2025-01-10 07:10:29,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:29,441 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:29,444 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-01-10 07:10:29,444 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-01-10 07:10:29,445 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-01-10 07:10:29,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:29,446 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19 [2025-01-10 07:10:29,446 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:29,446 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:29,446 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-01-10 07:10:29,446 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-01-10 07:10:29,451 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" [2025-01-10 07:10:29,452 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" [2025-01-10 07:10:29,455 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:29,456 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2025-01-10 07:10:29,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:29,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411325098] [2025-01-10 07:10:29,462 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:10:29,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:29,505 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:10:29,518 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:10:29,518 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:29,518 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:29,518 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:29,522 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:10:29,529 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:10:29,529 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:29,530 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:29,544 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:29,546 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:29,546 INFO L85 PathProgramCache]: Analyzing trace with hash 37, now seen corresponding path program 1 times [2025-01-10 07:10:29,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:29,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1622413390] [2025-01-10 07:10:29,547 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:10:29,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:29,553 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-01-10 07:10:29,561 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-01-10 07:10:29,561 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:29,561 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:29,561 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:29,564 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-01-10 07:10:29,566 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-01-10 07:10:29,568 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:29,568 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:29,570 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:29,572 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:29,572 INFO L85 PathProgramCache]: Analyzing trace with hash 29859, now seen corresponding path program 1 times [2025-01-10 07:10:29,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:29,575 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2147074639] [2025-01-10 07:10:29,575 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:10:29,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:29,581 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:29,596 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:29,596 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:29,596 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:29,596 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:29,598 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:29,605 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:29,605 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:29,605 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:29,612 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:29,855 INFO L204 LassoAnalysis]: Preferences: [2025-01-10 07:10:29,856 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-01-10 07:10:29,856 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-01-10 07:10:29,856 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-01-10 07:10:29,857 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-01-10 07:10:29,857 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:29,857 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-01-10 07:10:29,857 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-01-10 07:10:29,857 INFO L132 ssoRankerPreferences]: Filename of dumped script: sanfoundry_24-1.i_Iteration1_Lasso [2025-01-10 07:10:29,857 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-01-10 07:10:29,857 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-01-10 07:10:29,870 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:10:29,875 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:10:29,888 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:10:29,890 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:10:29,893 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:10:29,896 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:10:29,900 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:10:29,904 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:10:29,906 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:10:29,908 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:10:29,911 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:10:30,056 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:10:30,213 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-01-10 07:10:30,215 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-01-10 07:10:30,217 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,217 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,219 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,220 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-01-10 07:10:30,222 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,234 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,234 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:10:30,234 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,234 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,234 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,240 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:10:30,240 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:10:30,242 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,248 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2025-01-10 07:10:30,249 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,249 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,251 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,266 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-01-10 07:10:30,267 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,277 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,278 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,278 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,278 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,280 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-01-10 07:10:30,280 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-01-10 07:10:30,283 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,288 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2025-01-10 07:10:30,289 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,289 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,290 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,291 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-01-10 07:10:30,292 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,302 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,303 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,303 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,303 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,304 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-01-10 07:10:30,304 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-01-10 07:10:30,307 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,313 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2025-01-10 07:10:30,314 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,314 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,315 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,317 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-01-10 07:10:30,318 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,328 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,328 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:10:30,328 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,328 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,328 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,329 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:10:30,329 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:10:30,330 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,336 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2025-01-10 07:10:30,337 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,337 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,339 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,341 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-01-10 07:10:30,342 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,352 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,352 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:10:30,352 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,352 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,353 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,354 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:10:30,354 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:10:30,358 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,364 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2025-01-10 07:10:30,364 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,365 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,366 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,368 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-01-10 07:10:30,369 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,379 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,379 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:10:30,379 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,379 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,379 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,380 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:10:30,380 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:10:30,381 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,387 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2025-01-10 07:10:30,387 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,387 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,389 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,390 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-01-10 07:10:30,391 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,400 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,400 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:10:30,401 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,401 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,401 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,401 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:10:30,401 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:10:30,402 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,408 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2025-01-10 07:10:30,408 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,408 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,410 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,413 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2025-01-10 07:10:30,413 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,423 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,423 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:10:30,423 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,423 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,423 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,424 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:10:30,424 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:10:30,425 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,430 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2025-01-10 07:10:30,431 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,431 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,432 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,433 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2025-01-10 07:10:30,434 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,443 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,443 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:10:30,443 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,443 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,443 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,444 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:10:30,444 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:10:30,446 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,452 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2025-01-10 07:10:30,452 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,452 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,454 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,454 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2025-01-10 07:10:30,455 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,465 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,465 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:10:30,465 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,465 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,465 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,466 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:10:30,466 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:10:30,468 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,473 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2025-01-10 07:10:30,474 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,474 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,476 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,477 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2025-01-10 07:10:30,478 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,487 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,487 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:10:30,488 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,488 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,488 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,490 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:10:30,490 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:10:30,491 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,496 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2025-01-10 07:10:30,496 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,496 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,498 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,499 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2025-01-10 07:10:30,500 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,510 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,510 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,510 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,510 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,512 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-01-10 07:10:30,512 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-01-10 07:10:30,515 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,521 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2025-01-10 07:10:30,521 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,521 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,523 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,524 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2025-01-10 07:10:30,526 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,536 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,536 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:10:30,536 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,536 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,536 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,537 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:10:30,537 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:10:30,538 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,543 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2025-01-10 07:10:30,543 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,543 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,545 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,546 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2025-01-10 07:10:30,546 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,556 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,556 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,556 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,556 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,558 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-01-10 07:10:30,558 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-01-10 07:10:30,561 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,567 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2025-01-10 07:10:30,567 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,567 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,569 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,569 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2025-01-10 07:10:30,570 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,580 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,580 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,580 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,580 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,582 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-01-10 07:10:30,582 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-01-10 07:10:30,586 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,592 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2025-01-10 07:10:30,592 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,592 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,594 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,599 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2025-01-10 07:10:30,600 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,610 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,610 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,610 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,610 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,612 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-01-10 07:10:30,612 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-01-10 07:10:30,614 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,620 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2025-01-10 07:10:30,620 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,620 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,622 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,623 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2025-01-10 07:10:30,624 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,634 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,634 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,634 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,634 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,636 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-01-10 07:10:30,636 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-01-10 07:10:30,639 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,645 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2025-01-10 07:10:30,645 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,645 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,647 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,648 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2025-01-10 07:10:30,650 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,660 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,660 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,660 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,660 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,662 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-01-10 07:10:30,663 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-01-10 07:10:30,665 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:10:30,671 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2025-01-10 07:10:30,672 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,672 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,673 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,674 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2025-01-10 07:10:30,677 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:10:30,687 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:10:30,687 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:10:30,687 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:10:30,688 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:10:30,692 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-01-10 07:10:30,692 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-01-10 07:10:30,699 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-01-10 07:10:30,713 INFO L443 ModelExtractionUtils]: Simplification made 6 calls to the SMT solver. [2025-01-10 07:10:30,715 INFO L444 ModelExtractionUtils]: 7 out of 16 variables were initially zero. Simplification set additionally 5 variables to zero. [2025-01-10 07:10:30,716 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:10:30,716 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:30,718 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:10:30,719 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2025-01-10 07:10:30,720 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-01-10 07:10:30,730 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-01-10 07:10:30,731 INFO L474 LassoAnalysis]: Proved termination. [2025-01-10 07:10:30,731 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1, ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~#array~0#1.offset) = 1*v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~#array~0#1.offset Supporting invariants [] [2025-01-10 07:10:30,737 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2025-01-10 07:10:30,753 INFO L156 tatePredicateManager]: 4 out of 4 supporting invariants were superfluous and have been removed [2025-01-10 07:10:30,758 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: #length [2025-01-10 07:10:30,759 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#length,GLOBAL] [2025-01-10 07:10:30,760 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: ~#array~0!offset [2025-01-10 07:10:30,775 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:30,783 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-01-10 07:10:30,792 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-01-10 07:10:30,792 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:30,792 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:30,794 INFO L256 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-01-10 07:10:30,795 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:30,811 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-01-10 07:10:30,812 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-01-10 07:10:30,813 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:30,813 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:30,813 INFO L256 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-01-10 07:10:30,814 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:30,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:30,838 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2025-01-10 07:10:30,839 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:30,864 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 2 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 26 states and 36 transitions. Complement of second has 3 states. [2025-01-10 07:10:30,868 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 2 states 1 stem states 0 non-accepting loop states 1 accepting loop states [2025-01-10 07:10:30,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:30,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 3 transitions. [2025-01-10 07:10:30,875 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 3 transitions. Stem has 2 letters. Loop has 1 letters. [2025-01-10 07:10:30,875 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-01-10 07:10:30,875 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 3 transitions. Stem has 3 letters. Loop has 1 letters. [2025-01-10 07:10:30,875 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-01-10 07:10:30,875 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 3 transitions. Stem has 2 letters. Loop has 2 letters. [2025-01-10 07:10:30,875 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-01-10 07:10:30,876 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26 states and 36 transitions. [2025-01-10 07:10:30,877 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2025-01-10 07:10:30,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26 states to 23 states and 33 transitions. [2025-01-10 07:10:30,879 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2025-01-10 07:10:30,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2025-01-10 07:10:30,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 33 transitions. [2025-01-10 07:10:30,879 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:30,880 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23 states and 33 transitions. [2025-01-10 07:10:30,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 33 transitions. [2025-01-10 07:10:30,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 22. [2025-01-10 07:10:30,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.4090909090909092) internal successors, (31), 21 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:30,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 31 transitions. [2025-01-10 07:10:30,894 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22 states and 31 transitions. [2025-01-10 07:10:30,895 INFO L432 stractBuchiCegarLoop]: Abstraction has 22 states and 31 transitions. [2025-01-10 07:10:30,895 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-01-10 07:10:30,895 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 31 transitions. [2025-01-10 07:10:30,895 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2025-01-10 07:10:30,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:30,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:30,895 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2025-01-10 07:10:30,895 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:30,895 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" [2025-01-10 07:10:30,896 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" [2025-01-10 07:10:30,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:30,896 INFO L85 PathProgramCache]: Analyzing trace with hash 29861, now seen corresponding path program 1 times [2025-01-10 07:10:30,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:30,896 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529543374] [2025-01-10 07:10:30,896 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:10:30,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:30,899 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:30,901 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:30,901 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:30,901 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:30,901 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:30,903 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:30,908 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:30,908 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:30,908 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:30,909 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:30,910 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:30,910 INFO L85 PathProgramCache]: Analyzing trace with hash 42445, now seen corresponding path program 1 times [2025-01-10 07:10:30,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:30,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122515994] [2025-01-10 07:10:30,911 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:10:30,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:30,913 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:30,920 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:30,921 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:30,921 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:30,921 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:30,922 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:30,925 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:30,927 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:30,927 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:30,928 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:30,930 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:30,930 INFO L85 PathProgramCache]: Analyzing trace with hash 889601705, now seen corresponding path program 1 times [2025-01-10 07:10:30,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:30,930 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2033911741] [2025-01-10 07:10:30,930 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:10:30,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:30,937 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-01-10 07:10:30,945 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-01-10 07:10:30,945 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:30,945 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:31,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:31,018 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:31,018 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2033911741] [2025-01-10 07:10:31,018 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2033911741] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:10:31,018 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:10:31,019 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:10:31,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [851794692] [2025-01-10 07:10:31,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:10:31,060 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:31,061 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:10:31,061 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:10:31,062 INFO L87 Difference]: Start difference. First operand 22 states and 31 transitions. cyclomatic complexity: 12 Second operand has 4 states, 4 states have (on average 1.5) internal successors, (6), 4 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:31,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:31,093 INFO L93 Difference]: Finished difference Result 38 states and 45 transitions. [2025-01-10 07:10:31,093 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 45 transitions. [2025-01-10 07:10:31,094 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:31,094 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 28 states and 34 transitions. [2025-01-10 07:10:31,094 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2025-01-10 07:10:31,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2025-01-10 07:10:31,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 34 transitions. [2025-01-10 07:10:31,094 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:31,094 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28 states and 34 transitions. [2025-01-10 07:10:31,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 34 transitions. [2025-01-10 07:10:31,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 17. [2025-01-10 07:10:31,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.2352941176470589) internal successors, (21), 16 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:31,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 21 transitions. [2025-01-10 07:10:31,096 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17 states and 21 transitions. [2025-01-10 07:10:31,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:10:31,096 INFO L432 stractBuchiCegarLoop]: Abstraction has 17 states and 21 transitions. [2025-01-10 07:10:31,096 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-01-10 07:10:31,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 21 transitions. [2025-01-10 07:10:31,097 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:31,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:31,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:31,097 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2025-01-10 07:10:31,097 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:31,097 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:31,097 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:31,097 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:31,097 INFO L85 PathProgramCache]: Analyzing trace with hash 28694759, now seen corresponding path program 1 times [2025-01-10 07:10:31,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:31,097 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [657947854] [2025-01-10 07:10:31,097 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:10:31,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:31,100 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-01-10 07:10:31,110 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-01-10 07:10:31,110 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:31,110 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:31,110 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:31,112 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-01-10 07:10:31,120 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-01-10 07:10:31,121 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:31,121 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:31,122 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:31,123 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:31,123 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 2 times [2025-01-10 07:10:31,123 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:31,123 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [529228694] [2025-01-10 07:10:31,123 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:10:31,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:31,127 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:31,129 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:31,129 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:10:31,129 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:31,129 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:31,130 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:31,142 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:31,142 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:31,142 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:31,145 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:31,146 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:31,146 INFO L85 PathProgramCache]: Analyzing trace with hash 147108259, now seen corresponding path program 1 times [2025-01-10 07:10:31,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:31,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2066214958] [2025-01-10 07:10:31,146 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:10:31,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:31,151 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-01-10 07:10:31,160 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-01-10 07:10:31,160 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:31,160 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:31,241 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:31,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:31,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2066214958] [2025-01-10 07:10:31,242 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2066214958] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:31,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [870404664] [2025-01-10 07:10:31,242 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:10:31,242 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:31,242 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:31,244 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:31,244 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2025-01-10 07:10:31,273 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-01-10 07:10:31,283 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-01-10 07:10:31,283 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:31,283 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:31,284 INFO L256 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjuncts are in the unsatisfiable core [2025-01-10 07:10:31,284 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:31,335 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:31,335 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:31,361 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:31,361 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [870404664] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:31,361 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:31,361 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 9 [2025-01-10 07:10:31,361 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [565945434] [2025-01-10 07:10:31,361 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:31,420 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2025-01-10 07:10:31,437 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:31,437 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-01-10 07:10:31,437 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2025-01-10 07:10:31,437 INFO L87 Difference]: Start difference. First operand 17 states and 21 transitions. cyclomatic complexity: 7 Second operand has 10 states, 9 states have (on average 2.111111111111111) internal successors, (19), 10 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:31,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:31,508 INFO L93 Difference]: Finished difference Result 55 states and 66 transitions. [2025-01-10 07:10:31,508 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 66 transitions. [2025-01-10 07:10:31,509 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:31,509 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 41 states and 49 transitions. [2025-01-10 07:10:31,509 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2025-01-10 07:10:31,510 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2025-01-10 07:10:31,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41 states and 49 transitions. [2025-01-10 07:10:31,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:31,510 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41 states and 49 transitions. [2025-01-10 07:10:31,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states and 49 transitions. [2025-01-10 07:10:31,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 24. [2025-01-10 07:10:31,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 23 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:31,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 29 transitions. [2025-01-10 07:10:31,511 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 29 transitions. [2025-01-10 07:10:31,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-01-10 07:10:31,512 INFO L432 stractBuchiCegarLoop]: Abstraction has 24 states and 29 transitions. [2025-01-10 07:10:31,512 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-01-10 07:10:31,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 29 transitions. [2025-01-10 07:10:31,513 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:31,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:31,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:31,513 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1] [2025-01-10 07:10:31,513 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:31,513 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:31,514 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:31,514 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:31,514 INFO L85 PathProgramCache]: Analyzing trace with hash 203750019, now seen corresponding path program 2 times [2025-01-10 07:10:31,514 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:31,514 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927727810] [2025-01-10 07:10:31,514 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:10:31,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:31,520 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 9 statements into 2 equivalence classes. [2025-01-10 07:10:31,530 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 9 of 9 statements. [2025-01-10 07:10:31,530 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-01-10 07:10:31,530 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:31,530 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:31,533 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-01-10 07:10:31,542 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-01-10 07:10:31,542 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:31,542 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:31,544 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:31,544 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:31,544 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 3 times [2025-01-10 07:10:31,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:31,546 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076831251] [2025-01-10 07:10:31,546 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:31,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:31,550 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:31,553 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:31,556 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:10:31,556 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:31,556 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:31,557 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:31,560 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:31,561 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:31,562 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:31,563 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:31,563 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:31,563 INFO L85 PathProgramCache]: Analyzing trace with hash 1128061575, now seen corresponding path program 3 times [2025-01-10 07:10:31,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:31,563 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77497632] [2025-01-10 07:10:31,563 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:31,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:31,567 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 12 statements into 3 equivalence classes. [2025-01-10 07:10:31,576 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 12 of 12 statements. [2025-01-10 07:10:31,576 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-01-10 07:10:31,576 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:31,697 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:31,697 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:31,697 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [77497632] [2025-01-10 07:10:31,697 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [77497632] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:31,697 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [822413798] [2025-01-10 07:10:31,697 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:31,697 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:31,697 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:31,699 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:31,700 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2025-01-10 07:10:31,735 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 12 statements into 3 equivalence classes. [2025-01-10 07:10:31,746 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 12 of 12 statements. [2025-01-10 07:10:31,746 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-01-10 07:10:31,746 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:31,747 INFO L256 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 8 conjuncts are in the unsatisfiable core [2025-01-10 07:10:31,748 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:31,809 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:31,809 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:31,845 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:31,845 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [822413798] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:31,845 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:31,845 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 12 [2025-01-10 07:10:31,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988363529] [2025-01-10 07:10:31,846 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:31,882 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:31,883 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-01-10 07:10:31,883 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=109, Unknown=0, NotChecked=0, Total=156 [2025-01-10 07:10:31,883 INFO L87 Difference]: Start difference. First operand 24 states and 29 transitions. cyclomatic complexity: 8 Second operand has 13 states, 12 states have (on average 2.1666666666666665) internal successors, (26), 13 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:31,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:31,975 INFO L93 Difference]: Finished difference Result 80 states and 95 transitions. [2025-01-10 07:10:31,975 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80 states and 95 transitions. [2025-01-10 07:10:31,977 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:31,977 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80 states to 54 states and 64 transitions. [2025-01-10 07:10:31,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2025-01-10 07:10:31,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2025-01-10 07:10:31,977 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54 states and 64 transitions. [2025-01-10 07:10:31,977 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:31,977 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54 states and 64 transitions. [2025-01-10 07:10:31,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states and 64 transitions. [2025-01-10 07:10:31,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 31. [2025-01-10 07:10:31,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.1935483870967742) internal successors, (37), 30 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:31,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 37 transitions. [2025-01-10 07:10:31,983 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31 states and 37 transitions. [2025-01-10 07:10:31,983 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-01-10 07:10:31,983 INFO L432 stractBuchiCegarLoop]: Abstraction has 31 states and 37 transitions. [2025-01-10 07:10:31,983 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-01-10 07:10:31,983 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 37 transitions. [2025-01-10 07:10:31,984 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:31,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:31,984 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:31,984 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 1, 1, 1] [2025-01-10 07:10:31,984 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:31,984 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:31,984 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:31,985 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:31,985 INFO L85 PathProgramCache]: Analyzing trace with hash -1718766745, now seen corresponding path program 4 times [2025-01-10 07:10:31,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:31,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [52772254] [2025-01-10 07:10:31,985 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:10:31,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:31,993 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 13 statements into 2 equivalence classes. [2025-01-10 07:10:32,016 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 13 of 13 statements. [2025-01-10 07:10:32,017 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:10:32,017 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:32,017 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:32,021 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-01-10 07:10:32,026 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-01-10 07:10:32,026 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:32,026 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:32,029 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:32,032 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:32,033 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 4 times [2025-01-10 07:10:32,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:32,033 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2096082439] [2025-01-10 07:10:32,033 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:10:32,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:32,036 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-01-10 07:10:32,039 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:32,040 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:10:32,040 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:32,041 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:32,041 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:32,044 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:32,047 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:32,048 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:32,049 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:32,052 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:32,052 INFO L85 PathProgramCache]: Analyzing trace with hash 820037411, now seen corresponding path program 5 times [2025-01-10 07:10:32,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:32,052 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109142633] [2025-01-10 07:10:32,052 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:32,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:32,058 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 16 statements into 4 equivalence classes. [2025-01-10 07:10:32,072 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) and asserted 16 of 16 statements. [2025-01-10 07:10:32,075 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2025-01-10 07:10:32,075 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:32,197 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:32,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:32,198 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2109142633] [2025-01-10 07:10:32,198 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2109142633] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:32,198 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [277122693] [2025-01-10 07:10:32,198 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:32,198 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:32,198 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:32,217 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:32,233 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2025-01-10 07:10:32,259 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 16 statements into 4 equivalence classes. [2025-01-10 07:10:32,273 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) and asserted 16 of 16 statements. [2025-01-10 07:10:32,273 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2025-01-10 07:10:32,273 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:32,274 INFO L256 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 10 conjuncts are in the unsatisfiable core [2025-01-10 07:10:32,274 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:32,366 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:32,366 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:32,423 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:32,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [277122693] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:32,424 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:32,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 13 [2025-01-10 07:10:32,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141045718] [2025-01-10 07:10:32,424 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:32,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:32,461 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2025-01-10 07:10:32,461 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2025-01-10 07:10:32,461 INFO L87 Difference]: Start difference. First operand 31 states and 37 transitions. cyclomatic complexity: 9 Second operand has 14 states, 13 states have (on average 2.076923076923077) internal successors, (27), 14 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:32,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:32,590 INFO L93 Difference]: Finished difference Result 105 states and 124 transitions. [2025-01-10 07:10:32,590 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 124 transitions. [2025-01-10 07:10:32,592 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:32,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 67 states and 79 transitions. [2025-01-10 07:10:32,592 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63 [2025-01-10 07:10:32,592 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63 [2025-01-10 07:10:32,592 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 79 transitions. [2025-01-10 07:10:32,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:32,593 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67 states and 79 transitions. [2025-01-10 07:10:32,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 79 transitions. [2025-01-10 07:10:32,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 38. [2025-01-10 07:10:32,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.1842105263157894) internal successors, (45), 37 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:32,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 45 transitions. [2025-01-10 07:10:32,595 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38 states and 45 transitions. [2025-01-10 07:10:32,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-01-10 07:10:32,596 INFO L432 stractBuchiCegarLoop]: Abstraction has 38 states and 45 transitions. [2025-01-10 07:10:32,596 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-01-10 07:10:32,596 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 45 transitions. [2025-01-10 07:10:32,596 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:32,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:32,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:32,597 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 1, 1, 1] [2025-01-10 07:10:32,597 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:32,597 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:32,597 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:32,597 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:32,597 INFO L85 PathProgramCache]: Analyzing trace with hash -816173053, now seen corresponding path program 6 times [2025-01-10 07:10:32,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:32,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017936120] [2025-01-10 07:10:32,597 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:10:32,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:32,603 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 17 statements into 4 equivalence classes. [2025-01-10 07:10:32,615 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) and asserted 17 of 17 statements. [2025-01-10 07:10:32,615 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2025-01-10 07:10:32,615 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:32,615 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:32,617 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes. [2025-01-10 07:10:32,622 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements. [2025-01-10 07:10:32,623 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:32,623 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:32,625 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:32,625 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:32,625 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 5 times [2025-01-10 07:10:32,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:32,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228469078] [2025-01-10 07:10:32,626 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:32,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:32,627 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:32,628 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:32,628 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:10:32,628 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:32,629 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:32,629 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:32,635 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:32,636 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:32,636 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:32,637 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:32,637 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:32,637 INFO L85 PathProgramCache]: Analyzing trace with hash -801524473, now seen corresponding path program 7 times [2025-01-10 07:10:32,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:32,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [812313824] [2025-01-10 07:10:32,637 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:32,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:32,644 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-01-10 07:10:32,651 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-01-10 07:10:32,651 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:32,651 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:32,806 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 12 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:32,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:32,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [812313824] [2025-01-10 07:10:32,807 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [812313824] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:32,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [299940284] [2025-01-10 07:10:32,807 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:32,807 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:32,807 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:32,809 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:32,811 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2025-01-10 07:10:32,845 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-01-10 07:10:32,859 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-01-10 07:10:32,859 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:32,859 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:32,860 INFO L256 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 12 conjuncts are in the unsatisfiable core [2025-01-10 07:10:32,860 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:32,967 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 22 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:32,967 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:33,062 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 22 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:33,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [299940284] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:33,062 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:33,062 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 18 [2025-01-10 07:10:33,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1238190083] [2025-01-10 07:10:33,062 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:33,097 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:33,098 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2025-01-10 07:10:33,098 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=249, Unknown=0, NotChecked=0, Total=342 [2025-01-10 07:10:33,098 INFO L87 Difference]: Start difference. First operand 38 states and 45 transitions. cyclomatic complexity: 10 Second operand has 19 states, 18 states have (on average 2.2222222222222223) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:33,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:33,254 INFO L93 Difference]: Finished difference Result 130 states and 153 transitions. [2025-01-10 07:10:33,254 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 130 states and 153 transitions. [2025-01-10 07:10:33,255 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:33,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 130 states to 80 states and 94 transitions. [2025-01-10 07:10:33,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75 [2025-01-10 07:10:33,256 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75 [2025-01-10 07:10:33,256 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80 states and 94 transitions. [2025-01-10 07:10:33,256 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:33,256 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80 states and 94 transitions. [2025-01-10 07:10:33,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states and 94 transitions. [2025-01-10 07:10:33,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 45. [2025-01-10 07:10:33,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.1777777777777778) internal successors, (53), 44 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:33,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 53 transitions. [2025-01-10 07:10:33,263 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45 states and 53 transitions. [2025-01-10 07:10:33,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2025-01-10 07:10:33,264 INFO L432 stractBuchiCegarLoop]: Abstraction has 45 states and 53 transitions. [2025-01-10 07:10:33,265 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-01-10 07:10:33,265 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 53 transitions. [2025-01-10 07:10:33,266 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:33,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:33,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:33,266 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 1, 1, 1] [2025-01-10 07:10:33,266 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:33,266 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:33,266 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:33,267 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:33,270 INFO L85 PathProgramCache]: Analyzing trace with hash 1343466983, now seen corresponding path program 8 times [2025-01-10 07:10:33,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:33,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1567897055] [2025-01-10 07:10:33,270 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:10:33,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:33,276 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 21 statements into 2 equivalence classes. [2025-01-10 07:10:33,297 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 21 of 21 statements. [2025-01-10 07:10:33,298 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-01-10 07:10:33,298 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:33,298 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:33,301 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-01-10 07:10:33,318 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-01-10 07:10:33,320 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:33,321 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:33,325 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:33,327 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:33,327 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 6 times [2025-01-10 07:10:33,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:33,327 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619065463] [2025-01-10 07:10:33,327 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:10:33,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:33,330 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:33,331 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:33,331 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-01-10 07:10:33,331 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:33,331 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:33,332 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:33,333 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:33,333 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:33,333 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:33,334 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:33,335 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:33,335 INFO L85 PathProgramCache]: Analyzing trace with hash -1575306077, now seen corresponding path program 9 times [2025-01-10 07:10:33,335 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:33,335 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079260227] [2025-01-10 07:10:33,335 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:33,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:33,342 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 24 statements into 6 equivalence classes. [2025-01-10 07:10:33,381 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 24 of 24 statements. [2025-01-10 07:10:33,381 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-01-10 07:10:33,381 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:33,549 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 22 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:33,550 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:33,550 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079260227] [2025-01-10 07:10:33,550 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2079260227] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:33,550 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1827597783] [2025-01-10 07:10:33,550 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:33,550 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:33,550 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:33,553 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:33,555 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2025-01-10 07:10:33,598 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 24 statements into 6 equivalence classes. [2025-01-10 07:10:33,620 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 24 of 24 statements. [2025-01-10 07:10:33,620 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-01-10 07:10:33,620 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:33,621 INFO L256 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 14 conjuncts are in the unsatisfiable core [2025-01-10 07:10:33,622 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:33,766 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 35 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:33,767 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:33,859 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 35 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:33,859 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1827597783] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:33,859 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:33,859 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 21 [2025-01-10 07:10:33,859 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1241660833] [2025-01-10 07:10:33,859 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:33,897 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:33,897 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-01-10 07:10:33,897 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=340, Unknown=0, NotChecked=0, Total=462 [2025-01-10 07:10:33,898 INFO L87 Difference]: Start difference. First operand 45 states and 53 transitions. cyclomatic complexity: 11 Second operand has 22 states, 21 states have (on average 2.238095238095238) internal successors, (47), 22 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:34,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:34,096 INFO L93 Difference]: Finished difference Result 155 states and 182 transitions. [2025-01-10 07:10:34,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155 states and 182 transitions. [2025-01-10 07:10:34,097 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:34,098 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 155 states to 93 states and 109 transitions. [2025-01-10 07:10:34,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 87 [2025-01-10 07:10:34,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 87 [2025-01-10 07:10:34,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93 states and 109 transitions. [2025-01-10 07:10:34,098 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:34,098 INFO L218 hiAutomatonCegarLoop]: Abstraction has 93 states and 109 transitions. [2025-01-10 07:10:34,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states and 109 transitions. [2025-01-10 07:10:34,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 52. [2025-01-10 07:10:34,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.1730769230769231) internal successors, (61), 51 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:34,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 61 transitions. [2025-01-10 07:10:34,103 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 61 transitions. [2025-01-10 07:10:34,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2025-01-10 07:10:34,105 INFO L432 stractBuchiCegarLoop]: Abstraction has 52 states and 61 transitions. [2025-01-10 07:10:34,105 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-01-10 07:10:34,105 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 61 transitions. [2025-01-10 07:10:34,105 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:34,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:34,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:34,106 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 1, 1, 1] [2025-01-10 07:10:34,106 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:34,106 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:34,106 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:34,106 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:34,106 INFO L85 PathProgramCache]: Analyzing trace with hash 1083000195, now seen corresponding path program 10 times [2025-01-10 07:10:34,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:34,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [120667341] [2025-01-10 07:10:34,106 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:10:34,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:34,113 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 25 statements into 2 equivalence classes. [2025-01-10 07:10:34,136 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 25 of 25 statements. [2025-01-10 07:10:34,136 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:10:34,136 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:34,136 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:34,139 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 25 statements into 1 equivalence classes. [2025-01-10 07:10:34,156 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 25 of 25 statements. [2025-01-10 07:10:34,157 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:34,157 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:34,162 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:34,162 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:34,162 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 7 times [2025-01-10 07:10:34,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:34,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1114106364] [2025-01-10 07:10:34,163 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:34,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:34,164 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:34,166 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:34,166 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:34,166 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:34,166 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:34,167 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:34,168 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:34,168 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:34,168 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:34,169 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:34,172 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:34,172 INFO L85 PathProgramCache]: Analyzing trace with hash -135483513, now seen corresponding path program 11 times [2025-01-10 07:10:34,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:34,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [394967943] [2025-01-10 07:10:34,172 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:34,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:34,177 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 28 statements into 7 equivalence classes. [2025-01-10 07:10:34,196 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) and asserted 28 of 28 statements. [2025-01-10 07:10:34,196 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2025-01-10 07:10:34,196 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:34,375 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 51 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:34,375 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:34,375 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [394967943] [2025-01-10 07:10:34,375 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [394967943] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:34,375 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1619477700] [2025-01-10 07:10:34,376 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:34,376 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:34,376 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:34,377 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:34,379 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2025-01-10 07:10:34,412 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 28 statements into 7 equivalence classes. [2025-01-10 07:10:34,446 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) and asserted 28 of 28 statements. [2025-01-10 07:10:34,446 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2025-01-10 07:10:34,446 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:34,447 INFO L256 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 16 conjuncts are in the unsatisfiable core [2025-01-10 07:10:34,448 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:34,608 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 51 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:34,608 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:34,716 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 51 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:34,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1619477700] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:34,716 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:34,716 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15] total 22 [2025-01-10 07:10:34,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [755462867] [2025-01-10 07:10:34,716 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:34,750 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:34,751 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2025-01-10 07:10:34,751 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=372, Unknown=0, NotChecked=0, Total=506 [2025-01-10 07:10:34,751 INFO L87 Difference]: Start difference. First operand 52 states and 61 transitions. cyclomatic complexity: 12 Second operand has 23 states, 22 states have (on average 2.1818181818181817) internal successors, (48), 23 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:34,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:34,949 INFO L93 Difference]: Finished difference Result 180 states and 211 transitions. [2025-01-10 07:10:34,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 180 states and 211 transitions. [2025-01-10 07:10:34,950 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:34,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 180 states to 106 states and 124 transitions. [2025-01-10 07:10:34,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99 [2025-01-10 07:10:34,951 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99 [2025-01-10 07:10:34,951 INFO L73 IsDeterministic]: Start isDeterministic. Operand 106 states and 124 transitions. [2025-01-10 07:10:34,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:34,951 INFO L218 hiAutomatonCegarLoop]: Abstraction has 106 states and 124 transitions. [2025-01-10 07:10:34,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states and 124 transitions. [2025-01-10 07:10:34,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 59. [2025-01-10 07:10:34,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 59 states have (on average 1.1694915254237288) internal successors, (69), 58 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:34,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 69 transitions. [2025-01-10 07:10:34,954 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59 states and 69 transitions. [2025-01-10 07:10:34,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2025-01-10 07:10:34,958 INFO L432 stractBuchiCegarLoop]: Abstraction has 59 states and 69 transitions. [2025-01-10 07:10:34,958 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-01-10 07:10:34,958 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 69 transitions. [2025-01-10 07:10:34,958 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:34,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:34,958 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:34,959 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 6, 1, 1, 1] [2025-01-10 07:10:34,959 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:34,959 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:34,959 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:34,963 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:34,963 INFO L85 PathProgramCache]: Analyzing trace with hash -1775253401, now seen corresponding path program 12 times [2025-01-10 07:10:34,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:34,963 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2004660947] [2025-01-10 07:10:34,963 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:10:34,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:34,970 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 29 statements into 7 equivalence classes. [2025-01-10 07:10:35,004 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) and asserted 29 of 29 statements. [2025-01-10 07:10:35,004 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2025-01-10 07:10:35,004 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:35,004 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:35,006 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-01-10 07:10:35,034 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-01-10 07:10:35,034 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:35,034 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:35,037 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:35,041 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:35,041 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 8 times [2025-01-10 07:10:35,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:35,041 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511936336] [2025-01-10 07:10:35,041 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:10:35,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:35,043 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:35,045 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:35,045 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:10:35,045 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:35,045 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:35,046 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:35,047 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:35,047 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:35,047 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:35,048 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:35,048 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:35,048 INFO L85 PathProgramCache]: Analyzing trace with hash 1653248547, now seen corresponding path program 13 times [2025-01-10 07:10:35,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:35,049 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452738624] [2025-01-10 07:10:35,049 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:35,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:35,055 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-01-10 07:10:35,062 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-01-10 07:10:35,063 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:35,063 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:35,316 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 51 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:35,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:35,317 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [452738624] [2025-01-10 07:10:35,317 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [452738624] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:35,317 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2098526333] [2025-01-10 07:10:35,317 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:35,317 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:35,317 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:35,319 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:35,320 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2025-01-10 07:10:35,357 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-01-10 07:10:35,374 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-01-10 07:10:35,374 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:35,374 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:35,375 INFO L256 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 18 conjuncts are in the unsatisfiable core [2025-01-10 07:10:35,376 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:35,565 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 70 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:35,565 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:35,716 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 70 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:35,717 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2098526333] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:35,717 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:35,717 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 27 [2025-01-10 07:10:35,717 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [44435950] [2025-01-10 07:10:35,717 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:35,751 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:35,752 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2025-01-10 07:10:35,752 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=564, Unknown=0, NotChecked=0, Total=756 [2025-01-10 07:10:35,752 INFO L87 Difference]: Start difference. First operand 59 states and 69 transitions. cyclomatic complexity: 13 Second operand has 28 states, 27 states have (on average 2.259259259259259) internal successors, (61), 28 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:35,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:35,995 INFO L93 Difference]: Finished difference Result 205 states and 240 transitions. [2025-01-10 07:10:35,995 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 205 states and 240 transitions. [2025-01-10 07:10:35,996 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:35,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 205 states to 119 states and 139 transitions. [2025-01-10 07:10:35,997 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 111 [2025-01-10 07:10:35,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 111 [2025-01-10 07:10:35,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 119 states and 139 transitions. [2025-01-10 07:10:35,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:35,997 INFO L218 hiAutomatonCegarLoop]: Abstraction has 119 states and 139 transitions. [2025-01-10 07:10:35,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states and 139 transitions. [2025-01-10 07:10:35,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 66. [2025-01-10 07:10:35,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.1666666666666667) internal successors, (77), 65 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:36,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 77 transitions. [2025-01-10 07:10:36,000 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66 states and 77 transitions. [2025-01-10 07:10:36,007 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2025-01-10 07:10:36,007 INFO L432 stractBuchiCegarLoop]: Abstraction has 66 states and 77 transitions. [2025-01-10 07:10:36,007 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-01-10 07:10:36,007 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 77 transitions. [2025-01-10 07:10:36,008 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:36,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:36,008 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:36,008 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 7, 1, 1, 1] [2025-01-10 07:10:36,008 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:36,008 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:36,008 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:36,008 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:36,008 INFO L85 PathProgramCache]: Analyzing trace with hash -2049557757, now seen corresponding path program 14 times [2025-01-10 07:10:36,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:36,009 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1479266007] [2025-01-10 07:10:36,009 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:10:36,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:36,017 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 33 statements into 2 equivalence classes. [2025-01-10 07:10:36,048 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 33 of 33 statements. [2025-01-10 07:10:36,048 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-01-10 07:10:36,048 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:36,048 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:36,053 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-01-10 07:10:36,069 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-01-10 07:10:36,069 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:36,069 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:36,075 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:36,076 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:36,076 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 9 times [2025-01-10 07:10:36,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:36,076 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230261146] [2025-01-10 07:10:36,076 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:36,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:36,078 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:36,079 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:36,079 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:10:36,079 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:36,079 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:36,079 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:36,080 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:36,080 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:36,080 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:36,082 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:36,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:36,083 INFO L85 PathProgramCache]: Analyzing trace with hash -1120024057, now seen corresponding path program 15 times [2025-01-10 07:10:36,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:36,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532211767] [2025-01-10 07:10:36,083 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:36,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:36,091 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 36 statements into 9 equivalence classes. [2025-01-10 07:10:36,130 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) and asserted 36 of 36 statements. [2025-01-10 07:10:36,130 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2025-01-10 07:10:36,130 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:36,396 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 70 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:36,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:36,396 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1532211767] [2025-01-10 07:10:36,396 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1532211767] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:36,396 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [411181124] [2025-01-10 07:10:36,397 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:36,397 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:36,397 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:36,399 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:36,400 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2025-01-10 07:10:36,437 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 36 statements into 9 equivalence classes. [2025-01-10 07:10:36,498 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) and asserted 36 of 36 statements. [2025-01-10 07:10:36,498 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2025-01-10 07:10:36,498 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:36,499 INFO L256 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 20 conjuncts are in the unsatisfiable core [2025-01-10 07:10:36,500 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:36,697 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 92 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:36,698 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:36,811 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 92 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:36,811 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [411181124] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:36,811 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:36,811 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 30 [2025-01-10 07:10:36,812 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1338160701] [2025-01-10 07:10:36,812 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:36,837 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:36,837 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2025-01-10 07:10:36,837 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=233, Invalid=697, Unknown=0, NotChecked=0, Total=930 [2025-01-10 07:10:36,838 INFO L87 Difference]: Start difference. First operand 66 states and 77 transitions. cyclomatic complexity: 14 Second operand has 31 states, 30 states have (on average 2.2666666666666666) internal successors, (68), 31 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:37,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:37,099 INFO L93 Difference]: Finished difference Result 230 states and 269 transitions. [2025-01-10 07:10:37,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230 states and 269 transitions. [2025-01-10 07:10:37,101 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:37,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230 states to 132 states and 154 transitions. [2025-01-10 07:10:37,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123 [2025-01-10 07:10:37,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123 [2025-01-10 07:10:37,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132 states and 154 transitions. [2025-01-10 07:10:37,102 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:37,102 INFO L218 hiAutomatonCegarLoop]: Abstraction has 132 states and 154 transitions. [2025-01-10 07:10:37,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states and 154 transitions. [2025-01-10 07:10:37,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 73. [2025-01-10 07:10:37,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.1643835616438356) internal successors, (85), 72 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:37,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 85 transitions. [2025-01-10 07:10:37,105 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73 states and 85 transitions. [2025-01-10 07:10:37,112 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2025-01-10 07:10:37,112 INFO L432 stractBuchiCegarLoop]: Abstraction has 73 states and 85 transitions. [2025-01-10 07:10:37,112 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-01-10 07:10:37,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 85 transitions. [2025-01-10 07:10:37,113 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:37,113 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:37,113 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:37,114 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 8, 1, 1, 1] [2025-01-10 07:10:37,114 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:37,114 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:37,114 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:37,114 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:37,114 INFO L85 PathProgramCache]: Analyzing trace with hash -1899363609, now seen corresponding path program 16 times [2025-01-10 07:10:37,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:37,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187725185] [2025-01-10 07:10:37,115 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:10:37,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:37,124 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 37 statements into 2 equivalence classes. [2025-01-10 07:10:37,140 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 37 of 37 statements. [2025-01-10 07:10:37,140 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:10:37,140 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:37,140 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:37,142 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-01-10 07:10:37,157 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-01-10 07:10:37,157 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:37,157 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:37,161 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:37,161 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:37,161 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 10 times [2025-01-10 07:10:37,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:37,161 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818690406] [2025-01-10 07:10:37,162 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:10:37,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:37,166 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-01-10 07:10:37,168 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:37,168 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:10:37,168 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:37,168 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:37,168 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:37,169 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:37,169 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:37,169 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:37,170 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:37,171 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:37,171 INFO L85 PathProgramCache]: Analyzing trace with hash -2042083421, now seen corresponding path program 17 times [2025-01-10 07:10:37,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:37,171 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698640563] [2025-01-10 07:10:37,171 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:37,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:37,177 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 40 statements into 10 equivalence classes. [2025-01-10 07:10:37,190 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:10:37,191 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2025-01-10 07:10:37,191 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:37,537 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 108 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:37,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:37,538 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1698640563] [2025-01-10 07:10:37,538 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1698640563] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:37,538 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [373256245] [2025-01-10 07:10:37,538 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:37,538 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:37,538 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:37,540 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:37,542 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2025-01-10 07:10:37,586 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 40 statements into 10 equivalence classes. [2025-01-10 07:10:37,647 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:10:37,647 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2025-01-10 07:10:37,647 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:37,648 INFO L256 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 22 conjuncts are in the unsatisfiable core [2025-01-10 07:10:37,650 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:38,051 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 117 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:38,051 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:38,296 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 117 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:38,296 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [373256245] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:38,296 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:38,296 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21, 21] total 42 [2025-01-10 07:10:38,296 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919394439] [2025-01-10 07:10:38,296 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:38,330 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:38,331 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2025-01-10 07:10:38,331 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=318, Invalid=1488, Unknown=0, NotChecked=0, Total=1806 [2025-01-10 07:10:38,332 INFO L87 Difference]: Start difference. First operand 73 states and 85 transitions. cyclomatic complexity: 15 Second operand has 43 states, 42 states have (on average 1.9285714285714286) internal successors, (81), 43 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:39,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:39,191 INFO L93 Difference]: Finished difference Result 310 states and 361 transitions. [2025-01-10 07:10:39,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 310 states and 361 transitions. [2025-01-10 07:10:39,193 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:39,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 310 states to 145 states and 169 transitions. [2025-01-10 07:10:39,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 135 [2025-01-10 07:10:39,194 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 135 [2025-01-10 07:10:39,194 INFO L73 IsDeterministic]: Start isDeterministic. Operand 145 states and 169 transitions. [2025-01-10 07:10:39,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:39,194 INFO L218 hiAutomatonCegarLoop]: Abstraction has 145 states and 169 transitions. [2025-01-10 07:10:39,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states and 169 transitions. [2025-01-10 07:10:39,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 80. [2025-01-10 07:10:39,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.1625) internal successors, (93), 79 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:39,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 93 transitions. [2025-01-10 07:10:39,199 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 93 transitions. [2025-01-10 07:10:39,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2025-01-10 07:10:39,202 INFO L432 stractBuchiCegarLoop]: Abstraction has 80 states and 93 transitions. [2025-01-10 07:10:39,202 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-01-10 07:10:39,203 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 93 transitions. [2025-01-10 07:10:39,203 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:39,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:39,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:39,203 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 9, 9, 1, 1, 1] [2025-01-10 07:10:39,203 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:39,204 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:39,204 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:39,204 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:39,204 INFO L85 PathProgramCache]: Analyzing trace with hash -749924221, now seen corresponding path program 18 times [2025-01-10 07:10:39,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:39,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523557414] [2025-01-10 07:10:39,204 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:10:39,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:39,211 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 41 statements into 10 equivalence classes. [2025-01-10 07:10:39,257 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:10:39,257 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2025-01-10 07:10:39,257 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:39,257 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:39,260 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:10:39,281 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:10:39,281 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:39,281 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:39,285 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:39,285 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:39,285 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 11 times [2025-01-10 07:10:39,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:39,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1595659069] [2025-01-10 07:10:39,286 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:39,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:39,287 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:39,288 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:39,288 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:10:39,288 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:39,288 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:39,288 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:39,289 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:39,289 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:39,290 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:39,291 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:39,291 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:39,291 INFO L85 PathProgramCache]: Analyzing trace with hash 1427440775, now seen corresponding path program 19 times [2025-01-10 07:10:39,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:39,291 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400877195] [2025-01-10 07:10:39,291 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:39,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:39,297 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-01-10 07:10:39,304 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-01-10 07:10:39,304 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:39,304 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:39,627 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 117 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:39,628 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:39,628 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400877195] [2025-01-10 07:10:39,628 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1400877195] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:39,628 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1194383546] [2025-01-10 07:10:39,628 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:39,628 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:39,628 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:39,630 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:39,632 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2025-01-10 07:10:39,678 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-01-10 07:10:39,697 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-01-10 07:10:39,698 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:39,698 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:39,699 INFO L256 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 24 conjuncts are in the unsatisfiable core [2025-01-10 07:10:39,700 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:39,957 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 145 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:39,957 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:40,122 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 145 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:40,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1194383546] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:40,123 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:40,123 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23] total 36 [2025-01-10 07:10:40,123 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [317643653] [2025-01-10 07:10:40,123 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:40,149 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:40,149 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2025-01-10 07:10:40,150 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=327, Invalid=1005, Unknown=0, NotChecked=0, Total=1332 [2025-01-10 07:10:40,150 INFO L87 Difference]: Start difference. First operand 80 states and 93 transitions. cyclomatic complexity: 16 Second operand has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 37 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:40,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:40,481 INFO L93 Difference]: Finished difference Result 280 states and 327 transitions. [2025-01-10 07:10:40,481 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 280 states and 327 transitions. [2025-01-10 07:10:40,482 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:40,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 280 states to 158 states and 184 transitions. [2025-01-10 07:10:40,483 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147 [2025-01-10 07:10:40,483 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147 [2025-01-10 07:10:40,483 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 184 transitions. [2025-01-10 07:10:40,483 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:40,483 INFO L218 hiAutomatonCegarLoop]: Abstraction has 158 states and 184 transitions. [2025-01-10 07:10:40,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 184 transitions. [2025-01-10 07:10:40,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 87. [2025-01-10 07:10:40,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 87 states have (on average 1.160919540229885) internal successors, (101), 86 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:40,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 101 transitions. [2025-01-10 07:10:40,490 INFO L240 hiAutomatonCegarLoop]: Abstraction has 87 states and 101 transitions. [2025-01-10 07:10:40,490 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2025-01-10 07:10:40,491 INFO L432 stractBuchiCegarLoop]: Abstraction has 87 states and 101 transitions. [2025-01-10 07:10:40,491 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-01-10 07:10:40,491 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 101 transitions. [2025-01-10 07:10:40,491 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:40,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:40,494 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:40,494 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 10, 1, 1, 1] [2025-01-10 07:10:40,496 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:40,496 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:40,497 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:40,497 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:40,497 INFO L85 PathProgramCache]: Analyzing trace with hash -1899340441, now seen corresponding path program 20 times [2025-01-10 07:10:40,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:40,497 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406805098] [2025-01-10 07:10:40,497 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:10:40,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:40,503 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 45 statements into 2 equivalence classes. [2025-01-10 07:10:40,537 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 45 of 45 statements. [2025-01-10 07:10:40,537 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-01-10 07:10:40,537 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:40,537 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:40,540 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 45 statements into 1 equivalence classes. [2025-01-10 07:10:40,562 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 45 of 45 statements. [2025-01-10 07:10:40,562 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:40,562 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:40,567 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:40,567 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:40,568 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 12 times [2025-01-10 07:10:40,568 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:40,568 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985955136] [2025-01-10 07:10:40,568 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:10:40,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:40,570 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:40,570 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:40,570 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-01-10 07:10:40,570 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:40,570 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:40,571 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:40,576 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:40,576 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:40,576 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:40,577 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:40,577 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:40,577 INFO L85 PathProgramCache]: Analyzing trace with hash -1351885533, now seen corresponding path program 21 times [2025-01-10 07:10:40,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:40,577 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284296610] [2025-01-10 07:10:40,577 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:40,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:40,590 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 48 statements into 12 equivalence classes. [2025-01-10 07:10:40,658 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) and asserted 48 of 48 statements. [2025-01-10 07:10:40,658 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2025-01-10 07:10:40,658 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:41,019 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 145 proven. 97 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:41,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:41,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284296610] [2025-01-10 07:10:41,019 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [284296610] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:41,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2110039010] [2025-01-10 07:10:41,019 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:41,019 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:41,019 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:41,021 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:41,023 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2025-01-10 07:10:41,074 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 48 statements into 12 equivalence classes. [2025-01-10 07:10:41,208 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) and asserted 48 of 48 statements. [2025-01-10 07:10:41,208 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2025-01-10 07:10:41,208 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:41,210 INFO L256 TraceCheckSpWp]: Trace formula consists of 272 conjuncts, 26 conjuncts are in the unsatisfiable core [2025-01-10 07:10:41,211 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:41,512 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 176 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:41,513 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:41,746 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 176 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:41,746 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2110039010] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:41,746 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:41,746 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 39 [2025-01-10 07:10:41,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537603802] [2025-01-10 07:10:41,747 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:41,773 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:41,774 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2025-01-10 07:10:41,774 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=380, Invalid=1180, Unknown=0, NotChecked=0, Total=1560 [2025-01-10 07:10:41,774 INFO L87 Difference]: Start difference. First operand 87 states and 101 transitions. cyclomatic complexity: 17 Second operand has 40 states, 39 states have (on average 2.282051282051282) internal successors, (89), 40 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:42,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:42,137 INFO L93 Difference]: Finished difference Result 305 states and 356 transitions. [2025-01-10 07:10:42,137 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 305 states and 356 transitions. [2025-01-10 07:10:42,138 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:42,139 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 305 states to 171 states and 199 transitions. [2025-01-10 07:10:42,139 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 159 [2025-01-10 07:10:42,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 159 [2025-01-10 07:10:42,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 171 states and 199 transitions. [2025-01-10 07:10:42,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:42,139 INFO L218 hiAutomatonCegarLoop]: Abstraction has 171 states and 199 transitions. [2025-01-10 07:10:42,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states and 199 transitions. [2025-01-10 07:10:42,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 94. [2025-01-10 07:10:42,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 94 states, 94 states have (on average 1.1595744680851063) internal successors, (109), 93 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:42,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 109 transitions. [2025-01-10 07:10:42,141 INFO L240 hiAutomatonCegarLoop]: Abstraction has 94 states and 109 transitions. [2025-01-10 07:10:42,142 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2025-01-10 07:10:42,142 INFO L432 stractBuchiCegarLoop]: Abstraction has 94 states and 109 transitions. [2025-01-10 07:10:42,142 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-01-10 07:10:42,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94 states and 109 transitions. [2025-01-10 07:10:42,142 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:42,142 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:42,142 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:42,143 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 11, 11, 1, 1, 1] [2025-01-10 07:10:42,143 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:42,143 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:42,143 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:42,143 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:42,143 INFO L85 PathProgramCache]: Analyzing trace with hash -351681021, now seen corresponding path program 22 times [2025-01-10 07:10:42,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:42,143 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61250559] [2025-01-10 07:10:42,143 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:10:42,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:42,151 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 49 statements into 2 equivalence classes. [2025-01-10 07:10:42,192 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:10:42,192 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:10:42,192 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:42,192 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:42,196 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:10:42,219 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:10:42,221 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:42,221 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:42,226 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:42,227 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:42,227 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 13 times [2025-01-10 07:10:42,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:42,227 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286090896] [2025-01-10 07:10:42,227 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:42,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:42,229 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:42,230 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:42,230 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:42,230 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:42,230 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:42,231 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:42,231 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:42,232 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:42,232 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:42,233 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:42,233 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:42,233 INFO L85 PathProgramCache]: Analyzing trace with hash -1504026873, now seen corresponding path program 23 times [2025-01-10 07:10:42,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:42,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080815766] [2025-01-10 07:10:42,234 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:42,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:42,240 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 52 statements into 13 equivalence classes. [2025-01-10 07:10:42,292 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) and asserted 52 of 52 statements. [2025-01-10 07:10:42,292 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2025-01-10 07:10:42,292 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:42,733 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:42,734 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:42,734 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2080815766] [2025-01-10 07:10:42,734 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2080815766] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:42,734 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1041427913] [2025-01-10 07:10:42,734 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:42,734 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:42,734 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:42,736 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:42,738 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2025-01-10 07:10:42,792 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 52 statements into 13 equivalence classes. [2025-01-10 07:10:42,869 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) and asserted 52 of 52 statements. [2025-01-10 07:10:42,869 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2025-01-10 07:10:42,869 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:42,872 INFO L256 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 28 conjuncts are in the unsatisfiable core [2025-01-10 07:10:42,873 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:43,207 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:43,208 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:43,450 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:43,451 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1041427913] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:43,451 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:43,451 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27] total 40 [2025-01-10 07:10:43,451 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [416517433] [2025-01-10 07:10:43,451 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:43,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:43,483 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2025-01-10 07:10:43,484 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=404, Invalid=1236, Unknown=0, NotChecked=0, Total=1640 [2025-01-10 07:10:43,484 INFO L87 Difference]: Start difference. First operand 94 states and 109 transitions. cyclomatic complexity: 18 Second operand has 41 states, 40 states have (on average 2.25) internal successors, (90), 41 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:43,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:43,816 INFO L93 Difference]: Finished difference Result 330 states and 385 transitions. [2025-01-10 07:10:43,816 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 330 states and 385 transitions. [2025-01-10 07:10:43,817 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:43,818 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 330 states to 184 states and 214 transitions. [2025-01-10 07:10:43,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 171 [2025-01-10 07:10:43,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 171 [2025-01-10 07:10:43,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 184 states and 214 transitions. [2025-01-10 07:10:43,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:43,819 INFO L218 hiAutomatonCegarLoop]: Abstraction has 184 states and 214 transitions. [2025-01-10 07:10:43,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states and 214 transitions. [2025-01-10 07:10:43,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 101. [2025-01-10 07:10:43,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101 states, 101 states have (on average 1.1584158415841583) internal successors, (117), 100 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:43,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 117 transitions. [2025-01-10 07:10:43,821 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101 states and 117 transitions. [2025-01-10 07:10:43,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2025-01-10 07:10:43,826 INFO L432 stractBuchiCegarLoop]: Abstraction has 101 states and 117 transitions. [2025-01-10 07:10:43,826 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-01-10 07:10:43,826 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101 states and 117 transitions. [2025-01-10 07:10:43,827 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:43,827 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:43,827 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:43,827 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 12, 12, 1, 1, 1] [2025-01-10 07:10:43,827 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:43,827 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:43,827 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:43,828 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:43,828 INFO L85 PathProgramCache]: Analyzing trace with hash -1659316249, now seen corresponding path program 24 times [2025-01-10 07:10:43,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:43,828 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822499151] [2025-01-10 07:10:43,828 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:10:43,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:43,837 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 53 statements into 13 equivalence classes. [2025-01-10 07:10:43,907 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) and asserted 53 of 53 statements. [2025-01-10 07:10:43,907 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2025-01-10 07:10:43,907 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:43,907 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:43,910 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 53 statements into 1 equivalence classes. [2025-01-10 07:10:43,938 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 53 of 53 statements. [2025-01-10 07:10:43,939 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:43,939 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:43,944 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:43,945 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:43,945 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 14 times [2025-01-10 07:10:43,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:43,946 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574833353] [2025-01-10 07:10:43,946 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:10:43,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:43,947 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:43,948 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:43,948 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:10:43,948 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:43,948 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:43,949 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:43,949 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:43,949 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:43,949 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:43,950 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:43,951 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:43,951 INFO L85 PathProgramCache]: Analyzing trace with hash -1911729501, now seen corresponding path program 25 times [2025-01-10 07:10:43,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:43,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625098322] [2025-01-10 07:10:43,951 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:43,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:43,958 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-01-10 07:10:43,965 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-01-10 07:10:43,965 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:43,965 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:44,407 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 210 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:44,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:44,408 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625098322] [2025-01-10 07:10:44,408 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [625098322] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:44,408 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1923576301] [2025-01-10 07:10:44,408 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:44,408 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:44,408 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:44,410 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:44,412 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2025-01-10 07:10:44,473 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-01-10 07:10:44,500 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-01-10 07:10:44,500 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:44,500 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:44,506 INFO L256 TraceCheckSpWp]: Trace formula consists of 314 conjuncts, 30 conjuncts are in the unsatisfiable core [2025-01-10 07:10:44,507 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:44,866 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 247 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:44,866 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:45,118 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 247 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:45,118 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1923576301] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:45,118 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:45,118 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29] total 45 [2025-01-10 07:10:45,118 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [637976371] [2025-01-10 07:10:45,118 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:45,149 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:45,150 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2025-01-10 07:10:45,150 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=498, Invalid=1572, Unknown=0, NotChecked=0, Total=2070 [2025-01-10 07:10:45,150 INFO L87 Difference]: Start difference. First operand 101 states and 117 transitions. cyclomatic complexity: 19 Second operand has 46 states, 45 states have (on average 2.2888888888888888) internal successors, (103), 46 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:45,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:45,592 INFO L93 Difference]: Finished difference Result 355 states and 414 transitions. [2025-01-10 07:10:45,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 355 states and 414 transitions. [2025-01-10 07:10:45,594 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:45,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 355 states to 197 states and 229 transitions. [2025-01-10 07:10:45,595 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 183 [2025-01-10 07:10:45,595 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 183 [2025-01-10 07:10:45,595 INFO L73 IsDeterministic]: Start isDeterministic. Operand 197 states and 229 transitions. [2025-01-10 07:10:45,595 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:45,595 INFO L218 hiAutomatonCegarLoop]: Abstraction has 197 states and 229 transitions. [2025-01-10 07:10:45,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states and 229 transitions. [2025-01-10 07:10:45,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 108. [2025-01-10 07:10:45,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.1574074074074074) internal successors, (125), 107 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:45,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 125 transitions. [2025-01-10 07:10:45,598 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 125 transitions. [2025-01-10 07:10:45,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2025-01-10 07:10:45,600 INFO L432 stractBuchiCegarLoop]: Abstraction has 108 states and 125 transitions. [2025-01-10 07:10:45,600 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-01-10 07:10:45,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 125 transitions. [2025-01-10 07:10:45,600 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:45,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:45,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:45,602 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [14, 14, 13, 13, 1, 1, 1] [2025-01-10 07:10:45,602 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:45,603 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:45,603 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:45,605 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:45,605 INFO L85 PathProgramCache]: Analyzing trace with hash -1658561661, now seen corresponding path program 26 times [2025-01-10 07:10:45,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:45,605 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877445127] [2025-01-10 07:10:45,605 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:10:45,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:45,614 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 57 statements into 2 equivalence classes. [2025-01-10 07:10:45,646 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 57 of 57 statements. [2025-01-10 07:10:45,646 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-01-10 07:10:45,646 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:45,646 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:45,650 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 57 statements into 1 equivalence classes. [2025-01-10 07:10:45,676 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 57 of 57 statements. [2025-01-10 07:10:45,677 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:45,677 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:45,681 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:45,682 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:45,682 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 15 times [2025-01-10 07:10:45,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:45,682 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [467062526] [2025-01-10 07:10:45,683 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:45,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:45,684 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:45,685 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:45,685 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:10:45,685 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:45,685 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:45,685 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:45,686 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:45,686 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:45,686 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:45,688 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:45,688 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:45,688 INFO L85 PathProgramCache]: Analyzing trace with hash -906634873, now seen corresponding path program 27 times [2025-01-10 07:10:45,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:45,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14060377] [2025-01-10 07:10:45,689 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:45,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:45,697 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 60 statements into 15 equivalence classes. [2025-01-10 07:10:45,800 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) and asserted 60 of 60 statements. [2025-01-10 07:10:45,800 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2025-01-10 07:10:45,800 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:46,326 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 247 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:46,326 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:46,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [14060377] [2025-01-10 07:10:46,326 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [14060377] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:46,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [672801917] [2025-01-10 07:10:46,326 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:46,326 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:46,326 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:46,329 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:46,331 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2025-01-10 07:10:46,394 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 60 statements into 15 equivalence classes. [2025-01-10 07:10:46,676 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) and asserted 60 of 60 statements. [2025-01-10 07:10:46,677 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2025-01-10 07:10:46,677 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:46,679 INFO L256 TraceCheckSpWp]: Trace formula consists of 335 conjuncts, 32 conjuncts are in the unsatisfiable core [2025-01-10 07:10:46,680 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:47,076 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 287 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:47,076 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:47,346 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 287 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:47,346 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [672801917] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:47,346 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:47,347 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31] total 48 [2025-01-10 07:10:47,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [650704950] [2025-01-10 07:10:47,347 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:47,372 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:47,373 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2025-01-10 07:10:47,373 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=563, Invalid=1789, Unknown=0, NotChecked=0, Total=2352 [2025-01-10 07:10:47,374 INFO L87 Difference]: Start difference. First operand 108 states and 125 transitions. cyclomatic complexity: 20 Second operand has 49 states, 48 states have (on average 2.2916666666666665) internal successors, (110), 49 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:47,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:47,768 INFO L93 Difference]: Finished difference Result 380 states and 443 transitions. [2025-01-10 07:10:47,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 380 states and 443 transitions. [2025-01-10 07:10:47,769 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:47,770 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 380 states to 210 states and 244 transitions. [2025-01-10 07:10:47,770 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2025-01-10 07:10:47,770 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2025-01-10 07:10:47,771 INFO L73 IsDeterministic]: Start isDeterministic. Operand 210 states and 244 transitions. [2025-01-10 07:10:47,771 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:47,771 INFO L218 hiAutomatonCegarLoop]: Abstraction has 210 states and 244 transitions. [2025-01-10 07:10:47,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states and 244 transitions. [2025-01-10 07:10:47,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 115. [2025-01-10 07:10:47,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115 states, 115 states have (on average 1.1565217391304348) internal successors, (133), 114 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:47,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 133 transitions. [2025-01-10 07:10:47,773 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115 states and 133 transitions. [2025-01-10 07:10:47,773 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2025-01-10 07:10:47,774 INFO L432 stractBuchiCegarLoop]: Abstraction has 115 states and 133 transitions. [2025-01-10 07:10:47,774 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-01-10 07:10:47,774 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115 states and 133 transitions. [2025-01-10 07:10:47,774 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:47,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:47,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:47,775 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 15, 14, 14, 1, 1, 1] [2025-01-10 07:10:47,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:47,775 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:47,776 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:47,777 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:47,777 INFO L85 PathProgramCache]: Analyzing trace with hash -224562585, now seen corresponding path program 28 times [2025-01-10 07:10:47,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:47,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594362206] [2025-01-10 07:10:47,777 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:10:47,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:47,786 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 61 statements into 2 equivalence classes. [2025-01-10 07:10:47,821 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 61 of 61 statements. [2025-01-10 07:10:47,821 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:10:47,822 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:47,822 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:47,827 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 61 statements into 1 equivalence classes. [2025-01-10 07:10:47,855 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 61 of 61 statements. [2025-01-10 07:10:47,855 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:47,855 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:47,862 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:47,863 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:47,863 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 16 times [2025-01-10 07:10:47,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:47,863 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725589151] [2025-01-10 07:10:47,863 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:10:47,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:47,865 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-01-10 07:10:47,866 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:47,866 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:10:47,866 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:47,866 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:47,866 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:47,868 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:47,868 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:47,868 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:47,870 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:47,870 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:47,870 INFO L85 PathProgramCache]: Analyzing trace with hash 1615112227, now seen corresponding path program 29 times [2025-01-10 07:10:47,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:47,870 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435134571] [2025-01-10 07:10:47,870 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:47,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:47,879 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 64 statements into 16 equivalence classes. [2025-01-10 07:10:47,909 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) and asserted 64 of 64 statements. [2025-01-10 07:10:47,909 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2025-01-10 07:10:47,909 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:48,437 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 330 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:48,438 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:48,438 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435134571] [2025-01-10 07:10:48,438 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435134571] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:48,438 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [457585821] [2025-01-10 07:10:48,438 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:48,438 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:48,438 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:48,440 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:48,442 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2025-01-10 07:10:48,510 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 64 statements into 16 equivalence classes. [2025-01-10 07:10:48,639 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) and asserted 64 of 64 statements. [2025-01-10 07:10:48,639 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2025-01-10 07:10:48,639 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:48,642 INFO L256 TraceCheckSpWp]: Trace formula consists of 356 conjuncts, 34 conjuncts are in the unsatisfiable core [2025-01-10 07:10:48,644 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:49,091 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 330 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:49,091 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:49,393 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 330 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:49,393 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [457585821] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:49,393 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:49,394 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33] total 49 [2025-01-10 07:10:49,394 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1491806982] [2025-01-10 07:10:49,394 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:49,419 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:49,419 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2025-01-10 07:10:49,420 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=593, Invalid=1857, Unknown=0, NotChecked=0, Total=2450 [2025-01-10 07:10:49,420 INFO L87 Difference]: Start difference. First operand 115 states and 133 transitions. cyclomatic complexity: 21 Second operand has 50 states, 49 states have (on average 2.2653061224489797) internal successors, (111), 50 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:49,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:49,851 INFO L93 Difference]: Finished difference Result 405 states and 472 transitions. [2025-01-10 07:10:49,851 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 405 states and 472 transitions. [2025-01-10 07:10:49,853 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:49,854 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 405 states to 223 states and 259 transitions. [2025-01-10 07:10:49,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 207 [2025-01-10 07:10:49,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 207 [2025-01-10 07:10:49,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 223 states and 259 transitions. [2025-01-10 07:10:49,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:49,854 INFO L218 hiAutomatonCegarLoop]: Abstraction has 223 states and 259 transitions. [2025-01-10 07:10:49,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states and 259 transitions. [2025-01-10 07:10:49,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 122. [2025-01-10 07:10:49,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122 states, 122 states have (on average 1.1557377049180328) internal successors, (141), 121 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:49,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 141 transitions. [2025-01-10 07:10:49,856 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122 states and 141 transitions. [2025-01-10 07:10:49,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2025-01-10 07:10:49,857 INFO L432 stractBuchiCegarLoop]: Abstraction has 122 states and 141 transitions. [2025-01-10 07:10:49,857 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-01-10 07:10:49,857 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122 states and 141 transitions. [2025-01-10 07:10:49,858 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:49,858 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:49,858 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:49,858 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [16, 16, 15, 15, 1, 1, 1] [2025-01-10 07:10:49,858 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:49,858 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:49,858 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:49,859 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:49,859 INFO L85 PathProgramCache]: Analyzing trace with hash 1203032323, now seen corresponding path program 30 times [2025-01-10 07:10:49,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:49,859 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1914904154] [2025-01-10 07:10:49,859 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:10:49,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:49,867 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 65 statements into 16 equivalence classes. [2025-01-10 07:10:49,999 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) and asserted 65 of 65 statements. [2025-01-10 07:10:49,999 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) [2025-01-10 07:10:49,999 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:49,999 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:50,003 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 65 statements into 1 equivalence classes. [2025-01-10 07:10:50,033 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 65 of 65 statements. [2025-01-10 07:10:50,033 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:50,033 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:50,038 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:50,039 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:50,039 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 17 times [2025-01-10 07:10:50,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:50,039 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1468815596] [2025-01-10 07:10:50,039 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:50,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:50,041 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:50,042 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:50,042 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:10:50,042 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:50,042 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:50,042 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:50,043 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:50,043 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:50,043 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:50,045 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:50,045 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:50,045 INFO L85 PathProgramCache]: Analyzing trace with hash -1966115833, now seen corresponding path program 31 times [2025-01-10 07:10:50,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:50,045 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094066729] [2025-01-10 07:10:50,045 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:50,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:50,053 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 68 statements into 1 equivalence classes. [2025-01-10 07:10:50,061 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 68 of 68 statements. [2025-01-10 07:10:50,061 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:50,061 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:50,687 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 330 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:50,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:50,688 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2094066729] [2025-01-10 07:10:50,688 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2094066729] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:50,688 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [892884257] [2025-01-10 07:10:50,688 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:50,688 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:50,688 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:50,690 INFO L229 MonitoredProcess]: Starting monitored process 37 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:50,691 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2025-01-10 07:10:50,766 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 68 statements into 1 equivalence classes. [2025-01-10 07:10:50,805 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 68 of 68 statements. [2025-01-10 07:10:50,805 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:50,805 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:50,807 INFO L256 TraceCheckSpWp]: Trace formula consists of 377 conjuncts, 36 conjuncts are in the unsatisfiable core [2025-01-10 07:10:50,808 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:51,294 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 376 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:51,294 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:51,627 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 376 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:51,628 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [892884257] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:51,628 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:51,628 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35] total 54 [2025-01-10 07:10:51,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260131306] [2025-01-10 07:10:51,628 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:51,663 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:51,664 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2025-01-10 07:10:51,665 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=705, Invalid=2265, Unknown=0, NotChecked=0, Total=2970 [2025-01-10 07:10:51,665 INFO L87 Difference]: Start difference. First operand 122 states and 141 transitions. cyclomatic complexity: 22 Second operand has 55 states, 54 states have (on average 2.2962962962962963) internal successors, (124), 55 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:52,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:52,152 INFO L93 Difference]: Finished difference Result 430 states and 501 transitions. [2025-01-10 07:10:52,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 501 transitions. [2025-01-10 07:10:52,154 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:52,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 236 states and 274 transitions. [2025-01-10 07:10:52,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 219 [2025-01-10 07:10:52,155 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 219 [2025-01-10 07:10:52,155 INFO L73 IsDeterministic]: Start isDeterministic. Operand 236 states and 274 transitions. [2025-01-10 07:10:52,155 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:52,155 INFO L218 hiAutomatonCegarLoop]: Abstraction has 236 states and 274 transitions. [2025-01-10 07:10:52,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states and 274 transitions. [2025-01-10 07:10:52,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 129. [2025-01-10 07:10:52,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 129 states, 129 states have (on average 1.1550387596899225) internal successors, (149), 128 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:52,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 149 transitions. [2025-01-10 07:10:52,161 INFO L240 hiAutomatonCegarLoop]: Abstraction has 129 states and 149 transitions. [2025-01-10 07:10:52,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2025-01-10 07:10:52,162 INFO L432 stractBuchiCegarLoop]: Abstraction has 129 states and 149 transitions. [2025-01-10 07:10:52,162 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-01-10 07:10:52,162 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 129 states and 149 transitions. [2025-01-10 07:10:52,162 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:52,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:52,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:52,163 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [17, 17, 16, 16, 1, 1, 1] [2025-01-10 07:10:52,163 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:52,163 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:52,163 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:52,163 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:52,164 INFO L85 PathProgramCache]: Analyzing trace with hash 2051026151, now seen corresponding path program 32 times [2025-01-10 07:10:52,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:52,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028442726] [2025-01-10 07:10:52,164 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:10:52,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:52,173 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 69 statements into 2 equivalence classes. [2025-01-10 07:10:52,206 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 69 of 69 statements. [2025-01-10 07:10:52,206 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-01-10 07:10:52,206 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:52,207 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:52,211 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 69 statements into 1 equivalence classes. [2025-01-10 07:10:52,273 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 69 of 69 statements. [2025-01-10 07:10:52,274 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:52,274 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:52,281 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:52,281 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:52,282 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 18 times [2025-01-10 07:10:52,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:52,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673790566] [2025-01-10 07:10:52,282 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:10:52,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:52,284 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:52,284 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:52,284 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-01-10 07:10:52,285 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:52,285 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:52,285 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:52,286 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:52,286 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:52,286 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:52,287 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:52,287 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:52,288 INFO L85 PathProgramCache]: Analyzing trace with hash 1915346339, now seen corresponding path program 33 times [2025-01-10 07:10:52,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:52,288 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579806206] [2025-01-10 07:10:52,288 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:52,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:52,299 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 72 statements into 18 equivalence classes. [2025-01-10 07:10:52,513 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) and asserted 72 of 72 statements. [2025-01-10 07:10:52,513 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2025-01-10 07:10:52,514 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:53,188 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 376 proven. 202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:53,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:53,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [579806206] [2025-01-10 07:10:53,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [579806206] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:53,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [563821658] [2025-01-10 07:10:53,188 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:10:53,188 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:53,188 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:53,191 INFO L229 MonitoredProcess]: Starting monitored process 38 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:53,192 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2025-01-10 07:10:53,271 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 72 statements into 18 equivalence classes. [2025-01-10 07:10:53,640 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) and asserted 72 of 72 statements. [2025-01-10 07:10:53,640 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2025-01-10 07:10:53,640 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:53,643 INFO L256 TraceCheckSpWp]: Trace formula consists of 398 conjuncts, 38 conjuncts are in the unsatisfiable core [2025-01-10 07:10:53,644 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:54,100 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 425 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:54,100 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:54,458 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 425 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:54,458 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [563821658] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:54,458 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:54,458 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37, 37] total 57 [2025-01-10 07:10:54,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1649143826] [2025-01-10 07:10:54,458 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:54,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:54,493 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2025-01-10 07:10:54,493 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=782, Invalid=2524, Unknown=0, NotChecked=0, Total=3306 [2025-01-10 07:10:54,493 INFO L87 Difference]: Start difference. First operand 129 states and 149 transitions. cyclomatic complexity: 23 Second operand has 58 states, 57 states have (on average 2.2982456140350878) internal successors, (131), 58 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:55,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:55,014 INFO L93 Difference]: Finished difference Result 455 states and 530 transitions. [2025-01-10 07:10:55,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 455 states and 530 transitions. [2025-01-10 07:10:55,016 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:55,017 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 455 states to 249 states and 289 transitions. [2025-01-10 07:10:55,017 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 231 [2025-01-10 07:10:55,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 231 [2025-01-10 07:10:55,017 INFO L73 IsDeterministic]: Start isDeterministic. Operand 249 states and 289 transitions. [2025-01-10 07:10:55,017 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:55,017 INFO L218 hiAutomatonCegarLoop]: Abstraction has 249 states and 289 transitions. [2025-01-10 07:10:55,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states and 289 transitions. [2025-01-10 07:10:55,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 136. [2025-01-10 07:10:55,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 136 states, 136 states have (on average 1.1544117647058822) internal successors, (157), 135 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:55,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 157 transitions. [2025-01-10 07:10:55,019 INFO L240 hiAutomatonCegarLoop]: Abstraction has 136 states and 157 transitions. [2025-01-10 07:10:55,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2025-01-10 07:10:55,020 INFO L432 stractBuchiCegarLoop]: Abstraction has 136 states and 157 transitions. [2025-01-10 07:10:55,020 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-01-10 07:10:55,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 136 states and 157 transitions. [2025-01-10 07:10:55,021 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:55,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:55,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:55,021 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [18, 18, 17, 17, 1, 1, 1] [2025-01-10 07:10:55,021 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:55,021 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:55,021 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:55,022 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:55,022 INFO L85 PathProgramCache]: Analyzing trace with hash 1456678531, now seen corresponding path program 34 times [2025-01-10 07:10:55,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:55,022 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449477101] [2025-01-10 07:10:55,022 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:10:55,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:55,031 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 73 statements into 2 equivalence classes. [2025-01-10 07:10:55,068 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 73 of 73 statements. [2025-01-10 07:10:55,068 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:10:55,068 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:55,068 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:55,072 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 73 statements into 1 equivalence classes. [2025-01-10 07:10:55,103 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 73 of 73 statements. [2025-01-10 07:10:55,103 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:55,103 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:55,108 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:55,109 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:55,109 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 19 times [2025-01-10 07:10:55,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:55,109 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485571809] [2025-01-10 07:10:55,109 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:55,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:55,111 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:55,112 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:55,112 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:55,112 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:55,112 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:55,112 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:55,113 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:55,113 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:55,113 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:55,114 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:55,115 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:55,115 INFO L85 PathProgramCache]: Analyzing trace with hash -439406969, now seen corresponding path program 35 times [2025-01-10 07:10:55,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:55,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753357029] [2025-01-10 07:10:55,115 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:55,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:55,124 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 76 statements into 19 equivalence classes. [2025-01-10 07:10:55,151 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) and asserted 76 of 76 statements. [2025-01-10 07:10:55,151 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2025-01-10 07:10:55,151 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:55,864 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:55,865 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:55,865 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [753357029] [2025-01-10 07:10:55,865 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [753357029] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:55,865 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [800275099] [2025-01-10 07:10:55,865 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:10:55,865 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:55,865 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:55,867 INFO L229 MonitoredProcess]: Starting monitored process 39 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:55,868 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2025-01-10 07:10:55,949 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 76 statements into 19 equivalence classes. [2025-01-10 07:10:56,325 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) and asserted 76 of 76 statements. [2025-01-10 07:10:56,326 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2025-01-10 07:10:56,326 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:56,332 INFO L256 TraceCheckSpWp]: Trace formula consists of 419 conjuncts, 40 conjuncts are in the unsatisfiable core [2025-01-10 07:10:56,333 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:56,903 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:56,903 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:57,277 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:57,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [800275099] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:57,278 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:57,278 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39, 39] total 58 [2025-01-10 07:10:57,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440384830] [2025-01-10 07:10:57,278 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:10:57,314 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:10:57,315 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2025-01-10 07:10:57,315 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=818, Invalid=2604, Unknown=0, NotChecked=0, Total=3422 [2025-01-10 07:10:57,316 INFO L87 Difference]: Start difference. First operand 136 states and 157 transitions. cyclomatic complexity: 24 Second operand has 59 states, 58 states have (on average 2.2758620689655173) internal successors, (132), 59 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:57,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:10:57,889 INFO L93 Difference]: Finished difference Result 480 states and 559 transitions. [2025-01-10 07:10:57,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 559 transitions. [2025-01-10 07:10:57,891 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:57,892 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 262 states and 304 transitions. [2025-01-10 07:10:57,892 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 243 [2025-01-10 07:10:57,892 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 243 [2025-01-10 07:10:57,892 INFO L73 IsDeterministic]: Start isDeterministic. Operand 262 states and 304 transitions. [2025-01-10 07:10:57,892 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:10:57,892 INFO L218 hiAutomatonCegarLoop]: Abstraction has 262 states and 304 transitions. [2025-01-10 07:10:57,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 262 states and 304 transitions. [2025-01-10 07:10:57,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 262 to 143. [2025-01-10 07:10:57,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 143 states, 143 states have (on average 1.1538461538461537) internal successors, (165), 142 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:10:57,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 165 transitions. [2025-01-10 07:10:57,895 INFO L240 hiAutomatonCegarLoop]: Abstraction has 143 states and 165 transitions. [2025-01-10 07:10:57,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2025-01-10 07:10:57,895 INFO L432 stractBuchiCegarLoop]: Abstraction has 143 states and 165 transitions. [2025-01-10 07:10:57,895 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-01-10 07:10:57,895 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 143 states and 165 transitions. [2025-01-10 07:10:57,896 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:10:57,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:10:57,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:10:57,896 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [19, 19, 18, 18, 1, 1, 1] [2025-01-10 07:10:57,896 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:10:57,897 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:57,897 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:10:57,897 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:57,897 INFO L85 PathProgramCache]: Analyzing trace with hash 1357449063, now seen corresponding path program 36 times [2025-01-10 07:10:57,897 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:57,897 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745421568] [2025-01-10 07:10:57,897 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:10:57,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:57,907 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 77 statements into 19 equivalence classes. [2025-01-10 07:10:58,029 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) and asserted 77 of 77 statements. [2025-01-10 07:10:58,029 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2025-01-10 07:10:58,029 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:58,029 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:58,034 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-01-10 07:10:58,085 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-01-10 07:10:58,085 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:58,085 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:58,092 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:58,093 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:58,093 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 20 times [2025-01-10 07:10:58,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:58,093 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446165559] [2025-01-10 07:10:58,093 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:10:58,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:58,096 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:58,097 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:58,097 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:10:58,097 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:58,097 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:10:58,097 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:10:58,098 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:10:58,098 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:58,098 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:10:58,100 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:10:58,100 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:10:58,100 INFO L85 PathProgramCache]: Analyzing trace with hash -1646988509, now seen corresponding path program 37 times [2025-01-10 07:10:58,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:10:58,100 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241082137] [2025-01-10 07:10:58,100 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:58,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:10:58,115 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-01-10 07:10:58,126 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-01-10 07:10:58,126 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:58,126 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:58,875 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 477 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:58,876 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:10:58,876 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241082137] [2025-01-10 07:10:58,876 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241082137] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:10:58,876 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [565641601] [2025-01-10 07:10:58,876 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:10:58,876 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:10:58,876 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:10:58,878 INFO L229 MonitoredProcess]: Starting monitored process 40 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:10:58,879 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2025-01-10 07:10:58,976 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-01-10 07:10:59,008 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-01-10 07:10:59,008 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:10:59,008 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:10:59,010 INFO L256 TraceCheckSpWp]: Trace formula consists of 440 conjuncts, 42 conjuncts are in the unsatisfiable core [2025-01-10 07:10:59,011 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:10:59,567 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 532 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:59,567 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:10:59,984 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 532 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:10:59,985 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [565641601] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:10:59,985 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:10:59,985 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41, 41] total 63 [2025-01-10 07:10:59,985 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [108759647] [2025-01-10 07:10:59,985 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:11:00,017 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:11:00,018 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2025-01-10 07:11:00,019 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=948, Invalid=3084, Unknown=0, NotChecked=0, Total=4032 [2025-01-10 07:11:00,019 INFO L87 Difference]: Start difference. First operand 143 states and 165 transitions. cyclomatic complexity: 25 Second operand has 64 states, 63 states have (on average 2.3015873015873014) internal successors, (145), 64 states have internal predecessors, (145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:00,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:11:00,628 INFO L93 Difference]: Finished difference Result 505 states and 588 transitions. [2025-01-10 07:11:00,628 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 505 states and 588 transitions. [2025-01-10 07:11:00,630 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:00,631 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 505 states to 275 states and 319 transitions. [2025-01-10 07:11:00,631 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 255 [2025-01-10 07:11:00,631 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 255 [2025-01-10 07:11:00,631 INFO L73 IsDeterministic]: Start isDeterministic. Operand 275 states and 319 transitions. [2025-01-10 07:11:00,631 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:11:00,631 INFO L218 hiAutomatonCegarLoop]: Abstraction has 275 states and 319 transitions. [2025-01-10 07:11:00,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 275 states and 319 transitions. [2025-01-10 07:11:00,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 275 to 150. [2025-01-10 07:11:00,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 150 states, 150 states have (on average 1.1533333333333333) internal successors, (173), 149 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:00,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 173 transitions. [2025-01-10 07:11:00,633 INFO L240 hiAutomatonCegarLoop]: Abstraction has 150 states and 173 transitions. [2025-01-10 07:11:00,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2025-01-10 07:11:00,634 INFO L432 stractBuchiCegarLoop]: Abstraction has 150 states and 173 transitions. [2025-01-10 07:11:00,634 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-01-10 07:11:00,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 150 states and 173 transitions. [2025-01-10 07:11:00,635 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:00,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:11:00,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:11:00,635 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [20, 20, 19, 19, 1, 1, 1] [2025-01-10 07:11:00,635 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:11:00,635 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:00,635 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:00,635 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:00,636 INFO L85 PathProgramCache]: Analyzing trace with hash -996713469, now seen corresponding path program 38 times [2025-01-10 07:11:00,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:00,636 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [525936664] [2025-01-10 07:11:00,636 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:11:00,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:00,648 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 81 statements into 2 equivalence classes. [2025-01-10 07:11:00,685 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 81 of 81 statements. [2025-01-10 07:11:00,685 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-01-10 07:11:00,685 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:00,686 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:00,691 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-01-10 07:11:00,730 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-01-10 07:11:00,730 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:00,730 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:00,737 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:00,738 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:00,738 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 21 times [2025-01-10 07:11:00,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:00,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698009411] [2025-01-10 07:11:00,738 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:11:00,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:00,741 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:00,741 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:00,741 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:11:00,741 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:00,741 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:00,742 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:00,742 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:00,742 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:00,742 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:00,744 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:00,745 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:00,745 INFO L85 PathProgramCache]: Analyzing trace with hash -1982002937, now seen corresponding path program 39 times [2025-01-10 07:11:00,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:00,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773632211] [2025-01-10 07:11:00,745 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:11:00,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:00,756 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 84 statements into 21 equivalence classes. [2025-01-10 07:11:01,040 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) and asserted 84 of 84 statements. [2025-01-10 07:11:01,040 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2025-01-10 07:11:01,040 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:01,813 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 532 proven. 268 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:01,813 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:11:01,813 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [773632211] [2025-01-10 07:11:01,813 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [773632211] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:11:01,813 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1319815949] [2025-01-10 07:11:01,813 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:11:01,813 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:11:01,813 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:11:01,815 INFO L229 MonitoredProcess]: Starting monitored process 41 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:11:01,816 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2025-01-10 07:11:01,908 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 84 statements into 21 equivalence classes. [2025-01-10 07:11:02,582 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) and asserted 84 of 84 statements. [2025-01-10 07:11:02,582 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2025-01-10 07:11:02,582 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:02,585 INFO L256 TraceCheckSpWp]: Trace formula consists of 461 conjuncts, 44 conjuncts are in the unsatisfiable core [2025-01-10 07:11:02,587 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:11:03,178 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 590 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:03,178 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:11:03,630 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 590 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:03,630 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1319815949] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:11:03,630 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:11:03,630 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43, 43] total 66 [2025-01-10 07:11:03,631 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888516113] [2025-01-10 07:11:03,631 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:11:03,656 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:11:03,656 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2025-01-10 07:11:03,657 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1037, Invalid=3385, Unknown=0, NotChecked=0, Total=4422 [2025-01-10 07:11:03,658 INFO L87 Difference]: Start difference. First operand 150 states and 173 transitions. cyclomatic complexity: 26 Second operand has 67 states, 66 states have (on average 2.303030303030303) internal successors, (152), 67 states have internal predecessors, (152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:04,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:11:04,338 INFO L93 Difference]: Finished difference Result 530 states and 617 transitions. [2025-01-10 07:11:04,338 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 530 states and 617 transitions. [2025-01-10 07:11:04,340 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:04,341 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 530 states to 288 states and 334 transitions. [2025-01-10 07:11:04,341 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 267 [2025-01-10 07:11:04,341 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 267 [2025-01-10 07:11:04,341 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 334 transitions. [2025-01-10 07:11:04,342 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:11:04,342 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 334 transitions. [2025-01-10 07:11:04,342 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 334 transitions. [2025-01-10 07:11:04,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 157. [2025-01-10 07:11:04,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 157 states, 157 states have (on average 1.1528662420382165) internal successors, (181), 156 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:04,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 181 transitions. [2025-01-10 07:11:04,344 INFO L240 hiAutomatonCegarLoop]: Abstraction has 157 states and 181 transitions. [2025-01-10 07:11:04,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2025-01-10 07:11:04,345 INFO L432 stractBuchiCegarLoop]: Abstraction has 157 states and 181 transitions. [2025-01-10 07:11:04,345 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-01-10 07:11:04,345 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 157 states and 181 transitions. [2025-01-10 07:11:04,346 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:04,346 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:11:04,346 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:11:04,346 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [21, 21, 20, 20, 1, 1, 1] [2025-01-10 07:11:04,346 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:11:04,346 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:04,347 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:04,347 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:04,347 INFO L85 PathProgramCache]: Analyzing trace with hash 1166016999, now seen corresponding path program 40 times [2025-01-10 07:11:04,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:04,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1761224621] [2025-01-10 07:11:04,347 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:11:04,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:04,362 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 85 statements into 2 equivalence classes. [2025-01-10 07:11:04,440 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 85 of 85 statements. [2025-01-10 07:11:04,440 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:11:04,440 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:04,440 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:04,444 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 85 statements into 1 equivalence classes. [2025-01-10 07:11:04,483 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 85 of 85 statements. [2025-01-10 07:11:04,483 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:04,483 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:04,489 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:04,490 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:04,490 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 22 times [2025-01-10 07:11:04,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:04,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [197295792] [2025-01-10 07:11:04,490 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:11:04,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:04,492 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-01-10 07:11:04,493 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:04,493 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:11:04,493 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:04,493 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:04,493 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:04,494 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:04,494 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:04,494 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:04,495 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:04,496 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:04,496 INFO L85 PathProgramCache]: Analyzing trace with hash -883038045, now seen corresponding path program 41 times [2025-01-10 07:11:04,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:04,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211917225] [2025-01-10 07:11:04,496 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:11:04,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:04,506 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 88 statements into 22 equivalence classes. [2025-01-10 07:11:04,544 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) and asserted 88 of 88 statements. [2025-01-10 07:11:04,544 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2025-01-10 07:11:04,544 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:05,353 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:05,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:11:05,353 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211917225] [2025-01-10 07:11:05,353 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1211917225] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:11:05,353 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [93298847] [2025-01-10 07:11:05,353 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:11:05,353 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:11:05,353 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:11:05,355 INFO L229 MonitoredProcess]: Starting monitored process 42 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:11:05,356 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2025-01-10 07:11:05,455 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 88 statements into 22 equivalence classes. [2025-01-10 07:11:05,912 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) and asserted 88 of 88 statements. [2025-01-10 07:11:05,912 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2025-01-10 07:11:05,912 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:05,917 INFO L256 TraceCheckSpWp]: Trace formula consists of 482 conjuncts, 46 conjuncts are in the unsatisfiable core [2025-01-10 07:11:05,918 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:11:06,578 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:06,578 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:11:07,046 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:07,046 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [93298847] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:11:07,046 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:11:07,046 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45, 45] total 67 [2025-01-10 07:11:07,046 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000454579] [2025-01-10 07:11:07,046 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:11:07,072 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:11:07,072 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2025-01-10 07:11:07,073 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1079, Invalid=3477, Unknown=0, NotChecked=0, Total=4556 [2025-01-10 07:11:07,074 INFO L87 Difference]: Start difference. First operand 157 states and 181 transitions. cyclomatic complexity: 27 Second operand has 68 states, 67 states have (on average 2.283582089552239) internal successors, (153), 68 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:07,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:11:07,771 INFO L93 Difference]: Finished difference Result 555 states and 646 transitions. [2025-01-10 07:11:07,771 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 555 states and 646 transitions. [2025-01-10 07:11:07,772 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:07,775 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 555 states to 301 states and 349 transitions. [2025-01-10 07:11:07,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 279 [2025-01-10 07:11:07,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 279 [2025-01-10 07:11:07,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 301 states and 349 transitions. [2025-01-10 07:11:07,775 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:11:07,775 INFO L218 hiAutomatonCegarLoop]: Abstraction has 301 states and 349 transitions. [2025-01-10 07:11:07,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 301 states and 349 transitions. [2025-01-10 07:11:07,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 301 to 164. [2025-01-10 07:11:07,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 164 states, 164 states have (on average 1.1524390243902438) internal successors, (189), 163 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:07,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 189 transitions. [2025-01-10 07:11:07,778 INFO L240 hiAutomatonCegarLoop]: Abstraction has 164 states and 189 transitions. [2025-01-10 07:11:07,781 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2025-01-10 07:11:07,782 INFO L432 stractBuchiCegarLoop]: Abstraction has 164 states and 189 transitions. [2025-01-10 07:11:07,782 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-01-10 07:11:07,782 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 164 states and 189 transitions. [2025-01-10 07:11:07,782 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:07,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:11:07,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:11:07,783 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 21, 21, 1, 1, 1] [2025-01-10 07:11:07,783 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:11:07,783 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:07,783 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:07,784 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:07,784 INFO L85 PathProgramCache]: Analyzing trace with hash -1726385789, now seen corresponding path program 42 times [2025-01-10 07:11:07,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:07,784 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265248403] [2025-01-10 07:11:07,784 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:11:07,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:07,799 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 89 statements into 22 equivalence classes. [2025-01-10 07:11:08,017 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) and asserted 89 of 89 statements. [2025-01-10 07:11:08,018 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2025-01-10 07:11:08,018 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:08,018 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:08,024 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-01-10 07:11:08,071 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-01-10 07:11:08,071 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:08,071 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:08,077 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:08,078 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:08,078 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 23 times [2025-01-10 07:11:08,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:08,078 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882065328] [2025-01-10 07:11:08,078 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:11:08,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:08,081 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:08,081 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:08,081 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:11:08,081 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:08,082 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:08,082 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:08,082 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:08,082 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:08,083 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:08,084 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:08,085 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:08,085 INFO L85 PathProgramCache]: Analyzing trace with hash 1474364295, now seen corresponding path program 43 times [2025-01-10 07:11:08,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:08,085 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [168238551] [2025-01-10 07:11:08,085 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:11:08,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:08,098 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 92 statements into 1 equivalence classes. [2025-01-10 07:11:08,107 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 92 of 92 statements. [2025-01-10 07:11:08,107 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:08,107 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:08,936 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 651 proven. 317 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:08,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:11:08,936 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [168238551] [2025-01-10 07:11:08,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [168238551] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:11:08,936 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [967059538] [2025-01-10 07:11:08,936 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:11:08,936 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:11:08,936 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:11:08,938 INFO L229 MonitoredProcess]: Starting monitored process 43 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:11:08,939 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2025-01-10 07:11:09,042 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 92 statements into 1 equivalence classes. [2025-01-10 07:11:09,078 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 92 of 92 statements. [2025-01-10 07:11:09,079 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:09,079 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:09,082 INFO L256 TraceCheckSpWp]: Trace formula consists of 503 conjuncts, 48 conjuncts are in the unsatisfiable core [2025-01-10 07:11:09,083 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:11:09,760 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 715 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:09,760 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:11:10,269 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 715 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:10,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [967059538] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:11:10,269 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:11:10,269 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47, 47] total 72 [2025-01-10 07:11:10,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73352661] [2025-01-10 07:11:10,269 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:11:10,294 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:11:10,294 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2025-01-10 07:11:10,295 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1227, Invalid=4029, Unknown=0, NotChecked=0, Total=5256 [2025-01-10 07:11:10,296 INFO L87 Difference]: Start difference. First operand 164 states and 189 transitions. cyclomatic complexity: 28 Second operand has 73 states, 72 states have (on average 2.3055555555555554) internal successors, (166), 73 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:11,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:11:11,021 INFO L93 Difference]: Finished difference Result 580 states and 675 transitions. [2025-01-10 07:11:11,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 580 states and 675 transitions. [2025-01-10 07:11:11,023 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:11,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 580 states to 314 states and 364 transitions. [2025-01-10 07:11:11,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 291 [2025-01-10 07:11:11,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291 [2025-01-10 07:11:11,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 314 states and 364 transitions. [2025-01-10 07:11:11,024 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:11:11,024 INFO L218 hiAutomatonCegarLoop]: Abstraction has 314 states and 364 transitions. [2025-01-10 07:11:11,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 314 states and 364 transitions. [2025-01-10 07:11:11,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 314 to 171. [2025-01-10 07:11:11,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 171 states, 171 states have (on average 1.152046783625731) internal successors, (197), 170 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:11,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 197 transitions. [2025-01-10 07:11:11,028 INFO L240 hiAutomatonCegarLoop]: Abstraction has 171 states and 197 transitions. [2025-01-10 07:11:11,028 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2025-01-10 07:11:11,028 INFO L432 stractBuchiCegarLoop]: Abstraction has 171 states and 197 transitions. [2025-01-10 07:11:11,028 INFO L338 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-01-10 07:11:11,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 171 states and 197 transitions. [2025-01-10 07:11:11,029 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:11,029 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:11:11,029 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:11:11,029 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 23, 22, 22, 1, 1, 1] [2025-01-10 07:11:11,029 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:11:11,029 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:11,030 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:11,030 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:11,030 INFO L85 PathProgramCache]: Analyzing trace with hash 1491934311, now seen corresponding path program 44 times [2025-01-10 07:11:11,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:11,030 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [471931828] [2025-01-10 07:11:11,030 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:11:11,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:11,041 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 93 statements into 2 equivalence classes. [2025-01-10 07:11:11,087 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 93 of 93 statements. [2025-01-10 07:11:11,087 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-01-10 07:11:11,087 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:11,087 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:11,092 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 93 statements into 1 equivalence classes. [2025-01-10 07:11:11,138 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 93 of 93 statements. [2025-01-10 07:11:11,138 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:11,138 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:11,146 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:11,146 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:11,146 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 24 times [2025-01-10 07:11:11,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:11,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814354510] [2025-01-10 07:11:11,147 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:11:11,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:11,149 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:11,150 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:11,150 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-01-10 07:11:11,150 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:11,150 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:11,150 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:11,151 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:11,151 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:11,151 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:11,153 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:11,153 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:11,153 INFO L85 PathProgramCache]: Analyzing trace with hash 1893514787, now seen corresponding path program 45 times [2025-01-10 07:11:11,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:11,153 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1050172161] [2025-01-10 07:11:11,153 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:11:11,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:11,165 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 96 statements into 24 equivalence classes. [2025-01-10 07:11:11,592 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) and asserted 96 of 96 statements. [2025-01-10 07:11:11,592 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2025-01-10 07:11:11,592 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:12,476 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 715 proven. 343 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:12,477 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:11:12,477 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1050172161] [2025-01-10 07:11:12,477 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1050172161] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:11:12,477 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [624407190] [2025-01-10 07:11:12,477 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:11:12,477 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:11:12,477 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:11:12,479 INFO L229 MonitoredProcess]: Starting monitored process 44 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:11:12,480 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2025-01-10 07:11:12,588 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 96 statements into 24 equivalence classes. [2025-01-10 07:11:14,947 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) and asserted 96 of 96 statements. [2025-01-10 07:11:14,948 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2025-01-10 07:11:14,948 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:14,955 INFO L256 TraceCheckSpWp]: Trace formula consists of 524 conjuncts, 50 conjuncts are in the unsatisfiable core [2025-01-10 07:11:14,956 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:11:15,700 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 782 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:15,700 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:11:16,258 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 782 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:16,258 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [624407190] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:11:16,258 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:11:16,258 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49] total 75 [2025-01-10 07:11:16,258 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [17685534] [2025-01-10 07:11:16,258 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:11:16,290 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:11:16,290 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2025-01-10 07:11:16,292 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1328, Invalid=4372, Unknown=0, NotChecked=0, Total=5700 [2025-01-10 07:11:16,292 INFO L87 Difference]: Start difference. First operand 171 states and 197 transitions. cyclomatic complexity: 29 Second operand has 76 states, 75 states have (on average 2.3066666666666666) internal successors, (173), 76 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:17,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:11:17,082 INFO L93 Difference]: Finished difference Result 605 states and 704 transitions. [2025-01-10 07:11:17,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 605 states and 704 transitions. [2025-01-10 07:11:17,085 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:17,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 605 states to 327 states and 379 transitions. [2025-01-10 07:11:17,086 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 303 [2025-01-10 07:11:17,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 303 [2025-01-10 07:11:17,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 379 transitions. [2025-01-10 07:11:17,086 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:11:17,086 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 379 transitions. [2025-01-10 07:11:17,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 379 transitions. [2025-01-10 07:11:17,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 178. [2025-01-10 07:11:17,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.151685393258427) internal successors, (205), 177 states have internal predecessors, (205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:17,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 205 transitions. [2025-01-10 07:11:17,089 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 205 transitions. [2025-01-10 07:11:17,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2025-01-10 07:11:17,090 INFO L432 stractBuchiCegarLoop]: Abstraction has 178 states and 205 transitions. [2025-01-10 07:11:17,090 INFO L338 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2025-01-10 07:11:17,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 205 transitions. [2025-01-10 07:11:17,091 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:17,091 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:11:17,091 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:11:17,091 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 24, 23, 23, 1, 1, 1] [2025-01-10 07:11:17,091 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:11:17,091 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:17,092 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:17,092 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:17,092 INFO L85 PathProgramCache]: Analyzing trace with hash 1785816835, now seen corresponding path program 46 times [2025-01-10 07:11:17,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:17,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431386027] [2025-01-10 07:11:17,092 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:11:17,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:17,107 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 97 statements into 2 equivalence classes. [2025-01-10 07:11:17,205 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 97 of 97 statements. [2025-01-10 07:11:17,205 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:11:17,205 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:17,205 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:17,211 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 97 statements into 1 equivalence classes. [2025-01-10 07:11:17,289 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 97 of 97 statements. [2025-01-10 07:11:17,290 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:17,290 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:17,299 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:17,300 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:17,300 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 25 times [2025-01-10 07:11:17,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:17,300 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114083894] [2025-01-10 07:11:17,300 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:11:17,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:17,304 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:17,304 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:17,304 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:17,304 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:17,305 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:17,305 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:17,306 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:17,306 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:17,306 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:17,307 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:17,308 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:17,308 INFO L85 PathProgramCache]: Analyzing trace with hash -490529273, now seen corresponding path program 47 times [2025-01-10 07:11:17,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:17,308 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [376762298] [2025-01-10 07:11:17,308 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:11:17,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:17,323 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 100 statements into 25 equivalence classes. [2025-01-10 07:11:17,383 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) and asserted 100 of 100 statements. [2025-01-10 07:11:17,383 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2025-01-10 07:11:17,383 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:18,371 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:18,371 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:11:18,371 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [376762298] [2025-01-10 07:11:18,371 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [376762298] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:11:18,371 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1018072989] [2025-01-10 07:11:18,371 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:11:18,372 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:11:18,372 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:11:18,374 INFO L229 MonitoredProcess]: Starting monitored process 45 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:11:18,375 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2025-01-10 07:11:18,501 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 100 statements into 25 equivalence classes. [2025-01-10 07:11:19,224 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) and asserted 100 of 100 statements. [2025-01-10 07:11:19,224 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2025-01-10 07:11:19,224 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:19,230 INFO L256 TraceCheckSpWp]: Trace formula consists of 545 conjuncts, 52 conjuncts are in the unsatisfiable core [2025-01-10 07:11:19,232 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:11:20,034 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:20,035 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:11:20,654 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:20,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1018072989] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:11:20,654 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:11:20,654 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51, 51] total 76 [2025-01-10 07:11:20,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000203180] [2025-01-10 07:11:20,654 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:11:20,680 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:11:20,681 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2025-01-10 07:11:20,682 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1376, Invalid=4476, Unknown=0, NotChecked=0, Total=5852 [2025-01-10 07:11:20,683 INFO L87 Difference]: Start difference. First operand 178 states and 205 transitions. cyclomatic complexity: 30 Second operand has 77 states, 76 states have (on average 2.289473684210526) internal successors, (174), 77 states have internal predecessors, (174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:21,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:11:21,542 INFO L93 Difference]: Finished difference Result 630 states and 733 transitions. [2025-01-10 07:11:21,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 630 states and 733 transitions. [2025-01-10 07:11:21,544 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:21,545 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 630 states to 340 states and 394 transitions. [2025-01-10 07:11:21,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 315 [2025-01-10 07:11:21,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 315 [2025-01-10 07:11:21,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 340 states and 394 transitions. [2025-01-10 07:11:21,546 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:11:21,546 INFO L218 hiAutomatonCegarLoop]: Abstraction has 340 states and 394 transitions. [2025-01-10 07:11:21,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states and 394 transitions. [2025-01-10 07:11:21,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 185. [2025-01-10 07:11:21,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 185 states, 185 states have (on average 1.1513513513513514) internal successors, (213), 184 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:21,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 213 transitions. [2025-01-10 07:11:21,548 INFO L240 hiAutomatonCegarLoop]: Abstraction has 185 states and 213 transitions. [2025-01-10 07:11:21,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2025-01-10 07:11:21,549 INFO L432 stractBuchiCegarLoop]: Abstraction has 185 states and 213 transitions. [2025-01-10 07:11:21,549 INFO L338 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2025-01-10 07:11:21,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 185 states and 213 transitions. [2025-01-10 07:11:21,550 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:21,550 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:11:21,550 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:11:21,550 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [25, 25, 24, 24, 1, 1, 1] [2025-01-10 07:11:21,550 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:11:21,551 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:21,551 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:21,551 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:21,551 INFO L85 PathProgramCache]: Analyzing trace with hash 1041782503, now seen corresponding path program 48 times [2025-01-10 07:11:21,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:21,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1059194545] [2025-01-10 07:11:21,551 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:11:21,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:21,563 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 101 statements into 25 equivalence classes. [2025-01-10 07:11:21,743 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) and asserted 101 of 101 statements. [2025-01-10 07:11:21,743 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2025-01-10 07:11:21,743 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:21,743 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:21,749 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 101 statements into 1 equivalence classes. [2025-01-10 07:11:21,828 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 101 of 101 statements. [2025-01-10 07:11:21,828 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:21,828 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:21,836 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:21,837 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:21,837 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 26 times [2025-01-10 07:11:21,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:21,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [846300588] [2025-01-10 07:11:21,837 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:11:21,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:21,840 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:21,840 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:21,840 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:11:21,840 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:21,840 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:21,840 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:21,841 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:21,841 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:21,841 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:21,843 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:21,843 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:21,843 INFO L85 PathProgramCache]: Analyzing trace with hash 308900771, now seen corresponding path program 49 times [2025-01-10 07:11:21,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:21,843 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415754621] [2025-01-10 07:11:21,843 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:11:21,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:21,855 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 104 statements into 1 equivalence classes. [2025-01-10 07:11:21,865 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 104 of 104 statements. [2025-01-10 07:11:21,865 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:21,865 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:22,883 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 852 proven. 398 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:22,883 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:11:22,883 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [415754621] [2025-01-10 07:11:22,883 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [415754621] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:11:22,883 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2071854313] [2025-01-10 07:11:22,883 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:11:22,883 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:11:22,883 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:11:22,885 INFO L229 MonitoredProcess]: Starting monitored process 46 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:11:22,886 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2025-01-10 07:11:23,009 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 104 statements into 1 equivalence classes. [2025-01-10 07:11:23,049 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 104 of 104 statements. [2025-01-10 07:11:23,049 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:23,049 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:23,052 INFO L256 TraceCheckSpWp]: Trace formula consists of 566 conjuncts, 54 conjuncts are in the unsatisfiable core [2025-01-10 07:11:23,053 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:11:23,921 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 925 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:23,921 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:11:24,573 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 925 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:24,574 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2071854313] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:11:24,574 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:11:24,574 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53, 53] total 81 [2025-01-10 07:11:24,574 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1591804547] [2025-01-10 07:11:24,574 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:11:24,607 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:11:24,608 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2025-01-10 07:11:24,609 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1542, Invalid=5100, Unknown=0, NotChecked=0, Total=6642 [2025-01-10 07:11:24,609 INFO L87 Difference]: Start difference. First operand 185 states and 213 transitions. cyclomatic complexity: 31 Second operand has 82 states, 81 states have (on average 2.308641975308642) internal successors, (187), 82 states have internal predecessors, (187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:25,451 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:11:25,451 INFO L93 Difference]: Finished difference Result 655 states and 762 transitions. [2025-01-10 07:11:25,451 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 655 states and 762 transitions. [2025-01-10 07:11:25,453 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:25,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 655 states to 353 states and 409 transitions. [2025-01-10 07:11:25,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2025-01-10 07:11:25,454 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2025-01-10 07:11:25,454 INFO L73 IsDeterministic]: Start isDeterministic. Operand 353 states and 409 transitions. [2025-01-10 07:11:25,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:11:25,455 INFO L218 hiAutomatonCegarLoop]: Abstraction has 353 states and 409 transitions. [2025-01-10 07:11:25,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 353 states and 409 transitions. [2025-01-10 07:11:25,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 353 to 192. [2025-01-10 07:11:25,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 192 states, 192 states have (on average 1.1510416666666667) internal successors, (221), 191 states have internal predecessors, (221), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:25,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 221 transitions. [2025-01-10 07:11:25,457 INFO L240 hiAutomatonCegarLoop]: Abstraction has 192 states and 221 transitions. [2025-01-10 07:11:25,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2025-01-10 07:11:25,458 INFO L432 stractBuchiCegarLoop]: Abstraction has 192 states and 221 transitions. [2025-01-10 07:11:25,458 INFO L338 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2025-01-10 07:11:25,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 192 states and 221 transitions. [2025-01-10 07:11:25,458 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:25,458 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:11:25,458 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:11:25,459 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [26, 26, 25, 25, 1, 1, 1] [2025-01-10 07:11:25,459 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:11:25,459 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:25,459 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:25,459 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:25,459 INFO L85 PathProgramCache]: Analyzing trace with hash -591971197, now seen corresponding path program 50 times [2025-01-10 07:11:25,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:25,459 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257187074] [2025-01-10 07:11:25,460 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:11:25,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:25,472 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 105 statements into 2 equivalence classes. [2025-01-10 07:11:25,522 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 105 of 105 statements. [2025-01-10 07:11:25,522 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-01-10 07:11:25,522 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:25,522 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:25,528 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 105 statements into 1 equivalence classes. [2025-01-10 07:11:25,596 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 105 of 105 statements. [2025-01-10 07:11:25,596 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:25,596 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:25,604 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:25,605 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:25,605 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 27 times [2025-01-10 07:11:25,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:25,605 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636271521] [2025-01-10 07:11:25,605 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:11:25,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:25,608 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:25,608 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:25,608 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:11:25,608 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:25,608 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:25,609 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:25,609 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:25,609 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:25,609 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:25,611 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:25,611 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:25,611 INFO L85 PathProgramCache]: Analyzing trace with hash -278177657, now seen corresponding path program 51 times [2025-01-10 07:11:25,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:25,612 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759699875] [2025-01-10 07:11:25,612 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:11:25,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:25,624 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 108 statements into 27 equivalence classes. [2025-01-10 07:11:26,030 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) and asserted 108 of 108 statements. [2025-01-10 07:11:26,030 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2025-01-10 07:11:26,031 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:27,104 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 925 proven. 427 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:27,105 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:11:27,105 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1759699875] [2025-01-10 07:11:27,105 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1759699875] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:11:27,105 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [938400642] [2025-01-10 07:11:27,105 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:11:27,105 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:11:27,105 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:11:27,107 INFO L229 MonitoredProcess]: Starting monitored process 47 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:11:27,108 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2025-01-10 07:11:27,251 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 108 statements into 27 equivalence classes. [2025-01-10 07:11:30,363 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) and asserted 108 of 108 statements. [2025-01-10 07:11:30,363 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2025-01-10 07:11:30,363 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:30,372 INFO L256 TraceCheckSpWp]: Trace formula consists of 587 conjuncts, 56 conjuncts are in the unsatisfiable core [2025-01-10 07:11:30,374 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:11:31,273 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 1001 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:31,273 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:11:31,958 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 1001 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:31,958 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [938400642] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:11:31,958 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:11:31,958 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55, 55] total 84 [2025-01-10 07:11:31,958 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [457364036] [2025-01-10 07:11:31,958 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:11:31,983 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:11:31,984 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2025-01-10 07:11:31,985 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1655, Invalid=5485, Unknown=0, NotChecked=0, Total=7140 [2025-01-10 07:11:31,985 INFO L87 Difference]: Start difference. First operand 192 states and 221 transitions. cyclomatic complexity: 32 Second operand has 85 states, 84 states have (on average 2.3095238095238093) internal successors, (194), 85 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:32,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:11:32,917 INFO L93 Difference]: Finished difference Result 680 states and 791 transitions. [2025-01-10 07:11:32,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 680 states and 791 transitions. [2025-01-10 07:11:32,919 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:32,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 680 states to 366 states and 424 transitions. [2025-01-10 07:11:32,920 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 339 [2025-01-10 07:11:32,920 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 339 [2025-01-10 07:11:32,921 INFO L73 IsDeterministic]: Start isDeterministic. Operand 366 states and 424 transitions. [2025-01-10 07:11:32,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:11:32,921 INFO L218 hiAutomatonCegarLoop]: Abstraction has 366 states and 424 transitions. [2025-01-10 07:11:32,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states and 424 transitions. [2025-01-10 07:11:32,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 199. [2025-01-10 07:11:32,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 199 states, 199 states have (on average 1.150753768844221) internal successors, (229), 198 states have internal predecessors, (229), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:32,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 229 transitions. [2025-01-10 07:11:32,923 INFO L240 hiAutomatonCegarLoop]: Abstraction has 199 states and 229 transitions. [2025-01-10 07:11:32,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2025-01-10 07:11:32,927 INFO L432 stractBuchiCegarLoop]: Abstraction has 199 states and 229 transitions. [2025-01-10 07:11:32,928 INFO L338 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2025-01-10 07:11:32,928 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 199 states and 229 transitions. [2025-01-10 07:11:32,928 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:32,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:11:32,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:11:32,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [27, 27, 26, 26, 1, 1, 1] [2025-01-10 07:11:32,929 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:11:32,929 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:32,929 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:32,929 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:32,929 INFO L85 PathProgramCache]: Analyzing trace with hash -638996121, now seen corresponding path program 52 times [2025-01-10 07:11:32,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:32,929 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1521559653] [2025-01-10 07:11:32,929 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:11:32,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:32,944 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 109 statements into 2 equivalence classes. [2025-01-10 07:11:33,046 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 109 of 109 statements. [2025-01-10 07:11:33,047 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:11:33,047 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:33,047 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:33,052 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 109 statements into 1 equivalence classes. [2025-01-10 07:11:33,132 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 109 of 109 statements. [2025-01-10 07:11:33,133 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:33,133 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:33,142 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:33,142 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:33,142 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 28 times [2025-01-10 07:11:33,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:33,142 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418924539] [2025-01-10 07:11:33,142 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:11:33,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:33,145 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-01-10 07:11:33,146 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:33,146 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:11:33,146 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:33,146 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:33,146 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:33,147 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:33,147 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:33,147 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:33,148 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:33,149 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:33,149 INFO L85 PathProgramCache]: Analyzing trace with hash -1038350045, now seen corresponding path program 53 times [2025-01-10 07:11:33,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:33,149 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609061004] [2025-01-10 07:11:33,149 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:11:33,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:33,160 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 112 statements into 28 equivalence classes. [2025-01-10 07:11:33,221 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) and asserted 112 of 112 statements. [2025-01-10 07:11:33,221 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2025-01-10 07:11:33,221 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:34,371 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1080 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:34,371 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:11:34,371 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1609061004] [2025-01-10 07:11:34,371 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1609061004] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:11:34,371 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1867510324] [2025-01-10 07:11:34,372 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:11:34,372 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:11:34,372 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:11:34,374 INFO L229 MonitoredProcess]: Starting monitored process 48 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:11:34,375 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2025-01-10 07:11:34,514 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 112 statements into 28 equivalence classes. [2025-01-10 07:11:36,489 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) and asserted 112 of 112 statements. [2025-01-10 07:11:36,489 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2025-01-10 07:11:36,489 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:36,499 INFO L256 TraceCheckSpWp]: Trace formula consists of 608 conjuncts, 59 conjuncts are in the unsatisfiable core [2025-01-10 07:11:36,501 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:11:38,103 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1053 proven. 405 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:38,103 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:11:39,616 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1053 proven. 405 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:39,616 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1867510324] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:11:39,616 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:11:39,616 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 58, 58] total 143 [2025-01-10 07:11:39,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1852940427] [2025-01-10 07:11:39,617 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:11:39,641 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:11:39,642 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 144 interpolants. [2025-01-10 07:11:39,645 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3394, Invalid=17198, Unknown=0, NotChecked=0, Total=20592 [2025-01-10 07:11:39,645 INFO L87 Difference]: Start difference. First operand 199 states and 229 transitions. cyclomatic complexity: 33 Second operand has 144 states, 143 states have (on average 1.7692307692307692) internal successors, (253), 144 states have internal predecessors, (253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:41,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:11:41,658 INFO L93 Difference]: Finished difference Result 868 states and 1009 transitions. [2025-01-10 07:11:41,658 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 868 states and 1009 transitions. [2025-01-10 07:11:41,661 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:41,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 868 states to 379 states and 439 transitions. [2025-01-10 07:11:41,662 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 351 [2025-01-10 07:11:41,662 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 351 [2025-01-10 07:11:41,662 INFO L73 IsDeterministic]: Start isDeterministic. Operand 379 states and 439 transitions. [2025-01-10 07:11:41,662 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:11:41,662 INFO L218 hiAutomatonCegarLoop]: Abstraction has 379 states and 439 transitions. [2025-01-10 07:11:41,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 379 states and 439 transitions. [2025-01-10 07:11:41,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 379 to 206. [2025-01-10 07:11:41,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 206 states, 206 states have (on average 1.1504854368932038) internal successors, (237), 205 states have internal predecessors, (237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:41,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 237 transitions. [2025-01-10 07:11:41,664 INFO L240 hiAutomatonCegarLoop]: Abstraction has 206 states and 237 transitions. [2025-01-10 07:11:41,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 114 states. [2025-01-10 07:11:41,666 INFO L432 stractBuchiCegarLoop]: Abstraction has 206 states and 237 transitions. [2025-01-10 07:11:41,666 INFO L338 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2025-01-10 07:11:41,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 206 states and 237 transitions. [2025-01-10 07:11:41,666 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:41,666 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:11:41,666 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:11:41,667 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [28, 28, 27, 27, 1, 1, 1] [2025-01-10 07:11:41,667 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:11:41,667 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:41,667 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:41,667 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:41,667 INFO L85 PathProgramCache]: Analyzing trace with hash 570618371, now seen corresponding path program 54 times [2025-01-10 07:11:41,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:41,668 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1385240767] [2025-01-10 07:11:41,668 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:11:41,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:41,682 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 113 statements into 28 equivalence classes. [2025-01-10 07:11:42,010 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) and asserted 113 of 113 statements. [2025-01-10 07:11:42,010 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) [2025-01-10 07:11:42,010 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:42,010 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:42,017 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 113 statements into 1 equivalence classes. [2025-01-10 07:11:42,115 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 113 of 113 statements. [2025-01-10 07:11:42,115 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:42,115 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:42,121 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:42,121 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:42,121 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 29 times [2025-01-10 07:11:42,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:42,121 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119492765] [2025-01-10 07:11:42,121 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:11:42,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:42,124 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:42,124 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:42,124 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:11:42,124 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:42,124 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:42,125 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:42,125 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:42,125 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:42,125 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:42,126 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:42,127 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:42,127 INFO L85 PathProgramCache]: Analyzing trace with hash -188632313, now seen corresponding path program 55 times [2025-01-10 07:11:42,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:42,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366603535] [2025-01-10 07:11:42,127 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:11:42,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:42,138 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 116 statements into 1 equivalence classes. [2025-01-10 07:11:42,150 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 116 of 116 statements. [2025-01-10 07:11:42,150 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:42,150 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:43,325 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1080 proven. 488 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:43,326 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:11:43,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1366603535] [2025-01-10 07:11:43,326 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1366603535] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:11:43,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [651694082] [2025-01-10 07:11:43,326 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:11:43,326 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:11:43,326 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:11:43,328 INFO L229 MonitoredProcess]: Starting monitored process 49 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:11:43,329 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2025-01-10 07:11:43,473 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 116 statements into 1 equivalence classes. [2025-01-10 07:11:43,519 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 116 of 116 statements. [2025-01-10 07:11:43,519 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:43,519 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:43,522 INFO L256 TraceCheckSpWp]: Trace formula consists of 629 conjuncts, 60 conjuncts are in the unsatisfiable core [2025-01-10 07:11:43,524 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:11:44,542 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1162 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:44,542 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-01-10 07:11:45,310 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1162 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:45,310 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [651694082] provided 0 perfect and 2 imperfect interpolant sequences [2025-01-10 07:11:45,310 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-01-10 07:11:45,310 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59] total 90 [2025-01-10 07:11:45,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2009054136] [2025-01-10 07:11:45,311 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-01-10 07:11:45,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:11:45,335 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2025-01-10 07:11:45,336 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1893, Invalid=6297, Unknown=0, NotChecked=0, Total=8190 [2025-01-10 07:11:45,336 INFO L87 Difference]: Start difference. First operand 206 states and 237 transitions. cyclomatic complexity: 34 Second operand has 91 states, 90 states have (on average 2.311111111111111) internal successors, (208), 91 states have internal predecessors, (208), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:46,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:11:46,375 INFO L93 Difference]: Finished difference Result 730 states and 849 transitions. [2025-01-10 07:11:46,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 730 states and 849 transitions. [2025-01-10 07:11:46,377 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:46,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 730 states to 392 states and 454 transitions. [2025-01-10 07:11:46,378 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 363 [2025-01-10 07:11:46,378 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 363 [2025-01-10 07:11:46,378 INFO L73 IsDeterministic]: Start isDeterministic. Operand 392 states and 454 transitions. [2025-01-10 07:11:46,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:11:46,379 INFO L218 hiAutomatonCegarLoop]: Abstraction has 392 states and 454 transitions. [2025-01-10 07:11:46,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states and 454 transitions. [2025-01-10 07:11:46,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 213. [2025-01-10 07:11:46,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 213 states, 213 states have (on average 1.1502347417840375) internal successors, (245), 212 states have internal predecessors, (245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:11:46,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 245 transitions. [2025-01-10 07:11:46,381 INFO L240 hiAutomatonCegarLoop]: Abstraction has 213 states and 245 transitions. [2025-01-10 07:11:46,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2025-01-10 07:11:46,381 INFO L432 stractBuchiCegarLoop]: Abstraction has 213 states and 245 transitions. [2025-01-10 07:11:46,381 INFO L338 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2025-01-10 07:11:46,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 213 states and 245 transitions. [2025-01-10 07:11:46,382 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-01-10 07:11:46,382 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:11:46,382 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:11:46,382 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [29, 29, 28, 28, 1, 1, 1] [2025-01-10 07:11:46,382 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-01-10 07:11:46,383 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:46,383 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-01-10 07:11:46,383 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:46,383 INFO L85 PathProgramCache]: Analyzing trace with hash -1018614809, now seen corresponding path program 56 times [2025-01-10 07:11:46,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:46,383 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [293727565] [2025-01-10 07:11:46,383 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:11:46,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:46,396 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 117 statements into 2 equivalence classes. [2025-01-10 07:11:46,460 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 117 of 117 statements. [2025-01-10 07:11:46,461 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-01-10 07:11:46,461 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:46,461 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:46,466 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 117 statements into 1 equivalence classes. [2025-01-10 07:11:46,543 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 117 of 117 statements. [2025-01-10 07:11:46,543 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:46,544 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:46,554 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:46,554 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:46,555 INFO L85 PathProgramCache]: Analyzing trace with hash 64585, now seen corresponding path program 30 times [2025-01-10 07:11:46,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:46,555 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799406151] [2025-01-10 07:11:46,555 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:11:46,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:46,558 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:46,558 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:46,558 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-01-10 07:11:46,558 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:46,559 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:11:46,559 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-01-10 07:11:46,559 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-01-10 07:11:46,559 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:11:46,559 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:11:46,561 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:11:46,561 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:11:46,561 INFO L85 PathProgramCache]: Analyzing trace with hash -1609793885, now seen corresponding path program 57 times [2025-01-10 07:11:46,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:11:46,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162718819] [2025-01-10 07:11:46,562 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:11:46,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:11:46,574 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 120 statements into 30 equivalence classes. [2025-01-10 07:11:47,039 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) and asserted 120 of 120 statements. [2025-01-10 07:11:47,039 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2025-01-10 07:11:47,040 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:11:48,327 INFO L134 CoverageAnalysis]: Checked inductivity of 1682 backedges. 1162 proven. 520 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:11:48,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:11:48,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162718819] [2025-01-10 07:11:48,328 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162718819] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-10 07:11:48,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1362629406] [2025-01-10 07:11:48,328 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:11:48,328 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-10 07:11:48,328 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:11:48,330 INFO L229 MonitoredProcess]: Starting monitored process 50 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-10 07:11:48,331 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2025-01-10 07:11:48,482 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 120 statements into 30 equivalence classes.