./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.03.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 551b0097 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.03.cil-1.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 --- Real Ultimate output --- This is Ultimate 0.3.0-?-551b009-m [2025-01-10 07:51:36,126 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-01-10 07:51:36,172 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-01-10 07:51:36,176 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-01-10 07:51:36,176 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-01-10 07:51:36,193 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-01-10 07:51:36,193 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-01-10 07:51:36,193 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-01-10 07:51:36,194 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-01-10 07:51:36,194 INFO L153 SettingsManager]: * Use memory slicer=true [2025-01-10 07:51:36,194 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-01-10 07:51:36,194 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-01-10 07:51:36,194 INFO L153 SettingsManager]: * Use SBE=true [2025-01-10 07:51:36,195 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * Use old map elimination=false [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-01-10 07:51:36,195 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * sizeof long=4 [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * sizeof long double=12 [2025-01-10 07:51:36,195 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-01-10 07:51:36,196 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-01-10 07:51:36,196 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-01-10 07:51:36,196 INFO L153 SettingsManager]: * Use constant arrays=true [2025-01-10 07:51:36,196 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2025-01-10 07:51:36,196 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-01-10 07:51:36,196 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-01-10 07:51:36,196 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-01-10 07:51:36,196 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-01-10 07:51:36,196 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 [2025-01-10 07:51:36,417 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-01-10 07:51:36,426 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-01-10 07:51:36,428 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-01-10 07:51:36,428 INFO L270 PluginConnector]: Initializing CDTParser... [2025-01-10 07:51:36,429 INFO L274 PluginConnector]: CDTParser initialized [2025-01-10 07:51:36,430 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2025-01-10 07:51:37,541 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/cfb9710ce/2ba17e18855d4e09ab5b5ef145df65ca/FLAG9bdab90bd [2025-01-10 07:51:37,848 INFO L384 CDTParser]: Found 1 translation units. [2025-01-10 07:51:37,854 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2025-01-10 07:51:37,884 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/cfb9710ce/2ba17e18855d4e09ab5b5ef145df65ca/FLAG9bdab90bd [2025-01-10 07:51:37,918 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/cfb9710ce/2ba17e18855d4e09ab5b5ef145df65ca [2025-01-10 07:51:37,920 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-01-10 07:51:37,921 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-01-10 07:51:37,922 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-01-10 07:51:37,922 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-01-10 07:51:37,925 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-01-10 07:51:37,926 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:51:37" (1/1) ... [2025-01-10 07:51:37,927 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@dfa1513 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:37, skipping insertion in model container [2025-01-10 07:51:37,928 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:51:37" (1/1) ... [2025-01-10 07:51:37,947 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-01-10 07:51:38,105 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:51:38,114 INFO L200 MainTranslator]: Completed pre-run [2025-01-10 07:51:38,153 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:51:38,170 INFO L204 MainTranslator]: Completed translation [2025-01-10 07:51:38,171 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38 WrapperNode [2025-01-10 07:51:38,171 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-01-10 07:51:38,172 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-01-10 07:51:38,172 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-01-10 07:51:38,172 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-01-10 07:51:38,176 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,180 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,220 INFO L138 Inliner]: procedures = 34, calls = 42, calls flagged for inlining = 37, calls inlined = 65, statements flattened = 818 [2025-01-10 07:51:38,220 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-01-10 07:51:38,221 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-01-10 07:51:38,221 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-01-10 07:51:38,221 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-01-10 07:51:38,235 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,235 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,242 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,262 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-01-10 07:51:38,262 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,263 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,273 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,277 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,286 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,292 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,293 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,300 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-01-10 07:51:38,300 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2025-01-10 07:51:38,301 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2025-01-10 07:51:38,301 INFO L274 PluginConnector]: RCFGBuilder initialized [2025-01-10 07:51:38,302 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (1/1) ... [2025-01-10 07:51:38,310 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:51:38,328 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:51:38,344 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:51:38,348 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-01-10 07:51:38,371 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-01-10 07:51:38,371 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-01-10 07:51:38,371 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-01-10 07:51:38,371 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-01-10 07:51:38,454 INFO L234 CfgBuilder]: Building ICFG [2025-01-10 07:51:38,456 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2025-01-10 07:51:39,011 INFO L? ?]: Removed 148 outVars from TransFormulas that were not future-live. [2025-01-10 07:51:39,011 INFO L283 CfgBuilder]: Performing block encoding [2025-01-10 07:51:39,024 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-01-10 07:51:39,025 INFO L312 CfgBuilder]: Removed 6 assume(true) statements. [2025-01-10 07:51:39,025 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:51:39 BoogieIcfgContainer [2025-01-10 07:51:39,025 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2025-01-10 07:51:39,026 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-01-10 07:51:39,026 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-01-10 07:51:39,031 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-01-10 07:51:39,031 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:51:39,031 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.01 07:51:37" (1/3) ... [2025-01-10 07:51:39,032 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4190128a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:51:39, skipping insertion in model container [2025-01-10 07:51:39,032 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:51:39,033 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:38" (2/3) ... [2025-01-10 07:51:39,033 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4190128a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:51:39, skipping insertion in model container [2025-01-10 07:51:39,033 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:51:39,033 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:51:39" (3/3) ... [2025-01-10 07:51:39,034 INFO L363 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-1.c [2025-01-10 07:51:39,082 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-01-10 07:51:39,083 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-01-10 07:51:39,083 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-01-10 07:51:39,083 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-01-10 07:51:39,083 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-01-10 07:51:39,083 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-01-10 07:51:39,083 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-01-10 07:51:39,083 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-01-10 07:51:39,088 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 331 states, 330 states have (on average 1.5212121212121212) internal successors, (502), 330 states have internal predecessors, (502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:39,108 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2025-01-10 07:51:39,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:39,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:39,116 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:39,116 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:39,117 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-01-10 07:51:39,118 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 331 states, 330 states have (on average 1.5212121212121212) internal successors, (502), 330 states have internal predecessors, (502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:39,128 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2025-01-10 07:51:39,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:39,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:39,130 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:39,130 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:39,135 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:39,136 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:51:39,139 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:39,140 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2025-01-10 07:51:39,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:39,145 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743150080] [2025-01-10 07:51:39,146 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:39,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:39,192 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-01-10 07:51:39,219 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-01-10 07:51:39,219 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:39,219 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:39,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:39,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:39,373 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1743150080] [2025-01-10 07:51:39,374 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1743150080] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:39,374 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:39,374 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:39,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2079370756] [2025-01-10 07:51:39,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:39,378 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:39,379 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:39,379 INFO L85 PathProgramCache]: Analyzing trace with hash -1318768256, now seen corresponding path program 1 times [2025-01-10 07:51:39,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:39,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043355284] [2025-01-10 07:51:39,379 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:39,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:39,386 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 58 statements into 1 equivalence classes. [2025-01-10 07:51:39,388 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 58 of 58 statements. [2025-01-10 07:51:39,388 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:39,388 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:39,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:39,441 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:39,441 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043355284] [2025-01-10 07:51:39,441 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1043355284] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:39,441 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:39,442 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:39,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1032160370] [2025-01-10 07:51:39,442 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:39,443 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:39,443 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:39,463 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:39,463 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:39,465 INFO L87 Difference]: Start difference. First operand has 331 states, 330 states have (on average 1.5212121212121212) internal successors, (502), 330 states have internal predecessors, (502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:39,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:39,494 INFO L93 Difference]: Finished difference Result 327 states and 489 transitions. [2025-01-10 07:51:39,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 489 transitions. [2025-01-10 07:51:39,503 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 266 [2025-01-10 07:51:39,509 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 321 states and 483 transitions. [2025-01-10 07:51:39,510 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 321 [2025-01-10 07:51:39,510 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 321 [2025-01-10 07:51:39,511 INFO L73 IsDeterministic]: Start isDeterministic. Operand 321 states and 483 transitions. [2025-01-10 07:51:39,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:39,512 INFO L218 hiAutomatonCegarLoop]: Abstraction has 321 states and 483 transitions. [2025-01-10 07:51:39,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states and 483 transitions. [2025-01-10 07:51:39,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 321. [2025-01-10 07:51:39,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 321 states, 321 states have (on average 1.5046728971962617) internal successors, (483), 320 states have internal predecessors, (483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:39,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 321 states to 321 states and 483 transitions. [2025-01-10 07:51:39,548 INFO L240 hiAutomatonCegarLoop]: Abstraction has 321 states and 483 transitions. [2025-01-10 07:51:39,550 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:39,552 INFO L432 stractBuchiCegarLoop]: Abstraction has 321 states and 483 transitions. [2025-01-10 07:51:39,553 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-01-10 07:51:39,554 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 321 states and 483 transitions. [2025-01-10 07:51:39,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 266 [2025-01-10 07:51:39,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:39,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:39,561 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:39,561 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:39,561 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:39,562 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:51:39,563 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:39,563 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2025-01-10 07:51:39,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:39,563 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589654601] [2025-01-10 07:51:39,563 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:39,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:39,575 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-01-10 07:51:39,579 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-01-10 07:51:39,579 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:39,579 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:39,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:39,611 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:39,611 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [589654601] [2025-01-10 07:51:39,611 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [589654601] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:39,611 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:39,611 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:39,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320292382] [2025-01-10 07:51:39,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:39,611 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:39,612 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:39,612 INFO L85 PathProgramCache]: Analyzing trace with hash 551508897, now seen corresponding path program 1 times [2025-01-10 07:51:39,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:39,612 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372072918] [2025-01-10 07:51:39,612 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:39,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:39,618 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes. [2025-01-10 07:51:39,628 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements. [2025-01-10 07:51:39,628 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:39,628 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:39,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:39,705 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:39,706 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [372072918] [2025-01-10 07:51:39,706 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [372072918] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:39,706 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:39,706 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:39,706 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547523772] [2025-01-10 07:51:39,706 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:39,706 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:39,706 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:39,706 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:39,706 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:39,707 INFO L87 Difference]: Start difference. First operand 321 states and 483 transitions. cyclomatic complexity: 163 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:39,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:39,733 INFO L93 Difference]: Finished difference Result 321 states and 482 transitions. [2025-01-10 07:51:39,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 321 states and 482 transitions. [2025-01-10 07:51:39,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 266 [2025-01-10 07:51:39,739 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 321 states to 321 states and 482 transitions. [2025-01-10 07:51:39,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 321 [2025-01-10 07:51:39,741 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 321 [2025-01-10 07:51:39,741 INFO L73 IsDeterministic]: Start isDeterministic. Operand 321 states and 482 transitions. [2025-01-10 07:51:39,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:39,745 INFO L218 hiAutomatonCegarLoop]: Abstraction has 321 states and 482 transitions. [2025-01-10 07:51:39,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states and 482 transitions. [2025-01-10 07:51:39,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 321. [2025-01-10 07:51:39,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 321 states, 321 states have (on average 1.5015576323987538) internal successors, (482), 320 states have internal predecessors, (482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:39,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 321 states to 321 states and 482 transitions. [2025-01-10 07:51:39,759 INFO L240 hiAutomatonCegarLoop]: Abstraction has 321 states and 482 transitions. [2025-01-10 07:51:39,760 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:39,760 INFO L432 stractBuchiCegarLoop]: Abstraction has 321 states and 482 transitions. [2025-01-10 07:51:39,760 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-01-10 07:51:39,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 321 states and 482 transitions. [2025-01-10 07:51:39,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 266 [2025-01-10 07:51:39,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:39,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:39,765 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:39,768 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:39,769 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:39,769 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:51:39,769 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:39,769 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2025-01-10 07:51:39,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:39,769 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [555910161] [2025-01-10 07:51:39,769 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:39,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:39,778 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-01-10 07:51:39,782 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-01-10 07:51:39,783 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:39,783 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:39,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:39,800 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:39,800 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [555910161] [2025-01-10 07:51:39,801 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [555910161] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:39,801 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:39,801 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:39,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1240100179] [2025-01-10 07:51:39,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:39,801 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:39,801 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:39,802 INFO L85 PathProgramCache]: Analyzing trace with hash -1121008734, now seen corresponding path program 1 times [2025-01-10 07:51:39,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:39,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [112454521] [2025-01-10 07:51:39,802 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:39,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:39,806 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes. [2025-01-10 07:51:39,811 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements. [2025-01-10 07:51:39,811 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:39,811 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:39,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:39,854 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:39,854 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [112454521] [2025-01-10 07:51:39,854 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [112454521] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:39,854 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:39,854 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:39,855 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126878198] [2025-01-10 07:51:39,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:39,855 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:39,855 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:39,855 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:39,855 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:39,856 INFO L87 Difference]: Start difference. First operand 321 states and 482 transitions. cyclomatic complexity: 162 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:39,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:39,869 INFO L93 Difference]: Finished difference Result 321 states and 481 transitions. [2025-01-10 07:51:39,869 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 321 states and 481 transitions. [2025-01-10 07:51:39,871 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 266 [2025-01-10 07:51:39,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 321 states to 321 states and 481 transitions. [2025-01-10 07:51:39,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 321 [2025-01-10 07:51:39,873 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 321 [2025-01-10 07:51:39,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 321 states and 481 transitions. [2025-01-10 07:51:39,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:39,874 INFO L218 hiAutomatonCegarLoop]: Abstraction has 321 states and 481 transitions. [2025-01-10 07:51:39,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states and 481 transitions. [2025-01-10 07:51:39,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 321. [2025-01-10 07:51:39,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 321 states, 321 states have (on average 1.4984423676012462) internal successors, (481), 320 states have internal predecessors, (481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:39,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 321 states to 321 states and 481 transitions. [2025-01-10 07:51:39,880 INFO L240 hiAutomatonCegarLoop]: Abstraction has 321 states and 481 transitions. [2025-01-10 07:51:39,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:39,882 INFO L432 stractBuchiCegarLoop]: Abstraction has 321 states and 481 transitions. [2025-01-10 07:51:39,882 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-01-10 07:51:39,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 321 states and 481 transitions. [2025-01-10 07:51:39,884 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 266 [2025-01-10 07:51:39,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:39,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:39,885 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:39,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:39,885 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:39,885 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:51:39,886 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:39,886 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2025-01-10 07:51:39,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:39,886 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636946399] [2025-01-10 07:51:39,886 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:39,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:39,892 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-01-10 07:51:39,897 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-01-10 07:51:39,897 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:39,897 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:39,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:39,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:39,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636946399] [2025-01-10 07:51:39,941 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1636946399] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:39,941 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:39,941 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:39,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [15790161] [2025-01-10 07:51:39,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:39,942 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:39,942 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:39,942 INFO L85 PathProgramCache]: Analyzing trace with hash -1025048862, now seen corresponding path program 1 times [2025-01-10 07:51:39,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:39,942 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006989061] [2025-01-10 07:51:39,942 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:39,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:39,948 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes. [2025-01-10 07:51:39,953 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements. [2025-01-10 07:51:39,953 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:39,953 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:40,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:40,021 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:40,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2006989061] [2025-01-10 07:51:40,021 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2006989061] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:40,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:40,022 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:40,022 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1818847499] [2025-01-10 07:51:40,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:40,022 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:40,022 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:40,023 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:40,023 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:40,023 INFO L87 Difference]: Start difference. First operand 321 states and 481 transitions. cyclomatic complexity: 161 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:40,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:40,103 INFO L93 Difference]: Finished difference Result 557 states and 830 transitions. [2025-01-10 07:51:40,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 830 transitions. [2025-01-10 07:51:40,107 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 494 [2025-01-10 07:51:40,111 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 830 transitions. [2025-01-10 07:51:40,111 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2025-01-10 07:51:40,112 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2025-01-10 07:51:40,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 830 transitions. [2025-01-10 07:51:40,113 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:40,114 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 830 transitions. [2025-01-10 07:51:40,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 830 transitions. [2025-01-10 07:51:40,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2025-01-10 07:51:40,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4901256732495511) internal successors, (830), 556 states have internal predecessors, (830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:40,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 830 transitions. [2025-01-10 07:51:40,133 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 830 transitions. [2025-01-10 07:51:40,133 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:51:40,134 INFO L432 stractBuchiCegarLoop]: Abstraction has 557 states and 830 transitions. [2025-01-10 07:51:40,135 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-01-10 07:51:40,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 830 transitions. [2025-01-10 07:51:40,138 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 494 [2025-01-10 07:51:40,138 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:40,138 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:40,139 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:40,139 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:40,139 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:40,139 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:51:40,141 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:40,141 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2025-01-10 07:51:40,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:40,142 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665808947] [2025-01-10 07:51:40,142 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:40,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:40,147 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-01-10 07:51:40,152 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-01-10 07:51:40,155 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:40,156 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:40,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:40,204 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:40,205 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [665808947] [2025-01-10 07:51:40,205 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [665808947] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:40,205 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:40,205 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:40,205 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1474125049] [2025-01-10 07:51:40,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:40,205 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:40,206 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:40,206 INFO L85 PathProgramCache]: Analyzing trace with hash -360186527, now seen corresponding path program 1 times [2025-01-10 07:51:40,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:40,206 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047877196] [2025-01-10 07:51:40,206 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:40,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:40,216 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes. [2025-01-10 07:51:40,224 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements. [2025-01-10 07:51:40,224 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:40,224 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:40,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:40,265 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:40,265 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1047877196] [2025-01-10 07:51:40,265 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1047877196] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:40,265 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:40,265 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:40,265 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [704887077] [2025-01-10 07:51:40,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:40,266 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:40,266 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:40,266 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:40,266 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:40,266 INFO L87 Difference]: Start difference. First operand 557 states and 830 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:40,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:40,318 INFO L93 Difference]: Finished difference Result 1025 states and 1503 transitions. [2025-01-10 07:51:40,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1025 states and 1503 transitions. [2025-01-10 07:51:40,325 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 959 [2025-01-10 07:51:40,330 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1025 states to 1025 states and 1503 transitions. [2025-01-10 07:51:40,331 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1025 [2025-01-10 07:51:40,332 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1025 [2025-01-10 07:51:40,332 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1025 states and 1503 transitions. [2025-01-10 07:51:40,334 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:40,334 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1025 states and 1503 transitions. [2025-01-10 07:51:40,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1025 states and 1503 transitions. [2025-01-10 07:51:40,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1025 to 971. [2025-01-10 07:51:40,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 971 states, 971 states have (on average 1.4716786817713696) internal successors, (1429), 970 states have internal predecessors, (1429), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:40,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 971 states to 971 states and 1429 transitions. [2025-01-10 07:51:40,354 INFO L240 hiAutomatonCegarLoop]: Abstraction has 971 states and 1429 transitions. [2025-01-10 07:51:40,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:40,355 INFO L432 stractBuchiCegarLoop]: Abstraction has 971 states and 1429 transitions. [2025-01-10 07:51:40,355 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-01-10 07:51:40,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 971 states and 1429 transitions. [2025-01-10 07:51:40,359 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 905 [2025-01-10 07:51:40,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:40,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:40,361 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:40,361 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:40,361 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:40,361 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:51:40,362 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:40,362 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2025-01-10 07:51:40,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:40,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716135991] [2025-01-10 07:51:40,362 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:40,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:40,367 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-01-10 07:51:40,370 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-01-10 07:51:40,370 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:40,370 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:40,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:40,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:40,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1716135991] [2025-01-10 07:51:40,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1716135991] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:40,397 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:40,397 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:40,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [140943042] [2025-01-10 07:51:40,398 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:40,398 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:40,398 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:40,398 INFO L85 PathProgramCache]: Analyzing trace with hash 1216371232, now seen corresponding path program 1 times [2025-01-10 07:51:40,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:40,398 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [570573310] [2025-01-10 07:51:40,398 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:40,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:40,404 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes. [2025-01-10 07:51:40,408 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements. [2025-01-10 07:51:40,408 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:40,408 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:40,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:40,448 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:40,448 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [570573310] [2025-01-10 07:51:40,448 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [570573310] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:40,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:40,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:40,449 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780827227] [2025-01-10 07:51:40,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:40,449 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:40,449 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:40,450 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:40,450 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:40,450 INFO L87 Difference]: Start difference. First operand 971 states and 1429 transitions. cyclomatic complexity: 462 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:40,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:40,496 INFO L93 Difference]: Finished difference Result 1741 states and 2543 transitions. [2025-01-10 07:51:40,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1741 states and 2543 transitions. [2025-01-10 07:51:40,507 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1664 [2025-01-10 07:51:40,517 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1741 states to 1741 states and 2543 transitions. [2025-01-10 07:51:40,517 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1741 [2025-01-10 07:51:40,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1741 [2025-01-10 07:51:40,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1741 states and 2543 transitions. [2025-01-10 07:51:40,522 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:40,522 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1741 states and 2543 transitions. [2025-01-10 07:51:40,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1741 states and 2543 transitions. [2025-01-10 07:51:40,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1741 to 1737. [2025-01-10 07:51:40,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1737 states, 1737 states have (on average 1.4617156016119748) internal successors, (2539), 1736 states have internal predecessors, (2539), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:40,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1737 states to 1737 states and 2539 transitions. [2025-01-10 07:51:40,582 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1737 states and 2539 transitions. [2025-01-10 07:51:40,583 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:40,583 INFO L432 stractBuchiCegarLoop]: Abstraction has 1737 states and 2539 transitions. [2025-01-10 07:51:40,584 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-01-10 07:51:40,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1737 states and 2539 transitions. [2025-01-10 07:51:40,593 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1660 [2025-01-10 07:51:40,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:40,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:40,595 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:40,595 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:40,596 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:40,596 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:51:40,597 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:40,597 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2025-01-10 07:51:40,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:40,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912659594] [2025-01-10 07:51:40,598 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:40,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:40,603 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-01-10 07:51:40,606 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-01-10 07:51:40,606 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:40,606 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:40,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:40,649 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:40,649 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [912659594] [2025-01-10 07:51:40,649 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [912659594] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:40,649 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:40,649 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:40,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [678512014] [2025-01-10 07:51:40,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:40,649 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:40,649 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:40,649 INFO L85 PathProgramCache]: Analyzing trace with hash -360186527, now seen corresponding path program 2 times [2025-01-10 07:51:40,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:40,649 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184441447] [2025-01-10 07:51:40,650 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:40,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:40,654 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 62 statements into 1 equivalence classes. [2025-01-10 07:51:40,659 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 62 of 62 statements. [2025-01-10 07:51:40,662 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:40,662 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:40,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:40,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:40,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184441447] [2025-01-10 07:51:40,704 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184441447] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:40,704 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:40,704 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:40,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2090141374] [2025-01-10 07:51:40,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:40,705 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:40,705 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:40,705 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:40,705 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:40,705 INFO L87 Difference]: Start difference. First operand 1737 states and 2539 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:40,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:40,736 INFO L93 Difference]: Finished difference Result 2531 states and 3698 transitions. [2025-01-10 07:51:40,736 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2531 states and 3698 transitions. [2025-01-10 07:51:40,749 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2448 [2025-01-10 07:51:40,761 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2531 states to 2531 states and 3698 transitions. [2025-01-10 07:51:40,762 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2531 [2025-01-10 07:51:40,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2531 [2025-01-10 07:51:40,765 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2531 states and 3698 transitions. [2025-01-10 07:51:40,770 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:40,770 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2531 states and 3698 transitions. [2025-01-10 07:51:40,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2531 states and 3698 transitions. [2025-01-10 07:51:40,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2531 to 1761. [2025-01-10 07:51:40,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1761 states, 1761 states have (on average 1.4645088018171493) internal successors, (2579), 1760 states have internal predecessors, (2579), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:40,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1761 states to 1761 states and 2579 transitions. [2025-01-10 07:51:40,813 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1761 states and 2579 transitions. [2025-01-10 07:51:40,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:40,815 INFO L432 stractBuchiCegarLoop]: Abstraction has 1761 states and 2579 transitions. [2025-01-10 07:51:40,816 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-01-10 07:51:40,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1761 states and 2579 transitions. [2025-01-10 07:51:40,826 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1692 [2025-01-10 07:51:40,826 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:40,826 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:40,827 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:40,827 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:40,827 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:40,828 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:51:40,828 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:40,828 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2025-01-10 07:51:40,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:40,828 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205311300] [2025-01-10 07:51:40,828 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:40,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:40,835 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-01-10 07:51:40,837 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-01-10 07:51:40,839 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:40,839 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:40,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:40,873 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:40,873 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1205311300] [2025-01-10 07:51:40,875 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1205311300] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:40,875 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:40,875 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:40,875 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [151771168] [2025-01-10 07:51:40,875 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:40,875 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:40,877 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:40,878 INFO L85 PathProgramCache]: Analyzing trace with hash 938534305, now seen corresponding path program 1 times [2025-01-10 07:51:40,878 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:40,878 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078505360] [2025-01-10 07:51:40,878 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:40,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:40,882 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes. [2025-01-10 07:51:40,885 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements. [2025-01-10 07:51:40,885 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:40,885 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:40,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:40,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:40,927 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1078505360] [2025-01-10 07:51:40,927 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1078505360] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:40,927 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:40,928 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:40,928 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [47216421] [2025-01-10 07:51:40,928 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:40,928 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:40,928 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:40,929 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:40,929 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:40,929 INFO L87 Difference]: Start difference. First operand 1761 states and 2579 transitions. cyclomatic complexity: 822 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:40,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:40,982 INFO L93 Difference]: Finished difference Result 2525 states and 3666 transitions. [2025-01-10 07:51:40,982 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2525 states and 3666 transitions. [2025-01-10 07:51:40,997 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2448 [2025-01-10 07:51:41,010 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2525 states to 2525 states and 3666 transitions. [2025-01-10 07:51:41,010 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2525 [2025-01-10 07:51:41,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2525 [2025-01-10 07:51:41,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2525 states and 3666 transitions. [2025-01-10 07:51:41,015 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:41,016 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2525 states and 3666 transitions. [2025-01-10 07:51:41,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2525 states and 3666 transitions. [2025-01-10 07:51:41,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2525 to 1761. [2025-01-10 07:51:41,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1761 states, 1761 states have (on average 1.454855195911414) internal successors, (2562), 1760 states have internal predecessors, (2562), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:41,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1761 states to 1761 states and 2562 transitions. [2025-01-10 07:51:41,050 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1761 states and 2562 transitions. [2025-01-10 07:51:41,050 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:51:41,051 INFO L432 stractBuchiCegarLoop]: Abstraction has 1761 states and 2562 transitions. [2025-01-10 07:51:41,051 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-01-10 07:51:41,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1761 states and 2562 transitions. [2025-01-10 07:51:41,057 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1692 [2025-01-10 07:51:41,057 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:41,057 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:41,058 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:41,058 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:41,059 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:41,059 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:51:41,059 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:41,059 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2025-01-10 07:51:41,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:41,060 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487310648] [2025-01-10 07:51:41,060 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:41,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:41,066 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-01-10 07:51:41,069 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-01-10 07:51:41,069 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,070 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:41,070 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:41,072 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-01-10 07:51:41,075 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-01-10 07:51:41,075 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,075 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:41,097 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:41,098 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:41,098 INFO L85 PathProgramCache]: Analyzing trace with hash -750409437, now seen corresponding path program 1 times [2025-01-10 07:51:41,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:41,098 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464324708] [2025-01-10 07:51:41,098 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:41,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:41,104 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes. [2025-01-10 07:51:41,107 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements. [2025-01-10 07:51:41,108 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,108 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:41,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:41,149 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:41,149 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464324708] [2025-01-10 07:51:41,149 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1464324708] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:41,149 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:41,149 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:41,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [593916072] [2025-01-10 07:51:41,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:41,150 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:41,150 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:41,150 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-10 07:51:41,150 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-10 07:51:41,150 INFO L87 Difference]: Start difference. First operand 1761 states and 2562 transitions. cyclomatic complexity: 805 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:41,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:41,217 INFO L93 Difference]: Finished difference Result 1817 states and 2618 transitions. [2025-01-10 07:51:41,217 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1817 states and 2618 transitions. [2025-01-10 07:51:41,227 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1748 [2025-01-10 07:51:41,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1817 states to 1817 states and 2618 transitions. [2025-01-10 07:51:41,237 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1817 [2025-01-10 07:51:41,238 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1817 [2025-01-10 07:51:41,238 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1817 states and 2618 transitions. [2025-01-10 07:51:41,241 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:41,241 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1817 states and 2618 transitions. [2025-01-10 07:51:41,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1817 states and 2618 transitions. [2025-01-10 07:51:41,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1817 to 1785. [2025-01-10 07:51:41,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4487394957983193) internal successors, (2586), 1784 states have internal predecessors, (2586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:41,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2586 transitions. [2025-01-10 07:51:41,279 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2586 transitions. [2025-01-10 07:51:41,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:51:41,280 INFO L432 stractBuchiCegarLoop]: Abstraction has 1785 states and 2586 transitions. [2025-01-10 07:51:41,280 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-01-10 07:51:41,281 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2586 transitions. [2025-01-10 07:51:41,289 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1716 [2025-01-10 07:51:41,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:41,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:41,290 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:41,290 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:41,291 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:41,291 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:51:41,292 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:41,292 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2025-01-10 07:51:41,292 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:41,292 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [492932358] [2025-01-10 07:51:41,292 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:41,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:41,298 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 51 statements into 1 equivalence classes. [2025-01-10 07:51:41,301 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-01-10 07:51:41,301 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:41,301 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:41,301 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:41,303 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-01-10 07:51:41,305 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-01-10 07:51:41,306 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,306 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:41,314 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:41,315 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:41,315 INFO L85 PathProgramCache]: Analyzing trace with hash -2142012485, now seen corresponding path program 1 times [2025-01-10 07:51:41,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:41,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1064452493] [2025-01-10 07:51:41,315 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:41,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:41,320 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 65 statements into 1 equivalence classes. [2025-01-10 07:51:41,324 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 65 of 65 statements. [2025-01-10 07:51:41,325 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,325 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:41,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:41,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:41,385 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1064452493] [2025-01-10 07:51:41,385 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1064452493] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:41,385 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:41,385 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:41,385 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785290065] [2025-01-10 07:51:41,385 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:41,386 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:41,386 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:41,386 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-10 07:51:41,386 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-10 07:51:41,386 INFO L87 Difference]: Start difference. First operand 1785 states and 2586 transitions. cyclomatic complexity: 805 Second operand has 5 states, 5 states have (on average 13.0) internal successors, (65), 5 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:41,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:41,517 INFO L93 Difference]: Finished difference Result 1845 states and 2629 transitions. [2025-01-10 07:51:41,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1845 states and 2629 transitions. [2025-01-10 07:51:41,528 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1776 [2025-01-10 07:51:41,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1845 states to 1845 states and 2629 transitions. [2025-01-10 07:51:41,538 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1845 [2025-01-10 07:51:41,539 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1845 [2025-01-10 07:51:41,540 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1845 states and 2629 transitions. [2025-01-10 07:51:41,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:41,543 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1845 states and 2629 transitions. [2025-01-10 07:51:41,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1845 states and 2629 transitions. [2025-01-10 07:51:41,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1845 to 1845. [2025-01-10 07:51:41,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1845 states, 1845 states have (on average 1.4249322493224932) internal successors, (2629), 1844 states have internal predecessors, (2629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:41,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1845 states to 1845 states and 2629 transitions. [2025-01-10 07:51:41,577 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1845 states and 2629 transitions. [2025-01-10 07:51:41,578 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:51:41,578 INFO L432 stractBuchiCegarLoop]: Abstraction has 1845 states and 2629 transitions. [2025-01-10 07:51:41,578 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-01-10 07:51:41,578 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1845 states and 2629 transitions. [2025-01-10 07:51:41,584 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1776 [2025-01-10 07:51:41,585 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:41,585 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:41,586 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:41,586 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:41,586 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:41,586 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:51:41,587 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:41,587 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2025-01-10 07:51:41,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:41,587 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [95039017] [2025-01-10 07:51:41,587 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:51:41,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:41,593 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 51 statements into 1 equivalence classes. [2025-01-10 07:51:41,598 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-01-10 07:51:41,598 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:51:41,598 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:41,598 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:41,600 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-01-10 07:51:41,604 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-01-10 07:51:41,604 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,604 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:41,610 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:41,611 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:41,611 INFO L85 PathProgramCache]: Analyzing trace with hash -1718365763, now seen corresponding path program 1 times [2025-01-10 07:51:41,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:41,611 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686419337] [2025-01-10 07:51:41,611 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:41,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:41,617 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 65 statements into 1 equivalence classes. [2025-01-10 07:51:41,620 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 65 of 65 statements. [2025-01-10 07:51:41,621 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,621 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:41,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:41,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:41,654 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1686419337] [2025-01-10 07:51:41,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1686419337] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:41,654 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:41,654 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:41,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1495572476] [2025-01-10 07:51:41,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:41,655 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:41,655 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:41,655 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:41,656 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:41,656 INFO L87 Difference]: Start difference. First operand 1845 states and 2629 transitions. cyclomatic complexity: 788 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:41,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:41,704 INFO L93 Difference]: Finished difference Result 2828 states and 3964 transitions. [2025-01-10 07:51:41,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2828 states and 3964 transitions. [2025-01-10 07:51:41,719 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2756 [2025-01-10 07:51:41,734 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2828 states to 2828 states and 3964 transitions. [2025-01-10 07:51:41,734 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2828 [2025-01-10 07:51:41,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2828 [2025-01-10 07:51:41,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2828 states and 3964 transitions. [2025-01-10 07:51:41,741 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:41,742 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2828 states and 3964 transitions. [2025-01-10 07:51:41,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2828 states and 3964 transitions. [2025-01-10 07:51:41,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2828 to 2738. [2025-01-10 07:51:41,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2738 states, 2738 states have (on average 1.4032140248356464) internal successors, (3842), 2737 states have internal predecessors, (3842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:41,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2738 states to 2738 states and 3842 transitions. [2025-01-10 07:51:41,804 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2738 states and 3842 transitions. [2025-01-10 07:51:41,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:41,805 INFO L432 stractBuchiCegarLoop]: Abstraction has 2738 states and 3842 transitions. [2025-01-10 07:51:41,805 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-01-10 07:51:41,805 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2738 states and 3842 transitions. [2025-01-10 07:51:41,816 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2666 [2025-01-10 07:51:41,816 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:41,816 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:41,817 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:41,817 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:41,817 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-01-10 07:51:41,818 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" [2025-01-10 07:51:41,818 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:41,818 INFO L85 PathProgramCache]: Analyzing trace with hash 1020217665, now seen corresponding path program 1 times [2025-01-10 07:51:41,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:41,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [418546459] [2025-01-10 07:51:41,819 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:41,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:41,825 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 52 statements into 1 equivalence classes. [2025-01-10 07:51:41,829 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 52 of 52 statements. [2025-01-10 07:51:41,829 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,829 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:41,829 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:41,832 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 52 statements into 1 equivalence classes. [2025-01-10 07:51:41,835 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 52 of 52 statements. [2025-01-10 07:51:41,835 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,835 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:41,843 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:41,844 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:41,844 INFO L85 PathProgramCache]: Analyzing trace with hash -919601682, now seen corresponding path program 1 times [2025-01-10 07:51:41,844 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:41,844 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398382194] [2025-01-10 07:51:41,844 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:41,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:41,847 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-01-10 07:51:41,848 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-01-10 07:51:41,848 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,849 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:41,849 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:41,849 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-01-10 07:51:41,850 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-01-10 07:51:41,850 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,850 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:41,851 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:41,852 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:41,852 INFO L85 PathProgramCache]: Analyzing trace with hash 1502768302, now seen corresponding path program 1 times [2025-01-10 07:51:41,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:41,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1727979029] [2025-01-10 07:51:41,852 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:41,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:41,856 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 63 statements into 1 equivalence classes. [2025-01-10 07:51:41,859 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 63 of 63 statements. [2025-01-10 07:51:41,859 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:41,859 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:41,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:41,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:41,878 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1727979029] [2025-01-10 07:51:41,878 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1727979029] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:41,878 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:41,878 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:41,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [714791411] [2025-01-10 07:51:41,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:41,929 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:41,930 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:41,930 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:41,930 INFO L87 Difference]: Start difference. First operand 2738 states and 3842 transitions. cyclomatic complexity: 1110 Second operand has 3 states, 3 states have (on average 21.0) internal successors, (63), 3 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:41,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:41,979 INFO L93 Difference]: Finished difference Result 4900 states and 6805 transitions. [2025-01-10 07:51:41,979 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4900 states and 6805 transitions. [2025-01-10 07:51:42,003 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4762 [2025-01-10 07:51:42,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4900 states to 4900 states and 6805 transitions. [2025-01-10 07:51:42,025 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4900 [2025-01-10 07:51:42,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4900 [2025-01-10 07:51:42,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4900 states and 6805 transitions. [2025-01-10 07:51:42,037 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:42,037 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4900 states and 6805 transitions. [2025-01-10 07:51:42,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4900 states and 6805 transitions. [2025-01-10 07:51:42,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4900 to 4669. [2025-01-10 07:51:42,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4669 states, 4669 states have (on average 1.3930177768258727) internal successors, (6504), 4668 states have internal predecessors, (6504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:42,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4669 states to 4669 states and 6504 transitions. [2025-01-10 07:51:42,140 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4669 states and 6504 transitions. [2025-01-10 07:51:42,141 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:42,142 INFO L432 stractBuchiCegarLoop]: Abstraction has 4669 states and 6504 transitions. [2025-01-10 07:51:42,142 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-01-10 07:51:42,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4669 states and 6504 transitions. [2025-01-10 07:51:42,156 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4531 [2025-01-10 07:51:42,156 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:42,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:42,157 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:42,157 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:42,157 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-01-10 07:51:42,157 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" [2025-01-10 07:51:42,157 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:42,158 INFO L85 PathProgramCache]: Analyzing trace with hash 801142789, now seen corresponding path program 1 times [2025-01-10 07:51:42,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:42,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816574756] [2025-01-10 07:51:42,158 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:42,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:42,163 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 52 statements into 1 equivalence classes. [2025-01-10 07:51:42,165 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 52 of 52 statements. [2025-01-10 07:51:42,165 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:42,165 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:42,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:42,179 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:42,179 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816574756] [2025-01-10 07:51:42,179 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816574756] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:42,179 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:42,179 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:42,179 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [224202581] [2025-01-10 07:51:42,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:42,180 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:42,180 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:42,180 INFO L85 PathProgramCache]: Analyzing trace with hash 905461682, now seen corresponding path program 1 times [2025-01-10 07:51:42,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:42,180 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1432062180] [2025-01-10 07:51:42,180 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:42,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:42,182 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-01-10 07:51:42,183 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-01-10 07:51:42,184 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:42,184 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:42,184 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:42,184 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-01-10 07:51:42,185 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-01-10 07:51:42,185 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:42,185 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:42,186 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:42,230 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:42,231 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:42,231 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:42,231 INFO L87 Difference]: Start difference. First operand 4669 states and 6504 transitions. cyclomatic complexity: 1841 Second operand has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:42,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:42,247 INFO L93 Difference]: Finished difference Result 4621 states and 6436 transitions. [2025-01-10 07:51:42,247 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4621 states and 6436 transitions. [2025-01-10 07:51:42,261 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4531 [2025-01-10 07:51:42,277 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4621 states to 4621 states and 6436 transitions. [2025-01-10 07:51:42,277 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4621 [2025-01-10 07:51:42,281 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4621 [2025-01-10 07:51:42,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4621 states and 6436 transitions. [2025-01-10 07:51:42,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:42,289 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4621 states and 6436 transitions. [2025-01-10 07:51:42,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4621 states and 6436 transitions. [2025-01-10 07:51:42,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4621 to 4621. [2025-01-10 07:51:42,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4621 states, 4621 states have (on average 1.392772127245185) internal successors, (6436), 4620 states have internal predecessors, (6436), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:42,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4621 states to 4621 states and 6436 transitions. [2025-01-10 07:51:42,352 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4621 states and 6436 transitions. [2025-01-10 07:51:42,353 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:42,353 INFO L432 stractBuchiCegarLoop]: Abstraction has 4621 states and 6436 transitions. [2025-01-10 07:51:42,353 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-01-10 07:51:42,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4621 states and 6436 transitions. [2025-01-10 07:51:42,364 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4531 [2025-01-10 07:51:42,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:42,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:42,365 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:42,365 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:42,365 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-01-10 07:51:42,365 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" [2025-01-10 07:51:42,365 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:42,365 INFO L85 PathProgramCache]: Analyzing trace with hash 1020217665, now seen corresponding path program 2 times [2025-01-10 07:51:42,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:42,366 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019972970] [2025-01-10 07:51:42,366 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:42,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:42,370 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 52 statements into 1 equivalence classes. [2025-01-10 07:51:42,373 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 52 of 52 statements. [2025-01-10 07:51:42,373 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:42,373 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:42,373 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:42,375 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 52 statements into 1 equivalence classes. [2025-01-10 07:51:42,377 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 52 of 52 statements. [2025-01-10 07:51:42,377 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:42,377 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:42,382 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:42,382 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:42,382 INFO L85 PathProgramCache]: Analyzing trace with hash 905461682, now seen corresponding path program 2 times [2025-01-10 07:51:42,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:42,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344058748] [2025-01-10 07:51:42,382 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:42,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:42,385 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 13 statements into 1 equivalence classes. [2025-01-10 07:51:42,386 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-01-10 07:51:42,386 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:42,386 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:42,386 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:42,387 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-01-10 07:51:42,387 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-01-10 07:51:42,387 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:42,387 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:42,389 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:42,389 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:42,389 INFO L85 PathProgramCache]: Analyzing trace with hash 930741874, now seen corresponding path program 1 times [2025-01-10 07:51:42,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:42,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [890994667] [2025-01-10 07:51:42,389 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:42,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:42,394 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 65 statements into 1 equivalence classes. [2025-01-10 07:51:42,397 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 65 of 65 statements. [2025-01-10 07:51:42,397 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:42,397 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:42,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:42,417 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:42,418 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [890994667] [2025-01-10 07:51:42,418 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [890994667] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:42,418 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:42,418 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:42,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337364265] [2025-01-10 07:51:42,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:42,463 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:42,463 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:42,463 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:42,463 INFO L87 Difference]: Start difference. First operand 4621 states and 6436 transitions. cyclomatic complexity: 1821 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:42,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:42,511 INFO L93 Difference]: Finished difference Result 5186 states and 7187 transitions. [2025-01-10 07:51:42,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5186 states and 7187 transitions. [2025-01-10 07:51:42,528 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5104 [2025-01-10 07:51:42,543 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5186 states to 5186 states and 7187 transitions. [2025-01-10 07:51:42,543 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5186 [2025-01-10 07:51:42,546 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5186 [2025-01-10 07:51:42,547 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5186 states and 7187 transitions. [2025-01-10 07:51:42,554 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:42,554 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5186 states and 7187 transitions. [2025-01-10 07:51:42,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5186 states and 7187 transitions. [2025-01-10 07:51:42,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5186 to 5046. [2025-01-10 07:51:42,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5046 states, 5046 states have (on average 1.3882282996432818) internal successors, (7005), 5045 states have internal predecessors, (7005), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:42,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5046 states to 5046 states and 7005 transitions. [2025-01-10 07:51:42,621 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5046 states and 7005 transitions. [2025-01-10 07:51:42,621 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:42,622 INFO L432 stractBuchiCegarLoop]: Abstraction has 5046 states and 7005 transitions. [2025-01-10 07:51:42,622 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-01-10 07:51:42,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5046 states and 7005 transitions. [2025-01-10 07:51:42,633 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4964 [2025-01-10 07:51:42,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:42,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:42,634 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:42,634 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:42,634 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-01-10 07:51:42,634 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume !(0 == ~t3_st~0);" [2025-01-10 07:51:42,635 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:42,635 INFO L85 PathProgramCache]: Analyzing trace with hash 1020217665, now seen corresponding path program 3 times [2025-01-10 07:51:42,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:42,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1348461747] [2025-01-10 07:51:42,635 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:51:42,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:42,639 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 52 statements into 1 equivalence classes. [2025-01-10 07:51:42,641 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 52 of 52 statements. [2025-01-10 07:51:42,641 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:51:42,641 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:42,642 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:42,643 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 52 statements into 1 equivalence classes. [2025-01-10 07:51:42,645 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 52 of 52 statements. [2025-01-10 07:51:42,645 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:42,645 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:42,649 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:42,650 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:42,650 INFO L85 PathProgramCache]: Analyzing trace with hash -1733544658, now seen corresponding path program 1 times [2025-01-10 07:51:42,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:42,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760530406] [2025-01-10 07:51:42,650 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:42,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:42,653 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 15 statements into 1 equivalence classes. [2025-01-10 07:51:42,654 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 15 of 15 statements. [2025-01-10 07:51:42,655 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:42,655 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:42,655 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:42,656 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 15 statements into 1 equivalence classes. [2025-01-10 07:51:42,657 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 15 of 15 statements. [2025-01-10 07:51:42,657 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:42,657 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:42,658 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:42,659 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:42,659 INFO L85 PathProgramCache]: Analyzing trace with hash 1085883374, now seen corresponding path program 1 times [2025-01-10 07:51:42,659 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:42,659 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007586993] [2025-01-10 07:51:42,659 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:42,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:42,664 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-10 07:51:42,666 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-10 07:51:42,666 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:42,666 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:42,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:42,686 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:42,686 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1007586993] [2025-01-10 07:51:42,686 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1007586993] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:42,686 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:42,686 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:42,686 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760200173] [2025-01-10 07:51:42,686 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:42,730 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:42,730 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:42,730 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:42,731 INFO L87 Difference]: Start difference. First operand 5046 states and 7005 transitions. cyclomatic complexity: 1965 Second operand has 3 states, 2 states have (on average 33.5) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:42,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:42,786 INFO L93 Difference]: Finished difference Result 8460 states and 11673 transitions. [2025-01-10 07:51:42,786 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8460 states and 11673 transitions. [2025-01-10 07:51:42,817 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8350 [2025-01-10 07:51:42,893 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8460 states to 8460 states and 11673 transitions. [2025-01-10 07:51:42,893 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8460 [2025-01-10 07:51:42,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8460 [2025-01-10 07:51:42,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8460 states and 11673 transitions. [2025-01-10 07:51:42,919 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:42,920 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8460 states and 11673 transitions. [2025-01-10 07:51:42,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8460 states and 11673 transitions. [2025-01-10 07:51:43,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8460 to 8352. [2025-01-10 07:51:43,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8352 states, 8352 states have (on average 1.384698275862069) internal successors, (11565), 8351 states have internal predecessors, (11565), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:43,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8352 states to 8352 states and 11565 transitions. [2025-01-10 07:51:43,082 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8352 states and 11565 transitions. [2025-01-10 07:51:43,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:43,083 INFO L432 stractBuchiCegarLoop]: Abstraction has 8352 states and 11565 transitions. [2025-01-10 07:51:43,083 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-01-10 07:51:43,083 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8352 states and 11565 transitions. [2025-01-10 07:51:43,111 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8242 [2025-01-10 07:51:43,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:43,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:43,111 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:43,111 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:43,112 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-01-10 07:51:43,112 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" [2025-01-10 07:51:43,112 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:43,112 INFO L85 PathProgramCache]: Analyzing trace with hash 1020217665, now seen corresponding path program 4 times [2025-01-10 07:51:43,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:43,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880693347] [2025-01-10 07:51:43,112 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:51:43,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:43,122 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 52 statements into 2 equivalence classes. [2025-01-10 07:51:43,128 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 52 of 52 statements. [2025-01-10 07:51:43,128 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:51:43,128 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:43,128 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:43,129 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 52 statements into 1 equivalence classes. [2025-01-10 07:51:43,135 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 52 of 52 statements. [2025-01-10 07:51:43,135 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:43,135 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:43,142 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:43,142 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:43,142 INFO L85 PathProgramCache]: Analyzing trace with hash 510799858, now seen corresponding path program 1 times [2025-01-10 07:51:43,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:43,142 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919369516] [2025-01-10 07:51:43,142 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:43,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:43,144 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes. [2025-01-10 07:51:43,145 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements. [2025-01-10 07:51:43,145 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:43,145 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:43,145 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:43,145 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes. [2025-01-10 07:51:43,146 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements. [2025-01-10 07:51:43,146 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:43,146 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:43,147 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:43,147 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:43,147 INFO L85 PathProgramCache]: Analyzing trace with hash -143225166, now seen corresponding path program 1 times [2025-01-10 07:51:43,147 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:43,147 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404763808] [2025-01-10 07:51:43,147 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:43,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:43,158 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 69 statements into 1 equivalence classes. [2025-01-10 07:51:43,164 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 69 of 69 statements. [2025-01-10 07:51:43,167 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:43,167 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:43,167 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:43,169 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 69 statements into 1 equivalence classes. [2025-01-10 07:51:43,171 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 69 of 69 statements. [2025-01-10 07:51:43,171 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:43,171 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:43,175 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:43,814 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 52 statements into 1 equivalence classes. [2025-01-10 07:51:43,819 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 52 of 52 statements. [2025-01-10 07:51:43,819 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:43,819 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:43,819 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:43,827 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 52 statements into 1 equivalence classes. [2025-01-10 07:51:43,831 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 52 of 52 statements. [2025-01-10 07:51:43,831 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:43,831 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:43,913 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 10.01 07:51:43 BoogieIcfgContainer [2025-01-10 07:51:43,913 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-01-10 07:51:43,913 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-01-10 07:51:43,917 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-01-10 07:51:43,917 INFO L274 PluginConnector]: Witness Printer initialized [2025-01-10 07:51:43,918 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:51:39" (3/4) ... [2025-01-10 07:51:43,919 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-01-10 07:51:44,044 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-01-10 07:51:44,047 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-01-10 07:51:44,048 INFO L158 Benchmark]: Toolchain (without parser) took 6127.28ms. Allocated memory was 167.8MB in the beginning and 402.7MB in the end (delta: 234.9MB). Free memory was 129.6MB in the beginning and 336.9MB in the end (delta: -207.2MB). Peak memory consumption was 242.6MB. Max. memory is 16.1GB. [2025-01-10 07:51:44,048 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 226.5MB. Free memory is still 143.2MB. There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:51:44,048 INFO L158 Benchmark]: CACSL2BoogieTranslator took 249.17ms. Allocated memory is still 167.8MB. Free memory was 129.6MB in the beginning and 115.2MB in the end (delta: 14.5MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-01-10 07:51:44,049 INFO L158 Benchmark]: Boogie Procedure Inliner took 48.26ms. Allocated memory is still 167.8MB. Free memory was 115.2MB in the beginning and 111.4MB in the end (delta: 3.8MB). There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:51:44,049 INFO L158 Benchmark]: Boogie Preprocessor took 79.20ms. Allocated memory is still 167.8MB. Free memory was 111.4MB in the beginning and 107.6MB in the end (delta: 3.8MB). There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:51:44,049 INFO L158 Benchmark]: RCFGBuilder took 724.78ms. Allocated memory is still 167.8MB. Free memory was 107.6MB in the beginning and 63.4MB in the end (delta: 44.2MB). Peak memory consumption was 50.3MB. Max. memory is 16.1GB. [2025-01-10 07:51:44,049 INFO L158 Benchmark]: BuchiAutomizer took 4886.93ms. Allocated memory was 167.8MB in the beginning and 402.7MB in the end (delta: 234.9MB). Free memory was 63.4MB in the beginning and 133.2MB in the end (delta: -69.8MB). Peak memory consumption was 163.4MB. Max. memory is 16.1GB. [2025-01-10 07:51:44,049 INFO L158 Benchmark]: Witness Printer took 134.12ms. Allocated memory is still 402.7MB. Free memory was 133.2MB in the beginning and 336.9MB in the end (delta: -203.7MB). Peak memory consumption was 12.1MB. Max. memory is 16.1GB. [2025-01-10 07:51:44,050 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 226.5MB. Free memory is still 143.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 249.17ms. Allocated memory is still 167.8MB. Free memory was 129.6MB in the beginning and 115.2MB in the end (delta: 14.5MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 48.26ms. Allocated memory is still 167.8MB. Free memory was 115.2MB in the beginning and 111.4MB in the end (delta: 3.8MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 79.20ms. Allocated memory is still 167.8MB. Free memory was 111.4MB in the beginning and 107.6MB in the end (delta: 3.8MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 724.78ms. Allocated memory is still 167.8MB. Free memory was 107.6MB in the beginning and 63.4MB in the end (delta: 44.2MB). Peak memory consumption was 50.3MB. Max. memory is 16.1GB. * BuchiAutomizer took 4886.93ms. Allocated memory was 167.8MB in the beginning and 402.7MB in the end (delta: 234.9MB). Free memory was 63.4MB in the beginning and 133.2MB in the end (delta: -69.8MB). Peak memory consumption was 163.4MB. Max. memory is 16.1GB. * Witness Printer took 134.12ms. Allocated memory is still 402.7MB. Free memory was 133.2MB in the beginning and 336.9MB in the end (delta: -203.7MB). Peak memory consumption was 12.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (15 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.15 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 8352 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.7s and 16 iterations. TraceHistogramMax:1. Analysis of lassos took 2.4s. Construction of modules took 0.3s. Büchi inclusion checks took 1.7s. Highest rank in rank-based complementation 0. Minimization of det autom 15. Minimization of nondet autom 0. Automata minimization 0.8s AutomataMinimizationTime, 15 MinimizatonAttempts, 2193 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.4s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 6383 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 6383 mSDsluCounter, 13661 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 6154 mSDsCounter, 131 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 338 IncrementalHoareTripleChecker+Invalid, 469 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 131 mSolverCounterUnsat, 7507 mSDtfsCounter, 338 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc3 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 1]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L446] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L451] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L456] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L461] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L466] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L471] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L476] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L230] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L232] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L249] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L251] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L268] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L270] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L287] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L289] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L494] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L499] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L504] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L509] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L514] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L519] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L524] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L687] RET reset_delta_events() [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE !(\read(tmp_ndt_1)) [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE !(\read(tmp_ndt_2)) [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE !(\read(tmp_ndt_3)) [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 1]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L446] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L451] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L456] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L461] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L466] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L471] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L476] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L230] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L232] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L249] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L251] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L268] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L270] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L287] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L289] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L494] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L499] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L504] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L509] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L514] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L519] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L524] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L687] RET reset_delta_events() [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE !(\read(tmp_ndt_1)) [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE !(\read(tmp_ndt_2)) [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE !(\read(tmp_ndt_3)) [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-01-10 07:51:44,078 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)