./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/combinations/pc_sfifo_3.cil+token_ring.02.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 551b0097 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/combinations/pc_sfifo_3.cil+token_ring.02.cil-2.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d9dd329404607c04c3b8409033c911abc5eb1af40daa0f8673d76c8f1e85e1ae --- Real Ultimate output --- This is Ultimate 0.3.0-?-551b009-m [2025-01-09 06:06:25,213 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-01-09 06:06:25,259 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2025-01-09 06:06:25,264 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-01-09 06:06:25,264 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-01-09 06:06:25,282 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-01-09 06:06:25,283 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-01-09 06:06:25,283 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-01-09 06:06:25,283 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-01-09 06:06:25,283 INFO L153 SettingsManager]: * Use memory slicer=true [2025-01-09 06:06:25,283 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2025-01-09 06:06:25,283 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2025-01-09 06:06:25,284 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-01-09 06:06:25,284 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-01-09 06:06:25,284 INFO L153 SettingsManager]: * Use SBE=true [2025-01-09 06:06:25,284 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-01-09 06:06:25,284 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2025-01-09 06:06:25,284 INFO L153 SettingsManager]: * sizeof long=4 [2025-01-09 06:06:25,284 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-01-09 06:06:25,284 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-01-09 06:06:25,284 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-01-09 06:06:25,284 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2025-01-09 06:06:25,284 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2025-01-09 06:06:25,284 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2025-01-09 06:06:25,284 INFO L153 SettingsManager]: * sizeof long double=12 [2025-01-09 06:06:25,285 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-01-09 06:06:25,285 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-01-09 06:06:25,285 INFO L153 SettingsManager]: * Use constant arrays=true [2025-01-09 06:06:25,285 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-01-09 06:06:25,285 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-01-09 06:06:25,285 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2025-01-09 06:06:25,285 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2025-01-09 06:06:25,285 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2025-01-09 06:06:25,285 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2025-01-09 06:06:25,285 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-01-09 06:06:25,285 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2025-01-09 06:06:25,285 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2025-01-09 06:06:25,285 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2025-01-09 06:06:25,285 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-01-09 06:06:25,285 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2025-01-09 06:06:25,285 INFO L153 SettingsManager]: * Compute procedure contracts=false [2025-01-09 06:06:25,285 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2025-01-09 06:06:25,286 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-01-09 06:06:25,286 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2025-01-09 06:06:25,286 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2025-01-09 06:06:25,286 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2025-01-09 06:06:25,286 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2025-01-09 06:06:25,286 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2025-01-09 06:06:25,286 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d9dd329404607c04c3b8409033c911abc5eb1af40daa0f8673d76c8f1e85e1ae [2025-01-09 06:06:25,567 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-01-09 06:06:25,576 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-01-09 06:06:25,579 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-01-09 06:06:25,580 INFO L270 PluginConnector]: Initializing CDTParser... [2025-01-09 06:06:25,580 INFO L274 PluginConnector]: CDTParser initialized [2025-01-09 06:06:25,581 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/combinations/pc_sfifo_3.cil+token_ring.02.cil-2.c [2025-01-09 06:06:26,832 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/380426b3a/b99174cede034baa9fe865bdae30c2da/FLAG88ff8c41a [2025-01-09 06:06:27,096 INFO L384 CDTParser]: Found 1 translation units. [2025-01-09 06:06:27,096 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/combinations/pc_sfifo_3.cil+token_ring.02.cil-2.c [2025-01-09 06:06:27,113 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/380426b3a/b99174cede034baa9fe865bdae30c2da/FLAG88ff8c41a [2025-01-09 06:06:27,124 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/380426b3a/b99174cede034baa9fe865bdae30c2da [2025-01-09 06:06:27,126 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-01-09 06:06:27,127 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-01-09 06:06:27,128 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-01-09 06:06:27,128 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-01-09 06:06:27,131 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-01-09 06:06:27,132 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,133 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5c7891da and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27, skipping insertion in model container [2025-01-09 06:06:27,133 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,165 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-01-09 06:06:27,277 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/combinations/pc_sfifo_3.cil+token_ring.02.cil-2.c[911,924] [2025-01-09 06:06:27,328 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/combinations/pc_sfifo_3.cil+token_ring.02.cil-2.c[8416,8429] [2025-01-09 06:06:27,359 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-09 06:06:27,366 INFO L200 MainTranslator]: Completed pre-run [2025-01-09 06:06:27,374 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/combinations/pc_sfifo_3.cil+token_ring.02.cil-2.c[911,924] [2025-01-09 06:06:27,399 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/combinations/pc_sfifo_3.cil+token_ring.02.cil-2.c[8416,8429] [2025-01-09 06:06:27,413 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-09 06:06:27,433 INFO L204 MainTranslator]: Completed translation [2025-01-09 06:06:27,435 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27 WrapperNode [2025-01-09 06:06:27,436 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-01-09 06:06:27,437 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-01-09 06:06:27,437 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-01-09 06:06:27,437 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-01-09 06:06:27,442 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,457 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,487 INFO L138 Inliner]: procedures = 59, calls = 68, calls flagged for inlining = 27, calls inlined = 27, statements flattened = 485 [2025-01-09 06:06:27,487 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-01-09 06:06:27,491 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-01-09 06:06:27,491 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-01-09 06:06:27,491 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-01-09 06:06:27,497 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,498 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,505 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,523 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-01-09 06:06:27,526 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,526 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,533 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,537 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,546 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,549 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,550 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,555 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-01-09 06:06:27,557 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2025-01-09 06:06:27,557 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2025-01-09 06:06:27,558 INFO L274 PluginConnector]: RCFGBuilder initialized [2025-01-09 06:06:27,558 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27" (1/1) ... [2025-01-09 06:06:27,562 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2025-01-09 06:06:27,573 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-09 06:06:27,587 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2025-01-09 06:06:27,591 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2025-01-09 06:06:27,610 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-01-09 06:06:27,611 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2025-01-09 06:06:27,611 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2025-01-09 06:06:27,611 INFO L130 BoogieDeclarations]: Found specification of procedure is_do_write_p_triggered [2025-01-09 06:06:27,611 INFO L138 BoogieDeclarations]: Found implementation of procedure is_do_write_p_triggered [2025-01-09 06:06:27,611 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread1 [2025-01-09 06:06:27,611 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread1 [2025-01-09 06:06:27,611 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread2 [2025-01-09 06:06:27,611 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread2 [2025-01-09 06:06:27,612 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events1 [2025-01-09 06:06:27,612 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events1 [2025-01-09 06:06:27,612 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events2 [2025-01-09 06:06:27,612 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events2 [2025-01-09 06:06:27,612 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads2 [2025-01-09 06:06:27,612 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads2 [2025-01-09 06:06:27,612 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads1 [2025-01-09 06:06:27,612 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads1 [2025-01-09 06:06:27,613 INFO L130 BoogieDeclarations]: Found specification of procedure is_do_read_c_triggered [2025-01-09 06:06:27,613 INFO L138 BoogieDeclarations]: Found implementation of procedure is_do_read_c_triggered [2025-01-09 06:06:27,613 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels1 [2025-01-09 06:06:27,613 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels1 [2025-01-09 06:06:27,613 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels2 [2025-01-09 06:06:27,613 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels2 [2025-01-09 06:06:27,614 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-01-09 06:06:27,614 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events2 [2025-01-09 06:06:27,614 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events2 [2025-01-09 06:06:27,615 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events1 [2025-01-09 06:06:27,615 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events1 [2025-01-09 06:06:27,615 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-01-09 06:06:27,615 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-01-09 06:06:27,615 INFO L130 BoogieDeclarations]: Found specification of procedure error1 [2025-01-09 06:06:27,615 INFO L138 BoogieDeclarations]: Found implementation of procedure error1 [2025-01-09 06:06:27,615 INFO L130 BoogieDeclarations]: Found specification of procedure error2 [2025-01-09 06:06:27,615 INFO L138 BoogieDeclarations]: Found implementation of procedure error2 [2025-01-09 06:06:27,682 INFO L234 CfgBuilder]: Building ICFG [2025-01-09 06:06:27,684 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2025-01-09 06:06:28,068 INFO L727 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##48: assume !(1 == ~q_free~0); [2025-01-09 06:06:28,069 INFO L727 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##47: assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 2;~a_t~0 := do_read_c_~a~0#1; [2025-01-09 06:06:28,150 INFO L? ?]: Removed 74 outVars from TransFormulas that were not future-live. [2025-01-09 06:06:28,150 INFO L283 CfgBuilder]: Performing block encoding [2025-01-09 06:06:28,170 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-01-09 06:06:28,170 INFO L312 CfgBuilder]: Removed 9 assume(true) statements. [2025-01-09 06:06:28,170 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.01 06:06:28 BoogieIcfgContainer [2025-01-09 06:06:28,170 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2025-01-09 06:06:28,175 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2025-01-09 06:06:28,175 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2025-01-09 06:06:28,178 INFO L274 PluginConnector]: TraceAbstraction initialized [2025-01-09 06:06:28,179 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 09.01 06:06:27" (1/3) ... [2025-01-09 06:06:28,179 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@746f03a4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.01 06:06:28, skipping insertion in model container [2025-01-09 06:06:28,179 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.01 06:06:27" (2/3) ... [2025-01-09 06:06:28,179 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@746f03a4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.01 06:06:28, skipping insertion in model container [2025-01-09 06:06:28,179 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.01 06:06:28" (3/3) ... [2025-01-09 06:06:28,180 INFO L128 eAbstractionObserver]: Analyzing ICFG pc_sfifo_3.cil+token_ring.02.cil-2.c [2025-01-09 06:06:28,192 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2025-01-09 06:06:28,194 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG pc_sfifo_3.cil+token_ring.02.cil-2.c that has 16 procedures, 251 locations, 1 initial locations, 9 loop locations, and 2 error locations. [2025-01-09 06:06:28,248 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2025-01-09 06:06:28,257 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@47b26d3, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2025-01-09 06:06:28,258 INFO L334 AbstractCegarLoop]: Starting to check reachability of 2 error locations. [2025-01-09 06:06:28,262 INFO L276 IsEmpty]: Start isEmpty. Operand has 251 states, 201 states have (on average 1.5223880597014925) internal successors, (306), 207 states have internal predecessors, (306), 34 states have call successors, (34), 15 states have call predecessors, (34), 15 states have return successors, (34), 32 states have call predecessors, (34), 34 states have call successors, (34) [2025-01-09 06:06:28,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2025-01-09 06:06:28,269 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:28,270 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:28,270 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting error1Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:28,274 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:28,274 INFO L85 PathProgramCache]: Analyzing trace with hash -1923904682, now seen corresponding path program 1 times [2025-01-09 06:06:28,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:28,280 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [506507774] [2025-01-09 06:06:28,280 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:28,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:28,347 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 63 statements into 1 equivalence classes. [2025-01-09 06:06:28,367 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 63 of 63 statements. [2025-01-09 06:06:28,368 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:28,368 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:28,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:28,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:28,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [506507774] [2025-01-09 06:06:28,641 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [506507774] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:28,641 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:28,641 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-09 06:06:28,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1926944428] [2025-01-09 06:06:28,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:28,644 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-01-09 06:06:28,645 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:28,656 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-09 06:06:28,657 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-09 06:06:28,658 INFO L87 Difference]: Start difference. First operand has 251 states, 201 states have (on average 1.5223880597014925) internal successors, (306), 207 states have internal predecessors, (306), 34 states have call successors, (34), 15 states have call predecessors, (34), 15 states have return successors, (34), 32 states have call predecessors, (34), 34 states have call successors, (34) Second operand has 5 states, 5 states have (on average 9.6) internal successors, (48), 5 states have internal predecessors, (48), 3 states have call successors, (8), 3 states have call predecessors, (8), 3 states have return successors, (7), 3 states have call predecessors, (7), 3 states have call successors, (7) [2025-01-09 06:06:29,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:29,187 INFO L93 Difference]: Finished difference Result 598 states and 899 transitions. [2025-01-09 06:06:29,188 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-01-09 06:06:29,189 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 9.6) internal successors, (48), 5 states have internal predecessors, (48), 3 states have call successors, (8), 3 states have call predecessors, (8), 3 states have return successors, (7), 3 states have call predecessors, (7), 3 states have call successors, (7) Word has length 63 [2025-01-09 06:06:29,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:29,197 INFO L225 Difference]: With dead ends: 598 [2025-01-09 06:06:29,197 INFO L226 Difference]: Without dead ends: 355 [2025-01-09 06:06:29,201 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2025-01-09 06:06:29,203 INFO L435 NwaCegarLoop]: 242 mSDtfsCounter, 317 mSDsluCounter, 580 mSDsCounter, 0 mSdLazyCounter, 494 mSolverCounterSat, 55 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 326 SdHoareTripleChecker+Valid, 822 SdHoareTripleChecker+Invalid, 549 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 55 IncrementalHoareTripleChecker+Valid, 494 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:29,203 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [326 Valid, 822 Invalid, 549 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [55 Valid, 494 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2025-01-09 06:06:29,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 355 states. [2025-01-09 06:06:29,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 355 to 348. [2025-01-09 06:06:29,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 348 states, 277 states have (on average 1.4729241877256318) internal successors, (408), 284 states have internal predecessors, (408), 47 states have call successors, (47), 22 states have call predecessors, (47), 22 states have return successors, (48), 44 states have call predecessors, (48), 43 states have call successors, (48) [2025-01-09 06:06:29,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 348 states to 348 states and 503 transitions. [2025-01-09 06:06:29,260 INFO L78 Accepts]: Start accepts. Automaton has 348 states and 503 transitions. Word has length 63 [2025-01-09 06:06:29,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:29,260 INFO L471 AbstractCegarLoop]: Abstraction has 348 states and 503 transitions. [2025-01-09 06:06:29,261 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 9.6) internal successors, (48), 5 states have internal predecessors, (48), 3 states have call successors, (8), 3 states have call predecessors, (8), 3 states have return successors, (7), 3 states have call predecessors, (7), 3 states have call successors, (7) [2025-01-09 06:06:29,261 INFO L276 IsEmpty]: Start isEmpty. Operand 348 states and 503 transitions. [2025-01-09 06:06:29,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2025-01-09 06:06:29,263 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:29,263 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:29,264 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2025-01-09 06:06:29,264 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting error1Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:29,264 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:29,264 INFO L85 PathProgramCache]: Analyzing trace with hash 84544022, now seen corresponding path program 1 times [2025-01-09 06:06:29,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:29,264 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309045088] [2025-01-09 06:06:29,264 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:29,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:29,272 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 63 statements into 1 equivalence classes. [2025-01-09 06:06:29,279 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 63 of 63 statements. [2025-01-09 06:06:29,280 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:29,280 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:29,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:29,348 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:29,348 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [309045088] [2025-01-09 06:06:29,348 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [309045088] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:29,348 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:29,348 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-09 06:06:29,348 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [699005915] [2025-01-09 06:06:29,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:29,349 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-01-09 06:06:29,349 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:29,350 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-09 06:06:29,350 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-09 06:06:29,350 INFO L87 Difference]: Start difference. First operand 348 states and 503 transitions. Second operand has 4 states, 4 states have (on average 12.0) internal successors, (48), 4 states have internal predecessors, (48), 4 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 3 states have call predecessors, (7), 4 states have call successors, (7) [2025-01-09 06:06:29,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:29,578 INFO L93 Difference]: Finished difference Result 925 states and 1327 transitions. [2025-01-09 06:06:29,579 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-09 06:06:29,579 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 12.0) internal successors, (48), 4 states have internal predecessors, (48), 4 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 3 states have call predecessors, (7), 4 states have call successors, (7) Word has length 63 [2025-01-09 06:06:29,580 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:29,584 INFO L225 Difference]: With dead ends: 925 [2025-01-09 06:06:29,584 INFO L226 Difference]: Without dead ends: 724 [2025-01-09 06:06:29,585 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-09 06:06:29,585 INFO L435 NwaCegarLoop]: 462 mSDtfsCounter, 442 mSDsluCounter, 401 mSDsCounter, 0 mSdLazyCounter, 116 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 442 SdHoareTripleChecker+Valid, 863 SdHoareTripleChecker+Invalid, 129 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 116 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:29,585 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [442 Valid, 863 Invalid, 129 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 116 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-01-09 06:06:29,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 724 states. [2025-01-09 06:06:29,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 724 to 710. [2025-01-09 06:06:29,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 710 states, 567 states have (on average 1.4320987654320987) internal successors, (812), 578 states have internal predecessors, (812), 87 states have call successors, (87), 50 states have call predecessors, (87), 54 states have return successors, (100), 84 states have call predecessors, (100), 83 states have call successors, (100) [2025-01-09 06:06:29,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 710 states to 710 states and 999 transitions. [2025-01-09 06:06:29,642 INFO L78 Accepts]: Start accepts. Automaton has 710 states and 999 transitions. Word has length 63 [2025-01-09 06:06:29,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:29,642 INFO L471 AbstractCegarLoop]: Abstraction has 710 states and 999 transitions. [2025-01-09 06:06:29,643 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 12.0) internal successors, (48), 4 states have internal predecessors, (48), 4 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 3 states have call predecessors, (7), 4 states have call successors, (7) [2025-01-09 06:06:29,644 INFO L276 IsEmpty]: Start isEmpty. Operand 710 states and 999 transitions. [2025-01-09 06:06:29,645 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2025-01-09 06:06:29,645 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:29,645 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:29,646 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2025-01-09 06:06:29,646 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting error1Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:29,646 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:29,646 INFO L85 PathProgramCache]: Analyzing trace with hash -2009041951, now seen corresponding path program 1 times [2025-01-09 06:06:29,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:29,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052371580] [2025-01-09 06:06:29,646 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:29,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:29,655 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 64 statements into 1 equivalence classes. [2025-01-09 06:06:29,660 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 64 of 64 statements. [2025-01-09 06:06:29,661 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:29,661 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:29,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:29,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:29,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052371580] [2025-01-09 06:06:29,724 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2052371580] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:29,724 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:29,724 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-01-09 06:06:29,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [109951331] [2025-01-09 06:06:29,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:29,724 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2025-01-09 06:06:29,725 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:29,725 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-01-09 06:06:29,725 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-01-09 06:06:29,725 INFO L87 Difference]: Start difference. First operand 710 states and 999 transitions. Second operand has 6 states, 6 states have (on average 8.166666666666666) internal successors, (49), 5 states have internal predecessors, (49), 2 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) [2025-01-09 06:06:29,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:29,781 INFO L93 Difference]: Finished difference Result 1288 states and 1815 transitions. [2025-01-09 06:06:29,781 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-01-09 06:06:29,781 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 8.166666666666666) internal successors, (49), 5 states have internal predecessors, (49), 2 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) Word has length 64 [2025-01-09 06:06:29,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:29,786 INFO L225 Difference]: With dead ends: 1288 [2025-01-09 06:06:29,786 INFO L226 Difference]: Without dead ends: 725 [2025-01-09 06:06:29,788 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-01-09 06:06:29,789 INFO L435 NwaCegarLoop]: 346 mSDtfsCounter, 0 mSDsluCounter, 1378 mSDsCounter, 0 mSdLazyCounter, 20 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1724 SdHoareTripleChecker+Invalid, 20 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 20 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:29,791 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1724 Invalid, 20 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 20 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:06:29,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 725 states. [2025-01-09 06:06:29,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 725 to 725. [2025-01-09 06:06:29,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 725 states, 579 states have (on average 1.4179620034542315) internal successors, (821), 590 states have internal predecessors, (821), 87 states have call successors, (87), 50 states have call predecessors, (87), 57 states have return successors, (105), 87 states have call predecessors, (105), 83 states have call successors, (105) [2025-01-09 06:06:29,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 725 states to 725 states and 1013 transitions. [2025-01-09 06:06:29,839 INFO L78 Accepts]: Start accepts. Automaton has 725 states and 1013 transitions. Word has length 64 [2025-01-09 06:06:29,839 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:29,839 INFO L471 AbstractCegarLoop]: Abstraction has 725 states and 1013 transitions. [2025-01-09 06:06:29,839 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 8.166666666666666) internal successors, (49), 5 states have internal predecessors, (49), 2 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) [2025-01-09 06:06:29,839 INFO L276 IsEmpty]: Start isEmpty. Operand 725 states and 1013 transitions. [2025-01-09 06:06:29,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2025-01-09 06:06:29,843 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:29,843 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:29,843 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2025-01-09 06:06:29,843 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting error1Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:29,844 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:29,844 INFO L85 PathProgramCache]: Analyzing trace with hash 1891558559, now seen corresponding path program 1 times [2025-01-09 06:06:29,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:29,845 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744555982] [2025-01-09 06:06:29,845 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:29,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:29,854 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 64 statements into 1 equivalence classes. [2025-01-09 06:06:29,857 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 64 of 64 statements. [2025-01-09 06:06:29,859 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:29,859 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:29,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:29,917 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:29,917 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [744555982] [2025-01-09 06:06:29,917 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [744555982] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:29,917 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:29,917 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-01-09 06:06:29,917 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172075260] [2025-01-09 06:06:29,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:29,917 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2025-01-09 06:06:29,917 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:29,918 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-01-09 06:06:29,918 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-01-09 06:06:29,918 INFO L87 Difference]: Start difference. First operand 725 states and 1013 transitions. Second operand has 6 states, 6 states have (on average 8.166666666666666) internal successors, (49), 6 states have internal predecessors, (49), 4 states have call successors, (8), 2 states have call predecessors, (8), 4 states have return successors, (7), 4 states have call predecessors, (7), 4 states have call successors, (7) [2025-01-09 06:06:30,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:30,445 INFO L93 Difference]: Finished difference Result 2354 states and 3285 transitions. [2025-01-09 06:06:30,445 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-01-09 06:06:30,445 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 8.166666666666666) internal successors, (49), 6 states have internal predecessors, (49), 4 states have call successors, (8), 2 states have call predecessors, (8), 4 states have return successors, (7), 4 states have call predecessors, (7), 4 states have call successors, (7) Word has length 64 [2025-01-09 06:06:30,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:30,450 INFO L225 Difference]: With dead ends: 2354 [2025-01-09 06:06:30,450 INFO L226 Difference]: Without dead ends: 920 [2025-01-09 06:06:30,453 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2025-01-09 06:06:30,454 INFO L435 NwaCegarLoop]: 572 mSDtfsCounter, 1205 mSDsluCounter, 1105 mSDsCounter, 0 mSdLazyCounter, 435 mSolverCounterSat, 245 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1213 SdHoareTripleChecker+Valid, 1677 SdHoareTripleChecker+Invalid, 680 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 245 IncrementalHoareTripleChecker+Valid, 435 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:30,455 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1213 Valid, 1677 Invalid, 680 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [245 Valid, 435 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2025-01-09 06:06:30,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 920 states. [2025-01-09 06:06:30,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 920 to 677. [2025-01-09 06:06:30,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 677 states, 531 states have (on average 1.3822975517890772) internal successors, (734), 542 states have internal predecessors, (734), 87 states have call successors, (87), 50 states have call predecessors, (87), 57 states have return successors, (97), 87 states have call predecessors, (97), 83 states have call successors, (97) [2025-01-09 06:06:30,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 677 states to 677 states and 918 transitions. [2025-01-09 06:06:30,501 INFO L78 Accepts]: Start accepts. Automaton has 677 states and 918 transitions. Word has length 64 [2025-01-09 06:06:30,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:30,501 INFO L471 AbstractCegarLoop]: Abstraction has 677 states and 918 transitions. [2025-01-09 06:06:30,501 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 8.166666666666666) internal successors, (49), 6 states have internal predecessors, (49), 4 states have call successors, (8), 2 states have call predecessors, (8), 4 states have return successors, (7), 4 states have call predecessors, (7), 4 states have call successors, (7) [2025-01-09 06:06:30,501 INFO L276 IsEmpty]: Start isEmpty. Operand 677 states and 918 transitions. [2025-01-09 06:06:30,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2025-01-09 06:06:30,502 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:30,502 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:30,502 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2025-01-09 06:06:30,502 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting error1Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:30,502 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:30,503 INFO L85 PathProgramCache]: Analyzing trace with hash 1537209980, now seen corresponding path program 1 times [2025-01-09 06:06:30,503 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:30,503 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544189919] [2025-01-09 06:06:30,503 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:30,503 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:30,512 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 65 statements into 1 equivalence classes. [2025-01-09 06:06:30,516 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 65 of 65 statements. [2025-01-09 06:06:30,516 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:30,516 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:30,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:30,623 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:30,624 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [544189919] [2025-01-09 06:06:30,624 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [544189919] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:30,624 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:30,624 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-01-09 06:06:30,624 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1038204373] [2025-01-09 06:06:30,624 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:30,624 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-01-09 06:06:30,624 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:30,625 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-01-09 06:06:30,625 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2025-01-09 06:06:30,625 INFO L87 Difference]: Start difference. First operand 677 states and 918 transitions. Second operand has 7 states, 6 states have (on average 8.333333333333334) internal successors, (50), 6 states have internal predecessors, (50), 4 states have call successors, (8), 3 states have call predecessors, (8), 4 states have return successors, (7), 5 states have call predecessors, (7), 4 states have call successors, (7) [2025-01-09 06:06:31,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:31,138 INFO L93 Difference]: Finished difference Result 1470 states and 1981 transitions. [2025-01-09 06:06:31,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-01-09 06:06:31,138 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 6 states have (on average 8.333333333333334) internal successors, (50), 6 states have internal predecessors, (50), 4 states have call successors, (8), 3 states have call predecessors, (8), 4 states have return successors, (7), 5 states have call predecessors, (7), 4 states have call successors, (7) Word has length 65 [2025-01-09 06:06:31,141 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:31,143 INFO L225 Difference]: With dead ends: 1470 [2025-01-09 06:06:31,143 INFO L226 Difference]: Without dead ends: 133 [2025-01-09 06:06:31,145 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=74, Unknown=0, NotChecked=0, Total=110 [2025-01-09 06:06:31,145 INFO L435 NwaCegarLoop]: 239 mSDtfsCounter, 637 mSDsluCounter, 702 mSDsCounter, 0 mSdLazyCounter, 712 mSolverCounterSat, 84 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 670 SdHoareTripleChecker+Valid, 941 SdHoareTripleChecker+Invalid, 796 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 84 IncrementalHoareTripleChecker+Valid, 712 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:31,145 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [670 Valid, 941 Invalid, 796 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [84 Valid, 712 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2025-01-09 06:06:31,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2025-01-09 06:06:31,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 133. [2025-01-09 06:06:31,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133 states, 108 states have (on average 1.5) internal successors, (162), 110 states have internal predecessors, (162), 18 states have call successors, (18), 7 states have call predecessors, (18), 6 states have return successors, (16), 16 states have call predecessors, (16), 16 states have call successors, (16) [2025-01-09 06:06:31,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 196 transitions. [2025-01-09 06:06:31,154 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 196 transitions. Word has length 65 [2025-01-09 06:06:31,154 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:31,154 INFO L471 AbstractCegarLoop]: Abstraction has 133 states and 196 transitions. [2025-01-09 06:06:31,154 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 6 states have (on average 8.333333333333334) internal successors, (50), 6 states have internal predecessors, (50), 4 states have call successors, (8), 3 states have call predecessors, (8), 4 states have return successors, (7), 5 states have call predecessors, (7), 4 states have call successors, (7) [2025-01-09 06:06:31,154 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 196 transitions. [2025-01-09 06:06:31,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:31,155 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:31,155 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:31,155 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2025-01-09 06:06:31,155 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:31,156 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:31,156 INFO L85 PathProgramCache]: Analyzing trace with hash 311614495, now seen corresponding path program 1 times [2025-01-09 06:06:31,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:31,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844896671] [2025-01-09 06:06:31,156 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:31,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:31,166 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:31,170 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:31,170 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:31,170 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:31,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:31,194 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:31,194 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844896671] [2025-01-09 06:06:31,194 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [844896671] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:31,194 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:31,194 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-09 06:06:31,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1921966087] [2025-01-09 06:06:31,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:31,194 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-01-09 06:06:31,194 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:31,195 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-09 06:06:31,195 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-09 06:06:31,195 INFO L87 Difference]: Start difference. First operand 133 states and 196 transitions. Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:31,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:31,204 INFO L93 Difference]: Finished difference Result 258 states and 381 transitions. [2025-01-09 06:06:31,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-09 06:06:31,205 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2025-01-09 06:06:31,205 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:31,206 INFO L225 Difference]: With dead ends: 258 [2025-01-09 06:06:31,206 INFO L226 Difference]: Without dead ends: 133 [2025-01-09 06:06:31,206 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-09 06:06:31,207 INFO L435 NwaCegarLoop]: 194 mSDtfsCounter, 188 mSDsluCounter, 1 mSDsCounter, 0 mSdLazyCounter, 2 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 188 SdHoareTripleChecker+Valid, 195 SdHoareTripleChecker+Invalid, 2 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 2 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:31,207 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [188 Valid, 195 Invalid, 2 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 2 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:06:31,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2025-01-09 06:06:31,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 133. [2025-01-09 06:06:31,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133 states, 108 states have (on average 1.4907407407407407) internal successors, (161), 110 states have internal predecessors, (161), 18 states have call successors, (18), 7 states have call predecessors, (18), 6 states have return successors, (16), 16 states have call predecessors, (16), 16 states have call successors, (16) [2025-01-09 06:06:31,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 195 transitions. [2025-01-09 06:06:31,228 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 195 transitions. Word has length 67 [2025-01-09 06:06:31,228 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:31,228 INFO L471 AbstractCegarLoop]: Abstraction has 133 states and 195 transitions. [2025-01-09 06:06:31,228 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:31,228 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 195 transitions. [2025-01-09 06:06:31,229 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:31,229 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:31,229 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:31,229 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2025-01-09 06:06:31,230 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:31,230 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:31,230 INFO L85 PathProgramCache]: Analyzing trace with hash -122114591, now seen corresponding path program 1 times [2025-01-09 06:06:31,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:31,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902964981] [2025-01-09 06:06:31,230 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:31,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:31,238 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:31,241 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:31,242 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:31,242 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:31,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:31,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:31,286 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [902964981] [2025-01-09 06:06:31,286 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [902964981] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:31,286 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:31,286 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-09 06:06:31,287 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [624717780] [2025-01-09 06:06:31,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:31,287 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-01-09 06:06:31,287 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:31,287 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-09 06:06:31,288 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-09 06:06:31,288 INFO L87 Difference]: Start difference. First operand 133 states and 195 transitions. Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 4 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:31,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:31,467 INFO L93 Difference]: Finished difference Result 385 states and 573 transitions. [2025-01-09 06:06:31,467 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-01-09 06:06:31,467 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.2) internal successors, (56), 4 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2025-01-09 06:06:31,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:31,469 INFO L225 Difference]: With dead ends: 385 [2025-01-09 06:06:31,469 INFO L226 Difference]: Without dead ends: 263 [2025-01-09 06:06:31,470 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2025-01-09 06:06:31,470 INFO L435 NwaCegarLoop]: 151 mSDtfsCounter, 313 mSDsluCounter, 363 mSDsCounter, 0 mSdLazyCounter, 227 mSolverCounterSat, 40 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 323 SdHoareTripleChecker+Valid, 514 SdHoareTripleChecker+Invalid, 267 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 40 IncrementalHoareTripleChecker+Valid, 227 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:31,470 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [323 Valid, 514 Invalid, 267 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [40 Valid, 227 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-01-09 06:06:31,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 263 states. [2025-01-09 06:06:31,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 263 to 252. [2025-01-09 06:06:31,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 252 states, 209 states have (on average 1.507177033492823) internal successors, (315), 212 states have internal predecessors, (315), 29 states have call successors, (29), 13 states have call predecessors, (29), 13 states have return successors, (28), 27 states have call predecessors, (28), 27 states have call successors, (28) [2025-01-09 06:06:31,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 252 states to 252 states and 372 transitions. [2025-01-09 06:06:31,481 INFO L78 Accepts]: Start accepts. Automaton has 252 states and 372 transitions. Word has length 67 [2025-01-09 06:06:31,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:31,481 INFO L471 AbstractCegarLoop]: Abstraction has 252 states and 372 transitions. [2025-01-09 06:06:31,481 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.2) internal successors, (56), 4 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:31,481 INFO L276 IsEmpty]: Start isEmpty. Operand 252 states and 372 transitions. [2025-01-09 06:06:31,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:31,482 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:31,482 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:31,482 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2025-01-09 06:06:31,482 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:31,483 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:31,483 INFO L85 PathProgramCache]: Analyzing trace with hash 619890909, now seen corresponding path program 1 times [2025-01-09 06:06:31,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:31,483 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873907201] [2025-01-09 06:06:31,483 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:31,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:31,488 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:31,490 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:31,490 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:31,490 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:31,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:31,548 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:31,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873907201] [2025-01-09 06:06:31,549 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1873907201] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:31,549 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:31,549 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-01-09 06:06:31,549 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [185942471] [2025-01-09 06:06:31,549 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:31,549 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2025-01-09 06:06:31,550 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:31,550 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-01-09 06:06:31,551 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-01-09 06:06:31,551 INFO L87 Difference]: Start difference. First operand 252 states and 372 transitions. Second operand has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:31,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:31,839 INFO L93 Difference]: Finished difference Result 640 states and 952 transitions. [2025-01-09 06:06:31,839 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-01-09 06:06:31,840 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2025-01-09 06:06:31,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:31,842 INFO L225 Difference]: With dead ends: 640 [2025-01-09 06:06:31,842 INFO L226 Difference]: Without dead ends: 399 [2025-01-09 06:06:31,843 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2025-01-09 06:06:31,843 INFO L435 NwaCegarLoop]: 247 mSDtfsCounter, 302 mSDsluCounter, 704 mSDsCounter, 0 mSdLazyCounter, 437 mSolverCounterSat, 24 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 312 SdHoareTripleChecker+Valid, 951 SdHoareTripleChecker+Invalid, 461 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 24 IncrementalHoareTripleChecker+Valid, 437 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:31,843 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [312 Valid, 951 Invalid, 461 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [24 Valid, 437 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-01-09 06:06:31,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 399 states. [2025-01-09 06:06:31,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 399 to 364. [2025-01-09 06:06:31,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 364 states, 303 states have (on average 1.5016501650165017) internal successors, (455), 307 states have internal predecessors, (455), 40 states have call successors, (40), 19 states have call predecessors, (40), 20 states have return successors, (42), 39 states have call predecessors, (42), 38 states have call successors, (42) [2025-01-09 06:06:31,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 364 states to 364 states and 537 transitions. [2025-01-09 06:06:31,857 INFO L78 Accepts]: Start accepts. Automaton has 364 states and 537 transitions. Word has length 67 [2025-01-09 06:06:31,857 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:31,858 INFO L471 AbstractCegarLoop]: Abstraction has 364 states and 537 transitions. [2025-01-09 06:06:31,858 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:31,858 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 537 transitions. [2025-01-09 06:06:31,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:31,858 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:31,858 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:31,858 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2025-01-09 06:06:31,858 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:31,859 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:31,859 INFO L85 PathProgramCache]: Analyzing trace with hash 1063791583, now seen corresponding path program 1 times [2025-01-09 06:06:31,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:31,859 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [157337618] [2025-01-09 06:06:31,859 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:31,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:31,863 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:31,865 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:31,865 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:31,865 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:31,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:31,928 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:31,928 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [157337618] [2025-01-09 06:06:31,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [157337618] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:31,929 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:31,929 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-09 06:06:31,929 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [818175467] [2025-01-09 06:06:31,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:31,929 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-01-09 06:06:31,929 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:31,929 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-09 06:06:31,929 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-09 06:06:31,929 INFO L87 Difference]: Start difference. First operand 364 states and 537 transitions. Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:32,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:32,058 INFO L93 Difference]: Finished difference Result 737 states and 1096 transitions. [2025-01-09 06:06:32,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-09 06:06:32,059 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2025-01-09 06:06:32,060 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:32,062 INFO L225 Difference]: With dead ends: 737 [2025-01-09 06:06:32,062 INFO L226 Difference]: Without dead ends: 384 [2025-01-09 06:06:32,063 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2025-01-09 06:06:32,064 INFO L435 NwaCegarLoop]: 136 mSDtfsCounter, 230 mSDsluCounter, 211 mSDsCounter, 0 mSdLazyCounter, 170 mSolverCounterSat, 27 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 240 SdHoareTripleChecker+Valid, 347 SdHoareTripleChecker+Invalid, 197 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 27 IncrementalHoareTripleChecker+Valid, 170 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:32,064 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [240 Valid, 347 Invalid, 197 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [27 Valid, 170 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-01-09 06:06:32,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states. [2025-01-09 06:06:32,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 364. [2025-01-09 06:06:32,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 364 states, 303 states have (on average 1.4917491749174918) internal successors, (452), 307 states have internal predecessors, (452), 40 states have call successors, (40), 19 states have call predecessors, (40), 20 states have return successors, (42), 39 states have call predecessors, (42), 38 states have call successors, (42) [2025-01-09 06:06:32,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 364 states to 364 states and 534 transitions. [2025-01-09 06:06:32,082 INFO L78 Accepts]: Start accepts. Automaton has 364 states and 534 transitions. Word has length 67 [2025-01-09 06:06:32,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:32,082 INFO L471 AbstractCegarLoop]: Abstraction has 364 states and 534 transitions. [2025-01-09 06:06:32,082 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:32,083 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 534 transitions. [2025-01-09 06:06:32,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:32,083 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:32,083 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:32,083 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2025-01-09 06:06:32,083 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:32,084 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:32,084 INFO L85 PathProgramCache]: Analyzing trace with hash -964794527, now seen corresponding path program 1 times [2025-01-09 06:06:32,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:32,085 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238115411] [2025-01-09 06:06:32,085 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:32,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:32,090 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:32,092 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:32,093 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:32,093 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:32,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:32,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:32,154 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238115411] [2025-01-09 06:06:32,154 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1238115411] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:32,154 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:32,154 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-01-09 06:06:32,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1524822612] [2025-01-09 06:06:32,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:32,155 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2025-01-09 06:06:32,155 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:32,155 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-01-09 06:06:32,155 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-01-09 06:06:32,155 INFO L87 Difference]: Start difference. First operand 364 states and 534 transitions. Second operand has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:32,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:32,423 INFO L93 Difference]: Finished difference Result 992 states and 1458 transitions. [2025-01-09 06:06:32,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-01-09 06:06:32,424 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2025-01-09 06:06:32,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:32,427 INFO L225 Difference]: With dead ends: 992 [2025-01-09 06:06:32,428 INFO L226 Difference]: Without dead ends: 639 [2025-01-09 06:06:32,429 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2025-01-09 06:06:32,429 INFO L435 NwaCegarLoop]: 153 mSDtfsCounter, 341 mSDsluCounter, 477 mSDsCounter, 0 mSdLazyCounter, 367 mSolverCounterSat, 38 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 354 SdHoareTripleChecker+Valid, 630 SdHoareTripleChecker+Invalid, 405 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 38 IncrementalHoareTripleChecker+Valid, 367 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:32,429 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [354 Valid, 630 Invalid, 405 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [38 Valid, 367 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-01-09 06:06:32,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 639 states. [2025-01-09 06:06:32,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 639 to 567. [2025-01-09 06:06:32,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 567 states, 470 states have (on average 1.4702127659574469) internal successors, (691), 478 states have internal predecessors, (691), 60 states have call successors, (60), 31 states have call predecessors, (60), 36 states have return successors, (74), 61 states have call predecessors, (74), 58 states have call successors, (74) [2025-01-09 06:06:32,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 567 states to 567 states and 825 transitions. [2025-01-09 06:06:32,469 INFO L78 Accepts]: Start accepts. Automaton has 567 states and 825 transitions. Word has length 67 [2025-01-09 06:06:32,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:32,472 INFO L471 AbstractCegarLoop]: Abstraction has 567 states and 825 transitions. [2025-01-09 06:06:32,473 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:32,473 INFO L276 IsEmpty]: Start isEmpty. Operand 567 states and 825 transitions. [2025-01-09 06:06:32,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:32,473 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:32,474 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:32,474 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2025-01-09 06:06:32,474 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:32,474 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:32,474 INFO L85 PathProgramCache]: Analyzing trace with hash -1445874785, now seen corresponding path program 1 times [2025-01-09 06:06:32,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:32,474 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625943440] [2025-01-09 06:06:32,474 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:32,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:32,480 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:32,482 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:32,482 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:32,482 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:32,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:32,537 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:32,537 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625943440] [2025-01-09 06:06:32,537 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [625943440] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:32,537 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:32,537 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-01-09 06:06:32,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342416610] [2025-01-09 06:06:32,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:32,537 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2025-01-09 06:06:32,537 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:32,538 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-01-09 06:06:32,538 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-01-09 06:06:32,538 INFO L87 Difference]: Start difference. First operand 567 states and 825 transitions. Second operand has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:32,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:32,876 INFO L93 Difference]: Finished difference Result 1607 states and 2345 transitions. [2025-01-09 06:06:32,876 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-01-09 06:06:32,876 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2025-01-09 06:06:32,877 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:32,882 INFO L225 Difference]: With dead ends: 1607 [2025-01-09 06:06:32,882 INFO L226 Difference]: Without dead ends: 1051 [2025-01-09 06:06:32,883 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2025-01-09 06:06:32,884 INFO L435 NwaCegarLoop]: 229 mSDtfsCounter, 284 mSDsluCounter, 648 mSDsCounter, 0 mSdLazyCounter, 470 mSolverCounterSat, 26 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 293 SdHoareTripleChecker+Valid, 877 SdHoareTripleChecker+Invalid, 496 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 26 IncrementalHoareTripleChecker+Valid, 470 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:32,885 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [293 Valid, 877 Invalid, 496 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [26 Valid, 470 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2025-01-09 06:06:32,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1051 states. [2025-01-09 06:06:32,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1051 to 994. [2025-01-09 06:06:32,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 994 states, 821 states have (on average 1.4579780755176615) internal successors, (1197), 843 states have internal predecessors, (1197), 98 states have call successors, (98), 55 states have call predecessors, (98), 74 states have return successors, (160), 103 states have call predecessors, (160), 96 states have call successors, (160) [2025-01-09 06:06:32,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 994 states to 994 states and 1455 transitions. [2025-01-09 06:06:32,959 INFO L78 Accepts]: Start accepts. Automaton has 994 states and 1455 transitions. Word has length 67 [2025-01-09 06:06:32,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:32,959 INFO L471 AbstractCegarLoop]: Abstraction has 994 states and 1455 transitions. [2025-01-09 06:06:32,959 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:32,959 INFO L276 IsEmpty]: Start isEmpty. Operand 994 states and 1455 transitions. [2025-01-09 06:06:32,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:32,960 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:32,960 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:32,961 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2025-01-09 06:06:32,961 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:32,961 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:32,961 INFO L85 PathProgramCache]: Analyzing trace with hash -1461393503, now seen corresponding path program 1 times [2025-01-09 06:06:32,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:32,961 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [162990252] [2025-01-09 06:06:32,961 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:32,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:32,966 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:32,969 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:32,969 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:32,969 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:33,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:33,003 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:33,004 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [162990252] [2025-01-09 06:06:33,004 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [162990252] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:33,004 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:33,004 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-09 06:06:33,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [123444618] [2025-01-09 06:06:33,004 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:33,004 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-01-09 06:06:33,004 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:33,004 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-09 06:06:33,004 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-09 06:06:33,004 INFO L87 Difference]: Start difference. First operand 994 states and 1455 transitions. Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:33,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:33,066 INFO L93 Difference]: Finished difference Result 2003 states and 2968 transitions. [2025-01-09 06:06:33,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-09 06:06:33,066 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2025-01-09 06:06:33,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:33,072 INFO L225 Difference]: With dead ends: 2003 [2025-01-09 06:06:33,072 INFO L226 Difference]: Without dead ends: 1021 [2025-01-09 06:06:33,074 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-09 06:06:33,075 INFO L435 NwaCegarLoop]: 191 mSDtfsCounter, 0 mSDsluCounter, 567 mSDsCounter, 0 mSdLazyCounter, 17 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 758 SdHoareTripleChecker+Invalid, 17 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 17 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:33,075 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 758 Invalid, 17 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 17 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:06:33,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1021 states. [2025-01-09 06:06:33,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1021 to 1021. [2025-01-09 06:06:33,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1021 states, 848 states have (on average 1.4433962264150944) internal successors, (1224), 870 states have internal predecessors, (1224), 98 states have call successors, (98), 55 states have call predecessors, (98), 74 states have return successors, (160), 103 states have call predecessors, (160), 96 states have call successors, (160) [2025-01-09 06:06:33,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1021 states to 1021 states and 1482 transitions. [2025-01-09 06:06:33,131 INFO L78 Accepts]: Start accepts. Automaton has 1021 states and 1482 transitions. Word has length 67 [2025-01-09 06:06:33,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:33,131 INFO L471 AbstractCegarLoop]: Abstraction has 1021 states and 1482 transitions. [2025-01-09 06:06:33,131 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:33,132 INFO L276 IsEmpty]: Start isEmpty. Operand 1021 states and 1482 transitions. [2025-01-09 06:06:33,133 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:33,133 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:33,133 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:33,133 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2025-01-09 06:06:33,133 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:33,134 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:33,134 INFO L85 PathProgramCache]: Analyzing trace with hash 1461766495, now seen corresponding path program 1 times [2025-01-09 06:06:33,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:33,134 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240187355] [2025-01-09 06:06:33,134 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:33,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:33,139 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:33,142 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:33,143 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:33,143 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:33,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:33,168 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:33,168 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [240187355] [2025-01-09 06:06:33,168 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [240187355] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:33,168 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:33,168 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-09 06:06:33,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2034510257] [2025-01-09 06:06:33,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:33,169 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-01-09 06:06:33,169 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:33,169 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-09 06:06:33,169 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-09 06:06:33,170 INFO L87 Difference]: Start difference. First operand 1021 states and 1482 transitions. Second operand has 4 states, 4 states have (on average 14.0) internal successors, (56), 4 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:33,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:33,374 INFO L93 Difference]: Finished difference Result 3005 states and 4390 transitions. [2025-01-09 06:06:33,375 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-09 06:06:33,375 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.0) internal successors, (56), 4 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2025-01-09 06:06:33,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:33,384 INFO L225 Difference]: With dead ends: 3005 [2025-01-09 06:06:33,384 INFO L226 Difference]: Without dead ends: 1996 [2025-01-09 06:06:33,387 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-09 06:06:33,387 INFO L435 NwaCegarLoop]: 350 mSDtfsCounter, 334 mSDsluCounter, 289 mSDsCounter, 0 mSdLazyCounter, 79 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 334 SdHoareTripleChecker+Valid, 639 SdHoareTripleChecker+Invalid, 84 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 79 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:33,387 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [334 Valid, 639 Invalid, 84 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 79 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-01-09 06:06:33,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1996 states. [2025-01-09 06:06:33,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1996 to 1983. [2025-01-09 06:06:33,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1983 states, 1649 states have (on average 1.4329896907216495) internal successors, (2363), 1691 states have internal predecessors, (2363), 185 states have call successors, (185), 109 states have call predecessors, (185), 148 states have return successors, (304), 190 states have call predecessors, (304), 183 states have call successors, (304) [2025-01-09 06:06:33,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1983 states to 1983 states and 2852 transitions. [2025-01-09 06:06:33,499 INFO L78 Accepts]: Start accepts. Automaton has 1983 states and 2852 transitions. Word has length 67 [2025-01-09 06:06:33,499 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:33,499 INFO L471 AbstractCegarLoop]: Abstraction has 1983 states and 2852 transitions. [2025-01-09 06:06:33,499 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.0) internal successors, (56), 4 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:33,499 INFO L276 IsEmpty]: Start isEmpty. Operand 1983 states and 2852 transitions. [2025-01-09 06:06:33,500 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:33,500 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:33,500 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:33,500 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2025-01-09 06:06:33,500 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:33,501 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:33,501 INFO L85 PathProgramCache]: Analyzing trace with hash 1985087166, now seen corresponding path program 1 times [2025-01-09 06:06:33,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:33,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936475859] [2025-01-09 06:06:33,501 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:33,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:33,507 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:33,511 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:33,511 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:33,511 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:33,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:33,548 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:33,548 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [936475859] [2025-01-09 06:06:33,548 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [936475859] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:33,548 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:33,548 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-09 06:06:33,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257105030] [2025-01-09 06:06:33,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:33,548 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-01-09 06:06:33,548 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:33,548 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-09 06:06:33,549 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-09 06:06:33,549 INFO L87 Difference]: Start difference. First operand 1983 states and 2852 transitions. Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:33,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:33,674 INFO L93 Difference]: Finished difference Result 3981 states and 5795 transitions. [2025-01-09 06:06:33,674 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-09 06:06:33,674 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2025-01-09 06:06:33,675 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:33,682 INFO L225 Difference]: With dead ends: 3981 [2025-01-09 06:06:33,683 INFO L226 Difference]: Without dead ends: 2010 [2025-01-09 06:06:33,687 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-09 06:06:33,687 INFO L435 NwaCegarLoop]: 191 mSDtfsCounter, 0 mSDsluCounter, 567 mSDsCounter, 0 mSdLazyCounter, 17 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 758 SdHoareTripleChecker+Invalid, 17 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 17 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:33,687 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 758 Invalid, 17 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 17 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:06:33,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2010 states. [2025-01-09 06:06:33,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2010 to 2010. [2025-01-09 06:06:33,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2010 states, 1676 states have (on average 1.4206443914081146) internal successors, (2381), 1718 states have internal predecessors, (2381), 185 states have call successors, (185), 109 states have call predecessors, (185), 148 states have return successors, (304), 190 states have call predecessors, (304), 183 states have call successors, (304) [2025-01-09 06:06:33,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2010 states to 2010 states and 2870 transitions. [2025-01-09 06:06:33,803 INFO L78 Accepts]: Start accepts. Automaton has 2010 states and 2870 transitions. Word has length 67 [2025-01-09 06:06:33,804 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:33,804 INFO L471 AbstractCegarLoop]: Abstraction has 2010 states and 2870 transitions. [2025-01-09 06:06:33,804 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:33,804 INFO L276 IsEmpty]: Start isEmpty. Operand 2010 states and 2870 transitions. [2025-01-09 06:06:33,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:33,805 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:33,805 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:33,805 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2025-01-09 06:06:33,805 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:33,806 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:33,806 INFO L85 PathProgramCache]: Analyzing trace with hash -258896132, now seen corresponding path program 1 times [2025-01-09 06:06:33,806 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:33,806 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [365207980] [2025-01-09 06:06:33,806 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:33,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:33,810 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:33,813 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:33,813 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:33,813 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:33,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:33,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:33,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [365207980] [2025-01-09 06:06:33,838 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [365207980] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:33,838 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:33,838 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-09 06:06:33,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1340259952] [2025-01-09 06:06:33,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:33,839 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-01-09 06:06:33,839 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:33,839 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-09 06:06:33,839 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-09 06:06:33,839 INFO L87 Difference]: Start difference. First operand 2010 states and 2870 transitions. Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:33,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:33,933 INFO L93 Difference]: Finished difference Result 4062 states and 5867 transitions. [2025-01-09 06:06:33,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-09 06:06:33,934 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2025-01-09 06:06:33,934 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:33,942 INFO L225 Difference]: With dead ends: 4062 [2025-01-09 06:06:33,942 INFO L226 Difference]: Without dead ends: 2064 [2025-01-09 06:06:33,946 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-09 06:06:33,946 INFO L435 NwaCegarLoop]: 191 mSDtfsCounter, 0 mSDsluCounter, 567 mSDsCounter, 0 mSdLazyCounter, 17 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 758 SdHoareTripleChecker+Invalid, 17 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 17 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:33,947 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 758 Invalid, 17 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 17 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:06:33,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2064 states. [2025-01-09 06:06:34,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2064 to 2064. [2025-01-09 06:06:34,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2064 states, 1730 states have (on average 1.407514450867052) internal successors, (2435), 1772 states have internal predecessors, (2435), 185 states have call successors, (185), 109 states have call predecessors, (185), 148 states have return successors, (304), 190 states have call predecessors, (304), 183 states have call successors, (304) [2025-01-09 06:06:34,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2064 states to 2064 states and 2924 transitions. [2025-01-09 06:06:34,042 INFO L78 Accepts]: Start accepts. Automaton has 2064 states and 2924 transitions. Word has length 67 [2025-01-09 06:06:34,042 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:34,042 INFO L471 AbstractCegarLoop]: Abstraction has 2064 states and 2924 transitions. [2025-01-09 06:06:34,042 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:34,042 INFO L276 IsEmpty]: Start isEmpty. Operand 2064 states and 2924 transitions. [2025-01-09 06:06:34,043 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:34,043 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:34,043 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:34,044 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2025-01-09 06:06:34,044 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:34,044 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:34,044 INFO L85 PathProgramCache]: Analyzing trace with hash -768369222, now seen corresponding path program 1 times [2025-01-09 06:06:34,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:34,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [739720031] [2025-01-09 06:06:34,044 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:34,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:34,048 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:34,050 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:34,051 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:34,051 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:34,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:34,133 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:34,133 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [739720031] [2025-01-09 06:06:34,133 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [739720031] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:34,133 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:34,133 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-01-09 06:06:34,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [939160701] [2025-01-09 06:06:34,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:34,133 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2025-01-09 06:06:34,133 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:34,134 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-01-09 06:06:34,134 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-01-09 06:06:34,134 INFO L87 Difference]: Start difference. First operand 2064 states and 2924 transitions. Second operand has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 6 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 3 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:34,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:34,431 INFO L93 Difference]: Finished difference Result 2650 states and 3762 transitions. [2025-01-09 06:06:34,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-01-09 06:06:34,431 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 6 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 3 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2025-01-09 06:06:34,431 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:34,438 INFO L225 Difference]: With dead ends: 2650 [2025-01-09 06:06:34,438 INFO L226 Difference]: Without dead ends: 1453 [2025-01-09 06:06:34,440 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2025-01-09 06:06:34,441 INFO L435 NwaCegarLoop]: 153 mSDtfsCounter, 295 mSDsluCounter, 490 mSDsCounter, 0 mSdLazyCounter, 347 mSolverCounterSat, 36 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 304 SdHoareTripleChecker+Valid, 643 SdHoareTripleChecker+Invalid, 383 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 36 IncrementalHoareTripleChecker+Valid, 347 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:34,441 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [304 Valid, 643 Invalid, 383 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [36 Valid, 347 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-01-09 06:06:34,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1453 states. [2025-01-09 06:06:34,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1453 to 1359. [2025-01-09 06:06:34,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1359 states, 1146 states have (on average 1.4013961605584642) internal successors, (1606), 1160 states have internal predecessors, (1606), 128 states have call successors, (128), 73 states have call predecessors, (128), 84 states have return successors, (155), 129 states have call predecessors, (155), 126 states have call successors, (155) [2025-01-09 06:06:34,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1359 states to 1359 states and 1889 transitions. [2025-01-09 06:06:34,528 INFO L78 Accepts]: Start accepts. Automaton has 1359 states and 1889 transitions. Word has length 67 [2025-01-09 06:06:34,528 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:34,528 INFO L471 AbstractCegarLoop]: Abstraction has 1359 states and 1889 transitions. [2025-01-09 06:06:34,529 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 6 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 3 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:34,529 INFO L276 IsEmpty]: Start isEmpty. Operand 1359 states and 1889 transitions. [2025-01-09 06:06:34,530 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:34,530 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:34,530 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:34,530 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2025-01-09 06:06:34,530 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:34,531 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:34,531 INFO L85 PathProgramCache]: Analyzing trace with hash 1721159740, now seen corresponding path program 1 times [2025-01-09 06:06:34,531 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:34,531 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1470171210] [2025-01-09 06:06:34,531 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:34,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:34,537 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:34,540 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:34,541 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:34,541 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:34,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:34,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:34,632 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1470171210] [2025-01-09 06:06:34,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1470171210] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:34,632 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:34,632 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-01-09 06:06:34,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1483978489] [2025-01-09 06:06:34,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:34,632 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2025-01-09 06:06:34,633 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:34,633 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-01-09 06:06:34,633 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-01-09 06:06:34,633 INFO L87 Difference]: Start difference. First operand 1359 states and 1889 transitions. Second operand has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 6 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 3 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:35,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:35,060 INFO L93 Difference]: Finished difference Result 3723 states and 5213 transitions. [2025-01-09 06:06:35,060 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-01-09 06:06:35,060 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 6 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 3 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2025-01-09 06:06:35,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:35,076 INFO L225 Difference]: With dead ends: 3723 [2025-01-09 06:06:35,076 INFO L226 Difference]: Without dead ends: 2377 [2025-01-09 06:06:35,081 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2025-01-09 06:06:35,081 INFO L435 NwaCegarLoop]: 154 mSDtfsCounter, 287 mSDsluCounter, 491 mSDsCounter, 0 mSdLazyCounter, 354 mSolverCounterSat, 37 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 296 SdHoareTripleChecker+Valid, 645 SdHoareTripleChecker+Invalid, 391 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 37 IncrementalHoareTripleChecker+Valid, 354 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:35,081 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [296 Valid, 645 Invalid, 391 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [37 Valid, 354 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-01-09 06:06:35,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2377 states. [2025-01-09 06:06:35,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2377 to 2255. [2025-01-09 06:06:35,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2255 states, 1896 states have (on average 1.3818565400843883) internal successors, (2620), 1928 states have internal predecessors, (2620), 208 states have call successors, (208), 121 states have call predecessors, (208), 150 states have return successors, (279), 213 states have call predecessors, (279), 206 states have call successors, (279) [2025-01-09 06:06:35,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2255 states to 2255 states and 3107 transitions. [2025-01-09 06:06:35,226 INFO L78 Accepts]: Start accepts. Automaton has 2255 states and 3107 transitions. Word has length 67 [2025-01-09 06:06:35,226 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:35,226 INFO L471 AbstractCegarLoop]: Abstraction has 2255 states and 3107 transitions. [2025-01-09 06:06:35,226 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 6 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 3 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:35,226 INFO L276 IsEmpty]: Start isEmpty. Operand 2255 states and 3107 transitions. [2025-01-09 06:06:35,227 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:35,227 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:35,227 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:35,228 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2025-01-09 06:06:35,228 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:35,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:35,228 INFO L85 PathProgramCache]: Analyzing trace with hash 1940014458, now seen corresponding path program 1 times [2025-01-09 06:06:35,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:35,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1136582044] [2025-01-09 06:06:35,229 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:35,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:35,233 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:35,236 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:35,236 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:35,236 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:35,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:35,281 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:35,281 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1136582044] [2025-01-09 06:06:35,282 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1136582044] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:35,282 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:35,282 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-09 06:06:35,282 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [443830013] [2025-01-09 06:06:35,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:35,282 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-01-09 06:06:35,282 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:35,283 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-09 06:06:35,283 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-09 06:06:35,283 INFO L87 Difference]: Start difference. First operand 2255 states and 3107 transitions. Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 3 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:35,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:35,578 INFO L93 Difference]: Finished difference Result 5551 states and 7616 transitions. [2025-01-09 06:06:35,579 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-01-09 06:06:35,579 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 3 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2025-01-09 06:06:35,579 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:35,590 INFO L225 Difference]: With dead ends: 5551 [2025-01-09 06:06:35,590 INFO L226 Difference]: Without dead ends: 3309 [2025-01-09 06:06:35,595 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2025-01-09 06:06:35,595 INFO L435 NwaCegarLoop]: 133 mSDtfsCounter, 271 mSDsluCounter, 201 mSDsCounter, 0 mSdLazyCounter, 260 mSolverCounterSat, 31 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 280 SdHoareTripleChecker+Valid, 334 SdHoareTripleChecker+Invalid, 291 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 31 IncrementalHoareTripleChecker+Valid, 260 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:35,595 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [280 Valid, 334 Invalid, 291 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [31 Valid, 260 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-01-09 06:06:35,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3309 states. [2025-01-09 06:06:35,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3309 to 2837. [2025-01-09 06:06:35,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2837 states, 2430 states have (on average 1.3325102880658437) internal successors, (3238), 2462 states have internal predecessors, (3238), 222 states have call successors, (222), 155 states have call predecessors, (222), 184 states have return successors, (327), 227 states have call predecessors, (327), 220 states have call successors, (327) [2025-01-09 06:06:35,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2837 states to 2837 states and 3787 transitions. [2025-01-09 06:06:35,731 INFO L78 Accepts]: Start accepts. Automaton has 2837 states and 3787 transitions. Word has length 67 [2025-01-09 06:06:35,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:35,731 INFO L471 AbstractCegarLoop]: Abstraction has 2837 states and 3787 transitions. [2025-01-09 06:06:35,731 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 3 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:35,731 INFO L276 IsEmpty]: Start isEmpty. Operand 2837 states and 3787 transitions. [2025-01-09 06:06:35,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:35,732 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:35,732 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:35,732 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2025-01-09 06:06:35,733 INFO L396 AbstractCegarLoop]: === Iteration 19 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:35,733 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:35,733 INFO L85 PathProgramCache]: Analyzing trace with hash -1932251012, now seen corresponding path program 1 times [2025-01-09 06:06:35,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:35,733 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014061081] [2025-01-09 06:06:35,734 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:35,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:35,739 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:35,742 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:35,742 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:35,742 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:35,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:35,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:35,822 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014061081] [2025-01-09 06:06:35,822 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2014061081] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:35,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:35,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-01-09 06:06:35,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1589085687] [2025-01-09 06:06:35,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:35,823 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2025-01-09 06:06:35,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:35,823 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-01-09 06:06:35,823 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-01-09 06:06:35,823 INFO L87 Difference]: Start difference. First operand 2837 states and 3787 transitions. Second operand has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 6 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 3 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:36,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:36,193 INFO L93 Difference]: Finished difference Result 4211 states and 5610 transitions. [2025-01-09 06:06:36,193 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-01-09 06:06:36,193 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 6 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 3 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2025-01-09 06:06:36,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:36,203 INFO L225 Difference]: With dead ends: 4211 [2025-01-09 06:06:36,203 INFO L226 Difference]: Without dead ends: 2473 [2025-01-09 06:06:36,206 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2025-01-09 06:06:36,206 INFO L435 NwaCegarLoop]: 144 mSDtfsCounter, 276 mSDsluCounter, 454 mSDsCounter, 0 mSdLazyCounter, 382 mSolverCounterSat, 37 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 284 SdHoareTripleChecker+Valid, 598 SdHoareTripleChecker+Invalid, 419 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 37 IncrementalHoareTripleChecker+Valid, 382 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:36,206 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [284 Valid, 598 Invalid, 419 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [37 Valid, 382 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-01-09 06:06:36,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2473 states. [2025-01-09 06:06:36,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2473 to 2291. [2025-01-09 06:06:36,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2291 states, 1970 states have (on average 1.33248730964467) internal successors, (2625), 1986 states have internal predecessors, (2625), 182 states have call successors, (182), 125 states have call predecessors, (182), 138 states have return successors, (237), 183 states have call predecessors, (237), 180 states have call successors, (237) [2025-01-09 06:06:36,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2291 states to 2291 states and 3044 transitions. [2025-01-09 06:06:36,315 INFO L78 Accepts]: Start accepts. Automaton has 2291 states and 3044 transitions. Word has length 67 [2025-01-09 06:06:36,315 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:36,315 INFO L471 AbstractCegarLoop]: Abstraction has 2291 states and 3044 transitions. [2025-01-09 06:06:36,316 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 9.333333333333334) internal successors, (56), 6 states have internal predecessors, (56), 2 states have call successors, (6), 3 states have call predecessors, (6), 3 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2025-01-09 06:06:36,316 INFO L276 IsEmpty]: Start isEmpty. Operand 2291 states and 3044 transitions. [2025-01-09 06:06:36,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-01-09 06:06:36,316 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:36,317 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:36,317 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2025-01-09 06:06:36,317 INFO L396 AbstractCegarLoop]: === Iteration 20 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:36,317 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:36,318 INFO L85 PathProgramCache]: Analyzing trace with hash 673772542, now seen corresponding path program 1 times [2025-01-09 06:06:36,318 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:36,318 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1526237370] [2025-01-09 06:06:36,318 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:36,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:36,323 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-09 06:06:36,328 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-09 06:06:36,328 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:36,328 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:36,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-09 06:06:36,343 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:36,343 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1526237370] [2025-01-09 06:06:36,343 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1526237370] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:36,343 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:36,343 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-09 06:06:36,343 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942999962] [2025-01-09 06:06:36,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:36,344 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-01-09 06:06:36,344 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:36,344 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-09 06:06:36,344 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-09 06:06:36,344 INFO L87 Difference]: Start difference. First operand 2291 states and 3044 transitions. Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-01-09 06:06:36,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:36,544 INFO L93 Difference]: Finished difference Result 5900 states and 7895 transitions. [2025-01-09 06:06:36,546 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-09 06:06:36,547 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 67 [2025-01-09 06:06:36,547 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:36,562 INFO L225 Difference]: With dead ends: 5900 [2025-01-09 06:06:36,562 INFO L226 Difference]: Without dead ends: 3622 [2025-01-09 06:06:36,571 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-09 06:06:36,571 INFO L435 NwaCegarLoop]: 190 mSDtfsCounter, 149 mSDsluCounter, 166 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 149 SdHoareTripleChecker+Valid, 356 SdHoareTripleChecker+Invalid, 10 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:36,572 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [149 Valid, 356 Invalid, 10 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:06:36,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3622 states. [2025-01-09 06:06:36,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3622 to 3594. [2025-01-09 06:06:36,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3594 states, 3072 states have (on average 1.3151041666666667) internal successors, (4040), 3103 states have internal predecessors, (4040), 298 states have call successors, (298), 205 states have call predecessors, (298), 223 states have return successors, (353), 289 states have call predecessors, (353), 296 states have call successors, (353) [2025-01-09 06:06:36,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3594 states to 3594 states and 4691 transitions. [2025-01-09 06:06:36,778 INFO L78 Accepts]: Start accepts. Automaton has 3594 states and 4691 transitions. Word has length 67 [2025-01-09 06:06:36,778 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:36,778 INFO L471 AbstractCegarLoop]: Abstraction has 3594 states and 4691 transitions. [2025-01-09 06:06:36,779 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 2 states have call successors, (6), 2 states have call predecessors, (6), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-01-09 06:06:36,779 INFO L276 IsEmpty]: Start isEmpty. Operand 3594 states and 4691 transitions. [2025-01-09 06:06:36,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2025-01-09 06:06:36,782 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:36,782 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:36,782 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2025-01-09 06:06:36,782 INFO L396 AbstractCegarLoop]: === Iteration 21 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:36,783 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:36,783 INFO L85 PathProgramCache]: Analyzing trace with hash -1087795675, now seen corresponding path program 1 times [2025-01-09 06:06:36,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:36,783 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779288388] [2025-01-09 06:06:36,783 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:36,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:36,789 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 108 statements into 1 equivalence classes. [2025-01-09 06:06:36,794 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 108 of 108 statements. [2025-01-09 06:06:36,794 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:36,794 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:36,849 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2025-01-09 06:06:36,850 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:36,850 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1779288388] [2025-01-09 06:06:36,850 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1779288388] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:36,850 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:36,850 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-09 06:06:36,850 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [991438369] [2025-01-09 06:06:36,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:36,851 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-01-09 06:06:36,851 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:36,851 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-09 06:06:36,851 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-09 06:06:36,851 INFO L87 Difference]: Start difference. First operand 3594 states and 4691 transitions. Second operand has 4 states, 4 states have (on average 17.0) internal successors, (68), 4 states have internal predecessors, (68), 4 states have call successors, (9), 3 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) [2025-01-09 06:06:37,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:37,214 INFO L93 Difference]: Finished difference Result 9763 states and 12838 transitions. [2025-01-09 06:06:37,214 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-09 06:06:37,214 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 17.0) internal successors, (68), 4 states have internal predecessors, (68), 4 states have call successors, (9), 3 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) Word has length 108 [2025-01-09 06:06:37,215 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:37,241 INFO L225 Difference]: With dead ends: 9763 [2025-01-09 06:06:37,242 INFO L226 Difference]: Without dead ends: 6184 [2025-01-09 06:06:37,248 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-01-09 06:06:37,249 INFO L435 NwaCegarLoop]: 149 mSDtfsCounter, 250 mSDsluCounter, 216 mSDsCounter, 0 mSdLazyCounter, 130 mSolverCounterSat, 40 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 256 SdHoareTripleChecker+Valid, 365 SdHoareTripleChecker+Invalid, 170 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 40 IncrementalHoareTripleChecker+Valid, 130 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:37,249 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [256 Valid, 365 Invalid, 170 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [40 Valid, 130 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-01-09 06:06:37,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6184 states. [2025-01-09 06:06:37,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6184 to 6156. [2025-01-09 06:06:37,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6156 states, 5268 states have (on average 1.2997342444950646) internal successors, (6847), 5349 states have internal predecessors, (6847), 468 states have call successors, (468), 329 states have call predecessors, (468), 419 states have return successors, (701), 481 states have call predecessors, (701), 466 states have call successors, (701) [2025-01-09 06:06:37,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6156 states to 6156 states and 8016 transitions. [2025-01-09 06:06:37,565 INFO L78 Accepts]: Start accepts. Automaton has 6156 states and 8016 transitions. Word has length 108 [2025-01-09 06:06:37,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:37,566 INFO L471 AbstractCegarLoop]: Abstraction has 6156 states and 8016 transitions. [2025-01-09 06:06:37,567 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 17.0) internal successors, (68), 4 states have internal predecessors, (68), 4 states have call successors, (9), 3 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) [2025-01-09 06:06:37,567 INFO L276 IsEmpty]: Start isEmpty. Operand 6156 states and 8016 transitions. [2025-01-09 06:06:37,571 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2025-01-09 06:06:37,571 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:37,571 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:37,571 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2025-01-09 06:06:37,571 INFO L396 AbstractCegarLoop]: === Iteration 22 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:37,572 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:37,572 INFO L85 PathProgramCache]: Analyzing trace with hash -710179770, now seen corresponding path program 1 times [2025-01-09 06:06:37,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:37,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132444868] [2025-01-09 06:06:37,572 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:37,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:37,577 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 110 statements into 1 equivalence classes. [2025-01-09 06:06:37,580 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 110 of 110 statements. [2025-01-09 06:06:37,581 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:37,581 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:37,634 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2025-01-09 06:06:37,634 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:37,634 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132444868] [2025-01-09 06:06:37,634 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1132444868] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:37,634 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:37,634 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-09 06:06:37,634 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1779443178] [2025-01-09 06:06:37,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:37,635 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-01-09 06:06:37,635 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:37,635 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-09 06:06:37,635 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-09 06:06:37,635 INFO L87 Difference]: Start difference. First operand 6156 states and 8016 transitions. Second operand has 4 states, 4 states have (on average 17.5) internal successors, (70), 4 states have internal predecessors, (70), 4 states have call successors, (9), 3 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) [2025-01-09 06:06:38,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:38,444 INFO L93 Difference]: Finished difference Result 17082 states and 22374 transitions. [2025-01-09 06:06:38,444 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-09 06:06:38,445 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 17.5) internal successors, (70), 4 states have internal predecessors, (70), 4 states have call successors, (9), 3 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) Word has length 110 [2025-01-09 06:06:38,445 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:38,482 INFO L225 Difference]: With dead ends: 17082 [2025-01-09 06:06:38,483 INFO L226 Difference]: Without dead ends: 10941 [2025-01-09 06:06:38,499 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-01-09 06:06:38,501 INFO L435 NwaCegarLoop]: 209 mSDtfsCounter, 226 mSDsluCounter, 253 mSDsCounter, 0 mSdLazyCounter, 150 mSolverCounterSat, 35 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 232 SdHoareTripleChecker+Valid, 462 SdHoareTripleChecker+Invalid, 185 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 35 IncrementalHoareTripleChecker+Valid, 150 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:38,501 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [232 Valid, 462 Invalid, 185 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [35 Valid, 150 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-01-09 06:06:38,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10941 states. [2025-01-09 06:06:39,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10941 to 10621. [2025-01-09 06:06:39,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10621 states, 8945 states have (on average 1.296702068194522) internal successors, (11599), 9148 states have internal predecessors, (11599), 849 states have call successors, (849), 573 states have call predecessors, (849), 826 states have return successors, (1511), 907 states have call predecessors, (1511), 847 states have call successors, (1511) [2025-01-09 06:06:39,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10621 states to 10621 states and 13959 transitions. [2025-01-09 06:06:39,117 INFO L78 Accepts]: Start accepts. Automaton has 10621 states and 13959 transitions. Word has length 110 [2025-01-09 06:06:39,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:39,117 INFO L471 AbstractCegarLoop]: Abstraction has 10621 states and 13959 transitions. [2025-01-09 06:06:39,118 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 17.5) internal successors, (70), 4 states have internal predecessors, (70), 4 states have call successors, (9), 3 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) [2025-01-09 06:06:39,118 INFO L276 IsEmpty]: Start isEmpty. Operand 10621 states and 13959 transitions. [2025-01-09 06:06:39,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2025-01-09 06:06:39,125 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:39,125 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:39,125 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2025-01-09 06:06:39,125 INFO L396 AbstractCegarLoop]: === Iteration 23 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:39,126 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:39,126 INFO L85 PathProgramCache]: Analyzing trace with hash 1187316996, now seen corresponding path program 1 times [2025-01-09 06:06:39,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:39,126 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1027698571] [2025-01-09 06:06:39,126 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:39,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:39,133 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 110 statements into 1 equivalence classes. [2025-01-09 06:06:39,138 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 110 of 110 statements. [2025-01-09 06:06:39,138 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:39,138 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:39,155 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2025-01-09 06:06:39,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:39,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1027698571] [2025-01-09 06:06:39,155 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1027698571] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:39,155 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:39,155 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-09 06:06:39,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [250809366] [2025-01-09 06:06:39,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:39,156 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-01-09 06:06:39,156 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:39,157 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-09 06:06:39,157 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-09 06:06:39,157 INFO L87 Difference]: Start difference. First operand 10621 states and 13959 transitions. Second operand has 3 states, 3 states have (on average 22.0) internal successors, (66), 3 states have internal predecessors, (66), 3 states have call successors, (8), 2 states have call predecessors, (8), 1 states have return successors, (7), 3 states have call predecessors, (7), 3 states have call successors, (7) [2025-01-09 06:06:39,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:39,645 INFO L93 Difference]: Finished difference Result 21223 states and 27882 transitions. [2025-01-09 06:06:39,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-09 06:06:39,646 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 22.0) internal successors, (66), 3 states have internal predecessors, (66), 3 states have call successors, (8), 2 states have call predecessors, (8), 1 states have return successors, (7), 3 states have call predecessors, (7), 3 states have call successors, (7) Word has length 110 [2025-01-09 06:06:39,646 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:39,683 INFO L225 Difference]: With dead ends: 21223 [2025-01-09 06:06:39,683 INFO L226 Difference]: Without dead ends: 10615 [2025-01-09 06:06:39,703 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-09 06:06:39,704 INFO L435 NwaCegarLoop]: 190 mSDtfsCounter, 183 mSDsluCounter, 1 mSDsCounter, 0 mSdLazyCounter, 2 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 183 SdHoareTripleChecker+Valid, 191 SdHoareTripleChecker+Invalid, 2 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 2 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:39,704 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [183 Valid, 191 Invalid, 2 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 2 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:06:39,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10615 states. [2025-01-09 06:06:40,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10615 to 10615. [2025-01-09 06:06:40,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10615 states, 8944 states have (on average 1.29662343470483) internal successors, (11597), 9146 states have internal predecessors, (11597), 844 states have call successors, (844), 573 states have call predecessors, (844), 826 states have return successors, (1501), 899 states have call predecessors, (1501), 842 states have call successors, (1501) [2025-01-09 06:06:40,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10615 states to 10615 states and 13942 transitions. [2025-01-09 06:06:40,520 INFO L78 Accepts]: Start accepts. Automaton has 10615 states and 13942 transitions. Word has length 110 [2025-01-09 06:06:40,520 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:40,520 INFO L471 AbstractCegarLoop]: Abstraction has 10615 states and 13942 transitions. [2025-01-09 06:06:40,520 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 22.0) internal successors, (66), 3 states have internal predecessors, (66), 3 states have call successors, (8), 2 states have call predecessors, (8), 1 states have return successors, (7), 3 states have call predecessors, (7), 3 states have call successors, (7) [2025-01-09 06:06:40,520 INFO L276 IsEmpty]: Start isEmpty. Operand 10615 states and 13942 transitions. [2025-01-09 06:06:40,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2025-01-09 06:06:40,527 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:40,527 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:40,527 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2025-01-09 06:06:40,527 INFO L396 AbstractCegarLoop]: === Iteration 24 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:40,528 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:40,528 INFO L85 PathProgramCache]: Analyzing trace with hash 1059307365, now seen corresponding path program 1 times [2025-01-09 06:06:40,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:40,528 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1569154020] [2025-01-09 06:06:40,528 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:40,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:40,537 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 112 statements into 1 equivalence classes. [2025-01-09 06:06:40,542 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 112 of 112 statements. [2025-01-09 06:06:40,542 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:40,542 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:40,609 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2025-01-09 06:06:40,609 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:40,609 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1569154020] [2025-01-09 06:06:40,609 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1569154020] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:40,609 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:40,609 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-01-09 06:06:40,609 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [921044030] [2025-01-09 06:06:40,610 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:40,610 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-01-09 06:06:40,610 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:40,610 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-01-09 06:06:40,610 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-01-09 06:06:40,610 INFO L87 Difference]: Start difference. First operand 10615 states and 13942 transitions. Second operand has 7 states, 7 states have (on average 10.714285714285714) internal successors, (75), 6 states have internal predecessors, (75), 4 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (8), 3 states have call predecessors, (8), 3 states have call successors, (8) [2025-01-09 06:06:42,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:42,188 INFO L93 Difference]: Finished difference Result 31099 states and 41164 transitions. [2025-01-09 06:06:42,188 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2025-01-09 06:06:42,188 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 10.714285714285714) internal successors, (75), 6 states have internal predecessors, (75), 4 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (8), 3 states have call predecessors, (8), 3 states have call successors, (8) Word has length 112 [2025-01-09 06:06:42,188 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:42,253 INFO L225 Difference]: With dead ends: 31099 [2025-01-09 06:06:42,253 INFO L226 Difference]: Without dead ends: 15597 [2025-01-09 06:06:42,289 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 11 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=71, Invalid=201, Unknown=0, NotChecked=0, Total=272 [2025-01-09 06:06:42,290 INFO L435 NwaCegarLoop]: 220 mSDtfsCounter, 1195 mSDsluCounter, 766 mSDsCounter, 0 mSdLazyCounter, 581 mSolverCounterSat, 251 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1207 SdHoareTripleChecker+Valid, 986 SdHoareTripleChecker+Invalid, 832 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 251 IncrementalHoareTripleChecker+Valid, 581 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:42,290 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1207 Valid, 986 Invalid, 832 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [251 Valid, 581 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2025-01-09 06:06:42,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15597 states. [2025-01-09 06:06:43,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15597 to 15407. [2025-01-09 06:06:43,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15407 states, 13084 states have (on average 1.2707123203913175) internal successors, (16626), 13376 states have internal predecessors, (16626), 1130 states have call successors, (1130), 813 states have call predecessors, (1130), 1192 states have return successors, (1925), 1221 states have call predecessors, (1925), 1128 states have call successors, (1925) [2025-01-09 06:06:43,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15407 states to 15407 states and 19681 transitions. [2025-01-09 06:06:43,121 INFO L78 Accepts]: Start accepts. Automaton has 15407 states and 19681 transitions. Word has length 112 [2025-01-09 06:06:43,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:43,121 INFO L471 AbstractCegarLoop]: Abstraction has 15407 states and 19681 transitions. [2025-01-09 06:06:43,122 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 10.714285714285714) internal successors, (75), 6 states have internal predecessors, (75), 4 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (8), 3 states have call predecessors, (8), 3 states have call successors, (8) [2025-01-09 06:06:43,122 INFO L276 IsEmpty]: Start isEmpty. Operand 15407 states and 19681 transitions. [2025-01-09 06:06:43,133 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2025-01-09 06:06:43,133 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:43,133 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:43,134 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23 [2025-01-09 06:06:43,134 INFO L396 AbstractCegarLoop]: === Iteration 25 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:43,134 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:43,134 INFO L85 PathProgramCache]: Analyzing trace with hash -1038732691, now seen corresponding path program 1 times [2025-01-09 06:06:43,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:43,134 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2110538400] [2025-01-09 06:06:43,134 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:43,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:43,142 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 142 statements into 1 equivalence classes. [2025-01-09 06:06:43,146 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 142 of 142 statements. [2025-01-09 06:06:43,146 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:43,147 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:43,165 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2025-01-09 06:06:43,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:43,166 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2110538400] [2025-01-09 06:06:43,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2110538400] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:43,166 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:43,166 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-09 06:06:43,166 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [7906707] [2025-01-09 06:06:43,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:43,166 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-01-09 06:06:43,167 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:43,167 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-09 06:06:43,167 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-09 06:06:43,167 INFO L87 Difference]: Start difference. First operand 15407 states and 19681 transitions. Second operand has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 3 states have call successors, (10), 2 states have call predecessors, (10), 1 states have return successors, (9), 3 states have call predecessors, (9), 3 states have call successors, (9) [2025-01-09 06:06:43,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:43,988 INFO L93 Difference]: Finished difference Result 35138 states and 44845 transitions. [2025-01-09 06:06:43,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-09 06:06:43,988 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 3 states have call successors, (10), 2 states have call predecessors, (10), 1 states have return successors, (9), 3 states have call predecessors, (9), 3 states have call successors, (9) Word has length 142 [2025-01-09 06:06:43,988 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:44,057 INFO L225 Difference]: With dead ends: 35138 [2025-01-09 06:06:44,058 INFO L226 Difference]: Without dead ends: 19744 [2025-01-09 06:06:44,087 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-09 06:06:44,087 INFO L435 NwaCegarLoop]: 190 mSDtfsCounter, 125 mSDsluCounter, 166 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 125 SdHoareTripleChecker+Valid, 356 SdHoareTripleChecker+Invalid, 10 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:44,088 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [125 Valid, 356 Invalid, 10 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:06:44,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19744 states. [2025-01-09 06:06:45,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19744 to 19678. [2025-01-09 06:06:45,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19678 states, 16692 states have (on average 1.2565899832254972) internal successors, (20975), 17037 states have internal predecessors, (20975), 1482 states have call successors, (1482), 1065 states have call predecessors, (1482), 1503 states have return successors, (2391), 1579 states have call predecessors, (2391), 1480 states have call successors, (2391) [2025-01-09 06:06:45,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19678 states to 19678 states and 24848 transitions. [2025-01-09 06:06:45,759 INFO L78 Accepts]: Start accepts. Automaton has 19678 states and 24848 transitions. Word has length 142 [2025-01-09 06:06:45,760 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:45,760 INFO L471 AbstractCegarLoop]: Abstraction has 19678 states and 24848 transitions. [2025-01-09 06:06:45,760 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 3 states have call successors, (10), 2 states have call predecessors, (10), 1 states have return successors, (9), 3 states have call predecessors, (9), 3 states have call successors, (9) [2025-01-09 06:06:45,760 INFO L276 IsEmpty]: Start isEmpty. Operand 19678 states and 24848 transitions. [2025-01-09 06:06:45,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2025-01-09 06:06:45,781 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:45,781 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:45,781 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24 [2025-01-09 06:06:45,782 INFO L396 AbstractCegarLoop]: === Iteration 26 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:45,782 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:45,782 INFO L85 PathProgramCache]: Analyzing trace with hash 1939951344, now seen corresponding path program 1 times [2025-01-09 06:06:45,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:45,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1262715939] [2025-01-09 06:06:45,782 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:45,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:45,790 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 161 statements into 1 equivalence classes. [2025-01-09 06:06:45,795 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 161 of 161 statements. [2025-01-09 06:06:45,796 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:45,796 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:45,868 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2025-01-09 06:06:45,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:45,869 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1262715939] [2025-01-09 06:06:45,869 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1262715939] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:45,869 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:06:45,869 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-01-09 06:06:45,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1561166216] [2025-01-09 06:06:45,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:45,870 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2025-01-09 06:06:45,870 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:45,871 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-01-09 06:06:45,871 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-01-09 06:06:45,871 INFO L87 Difference]: Start difference. First operand 19678 states and 24848 transitions. Second operand has 6 states, 6 states have (on average 15.833333333333334) internal successors, (95), 5 states have internal predecessors, (95), 4 states have call successors, (11), 3 states have call predecessors, (11), 2 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) [2025-01-09 06:06:47,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:47,476 INFO L93 Difference]: Finished difference Result 35714 states and 45286 transitions. [2025-01-09 06:06:47,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-01-09 06:06:47,476 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 15.833333333333334) internal successors, (95), 5 states have internal predecessors, (95), 4 states have call successors, (11), 3 states have call predecessors, (11), 2 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) Word has length 161 [2025-01-09 06:06:47,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:47,549 INFO L225 Difference]: With dead ends: 35714 [2025-01-09 06:06:47,549 INFO L226 Difference]: Without dead ends: 20322 [2025-01-09 06:06:47,573 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=59, Invalid=123, Unknown=0, NotChecked=0, Total=182 [2025-01-09 06:06:47,573 INFO L435 NwaCegarLoop]: 209 mSDtfsCounter, 688 mSDsluCounter, 677 mSDsCounter, 0 mSdLazyCounter, 473 mSolverCounterSat, 103 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 702 SdHoareTripleChecker+Valid, 886 SdHoareTripleChecker+Invalid, 576 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 103 IncrementalHoareTripleChecker+Valid, 473 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:47,574 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [702 Valid, 886 Invalid, 576 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [103 Valid, 473 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2025-01-09 06:06:47,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20322 states. [2025-01-09 06:06:48,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20322 to 19678. [2025-01-09 06:06:48,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19678 states, 16692 states have (on average 1.252755811167026) internal successors, (20911), 17037 states have internal predecessors, (20911), 1482 states have call successors, (1482), 1065 states have call predecessors, (1482), 1503 states have return successors, (2373), 1579 states have call predecessors, (2373), 1480 states have call successors, (2373) [2025-01-09 06:06:48,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19678 states to 19678 states and 24766 transitions. [2025-01-09 06:06:48,480 INFO L78 Accepts]: Start accepts. Automaton has 19678 states and 24766 transitions. Word has length 161 [2025-01-09 06:06:48,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:48,481 INFO L471 AbstractCegarLoop]: Abstraction has 19678 states and 24766 transitions. [2025-01-09 06:06:48,481 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 15.833333333333334) internal successors, (95), 5 states have internal predecessors, (95), 4 states have call successors, (11), 3 states have call predecessors, (11), 2 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) [2025-01-09 06:06:48,481 INFO L276 IsEmpty]: Start isEmpty. Operand 19678 states and 24766 transitions. [2025-01-09 06:06:48,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2025-01-09 06:06:48,498 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:48,498 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:48,498 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable25 [2025-01-09 06:06:48,498 INFO L396 AbstractCegarLoop]: === Iteration 27 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:48,498 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:48,499 INFO L85 PathProgramCache]: Analyzing trace with hash 1177589254, now seen corresponding path program 1 times [2025-01-09 06:06:48,499 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:48,499 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882040450] [2025-01-09 06:06:48,499 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:48,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:48,507 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 162 statements into 1 equivalence classes. [2025-01-09 06:06:48,565 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 162 of 162 statements. [2025-01-09 06:06:48,565 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:48,565 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:48,657 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 26 proven. 7 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2025-01-09 06:06:48,657 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:48,657 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882040450] [2025-01-09 06:06:48,657 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882040450] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-09 06:06:48,657 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [295390531] [2025-01-09 06:06:48,658 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:48,658 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-09 06:06:48,658 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-09 06:06:48,660 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-09 06:06:48,662 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2025-01-09 06:06:48,714 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 162 statements into 1 equivalence classes. [2025-01-09 06:06:48,755 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 162 of 162 statements. [2025-01-09 06:06:48,756 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:48,756 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:48,759 INFO L256 TraceCheckSpWp]: Trace formula consists of 539 conjuncts, 3 conjuncts are in the unsatisfiable core [2025-01-09 06:06:48,765 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-09 06:06:48,866 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2025-01-09 06:06:48,866 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-01-09 06:06:48,866 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [295390531] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:48,866 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-01-09 06:06:48,866 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [7] total 7 [2025-01-09 06:06:48,866 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [927499773] [2025-01-09 06:06:48,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:48,867 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-01-09 06:06:48,867 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:48,867 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-09 06:06:48,867 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-01-09 06:06:48,867 INFO L87 Difference]: Start difference. First operand 19678 states and 24766 transitions. Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 3 states have call successors, (11), 3 states have call predecessors, (11), 3 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2025-01-09 06:06:49,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:49,618 INFO L93 Difference]: Finished difference Result 36871 states and 47562 transitions. [2025-01-09 06:06:49,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-09 06:06:49,619 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 3 states have call successors, (11), 3 states have call predecessors, (11), 3 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 162 [2025-01-09 06:06:49,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:49,691 INFO L225 Difference]: With dead ends: 36871 [2025-01-09 06:06:49,691 INFO L226 Difference]: Without dead ends: 18923 [2025-01-09 06:06:49,729 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 170 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-01-09 06:06:49,730 INFO L435 NwaCegarLoop]: 190 mSDtfsCounter, 141 mSDsluCounter, 46 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 141 SdHoareTripleChecker+Valid, 236 SdHoareTripleChecker+Invalid, 14 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:49,730 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [141 Valid, 236 Invalid, 14 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:06:49,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18923 states. [2025-01-09 06:06:50,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18923 to 18823. [2025-01-09 06:06:50,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18823 states, 16066 states have (on average 1.2350304991908378) internal successors, (19842), 16364 states have internal predecessors, (19842), 1380 states have call successors, (1380), 1035 states have call predecessors, (1380), 1376 states have return successors, (2325), 1427 states have call predecessors, (2325), 1378 states have call successors, (2325) [2025-01-09 06:06:50,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18823 states to 18823 states and 23547 transitions. [2025-01-09 06:06:50,696 INFO L78 Accepts]: Start accepts. Automaton has 18823 states and 23547 transitions. Word has length 162 [2025-01-09 06:06:50,697 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:50,697 INFO L471 AbstractCegarLoop]: Abstraction has 18823 states and 23547 transitions. [2025-01-09 06:06:50,697 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 3 states have call successors, (11), 3 states have call predecessors, (11), 3 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2025-01-09 06:06:50,697 INFO L276 IsEmpty]: Start isEmpty. Operand 18823 states and 23547 transitions. [2025-01-09 06:06:50,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2025-01-09 06:06:50,717 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:50,717 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:50,725 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2025-01-09 06:06:50,922 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable26 [2025-01-09 06:06:50,922 INFO L396 AbstractCegarLoop]: === Iteration 28 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:50,923 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:50,923 INFO L85 PathProgramCache]: Analyzing trace with hash 179203538, now seen corresponding path program 1 times [2025-01-09 06:06:50,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:50,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280879549] [2025-01-09 06:06:50,923 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:50,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:50,935 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 194 statements into 1 equivalence classes. [2025-01-09 06:06:50,942 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 194 of 194 statements. [2025-01-09 06:06:50,942 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:50,942 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:51,025 INFO L134 CoverageAnalysis]: Checked inductivity of 160 backedges. 26 proven. 3 refuted. 0 times theorem prover too weak. 131 trivial. 0 not checked. [2025-01-09 06:06:51,025 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:51,025 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280879549] [2025-01-09 06:06:51,025 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [280879549] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-09 06:06:51,025 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1846966938] [2025-01-09 06:06:51,026 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:51,026 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-09 06:06:51,026 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-09 06:06:51,028 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-09 06:06:51,030 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2025-01-09 06:06:51,083 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 194 statements into 1 equivalence classes. [2025-01-09 06:06:51,138 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 194 of 194 statements. [2025-01-09 06:06:51,138 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:51,138 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:51,140 INFO L256 TraceCheckSpWp]: Trace formula consists of 631 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-01-09 06:06:51,148 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-09 06:06:51,203 INFO L134 CoverageAnalysis]: Checked inductivity of 160 backedges. 125 proven. 0 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2025-01-09 06:06:51,203 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-01-09 06:06:51,203 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1846966938] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:51,203 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-01-09 06:06:51,203 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [7] total 8 [2025-01-09 06:06:51,204 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1461085476] [2025-01-09 06:06:51,204 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:51,204 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-01-09 06:06:51,204 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:51,204 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-09 06:06:51,209 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2025-01-09 06:06:51,209 INFO L87 Difference]: Start difference. First operand 18823 states and 23547 transitions. Second operand has 3 states, 3 states have (on average 46.0) internal successors, (138), 3 states have internal predecessors, (138), 3 states have call successors, (14), 3 states have call predecessors, (14), 3 states have return successors, (13), 3 states have call predecessors, (13), 3 states have call successors, (13) [2025-01-09 06:06:51,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:51,865 INFO L93 Difference]: Finished difference Result 33723 states and 43236 transitions. [2025-01-09 06:06:51,865 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-09 06:06:51,865 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 46.0) internal successors, (138), 3 states have internal predecessors, (138), 3 states have call successors, (14), 3 states have call predecessors, (14), 3 states have return successors, (13), 3 states have call predecessors, (13), 3 states have call successors, (13) Word has length 194 [2025-01-09 06:06:51,865 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:51,928 INFO L225 Difference]: With dead ends: 33723 [2025-01-09 06:06:51,928 INFO L226 Difference]: Without dead ends: 15227 [2025-01-09 06:06:51,964 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 201 GetRequests, 195 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2025-01-09 06:06:51,964 INFO L435 NwaCegarLoop]: 189 mSDtfsCounter, 142 mSDsluCounter, 30 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 142 SdHoareTripleChecker+Valid, 219 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:51,964 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [142 Valid, 219 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:06:51,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15227 states. [2025-01-09 06:06:52,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15227 to 15207. [2025-01-09 06:06:52,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15207 states, 12970 states have (on average 1.197841171935235) internal successors, (15536), 13114 states have internal predecessors, (15536), 1168 states have call successors, (1168), 897 states have call predecessors, (1168), 1068 states have return successors, (1679), 1197 states have call predecessors, (1679), 1166 states have call successors, (1679) [2025-01-09 06:06:52,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15207 states to 15207 states and 18383 transitions. [2025-01-09 06:06:52,879 INFO L78 Accepts]: Start accepts. Automaton has 15207 states and 18383 transitions. Word has length 194 [2025-01-09 06:06:52,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:52,880 INFO L471 AbstractCegarLoop]: Abstraction has 15207 states and 18383 transitions. [2025-01-09 06:06:52,880 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 46.0) internal successors, (138), 3 states have internal predecessors, (138), 3 states have call successors, (14), 3 states have call predecessors, (14), 3 states have return successors, (13), 3 states have call predecessors, (13), 3 states have call successors, (13) [2025-01-09 06:06:52,880 INFO L276 IsEmpty]: Start isEmpty. Operand 15207 states and 18383 transitions. [2025-01-09 06:06:52,891 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2025-01-09 06:06:52,891 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:52,892 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:52,898 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2025-01-09 06:06:53,092 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable27 [2025-01-09 06:06:53,094 INFO L396 AbstractCegarLoop]: === Iteration 29 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:53,094 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:53,094 INFO L85 PathProgramCache]: Analyzing trace with hash 293283186, now seen corresponding path program 1 times [2025-01-09 06:06:53,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:53,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [151543118] [2025-01-09 06:06:53,094 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:53,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:53,104 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 194 statements into 1 equivalence classes. [2025-01-09 06:06:53,110 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 194 of 194 statements. [2025-01-09 06:06:53,110 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:53,110 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:53,174 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 26 proven. 3 refuted. 0 times theorem prover too weak. 135 trivial. 0 not checked. [2025-01-09 06:06:53,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:53,175 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [151543118] [2025-01-09 06:06:53,175 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [151543118] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-09 06:06:53,175 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [889013523] [2025-01-09 06:06:53,175 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:53,175 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-09 06:06:53,175 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-09 06:06:53,178 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-09 06:06:53,180 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2025-01-09 06:06:53,234 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 194 statements into 1 equivalence classes. [2025-01-09 06:06:53,281 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 194 of 194 statements. [2025-01-09 06:06:53,281 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:53,281 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:53,284 INFO L256 TraceCheckSpWp]: Trace formula consists of 623 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-01-09 06:06:53,288 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-09 06:06:53,320 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 117 proven. 0 refuted. 0 times theorem prover too weak. 47 trivial. 0 not checked. [2025-01-09 06:06:53,320 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-01-09 06:06:53,320 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [889013523] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:53,320 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-01-09 06:06:53,320 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [7] total 8 [2025-01-09 06:06:53,320 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [961130770] [2025-01-09 06:06:53,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:53,323 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-01-09 06:06:53,323 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:53,323 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-09 06:06:53,323 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2025-01-09 06:06:53,324 INFO L87 Difference]: Start difference. First operand 15207 states and 18383 transitions. Second operand has 3 states, 3 states have (on average 43.333333333333336) internal successors, (130), 3 states have internal predecessors, (130), 3 states have call successors, (13), 3 states have call predecessors, (13), 2 states have return successors, (12), 2 states have call predecessors, (12), 3 states have call successors, (12) [2025-01-09 06:06:54,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:54,092 INFO L93 Difference]: Finished difference Result 24540 states and 29684 transitions. [2025-01-09 06:06:54,092 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-09 06:06:54,092 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 43.333333333333336) internal successors, (130), 3 states have internal predecessors, (130), 3 states have call successors, (13), 3 states have call predecessors, (13), 2 states have return successors, (12), 2 states have call predecessors, (12), 3 states have call successors, (12) Word has length 194 [2025-01-09 06:06:54,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:54,145 INFO L225 Difference]: With dead ends: 24540 [2025-01-09 06:06:54,145 INFO L226 Difference]: Without dead ends: 12586 [2025-01-09 06:06:54,165 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 201 GetRequests, 195 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2025-01-09 06:06:54,165 INFO L435 NwaCegarLoop]: 273 mSDtfsCounter, 144 mSDsluCounter, 176 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 144 SdHoareTripleChecker+Valid, 449 SdHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:54,166 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [144 Valid, 449 Invalid, 9 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:06:54,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12586 states. [2025-01-09 06:06:55,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12586 to 12462. [2025-01-09 06:06:55,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12462 states, 10705 states have (on average 1.2000934142923867) internal successors, (12847), 10824 states have internal predecessors, (12847), 901 states have call successors, (901), 713 states have call predecessors, (901), 855 states have return successors, (1240), 926 states have call predecessors, (1240), 899 states have call successors, (1240) [2025-01-09 06:06:55,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12462 states to 12462 states and 14988 transitions. [2025-01-09 06:06:55,231 INFO L78 Accepts]: Start accepts. Automaton has 12462 states and 14988 transitions. Word has length 194 [2025-01-09 06:06:55,231 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:55,231 INFO L471 AbstractCegarLoop]: Abstraction has 12462 states and 14988 transitions. [2025-01-09 06:06:55,232 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 43.333333333333336) internal successors, (130), 3 states have internal predecessors, (130), 3 states have call successors, (13), 3 states have call predecessors, (13), 2 states have return successors, (12), 2 states have call predecessors, (12), 3 states have call successors, (12) [2025-01-09 06:06:55,232 INFO L276 IsEmpty]: Start isEmpty. Operand 12462 states and 14988 transitions. [2025-01-09 06:06:55,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2025-01-09 06:06:55,238 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:55,238 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:55,246 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2025-01-09 06:06:55,439 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable28,4 /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-09 06:06:55,440 INFO L396 AbstractCegarLoop]: === Iteration 30 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:55,440 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:55,440 INFO L85 PathProgramCache]: Analyzing trace with hash 1766104708, now seen corresponding path program 1 times [2025-01-09 06:06:55,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:55,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706513419] [2025-01-09 06:06:55,440 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:55,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:55,452 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 195 statements into 1 equivalence classes. [2025-01-09 06:06:55,457 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 195 of 195 statements. [2025-01-09 06:06:55,457 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:55,457 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:55,491 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 35 proven. 15 refuted. 0 times theorem prover too weak. 114 trivial. 0 not checked. [2025-01-09 06:06:55,491 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:55,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706513419] [2025-01-09 06:06:55,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1706513419] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-09 06:06:55,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1908083315] [2025-01-09 06:06:55,491 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:55,491 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-09 06:06:55,491 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-09 06:06:55,493 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-09 06:06:55,498 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2025-01-09 06:06:55,553 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 195 statements into 1 equivalence classes. [2025-01-09 06:06:55,606 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 195 of 195 statements. [2025-01-09 06:06:55,606 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:55,606 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:55,609 INFO L256 TraceCheckSpWp]: Trace formula consists of 632 conjuncts, 3 conjuncts are in the unsatisfiable core [2025-01-09 06:06:55,612 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-09 06:06:55,650 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 128 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2025-01-09 06:06:55,651 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-01-09 06:06:55,651 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1908083315] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:55,651 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-01-09 06:06:55,651 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 4 [2025-01-09 06:06:55,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2004734744] [2025-01-09 06:06:55,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:55,651 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-01-09 06:06:55,652 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:55,652 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-09 06:06:55,652 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-09 06:06:55,652 INFO L87 Difference]: Start difference. First operand 12462 states and 14988 transitions. Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 3 states have call successors, (13), 3 states have call predecessors, (13), 3 states have return successors, (12), 3 states have call predecessors, (12), 3 states have call successors, (12) [2025-01-09 06:06:56,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:56,183 INFO L93 Difference]: Finished difference Result 22079 states and 27074 transitions. [2025-01-09 06:06:56,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-09 06:06:56,184 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 3 states have call successors, (13), 3 states have call predecessors, (13), 3 states have return successors, (12), 3 states have call predecessors, (12), 3 states have call successors, (12) Word has length 195 [2025-01-09 06:06:56,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:56,217 INFO L225 Difference]: With dead ends: 22079 [2025-01-09 06:06:56,217 INFO L226 Difference]: Without dead ends: 12282 [2025-01-09 06:06:56,232 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 196 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-09 06:06:56,232 INFO L435 NwaCegarLoop]: 284 mSDtfsCounter, 136 mSDsluCounter, 148 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 136 SdHoareTripleChecker+Valid, 432 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:56,232 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [136 Valid, 432 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:06:56,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12282 states. [2025-01-09 06:06:56,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12282 to 12270. [2025-01-09 06:06:56,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12270 states, 10513 states have (on average 1.1793969371254638) internal successors, (12399), 10632 states have internal predecessors, (12399), 901 states have call successors, (901), 713 states have call predecessors, (901), 855 states have return successors, (1240), 926 states have call predecessors, (1240), 899 states have call successors, (1240) [2025-01-09 06:06:56,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12270 states to 12270 states and 14540 transitions. [2025-01-09 06:06:56,892 INFO L78 Accepts]: Start accepts. Automaton has 12270 states and 14540 transitions. Word has length 195 [2025-01-09 06:06:56,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:56,892 INFO L471 AbstractCegarLoop]: Abstraction has 12270 states and 14540 transitions. [2025-01-09 06:06:56,892 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 3 states have call successors, (13), 3 states have call predecessors, (13), 3 states have return successors, (12), 3 states have call predecessors, (12), 3 states have call successors, (12) [2025-01-09 06:06:56,893 INFO L276 IsEmpty]: Start isEmpty. Operand 12270 states and 14540 transitions. [2025-01-09 06:06:56,897 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 198 [2025-01-09 06:06:56,897 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:56,898 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:56,904 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2025-01-09 06:06:57,098 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29,5 /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-09 06:06:57,098 INFO L396 AbstractCegarLoop]: === Iteration 31 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:57,098 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:57,099 INFO L85 PathProgramCache]: Analyzing trace with hash -1241425304, now seen corresponding path program 1 times [2025-01-09 06:06:57,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:57,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [708742527] [2025-01-09 06:06:57,099 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:57,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:57,105 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 197 statements into 1 equivalence classes. [2025-01-09 06:06:57,112 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 197 of 197 statements. [2025-01-09 06:06:57,112 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:57,112 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:57,140 INFO L134 CoverageAnalysis]: Checked inductivity of 167 backedges. 60 proven. 19 refuted. 0 times theorem prover too weak. 88 trivial. 0 not checked. [2025-01-09 06:06:57,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:57,141 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [708742527] [2025-01-09 06:06:57,141 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [708742527] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-09 06:06:57,141 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [416526360] [2025-01-09 06:06:57,141 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:57,141 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-09 06:06:57,141 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-09 06:06:57,143 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-09 06:06:57,144 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2025-01-09 06:06:57,195 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 197 statements into 1 equivalence classes. [2025-01-09 06:06:57,249 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 197 of 197 statements. [2025-01-09 06:06:57,249 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:57,249 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:57,252 INFO L256 TraceCheckSpWp]: Trace formula consists of 636 conjuncts, 3 conjuncts are in the unsatisfiable core [2025-01-09 06:06:57,254 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-09 06:06:57,270 INFO L134 CoverageAnalysis]: Checked inductivity of 167 backedges. 119 proven. 0 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2025-01-09 06:06:57,272 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-01-09 06:06:57,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [416526360] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:57,272 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-01-09 06:06:57,273 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 4 [2025-01-09 06:06:57,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1569871795] [2025-01-09 06:06:57,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:57,273 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-01-09 06:06:57,273 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:57,274 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-09 06:06:57,274 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-09 06:06:57,274 INFO L87 Difference]: Start difference. First operand 12270 states and 14540 transitions. Second operand has 3 states, 3 states have (on average 44.666666666666664) internal successors, (134), 3 states have internal predecessors, (134), 3 states have call successors, (13), 3 states have call predecessors, (13), 2 states have return successors, (12), 2 states have call predecessors, (12), 3 states have call successors, (12) [2025-01-09 06:06:57,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:57,775 INFO L93 Difference]: Finished difference Result 21401 states and 25807 transitions. [2025-01-09 06:06:57,775 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-09 06:06:57,775 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 44.666666666666664) internal successors, (134), 3 states have internal predecessors, (134), 3 states have call successors, (13), 3 states have call predecessors, (13), 2 states have return successors, (12), 2 states have call predecessors, (12), 3 states have call successors, (12) Word has length 197 [2025-01-09 06:06:57,775 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:57,824 INFO L225 Difference]: With dead ends: 21401 [2025-01-09 06:06:57,824 INFO L226 Difference]: Without dead ends: 11798 [2025-01-09 06:06:57,842 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 200 GetRequests, 198 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-09 06:06:57,842 INFO L435 NwaCegarLoop]: 272 mSDtfsCounter, 154 mSDsluCounter, 147 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 154 SdHoareTripleChecker+Valid, 419 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:57,842 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [154 Valid, 419 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:06:57,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11798 states. [2025-01-09 06:06:58,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11798 to 11786. [2025-01-09 06:06:58,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11786 states, 10085 states have (on average 1.162816063460585) internal successors, (11727), 10188 states have internal predecessors, (11727), 877 states have call successors, (877), 689 states have call predecessors, (877), 823 states have return successors, (1208), 910 states have call predecessors, (1208), 875 states have call successors, (1208) [2025-01-09 06:06:58,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11786 states to 11786 states and 13812 transitions. [2025-01-09 06:06:58,402 INFO L78 Accepts]: Start accepts. Automaton has 11786 states and 13812 transitions. Word has length 197 [2025-01-09 06:06:58,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:58,402 INFO L471 AbstractCegarLoop]: Abstraction has 11786 states and 13812 transitions. [2025-01-09 06:06:58,402 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 44.666666666666664) internal successors, (134), 3 states have internal predecessors, (134), 3 states have call successors, (13), 3 states have call predecessors, (13), 2 states have return successors, (12), 2 states have call predecessors, (12), 3 states have call successors, (12) [2025-01-09 06:06:58,402 INFO L276 IsEmpty]: Start isEmpty. Operand 11786 states and 13812 transitions. [2025-01-09 06:06:58,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2025-01-09 06:06:58,407 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:58,408 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:58,414 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2025-01-09 06:06:58,608 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30,6 /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-09 06:06:58,609 INFO L396 AbstractCegarLoop]: === Iteration 32 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:06:58,609 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:06:58,609 INFO L85 PathProgramCache]: Analyzing trace with hash 1585751445, now seen corresponding path program 1 times [2025-01-09 06:06:58,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:06:58,609 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1755916020] [2025-01-09 06:06:58,609 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:58,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:06:58,618 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 198 statements into 1 equivalence classes. [2025-01-09 06:06:58,623 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 198 of 198 statements. [2025-01-09 06:06:58,623 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:58,623 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:58,649 INFO L134 CoverageAnalysis]: Checked inductivity of 168 backedges. 53 proven. 14 refuted. 0 times theorem prover too weak. 101 trivial. 0 not checked. [2025-01-09 06:06:58,649 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:06:58,649 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1755916020] [2025-01-09 06:06:58,649 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1755916020] provided 0 perfect and 1 imperfect interpolant sequences [2025-01-09 06:06:58,649 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [314722946] [2025-01-09 06:06:58,649 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:06:58,649 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-01-09 06:06:58,649 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-09 06:06:58,651 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-01-09 06:06:58,653 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2025-01-09 06:06:58,699 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 198 statements into 1 equivalence classes. [2025-01-09 06:06:58,743 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 198 of 198 statements. [2025-01-09 06:06:58,744 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:06:58,744 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:06:58,746 INFO L256 TraceCheckSpWp]: Trace formula consists of 638 conjuncts, 3 conjuncts are in the unsatisfiable core [2025-01-09 06:06:58,748 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-09 06:06:58,801 INFO L134 CoverageAnalysis]: Checked inductivity of 168 backedges. 145 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2025-01-09 06:06:58,802 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-01-09 06:06:58,802 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [314722946] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:06:58,802 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-01-09 06:06:58,802 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 4 [2025-01-09 06:06:58,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1381970610] [2025-01-09 06:06:58,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:06:58,802 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-01-09 06:06:58,802 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:06:58,803 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-09 06:06:58,803 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-09 06:06:58,803 INFO L87 Difference]: Start difference. First operand 11786 states and 13812 transitions. Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 3 states have call successors, (13), 3 states have call predecessors, (13), 3 states have return successors, (13), 3 states have call predecessors, (13), 3 states have call successors, (13) [2025-01-09 06:06:59,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:06:59,338 INFO L93 Difference]: Finished difference Result 20367 states and 24210 transitions. [2025-01-09 06:06:59,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-09 06:06:59,338 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 3 states have call successors, (13), 3 states have call predecessors, (13), 3 states have return successors, (13), 3 states have call predecessors, (13), 3 states have call successors, (13) Word has length 198 [2025-01-09 06:06:59,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:06:59,377 INFO L225 Difference]: With dead ends: 20367 [2025-01-09 06:06:59,377 INFO L226 Difference]: Without dead ends: 11800 [2025-01-09 06:06:59,390 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 201 GetRequests, 199 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-09 06:06:59,391 INFO L435 NwaCegarLoop]: 269 mSDtfsCounter, 107 mSDsluCounter, 164 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 107 SdHoareTripleChecker+Valid, 433 SdHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:06:59,391 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [107 Valid, 433 Invalid, 9 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:06:59,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11800 states. [2025-01-09 06:06:59,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11800 to 11782. [2025-01-09 06:06:59,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11782 states, 10081 states have (on average 1.1444301160599146) internal successors, (11537), 10184 states have internal predecessors, (11537), 877 states have call successors, (877), 689 states have call predecessors, (877), 823 states have return successors, (1208), 910 states have call predecessors, (1208), 875 states have call successors, (1208) [2025-01-09 06:06:59,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11782 states to 11782 states and 13622 transitions. [2025-01-09 06:06:59,925 INFO L78 Accepts]: Start accepts. Automaton has 11782 states and 13622 transitions. Word has length 198 [2025-01-09 06:06:59,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:06:59,925 INFO L471 AbstractCegarLoop]: Abstraction has 11782 states and 13622 transitions. [2025-01-09 06:06:59,925 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 3 states have call successors, (13), 3 states have call predecessors, (13), 3 states have return successors, (13), 3 states have call predecessors, (13), 3 states have call successors, (13) [2025-01-09 06:06:59,925 INFO L276 IsEmpty]: Start isEmpty. Operand 11782 states and 13622 transitions. [2025-01-09 06:06:59,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2025-01-09 06:06:59,930 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:06:59,930 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:06:59,938 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2025-01-09 06:07:00,131 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable31 [2025-01-09 06:07:00,131 INFO L396 AbstractCegarLoop]: === Iteration 33 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:07:00,131 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:07:00,132 INFO L85 PathProgramCache]: Analyzing trace with hash 632998711, now seen corresponding path program 1 times [2025-01-09 06:07:00,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:07:00,132 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934735942] [2025-01-09 06:07:00,132 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:07:00,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:07:00,139 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 200 statements into 1 equivalence classes. [2025-01-09 06:07:00,146 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 200 of 200 statements. [2025-01-09 06:07:00,147 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:07:00,147 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:07:00,228 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 24 proven. 0 refuted. 0 times theorem prover too weak. 147 trivial. 0 not checked. [2025-01-09 06:07:00,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:07:00,229 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934735942] [2025-01-09 06:07:00,229 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934735942] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:07:00,229 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:07:00,229 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-09 06:07:00,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1764742025] [2025-01-09 06:07:00,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:07:00,229 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-01-09 06:07:00,229 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:07:00,229 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-09 06:07:00,230 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-09 06:07:00,230 INFO L87 Difference]: Start difference. First operand 11782 states and 13622 transitions. Second operand has 5 states, 5 states have (on average 22.0) internal successors, (110), 5 states have internal predecessors, (110), 5 states have call successors, (11), 2 states have call predecessors, (11), 1 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) [2025-01-09 06:07:01,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:07:01,695 INFO L93 Difference]: Finished difference Result 36067 states and 42171 transitions. [2025-01-09 06:07:01,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-09 06:07:01,696 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 22.0) internal successors, (110), 5 states have internal predecessors, (110), 5 states have call successors, (11), 2 states have call predecessors, (11), 1 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) Word has length 200 [2025-01-09 06:07:01,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:07:01,776 INFO L225 Difference]: With dead ends: 36067 [2025-01-09 06:07:01,776 INFO L226 Difference]: Without dead ends: 29223 [2025-01-09 06:07:01,791 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-09 06:07:01,791 INFO L435 NwaCegarLoop]: 459 mSDtfsCounter, 426 mSDsluCounter, 773 mSDsCounter, 0 mSdLazyCounter, 185 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 426 SdHoareTripleChecker+Valid, 1232 SdHoareTripleChecker+Invalid, 190 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 185 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-01-09 06:07:01,791 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [426 Valid, 1232 Invalid, 190 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 185 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-01-09 06:07:01,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29223 states. [2025-01-09 06:07:02,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29223 to 24551. [2025-01-09 06:07:02,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24551 states, 20982 states have (on average 1.1496520827375847) internal successors, (24122), 21211 states have internal predecessors, (24122), 1833 states have call successors, (1833), 1433 states have call predecessors, (1833), 1735 states have return successors, (2628), 1908 states have call predecessors, (2628), 1831 states have call successors, (2628) [2025-01-09 06:07:03,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24551 states to 24551 states and 28583 transitions. [2025-01-09 06:07:03,065 INFO L78 Accepts]: Start accepts. Automaton has 24551 states and 28583 transitions. Word has length 200 [2025-01-09 06:07:03,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:07:03,066 INFO L471 AbstractCegarLoop]: Abstraction has 24551 states and 28583 transitions. [2025-01-09 06:07:03,066 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 22.0) internal successors, (110), 5 states have internal predecessors, (110), 5 states have call successors, (11), 2 states have call predecessors, (11), 1 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) [2025-01-09 06:07:03,066 INFO L276 IsEmpty]: Start isEmpty. Operand 24551 states and 28583 transitions. [2025-01-09 06:07:03,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 205 [2025-01-09 06:07:03,071 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:07:03,071 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:07:03,071 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable32 [2025-01-09 06:07:03,071 INFO L396 AbstractCegarLoop]: === Iteration 34 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:07:03,071 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:07:03,072 INFO L85 PathProgramCache]: Analyzing trace with hash 399754463, now seen corresponding path program 1 times [2025-01-09 06:07:03,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:07:03,072 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199272764] [2025-01-09 06:07:03,072 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:07:03,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:07:03,078 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 204 statements into 1 equivalence classes. [2025-01-09 06:07:03,082 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 204 of 204 statements. [2025-01-09 06:07:03,083 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:07:03,083 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-09 06:07:03,102 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 171 trivial. 0 not checked. [2025-01-09 06:07:03,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-09 06:07:03,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [199272764] [2025-01-09 06:07:03,103 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [199272764] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-09 06:07:03,103 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-09 06:07:03,103 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-09 06:07:03,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679773563] [2025-01-09 06:07:03,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-09 06:07:03,103 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-01-09 06:07:03,103 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-09 06:07:03,104 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-09 06:07:03,104 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-09 06:07:03,104 INFO L87 Difference]: Start difference. First operand 24551 states and 28583 transitions. Second operand has 3 states, 3 states have (on average 33.0) internal successors, (99), 3 states have internal predecessors, (99), 2 states have call successors, (10), 2 states have call predecessors, (10), 1 states have return successors, (9), 1 states have call predecessors, (9), 1 states have call successors, (9) [2025-01-09 06:07:04,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-09 06:07:04,260 INFO L93 Difference]: Finished difference Result 43922 states and 51276 transitions. [2025-01-09 06:07:04,260 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-09 06:07:04,260 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 33.0) internal successors, (99), 3 states have internal predecessors, (99), 2 states have call successors, (10), 2 states have call predecessors, (10), 1 states have return successors, (9), 1 states have call predecessors, (9), 1 states have call successors, (9) Word has length 204 [2025-01-09 06:07:04,261 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-01-09 06:07:04,340 INFO L225 Difference]: With dead ends: 43922 [2025-01-09 06:07:04,341 INFO L226 Difference]: Without dead ends: 24571 [2025-01-09 06:07:04,373 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-09 06:07:04,373 INFO L435 NwaCegarLoop]: 183 mSDtfsCounter, 0 mSDsluCounter, 172 mSDsCounter, 0 mSdLazyCounter, 12 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 355 SdHoareTripleChecker+Invalid, 12 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 12 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-01-09 06:07:04,373 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 355 Invalid, 12 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 12 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-01-09 06:07:04,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24571 states. [2025-01-09 06:07:05,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24571 to 24571. [2025-01-09 06:07:05,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24571 states, 21002 states have (on average 1.1495095705170937) internal successors, (24142), 21231 states have internal predecessors, (24142), 1833 states have call successors, (1833), 1433 states have call predecessors, (1833), 1735 states have return successors, (2628), 1908 states have call predecessors, (2628), 1831 states have call successors, (2628) [2025-01-09 06:07:05,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24571 states to 24571 states and 28603 transitions. [2025-01-09 06:07:05,745 INFO L78 Accepts]: Start accepts. Automaton has 24571 states and 28603 transitions. Word has length 204 [2025-01-09 06:07:05,746 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-01-09 06:07:05,746 INFO L471 AbstractCegarLoop]: Abstraction has 24571 states and 28603 transitions. [2025-01-09 06:07:05,746 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 33.0) internal successors, (99), 3 states have internal predecessors, (99), 2 states have call successors, (10), 2 states have call predecessors, (10), 1 states have return successors, (9), 1 states have call predecessors, (9), 1 states have call successors, (9) [2025-01-09 06:07:05,746 INFO L276 IsEmpty]: Start isEmpty. Operand 24571 states and 28603 transitions. [2025-01-09 06:07:05,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 206 [2025-01-09 06:07:05,752 INFO L210 NwaCegarLoop]: Found error trace [2025-01-09 06:07:05,752 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:07:05,752 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable33 [2025-01-09 06:07:05,753 INFO L396 AbstractCegarLoop]: === Iteration 35 === Targeting error2Err0ASSERT_VIOLATIONERROR_FUNCTION === [error1Err0ASSERT_VIOLATIONERROR_FUNCTION, error2Err0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-01-09 06:07:05,753 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-09 06:07:05,753 INFO L85 PathProgramCache]: Analyzing trace with hash 736537260, now seen corresponding path program 1 times [2025-01-09 06:07:05,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-09 06:07:05,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998007767] [2025-01-09 06:07:05,753 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-09 06:07:05,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-09 06:07:05,760 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 205 statements into 1 equivalence classes. [2025-01-09 06:07:05,766 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 205 of 205 statements. [2025-01-09 06:07:05,766 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:07:05,766 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-09 06:07:05,766 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-09 06:07:05,770 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 205 statements into 1 equivalence classes. [2025-01-09 06:07:05,777 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 205 of 205 statements. [2025-01-09 06:07:05,777 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-09 06:07:05,777 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-09 06:07:05,847 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-09 06:07:05,847 INFO L340 BasicCegarLoop]: Counterexample is feasible [2025-01-09 06:07:05,849 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location error2Err0ASSERT_VIOLATIONERROR_FUNCTION (1 of 2 remaining) [2025-01-09 06:07:05,851 INFO L782 garLoopResultBuilder]: Registering result UNKNOWN for location error1Err0ASSERT_VIOLATIONERROR_FUNCTION (0 of 2 remaining) [2025-01-09 06:07:05,851 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable34 [2025-01-09 06:07:05,854 INFO L422 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-09 06:07:06,003 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2025-01-09 06:07:06,005 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 09.01 06:07:06 BoogieIcfgContainer [2025-01-09 06:07:06,005 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2025-01-09 06:07:06,006 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-01-09 06:07:06,006 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-01-09 06:07:06,006 INFO L274 PluginConnector]: Witness Printer initialized [2025-01-09 06:07:06,007 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.01 06:06:28" (3/4) ... [2025-01-09 06:07:06,007 INFO L140 WitnessPrinter]: Generating witness for reachability counterexample [2025-01-09 06:07:06,172 INFO L127 tionWitnessGenerator]: Generated YAML witness of length 151. [2025-01-09 06:07:06,280 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-01-09 06:07:06,285 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.yml [2025-01-09 06:07:06,285 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-01-09 06:07:06,285 INFO L158 Benchmark]: Toolchain (without parser) took 39158.22ms. Allocated memory was 167.8MB in the beginning and 4.9GB in the end (delta: 4.8GB). Free memory was 133.5MB in the beginning and 4.2GB in the end (delta: -4.0GB). Peak memory consumption was 756.3MB. Max. memory is 16.1GB. [2025-01-09 06:07:06,285 INFO L158 Benchmark]: CDTParser took 0.24ms. Allocated memory is still 201.3MB. Free memory is still 127.8MB. There was no memory consumed. Max. memory is 16.1GB. [2025-01-09 06:07:06,286 INFO L158 Benchmark]: CACSL2BoogieTranslator took 307.83ms. Allocated memory is still 167.8MB. Free memory was 133.1MB in the beginning and 115.3MB in the end (delta: 17.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-01-09 06:07:06,286 INFO L158 Benchmark]: Boogie Procedure Inliner took 50.69ms. Allocated memory is still 167.8MB. Free memory was 115.3MB in the beginning and 112.8MB in the end (delta: 2.5MB). There was no memory consumed. Max. memory is 16.1GB. [2025-01-09 06:07:06,286 INFO L158 Benchmark]: Boogie Preprocessor took 65.67ms. Allocated memory is still 167.8MB. Free memory was 112.8MB in the beginning and 109.8MB in the end (delta: 2.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-01-09 06:07:06,286 INFO L158 Benchmark]: RCFGBuilder took 613.64ms. Allocated memory is still 167.8MB. Free memory was 109.8MB in the beginning and 75.0MB in the end (delta: 34.8MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2025-01-09 06:07:06,286 INFO L158 Benchmark]: TraceAbstraction took 37830.50ms. Allocated memory was 167.8MB in the beginning and 4.9GB in the end (delta: 4.8GB). Free memory was 74.6MB in the beginning and 4.2GB in the end (delta: -4.1GB). Peak memory consumption was 655.6MB. Max. memory is 16.1GB. [2025-01-09 06:07:06,286 INFO L158 Benchmark]: Witness Printer took 278.97ms. Allocated memory is still 4.9GB. Free memory was 4.2GB in the beginning and 4.2GB in the end (delta: 41.9MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2025-01-09 06:07:06,287 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24ms. Allocated memory is still 201.3MB. Free memory is still 127.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 307.83ms. Allocated memory is still 167.8MB. Free memory was 133.1MB in the beginning and 115.3MB in the end (delta: 17.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 50.69ms. Allocated memory is still 167.8MB. Free memory was 115.3MB in the beginning and 112.8MB in the end (delta: 2.5MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 65.67ms. Allocated memory is still 167.8MB. Free memory was 112.8MB in the beginning and 109.8MB in the end (delta: 2.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 613.64ms. Allocated memory is still 167.8MB. Free memory was 109.8MB in the beginning and 75.0MB in the end (delta: 34.8MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. * TraceAbstraction took 37830.50ms. Allocated memory was 167.8MB in the beginning and 4.9GB in the end (delta: 4.8GB). Free memory was 74.6MB in the beginning and 4.2GB in the end (delta: -4.1GB). Peak memory consumption was 655.6MB. Max. memory is 16.1GB. * Witness Printer took 278.97ms. Allocated memory is still 4.9GB. Free memory was 4.2GB in the beginning and 4.2GB in the end (delta: 41.9MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 599]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L32] int fast_clk_edge ; [L33] int slow_clk_edge ; [L34] int q_buf_0 ; [L35] int q_free ; [L36] int q_read_ev ; [L37] int q_write_ev ; [L38] int q_req_up ; [L39] int q_ev ; [L60] int p_num_write ; [L61] int p_last_write ; [L62] int p_dw_st ; [L63] int p_dw_pc ; [L64] int p_dw_i ; [L65] int c_num_read ; [L66] int c_last_read ; [L67] int c_dr_st ; [L68] int c_dr_pc ; [L69] int c_dr_i ; [L202] static int a_t ; [L352] static int t = 0; [L603] int m_pc = 0; [L604] int t1_pc = 0; [L605] int t2_pc = 0; [L606] int m_st ; [L607] int t1_st ; [L608] int t2_st ; [L609] int m_i ; [L610] int t1_i ; [L611] int t2_i ; [L612] int M_E = 2; [L613] int T1_E = 2; [L614] int T2_E = 2; [L615] int E_M = 2; [L616] int E_1 = 2; [L617] int E_2 = 2; [L622] int token ; [L624] int local ; VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=0, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t=0, token=0] [L1202] COND FALSE !(__VERIFIER_nondet_int()) [L1205] CALL main2() [L1189] int __retres1 ; [L1193] CALL init_model2() [L1103] m_i = 1 [L1104] t1_i = 1 [L1105] t2_i = 1 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1193] RET init_model2() [L1194] CALL start_simulation2() [L1130] int kernel_st ; [L1131] int tmp ; [L1132] int tmp___0 ; [L1136] kernel_st = 0 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1137] FCALL update_channels2() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1138] CALL init_threads2() [L822] COND TRUE m_i == 1 [L823] m_st = 0 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L827] COND TRUE t1_i == 1 [L828] t1_st = 0 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L832] COND TRUE t2_i == 1 [L833] t2_st = 0 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1138] RET init_threads2() [L1139] CALL fire_delta_events2() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(E_1)=2, \old(E_2)=2, \old(E_M)=2, \old(M_E)=2, \old(T1_E)=2, \old(T2_E)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L935] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(E_1)=2, \old(E_2)=2, \old(E_M)=2, \old(M_E)=2, \old(T1_E)=2, \old(T2_E)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L940] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(E_1)=2, \old(E_2)=2, \old(E_M)=2, \old(M_E)=2, \old(T1_E)=2, \old(T2_E)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L945] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(E_1)=2, \old(E_2)=2, \old(E_M)=2, \old(M_E)=2, \old(T1_E)=2, \old(T2_E)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L950] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(E_1)=2, \old(E_2)=2, \old(E_M)=2, \old(M_E)=2, \old(T1_E)=2, \old(T2_E)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L955] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(E_1)=2, \old(E_2)=2, \old(E_M)=2, \old(M_E)=2, \old(T1_E)=2, \old(T2_E)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L960] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(E_1)=2, \old(E_2)=2, \old(E_M)=2, \old(M_E)=2, \old(T1_E)=2, \old(T2_E)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1139] RET fire_delta_events2() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1140] CALL activate_threads2() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1008] int tmp ; [L1009] int tmp___0 ; [L1010] int tmp___1 ; [L1014] CALL, EXPR is_master_triggered() [L754] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L757] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L767] __retres1 = 0 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, __retres1=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L769] return (__retres1); VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, \result=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1014] RET, EXPR is_master_triggered() [L1014] tmp = is_master_triggered() [L1016] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1022] CALL, EXPR is_transmit1_triggered() [L773] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L776] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L786] __retres1 = 0 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, __retres1=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L788] return (__retres1); VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, \result=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1022] RET, EXPR is_transmit1_triggered() [L1022] tmp___0 = is_transmit1_triggered() [L1024] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1030] CALL, EXPR is_transmit2_triggered() [L792] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L795] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L805] __retres1 = 0 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, __retres1=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L807] return (__retres1); VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, \result=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1030] RET, EXPR is_transmit2_triggered() [L1030] tmp___1 = is_transmit2_triggered() [L1032] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=0, \old(t1_st)=0, \old(t2_st)=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1140] RET activate_threads2() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1141] CALL reset_delta_events2() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(E_1)=2, \old(E_2)=2, \old(E_M)=2, \old(M_E)=2, \old(T1_E)=2, \old(T2_E)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L973] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(E_1)=2, \old(E_2)=2, \old(E_M)=2, \old(M_E)=2, \old(T1_E)=2, \old(T2_E)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L978] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(E_1)=2, \old(E_2)=2, \old(E_M)=2, \old(M_E)=2, \old(T1_E)=2, \old(T2_E)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L983] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(E_1)=2, \old(E_2)=2, \old(E_M)=2, \old(M_E)=2, \old(T1_E)=2, \old(T2_E)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L988] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(E_1)=2, \old(E_2)=2, \old(E_M)=2, \old(M_E)=2, \old(T1_E)=2, \old(T2_E)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L993] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(E_1)=2, \old(E_2)=2, \old(E_M)=2, \old(M_E)=2, \old(T1_E)=2, \old(T2_E)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L998] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(E_1)=2, \old(E_2)=2, \old(E_M)=2, \old(M_E)=2, \old(T1_E)=2, \old(T2_E)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1141] RET reset_delta_events2() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L1147] kernel_st = 1 [L1148] CALL eval2() [L868] int tmp ; VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L875] CALL, EXPR exists_runnable_thread2() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L842] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L845] COND TRUE m_st == 0 [L846] __retres1 = 1 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, __retres1=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L863] return (__retres1); VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \result=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L875] RET, EXPR exists_runnable_thread2() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L875] tmp = exists_runnable_thread2() [L877] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L882] COND TRUE m_st == 0 [L883] int tmp_ndt_1; [L884] tmp_ndt_1 = __VERIFIER_nondet_int() [L885] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L896] COND TRUE t1_st == 0 [L897] int tmp_ndt_2; [L898] tmp_ndt_2 = __VERIFIER_nondet_int() [L899] COND TRUE \read(tmp_ndt_2) [L901] t1_st = 1 [L902] CALL transmit1() [L685] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=0, t1_st=1, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L698] t1_pc = 1 [L699] t1_st = 2 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=0, t2_st=0, t=0, token=0] [L902] RET transmit1() [L910] COND TRUE t2_st == 0 [L911] int tmp_ndt_3; [L912] tmp_ndt_3 = __VERIFIER_nondet_int() [L913] COND TRUE \read(tmp_ndt_3) [L915] t2_st = 1 [L916] CALL transmit2() [L721] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=0, t2_st=1, t=0, token=0] [L734] t2_pc = 1 [L735] t2_st = 2 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L916] RET transmit2() [L875] CALL, EXPR exists_runnable_thread2() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L842] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L845] COND TRUE m_st == 0 [L846] __retres1 = 1 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, __retres1=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L863] return (__retres1); VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \result=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L875] RET, EXPR exists_runnable_thread2() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L875] tmp = exists_runnable_thread2() [L877] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L882] COND TRUE m_st == 0 [L883] int tmp_ndt_1; [L884] tmp_ndt_1 = __VERIFIER_nondet_int() [L885] COND TRUE \read(tmp_ndt_1) [L887] m_st = 1 [L888] CALL master() [L627] int tmp_var = __VERIFIER_nondet_int(); [L629] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, tmp_var=0, token=0] [L643] token = __VERIFIER_nondet_int() [L644] local = token [L645] E_1 = 1 VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, tmp_var=0, token=0] [L646] CALL immediate_notify() VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L1046] CALL activate_threads2() VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L1008] int tmp ; [L1009] int tmp___0 ; [L1010] int tmp___1 ; [L1014] CALL, EXPR is_master_triggered() [L754] int __retres1 ; VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L757] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L767] __retres1 = 0 VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, __retres1=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L769] return (__retres1); VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, \result=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L1014] RET, EXPR is_master_triggered() [L1014] tmp = is_master_triggered() [L1016] COND FALSE !(\read(tmp)) VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L1022] CALL, EXPR is_transmit1_triggered() [L773] int __retres1 ; VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L776] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L777] COND TRUE E_1 == 1 [L778] __retres1 = 1 VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, __retres1=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L788] return (__retres1); VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, \result=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L1022] RET, EXPR is_transmit1_triggered() [L1022] tmp___0 = is_transmit1_triggered() [L1024] COND TRUE \read(tmp___0) [L1025] t1_st = 0 VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=0, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L1030] CALL, EXPR is_transmit2_triggered() [L792] int __retres1 ; VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=0, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L795] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=0, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L796] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=0, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L805] __retres1 = 0 VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, __retres1=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=0, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L807] return (__retres1); VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, \result=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=0, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L1030] RET, EXPR is_transmit2_triggered() [L1030] tmp___1 = is_transmit2_triggered() [L1032] COND FALSE !(\read(tmp___1)) VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=0, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L1046] RET activate_threads2() VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=1, \old(t1_st)=2, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=0, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L646] RET immediate_notify() VAL [E_1=1, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=0, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=0, t2_i=1, t2_pc=1, t2_st=2, t=0, tmp_var=0, token=0] [L647] E_1 = 2 [L648] m_pc = 1 [L649] m_st = 2 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=0, t2_i=1, t2_pc=1, t2_st=2, t=0, tmp_var=0, token=0] [L888] RET master() [L896] COND TRUE t1_st == 0 [L897] int tmp_ndt_2; [L898] tmp_ndt_2 = __VERIFIER_nondet_int() [L899] COND TRUE \read(tmp_ndt_2) [L901] t1_st = 1 [L902] CALL transmit1() [L685] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L688] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=0] [L704] token += 1 [L705] E_2 = 1 VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L706] CALL immediate_notify() VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L1046] CALL activate_threads2() VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L1008] int tmp ; [L1009] int tmp___0 ; [L1010] int tmp___1 ; [L1014] CALL, EXPR is_master_triggered() [L754] int __retres1 ; VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L757] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L758] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L767] __retres1 = 0 VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, __retres1=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L769] return (__retres1); VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, \result=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L1014] RET, EXPR is_master_triggered() [L1014] tmp = is_master_triggered() [L1016] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L1022] CALL, EXPR is_transmit1_triggered() [L773] int __retres1 ; VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L776] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L777] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L786] __retres1 = 0 VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, __retres1=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L788] return (__retres1); VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, \result=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L1022] RET, EXPR is_transmit1_triggered() [L1022] tmp___0 = is_transmit1_triggered() [L1024] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L1030] CALL, EXPR is_transmit2_triggered() [L792] int __retres1 ; VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L795] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L796] COND TRUE E_2 == 1 [L797] __retres1 = 1 VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, __retres1=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L807] return (__retres1); VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, \result=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=2, t=0, token=1] [L1030] RET, EXPR is_transmit2_triggered() [L1030] tmp___1 = is_transmit2_triggered() [L1032] COND TRUE \read(tmp___1) [L1033] t2_st = 0 VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=0, t=0, token=1] [L1046] RET activate_threads2() VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=1, \old(t2_st)=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=0, t=0, token=1] [L706] RET immediate_notify() VAL [E_1=2, E_2=1, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=0, t=0, token=1] [L707] E_2 = 2 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=1, t2_i=1, t2_pc=1, t2_st=0, t=0, token=1] [L698] t1_pc = 1 [L699] t1_st = 2 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=0, t=0, token=1] [L902] RET transmit1() [L910] COND TRUE t2_st == 0 [L911] int tmp_ndt_3; [L912] tmp_ndt_3 = __VERIFIER_nondet_int() [L913] COND TRUE \read(tmp_ndt_3) [L915] t2_st = 1 [L916] CALL transmit2() [L721] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=1] [L724] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=1] [L740] token += 1 [L741] E_M = 1 VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L742] CALL immediate_notify() VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L1046] CALL activate_threads2() VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L1008] int tmp ; [L1009] int tmp___0 ; [L1010] int tmp___1 ; [L1014] CALL, EXPR is_master_triggered() [L754] int __retres1 ; VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L757] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L758] COND TRUE E_M == 1 [L759] __retres1 = 1 VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, __retres1=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L769] return (__retres1); VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, \result=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=2, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L1014] RET, EXPR is_master_triggered() [L1014] tmp = is_master_triggered() [L1016] COND TRUE \read(tmp) [L1017] m_st = 0 VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L1022] CALL, EXPR is_transmit1_triggered() [L773] int __retres1 ; VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L776] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L777] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L786] __retres1 = 0 VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, __retres1=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L788] return (__retres1); VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, \result=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L1022] RET, EXPR is_transmit1_triggered() [L1022] tmp___0 = is_transmit1_triggered() [L1024] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L1030] CALL, EXPR is_transmit2_triggered() [L792] int __retres1 ; VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L795] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L796] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L805] __retres1 = 0 VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, __retres1=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L807] return (__retres1); VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, \result=0, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L1030] RET, EXPR is_transmit2_triggered() [L1030] tmp___1 = is_transmit2_triggered() [L1032] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L1046] RET activate_threads2() VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, \old(m_st)=2, \old(t1_st)=2, \old(t2_st)=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L742] RET immediate_notify() VAL [E_1=2, E_2=2, E_M=1, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L743] E_M = 2 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=1, t=0, token=2] [L734] t2_pc = 1 [L735] t2_st = 2 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=2] [L916] RET transmit2() [L875] CALL, EXPR exists_runnable_thread2() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=2] [L842] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=2] [L845] COND TRUE m_st == 0 [L846] __retres1 = 1 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, __retres1=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=2] [L863] return (__retres1); VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, \result=1, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=2] [L875] RET, EXPR exists_runnable_thread2() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=2] [L875] tmp = exists_runnable_thread2() [L877] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=2] [L882] COND TRUE m_st == 0 [L883] int tmp_ndt_1; [L884] tmp_ndt_1 = __VERIFIER_nondet_int() [L885] COND TRUE \read(tmp_ndt_1) [L887] m_st = 1 [L888] CALL master() [L627] int tmp_var = __VERIFIER_nondet_int(); [L629] COND FALSE !(m_pc == 0) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, tmp_var=5, token=2] [L632] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, tmp_var=5, token=2] [L654] COND FALSE !(token != local + 2) VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, tmp_var=5, token=2] [L659] COND TRUE tmp_var <= 5 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, tmp_var=5, token=2] [L660] COND TRUE tmp_var >= 5 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, tmp_var=5, token=2] [L665] COND TRUE tmp_var <= 5 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, tmp_var=5, token=2] [L666] COND TRUE tmp_var >= 5 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, tmp_var=5, token=2] [L667] COND TRUE tmp_var == 5 VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=2] [L668] CALL error2() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=2] [L599] reach_error() VAL [E_1=2, E_2=2, E_M=2, M_E=2, T1_E=2, T2_E=2, a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, local=0, m_i=1, m_pc=1, m_st=1, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t1_i=1, t1_pc=1, t1_st=2, t2_i=1, t2_pc=1, t2_st=2, t=0, token=2] - UnprovableResult [Line: 27]: Unable to prove that a call to reach_error is unreachable Unable to prove that a call to reach_error is unreachable Reason: Not analyzed. - StatisticsResult: Ultimate Automizer benchmark data CFG has 16 procedures, 251 locations, 2 error locations. Started 1 CEGAR loops. OverallTime: 37.6s, OverallIterations: 35, TraceHistogramMax: 4, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.2s, AutomataDifference: 18.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 9963 SdHoareTripleChecker+Valid, 4.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 9788 mSDsluCounter, 22051 SdHoareTripleChecker+Invalid, 3.8s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 14097 mSDsCounter, 1152 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 6515 IncrementalHoareTripleChecker+Invalid, 7667 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1152 mSolverCounterUnsat, 7954 mSDtfsCounter, 6515 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 1421 GetRequests, 1265 SyntacticMatches, 0 SemanticMatches, 156 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 83 ImplicationChecksByTransitivity, 0.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=24571occurred in iteration=34, InterpolantAutomatonStates: 196, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 13.7s AutomataMinimizationTime, 34 MinimizatonAttempts, 7576 StatesRemovedByMinimization, 26 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.2s SsaConstructionTime, 0.6s SatisfiabilityAnalysisTime, 2.3s InterpolantComputationTime, 4956 NumberOfCodeBlocks, 4956 NumberOfCodeBlocksAsserted, 41 NumberOfCheckSat, 4711 ConstructedInterpolants, 0 QuantifiedInterpolants, 7325 SizeOfPredicates, 0 NumberOfNonLiveVariables, 3699 ConjunctsInSsa, 16 ConjunctsInUnsatCore, 40 InterpolantComputations, 34 PerfectInterpolantSequences, 2422/2483 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2025-01-09 06:07:06,308 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE