./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c00e63dc Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe --- Real Ultimate output --- This is Ultimate 0.3.0-?-c00e63d-m [2025-02-06 19:04:26,860 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-02-06 19:04:26,918 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf [2025-02-06 19:04:26,925 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-02-06 19:04:26,925 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-02-06 19:04:26,925 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-02-06 19:04:26,948 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-02-06 19:04:26,949 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-02-06 19:04:26,949 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-02-06 19:04:26,949 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-02-06 19:04:26,950 INFO L153 SettingsManager]: * Use memory slicer=true [2025-02-06 19:04:26,950 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-02-06 19:04:26,950 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-02-06 19:04:26,950 INFO L153 SettingsManager]: * Use SBE=true [2025-02-06 19:04:26,951 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-02-06 19:04:26,951 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-02-06 19:04:26,951 INFO L153 SettingsManager]: * Use old map elimination=false [2025-02-06 19:04:26,951 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-02-06 19:04:26,951 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-02-06 19:04:26,951 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-02-06 19:04:26,951 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-02-06 19:04:26,951 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-02-06 19:04:26,951 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-02-06 19:04:26,951 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-02-06 19:04:26,951 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-02-06 19:04:26,951 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-02-06 19:04:26,951 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-02-06 19:04:26,951 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-02-06 19:04:26,951 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-02-06 19:04:26,952 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-02-06 19:04:26,952 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-02-06 19:04:26,952 INFO L153 SettingsManager]: * Use constant arrays=true [2025-02-06 19:04:26,952 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-02-06 19:04:26,952 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-02-06 19:04:26,952 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-02-06 19:04:26,952 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-02-06 19:04:26,952 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-02-06 19:04:26,952 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe [2025-02-06 19:04:27,169 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-02-06 19:04:27,181 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-02-06 19:04:27,184 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-02-06 19:04:27,185 INFO L270 PluginConnector]: Initializing CDTParser... [2025-02-06 19:04:27,185 INFO L274 PluginConnector]: CDTParser initialized [2025-02-06 19:04:27,186 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i [2025-02-06 19:04:28,313 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/f57cc9a8a/006ef8d82149419ca700c76926c2cb44/FLAG0e29a7943 [2025-02-06 19:04:28,571 INFO L384 CDTParser]: Found 1 translation units. [2025-02-06 19:04:28,572 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i [2025-02-06 19:04:28,588 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/f57cc9a8a/006ef8d82149419ca700c76926c2cb44/FLAG0e29a7943 [2025-02-06 19:04:28,864 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/f57cc9a8a/006ef8d82149419ca700c76926c2cb44 [2025-02-06 19:04:28,866 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-02-06 19:04:28,867 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-02-06 19:04:28,868 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-02-06 19:04:28,868 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-02-06 19:04:28,871 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-02-06 19:04:28,872 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:04:28" (1/1) ... [2025-02-06 19:04:28,872 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1bb4cf07 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:28, skipping insertion in model container [2025-02-06 19:04:28,872 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:04:28" (1/1) ... [2025-02-06 19:04:28,888 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-02-06 19:04:29,064 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:04:29,072 INFO L200 MainTranslator]: Completed pre-run [2025-02-06 19:04:29,098 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:04:29,115 INFO L204 MainTranslator]: Completed translation [2025-02-06 19:04:29,115 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:29 WrapperNode [2025-02-06 19:04:29,115 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-02-06 19:04:29,116 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-02-06 19:04:29,116 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-02-06 19:04:29,116 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-02-06 19:04:29,120 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:29" (1/1) ... [2025-02-06 19:04:29,126 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:29" (1/1) ... [2025-02-06 19:04:29,138 INFO L138 Inliner]: procedures = 109, calls = 13, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 31 [2025-02-06 19:04:29,139 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-02-06 19:04:29,139 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-02-06 19:04:29,140 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-02-06 19:04:29,140 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-02-06 19:04:29,145 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:29" (1/1) ... [2025-02-06 19:04:29,145 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:29" (1/1) ... [2025-02-06 19:04:29,146 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:29" (1/1) ... [2025-02-06 19:04:29,152 INFO L175 MemorySlicer]: Split 7 memory accesses to 2 slices as follows [3, 4]. 57 percent of accesses are in the largest equivalence class. The 0 initializations are split as follows [0, 0]. The 3 writes are split as follows [1, 2]. [2025-02-06 19:04:29,153 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:29" (1/1) ... [2025-02-06 19:04:29,153 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:29" (1/1) ... [2025-02-06 19:04:29,155 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:29" (1/1) ... [2025-02-06 19:04:29,155 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:29" (1/1) ... [2025-02-06 19:04:29,156 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:29" (1/1) ... [2025-02-06 19:04:29,156 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:29" (1/1) ... [2025-02-06 19:04:29,160 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-02-06 19:04:29,161 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-02-06 19:04:29,161 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-02-06 19:04:29,161 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-02-06 19:04:29,162 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:29" (1/1) ... [2025-02-06 19:04:29,166 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:04:29,175 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:04:29,184 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:04:29,186 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-02-06 19:04:29,206 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-02-06 19:04:29,206 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-02-06 19:04:29,207 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-02-06 19:04:29,207 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-02-06 19:04:29,207 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-02-06 19:04:29,207 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-02-06 19:04:29,207 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-02-06 19:04:29,207 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-02-06 19:04:29,274 INFO L257 CfgBuilder]: Building ICFG [2025-02-06 19:04:29,275 INFO L287 CfgBuilder]: Building CFG for each procedure with an implementation [2025-02-06 19:04:29,346 INFO L? ?]: Removed 4 outVars from TransFormulas that were not future-live. [2025-02-06 19:04:29,346 INFO L308 CfgBuilder]: Performing block encoding [2025-02-06 19:04:29,351 INFO L332 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-02-06 19:04:29,351 INFO L337 CfgBuilder]: Removed 0 assume(true) statements. [2025-02-06 19:04:29,352 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:04:29 BoogieIcfgContainer [2025-02-06 19:04:29,352 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-02-06 19:04:29,352 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-02-06 19:04:29,352 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-02-06 19:04:29,356 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-02-06 19:04:29,356 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:04:29,356 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.02 07:04:28" (1/3) ... [2025-02-06 19:04:29,357 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@fa60017 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:04:29, skipping insertion in model container [2025-02-06 19:04:29,357 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:04:29,357 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:04:29" (2/3) ... [2025-02-06 19:04:29,357 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@fa60017 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:04:29, skipping insertion in model container [2025-02-06 19:04:29,357 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:04:29,357 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:04:29" (3/3) ... [2025-02-06 19:04:29,358 INFO L363 chiAutomizerObserver]: Analyzing ICFG Urban-2013WST-Fig2-modified1000-alloca.i [2025-02-06 19:04:29,389 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-02-06 19:04:29,389 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-02-06 19:04:29,389 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-02-06 19:04:29,389 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-02-06 19:04:29,389 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-02-06 19:04:29,389 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-02-06 19:04:29,389 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-02-06 19:04:29,389 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-02-06 19:04:29,392 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:04:29,403 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2025-02-06 19:04:29,403 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:04:29,403 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:04:29,406 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:04:29,406 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2025-02-06 19:04:29,406 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-02-06 19:04:29,406 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:04:29,407 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2025-02-06 19:04:29,407 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:04:29,407 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:04:29,407 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:04:29,407 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2025-02-06 19:04:29,412 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-02-06 19:04:29,412 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !true;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-02-06 19:04:29,415 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:04:29,416 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 1 times [2025-02-06 19:04:29,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:04:29,421 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745984209] [2025-02-06 19:04:29,421 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:04:29,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:04:29,479 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:04:29,494 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:04:29,494 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:04:29,494 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:04:29,495 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:04:29,498 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:04:29,503 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:04:29,504 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:04:29,504 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:04:29,517 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:04:29,519 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:04:29,519 INFO L85 PathProgramCache]: Analyzing trace with hash 1322586, now seen corresponding path program 1 times [2025-02-06 19:04:29,519 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:04:29,519 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1243645909] [2025-02-06 19:04:29,519 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:04:29,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:04:29,527 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-02-06 19:04:29,531 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-02-06 19:04:29,532 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:04:29,532 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:04:29,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:29,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:04:29,566 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1243645909] [2025-02-06 19:04:29,567 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1243645909] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:04:29,567 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:04:29,567 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:04:29,567 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [793241623] [2025-02-06 19:04:29,568 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:04:29,570 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:04:29,571 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:04:29,590 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-02-06 19:04:29,590 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-02-06 19:04:29,593 INFO L87 Difference]: Start difference. First operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:04:29,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:04:29,599 INFO L93 Difference]: Finished difference Result 11 states and 12 transitions. [2025-02-06 19:04:29,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 12 transitions. [2025-02-06 19:04:29,600 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2025-02-06 19:04:29,604 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 7 states and 8 transitions. [2025-02-06 19:04:29,605 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2025-02-06 19:04:29,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2025-02-06 19:04:29,606 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7 states and 8 transitions. [2025-02-06 19:04:29,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:04:29,607 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7 states and 8 transitions. [2025-02-06 19:04:29,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7 states and 8 transitions. [2025-02-06 19:04:29,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7 to 7. [2025-02-06 19:04:29,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:04:29,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 8 transitions. [2025-02-06 19:04:29,624 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7 states and 8 transitions. [2025-02-06 19:04:29,626 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-02-06 19:04:29,629 INFO L432 stractBuchiCegarLoop]: Abstraction has 7 states and 8 transitions. [2025-02-06 19:04:29,630 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-02-06 19:04:29,630 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 8 transitions. [2025-02-06 19:04:29,630 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2025-02-06 19:04:29,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:04:29,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:04:29,631 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:04:29,631 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-02-06 19:04:29,631 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-02-06 19:04:29,632 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-02-06 19:04:29,632 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:04:29,633 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 2 times [2025-02-06 19:04:29,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:04:29,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715053736] [2025-02-06 19:04:29,633 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:04:29,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:04:29,642 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:04:29,652 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:04:29,653 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:04:29,653 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:04:29,653 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:04:29,655 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:04:29,663 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:04:29,664 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:04:29,664 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:04:29,665 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:04:29,669 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:04:29,669 INFO L85 PathProgramCache]: Analyzing trace with hash 40999300, now seen corresponding path program 1 times [2025-02-06 19:04:29,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:04:29,669 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447770009] [2025-02-06 19:04:29,669 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:04:29,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:04:29,679 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-02-06 19:04:29,692 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-02-06 19:04:29,692 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:04:29,692 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:04:29,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:29,817 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:04:29,817 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [447770009] [2025-02-06 19:04:29,817 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [447770009] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:04:29,817 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:04:29,817 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:04:29,818 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1368772358] [2025-02-06 19:04:29,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:04:29,818 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:04:29,818 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:04:29,818 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:04:29,818 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:04:29,819 INFO L87 Difference]: Start difference. First operand 7 states and 8 transitions. cyclomatic complexity: 2 Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:04:29,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:04:29,859 INFO L93 Difference]: Finished difference Result 9 states and 10 transitions. [2025-02-06 19:04:29,859 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9 states and 10 transitions. [2025-02-06 19:04:29,859 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2025-02-06 19:04:29,860 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9 states to 9 states and 10 transitions. [2025-02-06 19:04:29,860 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2025-02-06 19:04:29,860 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2025-02-06 19:04:29,860 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 10 transitions. [2025-02-06 19:04:29,860 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:04:29,860 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2025-02-06 19:04:29,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 10 transitions. [2025-02-06 19:04:29,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2025-02-06 19:04:29,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 8 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:04:29,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 10 transitions. [2025-02-06 19:04:29,861 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2025-02-06 19:04:29,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:04:29,862 INFO L432 stractBuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2025-02-06 19:04:29,863 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-02-06 19:04:29,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 10 transitions. [2025-02-06 19:04:29,864 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2025-02-06 19:04:29,864 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:04:29,864 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:04:29,864 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:04:29,864 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1] [2025-02-06 19:04:29,864 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-02-06 19:04:29,864 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-02-06 19:04:29,865 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:04:29,865 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 3 times [2025-02-06 19:04:29,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:04:29,866 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760423939] [2025-02-06 19:04:29,866 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:04:29,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:04:29,878 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:04:29,881 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:04:29,881 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:04:29,881 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:04:29,881 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:04:29,883 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:04:29,884 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:04:29,885 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:04:29,885 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:04:29,887 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:04:29,888 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:04:29,888 INFO L85 PathProgramCache]: Analyzing trace with hash 745656389, now seen corresponding path program 1 times [2025-02-06 19:04:29,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:04:29,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952529662] [2025-02-06 19:04:29,889 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:04:29,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:04:29,897 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-02-06 19:04:29,906 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-02-06 19:04:29,909 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:04:29,910 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:04:30,128 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:30,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:04:30,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952529662] [2025-02-06 19:04:30,129 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952529662] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:04:30,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [264597221] [2025-02-06 19:04:30,129 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:04:30,129 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:04:30,129 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:04:30,132 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:04:30,133 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2025-02-06 19:04:30,166 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-02-06 19:04:30,175 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-02-06 19:04:30,175 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:04:30,175 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:04:30,176 INFO L256 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 6 conjuncts are in the unsatisfiable core [2025-02-06 19:04:30,178 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:04:30,209 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-02-06 19:04:30,230 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:30,250 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:30,251 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:04:30,293 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:30,295 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [264597221] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:04:30,295 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:04:30,295 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5] total 10 [2025-02-06 19:04:30,295 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [287260618] [2025-02-06 19:04:30,295 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:04:30,296 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:04:30,296 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:04:30,296 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-02-06 19:04:30,296 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2025-02-06 19:04:30,296 INFO L87 Difference]: Start difference. First operand 9 states and 10 transitions. cyclomatic complexity: 2 Second operand has 10 states, 10 states have (on average 1.5) internal successors, (15), 10 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:04:30,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:04:30,348 INFO L93 Difference]: Finished difference Result 15 states and 16 transitions. [2025-02-06 19:04:30,348 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 16 transitions. [2025-02-06 19:04:30,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2025-02-06 19:04:30,348 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 16 transitions. [2025-02-06 19:04:30,348 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2025-02-06 19:04:30,349 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2025-02-06 19:04:30,349 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 16 transitions. [2025-02-06 19:04:30,349 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:04:30,349 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2025-02-06 19:04:30,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 16 transitions. [2025-02-06 19:04:30,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2025-02-06 19:04:30,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 14 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:04:30,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions. [2025-02-06 19:04:30,350 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2025-02-06 19:04:30,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-06 19:04:30,351 INFO L432 stractBuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2025-02-06 19:04:30,351 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-02-06 19:04:30,351 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 16 transitions. [2025-02-06 19:04:30,351 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2025-02-06 19:04:30,351 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:04:30,351 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:04:30,352 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:04:30,352 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [5, 4, 1, 1, 1, 1] [2025-02-06 19:04:30,352 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-02-06 19:04:30,352 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-02-06 19:04:30,352 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:04:30,352 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 4 times [2025-02-06 19:04:30,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:04:30,353 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222026917] [2025-02-06 19:04:30,353 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:04:30,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:04:30,357 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-02-06 19:04:30,359 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:04:30,360 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:04:30,360 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:04:30,360 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:04:30,361 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:04:30,362 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:04:30,362 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:04:30,362 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:04:30,363 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:04:30,364 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:04:30,364 INFO L85 PathProgramCache]: Analyzing trace with hash 551987976, now seen corresponding path program 2 times [2025-02-06 19:04:30,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:04:30,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [518955468] [2025-02-06 19:04:30,364 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:04:30,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:04:30,369 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 13 statements into 2 equivalence classes. [2025-02-06 19:04:30,375 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 13 of 13 statements. [2025-02-06 19:04:30,375 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-06 19:04:30,375 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:04:30,686 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:30,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:04:30,687 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [518955468] [2025-02-06 19:04:30,687 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [518955468] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:04:30,688 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1176035096] [2025-02-06 19:04:30,688 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:04:30,688 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:04:30,688 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:04:30,690 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:04:30,692 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2025-02-06 19:04:30,724 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 13 statements into 2 equivalence classes. [2025-02-06 19:04:30,735 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 13 of 13 statements. [2025-02-06 19:04:30,736 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-06 19:04:30,736 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:04:30,736 INFO L256 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 12 conjuncts are in the unsatisfiable core [2025-02-06 19:04:30,738 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:04:30,741 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-02-06 19:04:30,749 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:30,765 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:30,783 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:30,802 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:30,819 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:30,819 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:04:30,911 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:30,911 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1176035096] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:04:30,911 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:04:30,912 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8] total 22 [2025-02-06 19:04:30,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [751288070] [2025-02-06 19:04:30,912 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:04:30,912 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:04:30,912 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:04:30,912 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-02-06 19:04:30,913 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=297, Unknown=0, NotChecked=0, Total=462 [2025-02-06 19:04:30,913 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. cyclomatic complexity: 2 Second operand has 22 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:04:31,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:04:31,085 INFO L93 Difference]: Finished difference Result 27 states and 28 transitions. [2025-02-06 19:04:31,085 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 28 transitions. [2025-02-06 19:04:31,085 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2025-02-06 19:04:31,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 28 transitions. [2025-02-06 19:04:31,086 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2025-02-06 19:04:31,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2025-02-06 19:04:31,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 28 transitions. [2025-02-06 19:04:31,086 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:04:31,086 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2025-02-06 19:04:31,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 28 transitions. [2025-02-06 19:04:31,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2025-02-06 19:04:31,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.037037037037037) internal successors, (28), 26 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:04:31,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2025-02-06 19:04:31,088 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2025-02-06 19:04:31,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2025-02-06 19:04:31,089 INFO L432 stractBuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2025-02-06 19:04:31,089 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-02-06 19:04:31,089 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 28 transitions. [2025-02-06 19:04:31,089 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2025-02-06 19:04:31,089 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:04:31,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:04:31,090 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:04:31,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [11, 10, 1, 1, 1, 1] [2025-02-06 19:04:31,090 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-02-06 19:04:31,090 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-02-06 19:04:31,090 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:04:31,090 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 5 times [2025-02-06 19:04:31,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:04:31,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740771225] [2025-02-06 19:04:31,090 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:04:31,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:04:31,094 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:04:31,096 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:04:31,096 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:04:31,096 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:04:31,096 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:04:31,097 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:04:31,098 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:04:31,098 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:04:31,098 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:04:31,099 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:04:31,100 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:04:31,100 INFO L85 PathProgramCache]: Analyzing trace with hash 1878717902, now seen corresponding path program 3 times [2025-02-06 19:04:31,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:04:31,100 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1444579148] [2025-02-06 19:04:31,100 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:04:31,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:04:31,109 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 25 statements into 11 equivalence classes. [2025-02-06 19:04:31,127 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) and asserted 25 of 25 statements. [2025-02-06 19:04:31,128 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2025-02-06 19:04:31,128 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:04:31,896 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:31,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:04:31,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1444579148] [2025-02-06 19:04:31,897 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1444579148] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:04:31,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [35317083] [2025-02-06 19:04:31,897 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:04:31,897 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:04:31,897 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:04:31,900 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:04:31,902 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2025-02-06 19:04:31,946 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 25 statements into 11 equivalence classes. [2025-02-06 19:04:31,992 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) and asserted 25 of 25 statements. [2025-02-06 19:04:31,992 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2025-02-06 19:04:31,992 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:04:31,993 INFO L256 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 24 conjuncts are in the unsatisfiable core [2025-02-06 19:04:32,000 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:04:32,006 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-02-06 19:04:32,016 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:32,042 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:32,060 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:32,077 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:32,095 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:32,115 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:32,130 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:32,150 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:32,171 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:32,190 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:32,211 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:32,212 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:04:32,461 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:32,461 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [35317083] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:04:32,461 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:04:32,461 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 14, 14] total 40 [2025-02-06 19:04:32,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [12034185] [2025-02-06 19:04:32,461 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:04:32,461 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:04:32,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:04:32,462 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2025-02-06 19:04:32,463 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=568, Invalid=992, Unknown=0, NotChecked=0, Total=1560 [2025-02-06 19:04:32,463 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. cyclomatic complexity: 2 Second operand has 40 states, 40 states have (on average 1.725) internal successors, (69), 40 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:04:32,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:04:32,950 INFO L93 Difference]: Finished difference Result 51 states and 52 transitions. [2025-02-06 19:04:32,950 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 52 transitions. [2025-02-06 19:04:32,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2025-02-06 19:04:32,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 51 states and 52 transitions. [2025-02-06 19:04:32,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2025-02-06 19:04:32,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2025-02-06 19:04:32,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 52 transitions. [2025-02-06 19:04:32,952 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:04:32,952 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2025-02-06 19:04:32,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 52 transitions. [2025-02-06 19:04:32,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2025-02-06 19:04:32,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.0196078431372548) internal successors, (52), 50 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:04:32,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 52 transitions. [2025-02-06 19:04:32,956 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2025-02-06 19:04:32,956 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2025-02-06 19:04:32,957 INFO L432 stractBuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2025-02-06 19:04:32,957 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-02-06 19:04:32,957 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 52 transitions. [2025-02-06 19:04:32,958 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2025-02-06 19:04:32,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:04:32,960 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:04:32,960 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:04:32,960 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [23, 22, 1, 1, 1, 1] [2025-02-06 19:04:32,960 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-02-06 19:04:32,960 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-02-06 19:04:32,961 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:04:32,961 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 6 times [2025-02-06 19:04:32,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:04:32,961 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [518621020] [2025-02-06 19:04:32,961 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:04:32,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:04:32,967 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:04:32,970 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:04:32,970 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 19:04:32,970 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:04:32,970 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:04:32,971 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:04:32,974 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:04:32,974 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:04:32,974 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:04:32,975 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:04:32,976 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:04:32,976 INFO L85 PathProgramCache]: Analyzing trace with hash -1594285990, now seen corresponding path program 4 times [2025-02-06 19:04:32,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:04:32,976 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [110770786] [2025-02-06 19:04:32,976 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:04:32,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:04:32,991 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 49 statements into 2 equivalence classes. [2025-02-06 19:04:33,015 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 49 of 49 statements. [2025-02-06 19:04:33,015 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:04:33,015 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:04:35,046 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:35,046 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:04:35,046 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [110770786] [2025-02-06 19:04:35,046 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [110770786] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:04:35,046 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1127724938] [2025-02-06 19:04:35,047 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:04:35,047 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:04:35,047 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:04:35,049 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:04:35,051 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2025-02-06 19:04:35,101 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 49 statements into 2 equivalence classes. [2025-02-06 19:04:35,275 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 49 of 49 statements. [2025-02-06 19:04:35,275 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:04:35,275 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:04:35,277 INFO L256 TraceCheckSpWp]: Trace formula consists of 362 conjuncts, 48 conjuncts are in the unsatisfiable core [2025-02-06 19:04:35,283 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:04:35,287 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-02-06 19:04:35,293 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,313 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,334 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,356 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,375 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,394 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,413 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,438 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,462 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,483 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,503 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,527 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,552 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,576 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,598 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,621 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,643 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,668 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,693 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,730 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,753 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,775 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:04:35,816 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:35,819 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:04:36,535 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:36,536 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1127724938] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:04:36,536 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:04:36,536 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 26, 26] total 94 [2025-02-06 19:04:36,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [702406442] [2025-02-06 19:04:36,537 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:04:36,537 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:04:36,538 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:04:36,540 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2025-02-06 19:04:36,543 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3036, Invalid=5706, Unknown=0, NotChecked=0, Total=8742 [2025-02-06 19:04:36,545 INFO L87 Difference]: Start difference. First operand 51 states and 52 transitions. cyclomatic complexity: 2 Second operand has 94 states, 94 states have (on average 1.5) internal successors, (141), 94 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:04:37,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:04:37,862 INFO L93 Difference]: Finished difference Result 99 states and 100 transitions. [2025-02-06 19:04:37,862 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 100 transitions. [2025-02-06 19:04:37,863 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-02-06 19:04:37,864 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 99 states and 100 transitions. [2025-02-06 19:04:37,864 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99 [2025-02-06 19:04:37,864 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99 [2025-02-06 19:04:37,864 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 100 transitions. [2025-02-06 19:04:37,864 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:04:37,864 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2025-02-06 19:04:37,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 100 transitions. [2025-02-06 19:04:37,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2025-02-06 19:04:37,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.0101010101010102) internal successors, (100), 98 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:04:37,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 100 transitions. [2025-02-06 19:04:37,867 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2025-02-06 19:04:37,868 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2025-02-06 19:04:37,868 INFO L432 stractBuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2025-02-06 19:04:37,868 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-02-06 19:04:37,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 100 transitions. [2025-02-06 19:04:37,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-02-06 19:04:37,869 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:04:37,869 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:04:37,870 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:04:37,870 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [47, 46, 1, 1, 1, 1] [2025-02-06 19:04:37,870 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-02-06 19:04:37,870 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-02-06 19:04:37,870 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:04:37,870 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 7 times [2025-02-06 19:04:37,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:04:37,870 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1470674556] [2025-02-06 19:04:37,871 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:04:37,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:04:37,875 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:04:37,876 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:04:37,876 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:04:37,876 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:04:37,876 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:04:37,880 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:04:37,881 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:04:37,881 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:04:37,881 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:04:37,882 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:04:37,883 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:04:37,883 INFO L85 PathProgramCache]: Analyzing trace with hash -1098528398, now seen corresponding path program 5 times [2025-02-06 19:04:37,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:04:37,883 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702113912] [2025-02-06 19:04:37,883 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:04:37,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:04:37,910 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 97 statements into 47 equivalence classes. [2025-02-06 19:04:38,016 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) and asserted 97 of 97 statements. [2025-02-06 19:04:38,017 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2025-02-06 19:04:38,017 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:04:42,166 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:04:42,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:04:42,166 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702113912] [2025-02-06 19:04:42,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [702113912] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:04:42,166 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [545860518] [2025-02-06 19:04:42,166 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:04:42,166 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:04:42,167 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:04:42,168 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:04:42,170 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2025-02-06 19:04:42,231 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 97 statements into 47 equivalence classes. [2025-02-06 19:05:03,488 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) and asserted 97 of 97 statements. [2025-02-06 19:05:03,488 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2025-02-06 19:05:03,488 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:05:03,499 INFO L256 TraceCheckSpWp]: Trace formula consists of 722 conjuncts, 96 conjuncts are in the unsatisfiable core [2025-02-06 19:05:03,517 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:05:03,520 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-02-06 19:05:03,528 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,542 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,556 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,578 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,593 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,614 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,631 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,653 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,669 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,688 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,712 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,731 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,751 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,773 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,792 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,818 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,840 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,863 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,886 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,912 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,934 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,959 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:03,983 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,007 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,031 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,055 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,079 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,108 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,136 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,165 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,193 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,220 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,249 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,277 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,306 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,337 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,372 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,403 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,432 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,463 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,496 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,533 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,572 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,611 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,652 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,690 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-02-06 19:05:04,725 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:05:04,725 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:05:06,767 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:05:06,767 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [545860518] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:05:06,767 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:05:06,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 50, 50] total 159 [2025-02-06 19:05:06,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [867036636] [2025-02-06 19:05:06,767 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:05:06,768 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:05:06,768 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:05:06,769 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 159 interpolants. [2025-02-06 19:05:06,778 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8962, Invalid=16160, Unknown=0, NotChecked=0, Total=25122 [2025-02-06 19:05:06,779 INFO L87 Difference]: Start difference. First operand 99 states and 100 transitions. cyclomatic complexity: 2 Second operand has 159 states, 159 states have (on average 1.7861635220125787) internal successors, (284), 159 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:05:10,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:05:10,282 INFO L93 Difference]: Finished difference Result 195 states and 196 transitions. [2025-02-06 19:05:10,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195 states and 196 transitions. [2025-02-06 19:05:10,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 193 [2025-02-06 19:05:10,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195 states to 195 states and 196 transitions. [2025-02-06 19:05:10,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2025-02-06 19:05:10,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2025-02-06 19:05:10,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 196 transitions. [2025-02-06 19:05:10,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:05:10,286 INFO L218 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2025-02-06 19:05:10,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 196 transitions. [2025-02-06 19:05:10,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195. [2025-02-06 19:05:10,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.005128205128205) internal successors, (196), 194 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:05:10,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 196 transitions. [2025-02-06 19:05:10,295 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2025-02-06 19:05:10,295 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 190 states. [2025-02-06 19:05:10,296 INFO L432 stractBuchiCegarLoop]: Abstraction has 195 states and 196 transitions. [2025-02-06 19:05:10,296 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-02-06 19:05:10,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 196 transitions. [2025-02-06 19:05:10,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 193 [2025-02-06 19:05:10,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:05:10,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:05:10,300 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:05:10,301 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [95, 94, 1, 1, 1, 1] [2025-02-06 19:05:10,302 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-02-06 19:05:10,302 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#1(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#1(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#1(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#0(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#0(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-02-06 19:05:10,302 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:05:10,302 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 8 times [2025-02-06 19:05:10,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:05:10,303 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511011348] [2025-02-06 19:05:10,303 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:05:10,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:05:10,305 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:05:10,306 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:05:10,306 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:05:10,306 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:05:10,306 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:05:10,307 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:05:10,307 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:05:10,307 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:05:10,307 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:05:10,308 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:05:10,310 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:05:10,310 INFO L85 PathProgramCache]: Analyzing trace with hash -676303966, now seen corresponding path program 6 times [2025-02-06 19:05:10,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:05:10,310 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612344460] [2025-02-06 19:05:10,310 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:05:10,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:05:10,337 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 193 statements into 95 equivalence classes. [2025-02-06 19:05:10,618 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) and asserted 193 of 193 statements. [2025-02-06 19:05:10,619 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2025-02-06 19:05:10,619 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:05:25,922 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:05:25,923 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:05:25,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [612344460] [2025-02-06 19:05:25,923 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [612344460] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:05:25,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2054209971] [2025-02-06 19:05:25,923 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:05:25,923 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:05:25,923 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:05:25,925 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:05:25,926 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2025-02-06 19:05:26,015 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 193 statements into 95 equivalence classes.